CN115293083A - Integrated circuit time sequence prediction method and device, electronic equipment and storage medium - Google Patents

Integrated circuit time sequence prediction method and device, electronic equipment and storage medium Download PDF

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CN115293083A
CN115293083A CN202211206488.4A CN202211206488A CN115293083A CN 115293083 A CN115293083 A CN 115293083A CN 202211206488 A CN202211206488 A CN 202211206488A CN 115293083 A CN115293083 A CN 115293083A
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CN115293083B (en
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冯春阳
田培杰
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Shenzhen Hongxin Micro Nano Technology Co ltd
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Abstract

The application provides an integrated circuit time sequence prediction method, an integrated circuit time sequence prediction device, electronic equipment and a storage medium, and relates to the technical field of integrated circuits. The method comprises the steps of predicting time margins of paths in a target integrated circuit by adopting a pre-trained time sequence prediction model to obtain a predicted time margin sequence corresponding to the target integrated circuit, wherein the time sequence prediction model is obtained based on a sample graph structure, sample graph characteristic information and real time sequence training of the sample integrated circuit, and information represented by the sample graph structure and the sample graph characteristic information is more detailed and abundant.

Description

Integrated circuit time sequence prediction method and device, electronic equipment and storage medium
Technical Field
The present disclosure relates to the field of integrated circuit technologies, and in particular, to a method and an apparatus for integrated circuit timing prediction, an electronic device, and a storage medium.
Background
An Integrated Circuit (IC) is a type of microelectronic device or component. In the manufacture of ICs, a certain process is used to interconnect the required elements such as transistors, resistors, capacitors and inductors in a circuit and wiring, and the interconnection is made on one or more small semiconductor chips or dielectric substrates, which are then packaged in a package to form a microstructure having the required circuit function.
In the prior art, when analyzing timing information of a device in an integrated circuit, a Graph-Based timing Analysis (GBA) is usually used to perform a preliminary rough Analysis, and then a Path-Based timing Analysis (PBA) is further performed Based on an Analysis result of the GBA to obtain a final Analysis result.
However, the accuracy of the analysis result of GBA is poor, so that the calculation amount is large when PBA analysis is performed, and the timing analysis efficiency is reduced.
Disclosure of Invention
An object of the present invention is to provide a method, an apparatus, an electronic device and a storage medium for integrated circuit timing prediction, so as to solve the problem of low efficiency of path timing analysis of the integrated circuit in the prior art.
In order to achieve the above purpose, the embodiments of the present application adopt the following technical solutions:
in a first aspect, an embodiment of the present application provides an integrated circuit timing prediction method, including:
adopting a pre-trained time sequence prediction model to predict time margins of a plurality of paths contained in a target integrated circuit, and generating a prediction time margin sequence corresponding to the target integrated circuit; the target integrated circuit comprises a plurality of paths formed from a circuit starting point to a circuit terminal point; the prediction time margins of all paths in the prediction time margin sequence are sequentially arranged according to the value; the time sequence prediction model is obtained by training according to the sample graph structure of the sample integrated circuit, the sample graph characteristic information and the real time sequence of the sample integrated circuit;
according to the predicted time margin sequence, performing path-based time sequence analysis calculation to obtain a target time margin sequence corresponding to the target integrated circuit;
and determining a target number of target paths from the plurality of paths according to the target time margin sequence.
Optionally, the sample graph structure of the sample integrated circuit is obtained by converting a circuit structure of the sample integrated circuit, where the sample graph structure includes nodes and node connecting lines, the nodes are used to characterize pins of each device in the sample integrated circuit, and the node connecting lines are used to characterize a connection relationship between the pins;
the predicting the time margins of a plurality of paths contained in a target integrated circuit by adopting a pre-trained time sequence predicting model to generate a predicting time margin sequence corresponding to the target integrated circuit comprises the following steps:
converting the circuit structure of the target integrated circuit to obtain a graph structure of the target integrated circuit, wherein the graph structure of the target integrated circuit comprises nodes and connecting lines;
acquiring graph feature information of the target integrated circuit according to the graph structure of the target integrated circuit;
and inputting the graph characteristic information into the time sequence prediction model to obtain a prediction time margin sequence corresponding to the target integrated circuit.
Optionally, the performing, according to the predicted time margin sequence, a path-based time sequence analysis calculation to obtain a target time margin sequence corresponding to the target integrated circuit includes:
and taking the predicted time margin sequence as input information of a path-based time sequence analysis algorithm, and performing time sequence analysis calculation through the path-based time sequence analysis algorithm to obtain the target time margin sequence.
Optionally, performing timing analysis calculation by the path-based timing analysis algorithm to obtain the target time margin sequence, including:
determining a current path to be analyzed according to the prediction time margin sequence;
determining a target time margin of the current path to be analyzed, and taking the target time margin of the current path to be analyzed as a current time margin threshold;
sequentially traversing paths behind the current path to be analyzed, determining a new current path to be analyzed, calculating and obtaining a target time margin of the new current path to be analyzed, and updating a current time margin threshold according to the target time margin of the new current path to be analyzed to obtain a new current time margin threshold;
and circularly executing until a preset condition is met, stopping calculation, and arranging the target time margins of all paths obtained by calculation according to the value to obtain a target time margin sequence corresponding to the target integrated circuit.
Optionally, the determining a current path to be analyzed according to the predicted time margin sequence includes:
and taking the path with the minimum prediction time margin in the prediction time margin sequence as the current path to be analyzed.
Optionally, determining a new current path to be analyzed, calculating and obtaining a target time margin of the new current path to be analyzed, and updating the current time margin threshold according to the target time margin of the new current path to be analyzed to obtain a new current time margin threshold, including:
according to the prediction time margin sequence, taking the next path of the current path to be analyzed as a new current path to be analyzed;
if the predicted time margin of the new path to be analyzed is smaller than the current time margin threshold, calculating and obtaining a target time margin of the new path to be analyzed;
and if the target time margin of the new path to be analyzed is smaller than the current time margin threshold, taking the target time margin of the new path to be analyzed as the new current time margin threshold.
Optionally, the loop is executed until a preset condition is met, and the stopping of the calculation includes:
and if the predicted time margin of the current path to be analyzed is larger than the current time margin threshold value and the number of the current calculated and acquired target paths meets the target number, stopping calculation.
Optionally, the determining a target number of target paths from the plurality of paths according to the target time margin sequence includes:
and sequentially selecting target time margins with target quantity according to the target time margin sequence of each path in the target time margin sequence, and determining the path corresponding to each selected target time margin as a target path.
In a second aspect, an embodiment of the present application further provides an integrated circuit timing prediction apparatus, including: the device comprises a generation module, a calculation module and a determination module;
the generating module is used for predicting the time margins of a plurality of paths contained in a target integrated circuit by adopting a pre-trained time sequence prediction model and generating a prediction time margin sequence corresponding to the target integrated circuit; the target integrated circuit comprises a plurality of paths formed from a circuit starting point to a circuit terminal point; the prediction time margins of all paths in the prediction time margin sequence are sequentially arranged according to the value; the time sequence prediction model is obtained by training according to the sample graph structure of the sample integrated circuit, the sample graph characteristic information and the real time sequence of the sample integrated circuit;
the calculation module is used for performing path-based time sequence analysis calculation according to the predicted time margin sequence to obtain a target time margin sequence corresponding to the target integrated circuit;
the determining module is configured to determine a target number of target paths from the plurality of paths according to the target time margin sequence.
Optionally, the sample graph structure of the sample integrated circuit is obtained by converting a circuit structure of the sample integrated circuit, where the sample graph structure includes nodes and node connecting lines, the nodes are used to characterize pins of each device in the sample integrated circuit, and the node connecting lines are used to characterize a connection relationship between the pins;
the generating module is specifically configured to convert the circuit structure of the target integrated circuit to obtain a graph structure of the target integrated circuit, where the graph structure of the target integrated circuit includes nodes and connecting lines;
acquiring graph feature information of the target integrated circuit according to the graph structure of the target integrated circuit;
and inputting the graph characteristic information into the time sequence prediction model to obtain a prediction time margin sequence corresponding to the target integrated circuit.
Optionally, the calculation module is specifically configured to use the predicted time margin sequence as input information of a path-based time sequence analysis algorithm, and perform time sequence analysis calculation through the path-based time sequence analysis algorithm to obtain the target time margin sequence.
Optionally, the calculating module is specifically configured to determine, according to the predicted time margin sequence, a current path to be analyzed;
determining a target time margin of the current path to be analyzed, and taking the target time margin of the current path to be analyzed as a current time margin threshold value;
sequentially traversing paths behind the current path to be analyzed, determining a new current path to be analyzed, calculating and obtaining a target time margin of the new current path to be analyzed, and updating a current time margin threshold according to the target time margin of the new current path to be analyzed to obtain a new current time margin threshold;
and circularly executing until a preset condition is met, stopping calculation, and arranging the target time margins of all paths obtained by calculation at present according to the value to obtain a target time margin sequence corresponding to the target integrated circuit.
Optionally, the calculation module is specifically configured to use a path with the smallest predicted time margin in the predicted time margin sequence as the current path to be analyzed.
Optionally, the calculation module is specifically configured to take a next path of the current path to be analyzed as a new current path to be analyzed according to the predicted time margin sequence;
if the predicted time margin of the new path to be analyzed is smaller than the current time margin threshold, calculating and obtaining a target time margin of the new path to be analyzed;
and if the target time margin of the new path to be analyzed is smaller than the current time margin threshold, taking the target time margin of the new path to be analyzed as a new current time margin threshold.
Optionally, the calculating module is specifically configured to stop calculating if the predicted time margin of the current path to be analyzed is greater than the current time margin threshold and the number of the currently calculated and acquired target paths meets the target number.
Optionally, the determining module is specifically configured to select target time margins of a target number in sequence according to the target time margin sequence of each path in the target time margin sequence, and determine a path corresponding to each selected target time margin as a target path.
In a third aspect, an embodiment of the present application provides an electronic device, including: a processor, a storage medium and a bus, the storage medium storing machine-readable instructions executable by the processor, the processor and the storage medium communicating via the bus when the electronic device is operated, the processor executing the machine-readable instructions to perform the steps of the method as provided in the first aspect when executed.
In a fourth aspect, embodiments of the present application provide a computer-readable storage medium, on which a computer program is stored, which, when executed by a processor, performs the steps of the method as provided in the first aspect.
The beneficial effect of this application is:
the method comprises the steps of predicting time margins of paths in a target integrated circuit by adopting a pre-trained time-sequence prediction model to obtain a predicted time margin sequence corresponding to the target integrated circuit, wherein the time-sequence prediction model is obtained by training a sample graph structure, sample graph characteristic information and a real time sequence of the sample integrated circuit, and information represented by the sample graph structure and the sample graph characteristic information is more detailed and abundant.
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In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained from the drawings without inventive effort.
FIG. 1 is a flowchart illustrating a first method for integrated circuit timing prediction according to an embodiment of the present disclosure;
FIG. 2 is a flowchart illustrating a second method for integrated circuit timing prediction according to an embodiment of the present disclosure;
FIG. 3 is a flowchart illustrating a third method for integrated circuit timing prediction according to an embodiment of the present disclosure;
FIG. 4 is a flowchart illustrating a fourth method for integrated circuit timing prediction according to an embodiment of the present disclosure;
FIG. 5 is a first timing margin sequence diagram provided in an embodiment of the present application;
FIG. 6 is a timing sequence diagram illustrating a second timing margin provided by an embodiment of the present application;
FIG. 7 is a schematic diagram of an apparatus for integrated circuit timing prediction according to an embodiment of the present disclosure;
fig. 8 is a schematic structural diagram of an electronic device according to an embodiment of the present application.
Detailed Description
In order to make the purpose, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it should be understood that the drawings in the present application are for illustrative and descriptive purposes only and are not used to limit the scope of protection of the present application. Additionally, it should be understood that the schematic drawings are not necessarily drawn to scale. The flowcharts used in this application illustrate operations implemented according to some embodiments of the present application. It should be understood that the operations of the flow diagrams may be performed out of order, and steps without logical context may be performed in reverse order or simultaneously. One skilled in the art, under the guidance of this application, may add one or more other operations to, or remove one or more operations from, the flowchart.
In addition, the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. The components of the embodiments of the present application, as generally described and illustrated in the figures herein, could be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present application, presented in the accompanying drawings, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present application without making any creative effort, shall fall within the protection scope of the present application.
It should be noted that in the embodiments of the present application, the term "comprising" is used to indicate the presence of the features stated hereinafter, but does not exclude the addition of further features.
The relevant background to which this application relates will first be briefly described:
in the circuit design of an integrated circuit, the timing sequence of each path in the circuit is usually analyzed to determine an unsatisfactory path (worst path) in the circuit, where the unsatisfactory path may mean that the signal propagation on the path is blocked, and the signal cannot propagate from the start point of the circuit to the end point of the circuit at a specified speed and in time. By carrying out time sequence analysis on the paths, the paths which do not meet the requirements can be accurately found out, so that designers are helped to improve the paths in time.
Among static timing Analysis, there are two Analysis methods, one is Graph-Based timing Analysis GBA (Graph-Based Analysis) and the other is Path-Based timing Analysis PBA (Path-Based Analysis). The GBA analysis speed is high, but the accuracy of the analysis result is poor; the PBA analysis speed is low, but the accuracy of the analysis result is high, and in the timing sequence checking stage, the PBA analysis is required to ensure the accuracy of the design.
When searching for the worst path in the PBA mode, there are also two modes, one is to directly recalculate the results according to the ordering obtained in the GBA mode, which is relatively fast. But the result is not accurate, i.e. the "worst" path obtained in PBA mode at this time is not necessarily the worst path. To ensure that the searched path is indeed the worst path, another Mode, called Exhaustive Mode, needs to be run. In the exhaustive mode, assuming that the worst path is obtained, the first one hundred paths are searched according to the GBA sorting, and the worst path is selected from the one hundred paths as the worst path of the whole design. How many paths are selected is not fixed and needs to be adjusted according to the number of worst paths required.
However, the number of worst paths needed is often very different from the number of paths that need to be searched. In practical designs, hundreds, thousands or even more paths may need to be searched to obtain a worst path, and a large amount of recalculation is required, which consumes a lot of time. If the number of search paths can be reduced, much time can be saved. One root cause for this is that the magnitude of the GBA and PBA time margins can in many cases be very different.
The input of the PBA exhaustive mode search algorithm is a series of ordered paths, so the ordering of the input paths is very important, and the initial ordering of the input PBA exhaustive mode influences the number of paths to be searched for finding the worst PBA time margin to a certain extent.
Based on the method, a training-based time sequence prediction model is provided, a series of prediction time margins which are closer to the real PBA time margin are obtained through prediction, the prediction time margins are used as input of a PBA exhaustion mode, and due to the fact that the sequence of the input time margins is improved, the number of paths required by searching is reduced, and the purpose of quickly searching and obtaining the worst path is achieved.
The process of the present application is illustrated by the following specific examples.
FIG. 1 is a flowchart illustrating a first method for integrated circuit timing prediction according to an embodiment of the present disclosure; as shown in fig. 1, the method includes:
s101, predicting time margins of a plurality of paths contained in a target integrated circuit by adopting a pre-trained time sequence prediction model, and generating a prediction time margin sequence corresponding to the target integrated circuit.
Wherein the target integrated circuit comprises a plurality of paths from a circuit starting point to a circuit ending point; the prediction time margins of all paths in the prediction time margin sequence are sequentially arranged according to the value; and the time sequence prediction model is obtained by training according to the sample graph structure of the sample integrated circuit, the sample graph characteristic information and the real time sequence of the sample integrated circuit.
In this embodiment, for a target integrated circuit to be analyzed, a trained time sequence prediction model may be first used to perform time margin prediction on each path in the target integrated circuit to obtain a predicted time margin sequence, where the predicted time margin sequence refers to a sequence generated after time margins of each path are arranged according to a preset ordering manner.
Because the time sequence prediction model adopted in the embodiment is obtained based on the sample graph structure of the sample integrated circuit, the sample graph characteristic information and the real time sequence training of the sample integrated circuit, compared with the time margin sequence predicted by adopting the traditional GBA mode, the accuracy of the predicted time margin sequence obtained by adopting the time sequence prediction model is higher, and therefore when the predicted time margin sequence is used for the subsequent PBA time margin calculation, the accuracy of the PBA time margin calculation result can be improved.
And S102, according to the predicted time margin sequence, performing path-based time sequence analysis and calculation to obtain a target time margin sequence corresponding to the target integrated circuit.
Optionally, although the accuracy of the obtained predicted time margin sequence is higher than that of the time margin sequence predicted by the conventional GBA method, the accuracy of the predicted time margin sequence is not yet required compared with that of the PBA time margin sequence, and therefore, the PBA calculation may be further performed based on the predicted time margin sequence to obtain a target time margin sequence corresponding to the target integrated circuit.
S103, determining target paths with a target number from the multiple paths according to the target time margin sequence.
It should be noted that the time margin is an index for measuring the quality of the paths, and each path correspondingly calculates a time margin. Generally, when the time margin is positive, the signal may be considered to reach the endpoint faster than the desired time as it travels along the path; when the time margin is 0, the signal is considered to reach the end point just according to the expected time when propagating along the path; and when the time margin is a negative value, the signal is considered to exceed the expected time to reach the end point when propagating along the path, namely, the signal propagation is blocked and cannot reach the end point according to the time.
In other words, a larger time margin indicates a better path and a smaller time margin indicates a worse path. Based on the target time margin sequence, the target paths with the target quantity can be determined from all the paths, wherein the target paths refer to worst paths. Based on the determined target path, the target path may be refined to meet signal propagation requirements.
In summary, according to the integrated circuit timing prediction method provided by this embodiment, a time margin prediction is performed on a path in a target integrated circuit by using a pre-trained timing prediction model to obtain a predicted time margin sequence corresponding to the target integrated circuit, and since the timing prediction model is obtained by training a sample diagram structure, sample diagram feature information, and a real timing of the sample integrated circuit based on the sample diagram structure and the sample diagram feature information, information represented by the sample diagram structure and the sample diagram feature information is more detailed and abundant.
FIG. 2 is a flowchart illustrating a second method for integrated circuit timing prediction according to an embodiment of the present disclosure; optionally, the sample diagram structure of the sample integrated circuit is obtained by converting a circuit structure of the sample integrated circuit, and the sample diagram structure includes nodes and node connecting lines, where the nodes are used to represent pins of each device in the sample integrated circuit, and the node connecting lines are used to represent connection relationships between the pins.
In the embodiment of the present application, the sample integrated circuit is formed by devices and connections between the devices, the devices in the circuit correspond to each node of the sample graph structure, and the connections between the devices correspond to the connections between the nodes of the sample graph structure. The sample integrated circuit is dissected in more detail, pins on each device are taken as a node, and the connecting lines among the pins correspond to the connecting lines of all nodes in the sample graph structure.
In addition, because different attributes and information are provided among the pins, the connection line from the input pin to the output pin can be represented by a time sequence arc, and the existence of the time sequence arc and the influence brought by the time sequence arc are expressed. The direction of the nodes in the directed graph can be used for representing the signal propagation direction in the sample integrated circuit, and the physical composition of the sample integrated circuit and the relation between the connecting lines of the pins can be presented to the greatest extent.
The sample graph feature information of the sample graph structure can be used for characterizing feature information of devices in the sample integrated circuit, and feature information corresponding to connecting lines between the devices.
In some embodiments, a preset tool or a preset algorithm may be used to perform feature extraction processing on each sample circuit structure, so as to directly or indirectly obtain sample graph feature information of the sample graph structure.
It should be noted that the feature extraction processing may be performed on a plurality of sample circuit structures simultaneously, or may also be performed on a plurality of sample circuit structures sequentially in a preset order, which is not specifically limited in the embodiment of the present application.
Similarly, a plurality of sample circuit structures may be simultaneously subjected to conversion processing, or a preset sequence may also be adopted to sequentially perform conversion processing on a plurality of sample circuit structures, and the embodiment of the present application does not specifically limit this.
In some embodiments, a graph neural network model is trained according to a sample graph structure, sample graph feature information, and real timing information of a sample integrated circuit, and a timing prediction model is obtained when model parameters meet preset conditions. And if the model parameters do not meet the preset conditions, continuing to train the graph neural network model until the model parameters meet the preset conditions to obtain a time sequence prediction model.
In step S101, performing time margin prediction on multiple paths included in the target integrated circuit by using a pre-trained time sequence prediction model, and generating a prediction time margin sequence corresponding to the target integrated circuit, which may include:
s201, converting the circuit structure of the target integrated circuit to obtain the graph structure of the target integrated circuit, wherein the graph structure of the target integrated circuit comprises nodes and connecting lines.
Similar to the process of training the timing prediction model, in the process of applying the timing prediction model, the circuit structure of the target integrated circuit needs to be converted first to obtain the graph structure of the target integrated circuit, so as to obtain the node and connection information included in the target integrated circuit.
S202, obtaining graph characteristic information of the target integrated circuit according to the graph structure of the target integrated circuit.
Optionally, a preset tool or a preset algorithm may be used to perform feature extraction processing on each sample circuit structure, so as to directly or indirectly obtain sample diagram feature information of the sample diagram structure, that is, obtain node feature information and connection feature information in the target integrated circuit.
In this embodiment, the node feature information may include: time of signal reaching node, switching time ratio, pin capacitance. The link characteristic information may include: conversion time ratio, delay.
Wherein the ratio of transition times (TR _ ratio) is the transition time on the current input pin (TR _ ratio)TR gba ) Divided by the maximum transition time on all input pins (TR_MAX gba ) A ratio is obtained and subtracted by 1. It is calculated as shown in the formula:
TR_ratio=1-（TR gba / TR_MAX gba ）
and the delay is obtained by subtracting the arrival time of the starting node from the arrival time of the end node of the edge.
And S203, inputting the graph characteristic information into a time sequence prediction model to obtain a prediction time margin sequence corresponding to the target integrated circuit.
Optionally, the obtained graph feature information of the target integrated circuit is input into the timing prediction model, so that a prediction time margin sequence corresponding to the target integrated circuit can be obtained in a predictable manner.
Optionally, in step S102, performing a path-based timing analysis calculation according to the predicted time margin sequence to obtain a target time margin sequence corresponding to the target integrated circuit, which may include: and taking the predicted time margin sequence as input information of a path-based time sequence analysis algorithm, and performing time sequence analysis calculation through the path-based time sequence analysis algorithm to obtain a target time margin sequence.
In some embodiments, the predicted time margin sequence may be input to a PBA algorithm as an input parameter, note that the PBA algorithm herein may refer to an exhaustive mode PBA algorithm, and an output result obtained by timing analysis and calculation of PBA is a target time margin sequence.
FIG. 3 is a flowchart illustrating a third method for integrated circuit timing prediction according to an embodiment of the present disclosure; optionally, in the foregoing step, performing timing analysis calculation by using a path-based timing analysis algorithm to obtain a target time margin sequence, where the step may include:
s301, determining the current path to be analyzed according to the prediction time margin sequence.
Usually, when performing the timing analysis calculation, each path is calculated sequentially, and optionally, the current path to be analyzed may be determined from each path according to the predicted time margin sequence.
S302, determining a target time margin of the current path to be analyzed, and taking the target time margin of the current path to be analyzed as a current time margin threshold value.
And calculating the target time margin of the current path to be analyzed by adopting a PBA algorithm, wherein the current path to be analyzed is the initial first path to be analyzed, and no other path is analyzed and calculated before the current path to be analyzed, so that only the target time margin of the current path to be analyzed is obtained by calculation at the moment, and the target time margin of the current path to be analyzed can be used as a current time margin threshold value because no other time margin data is used as a reference.
And S303, traversing paths behind the current path to be analyzed in sequence, determining a new current path to be analyzed, calculating and obtaining a target time margin of the new current path to be analyzed, and updating the current time margin threshold according to the target time margin of the new current path to be analyzed to obtain a new current time margin threshold.
And according to the path sequence in the prediction time margin sequence, sequentially traversing from the path behind the current path to be analyzed, determining each new path to be analyzed, and calculating the target time margin of the new path to be analyzed.
Here, since the current time margin threshold already exists, the current time margin threshold may be updated based on the obtained target time margin of the new current path to be analyzed, so as to obtain a new current time margin threshold.
And S304, executing in a circulating manner until preset conditions are met, stopping calculation, and arranging the target time margins of all paths obtained by calculation at present according to the value to obtain a target time margin sequence corresponding to the target integrated circuit.
And circularly executing the steps until the circulation stopping condition is met, sequencing the target time margins of all paths obtained by calculation at present according to the size of the margin value, and obtaining a target time margin sequence corresponding to the target integrated circuit.
It should be noted here that the ordering manner of each margin in the target time margin sequence and the prediction time margin sequence is the same, and when each margin in the prediction time margin sequence is ordered from small to large, each margin in the target time margin sequence is also ordered from small to large; when the margins in the prediction time margin sequence are ordered from large to small, the margins in the target time margin sequence are also ordered from large to small.
Optionally, in step S301, determining a current path to be analyzed according to the predicted time margin sequence, including: and taking the path with the minimum predicted time margin in the predicted time margin sequence as the current path to be analyzed.
In an implementation manner, according to the value of each time margin in the sequence of the predicted time margins, the path with the smallest predicted time margin may be used as the current path to be analyzed, that is, the first path to be analyzed. The path with the smallest prediction time margin refers to the path with the worst prediction time margin.
FIG. 4 is a flowchart illustrating a fourth method for integrated circuit timing prediction according to an embodiment of the present disclosure; optionally, in step S302, determining a new current path to be analyzed, calculating a target time margin for obtaining the new current path to be analyzed, and updating the current time margin threshold according to the target time margin of the new current path to be analyzed to obtain a new current time margin threshold, which may include:
s401, according to the prediction time margin sequence, taking the next path of the current path to be analyzed as a new current path to be analyzed.
Fig. 5 is a schematic diagram of a first timing margin sequence according to an embodiment of the present application. FIG. 5 illustrates a process for performing an exhaustive mode PBA time margin calculation at a given endpoint. Given an end point, all paths to be analyzed are here directed from the start point of the circuit to the same end point.
As shown in fig. 5, there are two parallel axes of time margins, the axis located below represents the predicted time margin sequence, the axis located above represents the target time margin sequence (PBA time margin sequence), and if points on both axes are at the same horizontal position, the two points represent the same time margin value. Note that, in the prediction time margin sequence, there are nine circles in total, each having a respective time margin value, respectively representing a corresponding path, which are arranged on the prediction time margin axis in the order of increasing prediction time margins.
Based on the above analysis, the determined current path to be analyzed is a path with a predicted time margin value of A1, and a target time margin of the A1 path is obtained through corresponding calculation as B1, where it should be noted that the naming of the path is named by the time margin of the path, for example: the time margin A1 may then refer to the time margin of the path A1.
And traversing each path, and taking A2 after the A1 path as a new current path to be analyzed.
S402, if the prediction time margin of the new path to be analyzed is smaller than the threshold of the current time margin, calculating and obtaining the target time margin of the new path to be analyzed.
In this embodiment, only the analysis and calculation of the current wheel, that is, the analysis and calculation of the current A2 path, are described. Firstly, whether the predicted time margin A2 of the path A2 is smaller than the current time margin threshold is judged, and based on the analysis, it is known that the current time margin threshold is B1, and then it is known that the predicted time margin of the path A2 is smaller than the current time margin threshold B1, and at this time, the target time margin of the path A2 may be smaller than B1, that is, the path A2 may be a path worse than the path A1, and then PBA calculation may be performed on the path A2 to obtain the target time margin of the path A2, and as shown in the figure, the target time margin of the path A2 is B2.
And S403, if the target time margin of the new path to be analyzed is smaller than the current time margin threshold, taking the target time margin of the new path to be analyzed as the new current time margin threshold.
At this time, the current time margin threshold B1 may also be updated according to the size of B2, when B2 is smaller than B1, the path A2 is considered to be the current worst path, then B2 may be used as a new current time margin threshold, and when B2 is larger than B1, the current time margin threshold is not updated, and the current time margin threshold remains at B1.
Optionally, in step S304, the loop is executed until a preset condition is met, and the stopping of the calculation may include: and if the predicted time margin of the current path to be analyzed is greater than the current time margin threshold value and the number of the current calculated and acquired target paths meets the target number, stopping calculation.
And the steps can be repeatedly executed, and for any round of calculation, if the predicted time margin of the current path to be analyzed is judged to be larger than the current time margin threshold value and the number of the current calculated and acquired target paths meets the target number, the calculation is stopped, and the target time margin sequence is output.
For example: in fig. 5, it is assumed that the current path to be analyzed is A3, A3 is smaller than the current time margin threshold B1, and since the predicted time margin is more pessimistic than the value of the target time margin, that is, the predicted time margin is usually greater than or equal to the target time margin and is not smaller than the target time margin, when the current path to be analyzed is A3, since A3 is greater than B1, the target time margin B3 corresponding to A3 that is calculated correspondingly is necessarily greater than B1, in this case, when we aim to find a worst path from the paths, the path that is worst path is necessarily A1, so the calculation of A3 can be ignored, that is, the stopping condition is satisfied, and the other paths after A3 and A3 will not be calculated any more.
If the target is to find the worst 3 paths from the paths, at this time, although A3 is larger than B1, A3 is smaller than B2, then the target time margin B3 calculated by the path A3 is likely to be smaller than B2, then when the worst 3 paths are to be found, the paths A1, A2, and A4 corresponding to the currently calculated B1, B2, and B4 cannot be directly taken as the worst 3 paths because the path A3 is also likely to be worse than A2 and A4, at this time, the above steps may be continuously performed with respect to the path A3, B3 is calculated, as shown in fig. 5, the calculated B3 is smaller than B4, and it may be temporarily considered that the worst 3 paths may be A1, A2, and A3. At this time, since A5 is smaller than B3, B5 calculated by the path A5 may also be smaller than B5, and the tentative paths A1, A2, and A3 cannot be directly determined as the final worst 3 paths, and then, similarly, the target time margin corresponding to the path A5 is calculated, as shown in the figure, the target time margin B5 corresponding to the path A5 is larger than B4, and then, at this time, the worst 3 paths are determined as A1, A2, and A3, at this time, the worst paths with the target number have been found from all the paths, and here, assuming that the target number is 3, the calculation may be stopped. Therefore, other paths after A5 do not need to be subjected to one-to-one traversal calculation, and compared with the huge calculation amount in the exhaustive mode, the method can greatly reduce the calculation amount.
Fig. 6 is a schematic diagram of a second time margin sequence according to an embodiment of the present application. The diagram shown in fig. 6 can represent the process diagram when PBA calculation is performed in the conventional manner that the GBA time margin sequence is used as the input sequence of the PBA algorithm.
Compared with the case that the predicted time margin sequence obtained by model prediction is used as the input sequence of the PBA algorithm in the embodiment of fig. 5, in this manner shown in fig. 6, because the corresponding relationship between the GBA time margin sequence and the target time margin sequence (PBA time margin sequence) is poor, the difference between the GBA time margin and the PBA time margin is large in many cases, for the GBA time margin A1 in fig. 6, the value of A1 is changed from the GBA axis to the PBA time margin B1 on the PBA axis, a large span is experienced, A2-A9 is spanned between A1 and B1, that is, the value of the GBA time margin B1 is larger than the GBA time margin of a path represented by A9 after 8 paths subsequent to the path represented by A1, paths after A9 have not been listed in fig. 6, and if there is some time margin between A9 and B1, the number of the paths after delay will still increase. Also, the PBA time margin B2 corresponding to GBA time margin A2 is larger than all the time margins A1-A5, and the span is also large. The large span of A2 to B2 is the root cause for searching many paths when PBA computation is performed in the exhaustive mode. Since B2 is the worst PBA time margin, all GBA time margins smaller than B2 need to be recalculated with PBA time margins, and therefore 5 paths need to be calculated in whole to find the worst PBA time margin. Then if the worst PBA time margin is larger, closer to the right on the PBA axis, then it may be necessary to recalculate ten or even tens of paths to find the value.
In the sequence of the predicted time margins obtained in this way according to this embodiment shown in fig. 5, the predicted time margins are sorted as A1, A2, A4, A3, and A5, and are in the same one-to-one correspondence with the PBA time margins on the PBA axis, and the number 12435 after the letter is extracted as the path sorting order. It can be seen that there is only one misalignment between 12435 and reference sequence 12345, which is only 4 and 3, already very close to the reference sequence. Then, when the PBA calculation is performed, after the three paths of the prediction time margins A1, A2, and A4 are recalculated, their values are all smaller than the PBA time margin B1 corresponding to the prediction time margin A1. Then comparing the worst PBA time margin B1 with the next predicted time margin A3 at the moment, and finding that A3 is larger than B1, the worst PBA time margin, namely B1, is considered to be found. Therefore, only 3 paths are searched by taking the prediction time margin as input, the worst PBA time margin is found by recalculating the corresponding 3 prediction time margins, the prediction time margins A3 and A5 are not recalculated (indicated by dotted lines), the number of the paths is reduced by 2 compared with the case of taking the GBA time margin sequence as input, and the consumed resources are reduced. If A1-A5 are the worst 5 PBA time margins, then if a second PBA time margin A2 and a third PBA time margin A3 are further searched, the same can be obtained, 6 paths need to be searched when the GBA time margin sequence is used as input, and 5 paths need to be calculated when the predicted time margin is used as input, the latter is one less than the former, and the same plays a role in reducing resource consumption.
It should be noted that although the predicted time margin sequence predicted by the model in this embodiment may not bring about reduction of the number of search paths when being used as input of the PBA algorithm, the number of search paths required when the predicted time margin sequence is used as input is absolutely no more than the number of search paths required when the GBA time margin sequence is used as input, that is, the effect brought by the processing manner of this embodiment is greater than or equal to that of the conventional manner. Because the sequence of the predicted time margin sequences obtained by model prediction is closer to the real sequence of the PBA time margin, the search path algorithm is more likely to benefit from the real sequence, and the sequence algorithm cannot be dragged to slow.
In summary, when the prediction time margin sequence is used as an input to perform the PBA calculation in the exhaustive mode in the present embodiment, a gain is almost certainly brought compared with the prior art. Since the number of paths in a large integrated circuit design is many thousands, and many times the PBA exhaustive model needs to find a significant number of paths, the number of paths traversed by the search algorithm will be a significant number. Then the improvement in the temporal margin ordering of the input PBA algorithm may span a large interval in the series of paths. For example, the time margin for ordering 10 on the GBA axis may be 1000 on the true PBA axis, and if the predicted ordering is increased to 90 after model prediction, the increase is huge. Spanning such large intervals, which almost certainly results in a reduction in the number of required search paths, such a large improvement is widespread across a considerable number of time margins, even if a certain sequence of prediction time margins does not reduce the number of required search paths, there is a high probability that the number of required search paths will be reduced in some ordering improvement at a certain location. In summary, compared with the prior art, the input sorting for improving the PBA exhaustive mode only brings positive effects to the search algorithm, but never brings negative effects, and is a beneficial and harmless method.
Optionally, in step S103, determining a target number of target paths from the multiple paths according to the target time margin sequence may include: and sequentially selecting target time margins with target quantity according to the target time margin sequence of each path in the target time margin sequence, and determining the path corresponding to each selected target time margin as a target path.
Taking the target time margin sequence obtained in fig. 5 as an example, assuming that the target number is 3, B1, B2, and B3 are sequentially ranked as the target time margin sequence of the worst 3 paths according to the ranking of the time margins in the target time margin sequence, and since B1, B2, and B3 are respectively corresponding to paths A1, A2, and A3, it is determined that the target paths are respectively A1, A2, and A3.
And assuming that the target number is 4, B1, B2, B3, and B4 are respectively sequentially ranked as the target time margin sequence of the worst 4 paths according to the ranking of the time margins in the target time margin sequence, and since B1, B2, B3, and B4 are respectively corresponding to paths A1, A2, A3, and A4, it is determined that the target paths are respectively A1, A2, A3, and A4.
In summary, according to the integrated circuit timing prediction method provided by this embodiment, a time margin prediction is performed on a path in a target integrated circuit by using a pre-trained timing prediction model to obtain a predicted time margin sequence corresponding to the target integrated circuit, and since the timing prediction model is obtained by training a sample diagram structure, sample diagram feature information, and a real timing of the sample integrated circuit based on the sample diagram structure and the sample diagram feature information, information represented by the sample diagram structure and the sample diagram feature information is more detailed and abundant.
Specific implementation processes and technical effects of apparatuses, devices, storage media and the like for executing the integrated circuit timing prediction method provided by the present application are described below, and are not described again below.
Fig. 7 is a schematic diagram of an integrated circuit timing prediction apparatus according to an embodiment of the present application, where functions implemented by the integrated circuit timing prediction apparatus correspond to steps executed by the foregoing method. The apparatus may be understood as a server or a processor of the server for executing the method, and may also be understood as a component which is independent of the server or the processor and implements the functions of the application under the control of the server, as shown in fig. 7, the apparatus may include: a generating module 710, a calculating module 720 and a determining module 730;
a generating module 710, configured to perform time margin prediction on multiple paths included in a target integrated circuit by using a pre-trained timing prediction model, and generate a prediction time margin sequence corresponding to the target integrated circuit; the target integrated circuit comprises a plurality of paths formed from a circuit starting point to a circuit terminal point; the prediction time margins of all paths in the prediction time margin sequence are sequentially arranged according to the value; the time sequence prediction model is obtained by training according to the sample graph structure of the sample integrated circuit, the sample graph characteristic information and the real time sequence of the sample integrated circuit;
a calculating module 720, configured to perform path-based timing analysis and calculation according to the predicted time margin sequence to obtain a target time margin sequence corresponding to the target integrated circuit;
a determining module 730, configured to determine a target number of target paths from the multiple paths according to the target time margin sequence.
Optionally, the sample graph structure of the sample integrated circuit is obtained by converting the circuit structure of the sample integrated circuit, the sample graph structure includes nodes and node connecting lines, the nodes are used for representing pins of each device in the sample integrated circuit, and the node connecting lines are used for representing the connection relationship between the pins;
a generating module 710, specifically configured to convert a circuit structure of a target integrated circuit to obtain a graph structure of the target integrated circuit, where the graph structure of the target integrated circuit includes nodes and connecting lines;
acquiring graph characteristic information of a target integrated circuit according to a graph structure of the target integrated circuit;
and inputting the graph characteristic information into a time sequence prediction model to obtain a prediction time margin sequence corresponding to the target integrated circuit.
Optionally, the calculating module 720 is specifically configured to use the predicted time margin sequence as input information of a path-based time sequence analysis algorithm, and perform time sequence analysis calculation through the path-based time sequence analysis algorithm to obtain a target time margin sequence.
Optionally, the calculating module 720 is specifically configured to determine a current path to be analyzed according to the predicted time margin sequence;
determining a target time margin of the current path to be analyzed, and taking the target time margin of the current path to be analyzed as a current time margin threshold value;
sequentially traversing paths behind the current path to be analyzed, determining a new current path to be analyzed, calculating and obtaining a target time margin of the new current path to be analyzed, and updating a current time margin threshold according to the target time margin of the new current path to be analyzed to obtain a new current time margin threshold;
and circularly executing until a preset condition is met, stopping calculation, and arranging the target time margins of all paths obtained by calculation at present according to the value to obtain a target time margin sequence corresponding to the target integrated circuit.
Optionally, the calculating module 720 is specifically configured to use a path with the smallest predicted time margin in the predicted time margin sequence as the current path to be analyzed.
Optionally, the calculating module 720 is specifically configured to take a next path of the current path to be analyzed as a new current path to be analyzed according to the predicted time margin sequence;
if the predicted time margin of the new current path to be analyzed is smaller than the current time margin threshold, calculating and obtaining the target time margin of the new current path to be analyzed;
and if the target time margin of the new current path to be analyzed is smaller than the current time margin threshold, taking the target time margin of the new current path to be analyzed as the new current time margin threshold.
Optionally, the calculating module 720 is specifically configured to stop calculating if the predicted time margin of the current path to be analyzed is greater than the current time margin threshold and the number of the currently calculated and acquired target paths meets the target number.
Optionally, the determining module 730 is specifically configured to select target time margins of a target number in sequence according to the target time margin sequence of each path in the target time margin sequence, and determine a path corresponding to each selected target time margin as a target path.
The above-mentioned apparatus is used for executing the method provided by the foregoing embodiment, and the implementation principle and technical effect are similar, which are not described herein again.
These above modules may be one or more integrated circuits configured to implement the above methods, such as: one or more Application Specific Integrated Circuits (ASICs), or one or more microprocessors (DSPs), or one or more Field Programmable Gate Arrays (FPGAs), among others. For another example, when one of the above modules is implemented in the form of a Processing element scheduler code, the Processing element may be a general-purpose processor, such as a Central Processing Unit (CPU) or other processor capable of calling program code. For another example, these modules may be integrated together and implemented in the form of a system-on-a-chip (SOC).
The modules may be connected or in communication with each other via a wired or wireless connection. The wired connection may include a metal cable, an optical cable, a hybrid cable, etc., or any combination thereof. The wireless connection may include a connection via a LAN, WAN, bluetooth, zigBee, NFC, or the like, or any combination thereof. Two or more modules may be combined into a single module, and any one module may be divided into two or more units. It can be clearly understood by those skilled in the art that, for convenience and brevity of description, the specific working processes of the system and the apparatus described above may refer to corresponding processes in the method embodiments, and are not described in detail in this application.
Fig. 8 is a schematic structural diagram of an electronic device according to an embodiment of the present application, where the electronic device may be a computing device with a data processing function.
The apparatus may include: a processor 801, a storage medium 802.
The storage medium 802 is used for storing a program, and the processor 801 calls the program stored in the storage medium 802 to execute the above-described method embodiments. The specific implementation and technical effects are similar, and are not described herein again.
The storage medium 802 stores therein program code that, when executed by the processor 801, causes the processor 801 to perform various steps in methods according to various exemplary embodiments of the present application described in the "exemplary methods" section above in this specification.
The Processor 801 may be a general-purpose Processor, such as a Central Processing Unit (CPU), a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other Programmable logic device, discrete Gate or transistor logic device, discrete hardware components, and may implement or execute the methods, steps, and logic blocks disclosed in the embodiments of the present Application. A general purpose processor may be a microprocessor or any conventional processor or the like. The steps of the method disclosed in connection with the embodiments of the present application may be directly implemented by a hardware processor, or implemented by a combination of hardware and software modules in a processor.
Storage medium 802, which is a non-volatile computer-readable storage medium, may be used to store non-volatile software programs, non-volatile computer-executable programs, and modules. The storage medium may include at least one type of storage medium, and may include, for example, a flash Memory, a hard disk, a multimedia card, a card-type storage medium, a Random Access Memory (RAM), a Static Random Access Memory (SRAM), a Programmable Read Only Memory (PROM), a Read Only Memory (ROM), a charge Erasable Programmable Read-Only Memory (EEPROM), a magnetic storage medium, a magnetic disk, an optical disk, and so on. A storage medium is any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer, but is not limited to such. The storage medium 802 in the embodiments of the present application may also be a circuit or any other device capable of implementing a storage function for storing program instructions and/or data.
Optionally, the present application also provides a program product, such as a computer readable storage medium, comprising a program which, when being executed by a processor, is adapted to carry out the above-mentioned method embodiments.
In the several embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the units is only one logical division, and other divisions may be realized in practice, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, or in a form of hardware plus a software functional unit.
The integrated unit implemented in the form of a software functional unit may be stored in a computer readable storage medium. The software functional unit is stored in a storage medium and includes several instructions for enabling a computer device (which may be a personal computer, a server, or a network device) or a processor (processor) to perform some steps of the methods according to the embodiments of the present application. And the aforementioned storage medium includes: a U disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.

Claims (11)

1. A method for integrated circuit timing prediction, comprising:
adopting a pre-trained time sequence prediction model to predict time margins of a plurality of paths contained in a target integrated circuit, and generating a prediction time margin sequence corresponding to the target integrated circuit; the target integrated circuit comprises a plurality of paths formed from a circuit starting point to a circuit terminal point; the prediction time margins of all paths in the prediction time margin sequence are sequentially arranged according to the value; the time sequence prediction model is obtained by training according to the sample graph structure of the sample integrated circuit, the sample graph characteristic information and the real time sequence of the sample integrated circuit;
according to the predicted time margin sequence, performing path-based time sequence analysis calculation to obtain a target time margin sequence corresponding to the target integrated circuit;
and determining a target number of target paths from the plurality of paths according to the target time margin sequence.
2. The method of claim 1, wherein the sample graph structure of the sample integrated circuit is obtained by converting a circuit structure of the sample integrated circuit, and the sample graph structure comprises nodes and node connecting lines, wherein the nodes are used for representing pins of each device in the sample integrated circuit, and the node connecting lines are used for representing connection relations among the pins;
the predicting the time margin of a plurality of paths contained in a target integrated circuit by adopting a pre-trained time sequence predicting model to generate a predicting time margin sequence corresponding to the target integrated circuit comprises the following steps:
converting the circuit structure of the target integrated circuit to obtain a graph structure of the target integrated circuit, wherein the graph structure of the target integrated circuit comprises nodes and connecting lines;
acquiring graph feature information of the target integrated circuit according to the graph structure of the target integrated circuit;
and inputting the graph characteristic information into the time sequence prediction model to obtain a prediction time margin sequence corresponding to the target integrated circuit.
3. The method of claim 1, wherein performing a path-based timing analysis calculation based on the predicted time margin sequence to obtain a target time margin sequence corresponding to the target integrated circuit comprises:
and taking the predicted time margin sequence as input information of a path-based time sequence analysis algorithm, and performing time sequence analysis calculation through the path-based time sequence analysis algorithm to obtain the target time margin sequence.
4. The method of claim 3, wherein performing timing analysis calculations by the path-based timing analysis algorithm to obtain the target sequence of time margins comprises:
determining a current path to be analyzed according to the prediction time margin sequence;
determining a target time margin of the current path to be analyzed, and taking the target time margin of the current path to be analyzed as a current time margin threshold;
sequentially traversing paths behind the current path to be analyzed, determining a new current path to be analyzed, calculating and obtaining a target time margin of the new current path to be analyzed, and updating a current time margin threshold according to the target time margin of the new current path to be analyzed to obtain a new current time margin threshold;
and circularly executing until a preset condition is met, stopping calculation, and arranging the target time margins of all paths obtained by calculation at present according to the value to obtain a target time margin sequence corresponding to the target integrated circuit.
5. The method of claim 4, wherein determining the current path to be analyzed according to the sequence of predicted time margins comprises:
and taking the path with the minimum prediction time margin in the prediction time margin sequence as the current path to be analyzed.
6. The method of claim 4, wherein determining a new current path to be analyzed, calculating a target time margin for obtaining the new current path to be analyzed, and updating the current time margin threshold according to the target time margin for the new current path to be analyzed to obtain a new current time margin threshold, comprises:
according to the prediction time margin sequence, taking the next path of the current path to be analyzed as a new current path to be analyzed;
if the predicted time margin of the new path to be analyzed is smaller than the current time margin threshold, calculating and obtaining a target time margin of the new path to be analyzed;
and if the target time margin of the new path to be analyzed is smaller than the current time margin threshold, taking the target time margin of the new path to be analyzed as a new current time margin threshold.
7. The method according to claim 6, wherein the loop is executed until a preset condition is met, and the calculation is stopped, and the method comprises the following steps:
and if the predicted time margin of the current path to be analyzed is larger than the current time margin threshold value and the number of the current calculated and acquired target paths meets the target number, stopping calculation.
8. The method of claim 1, wherein determining a target number of target paths from the plurality of paths according to the target sequence of time margins comprises:
and sequentially selecting target time margins with target quantity according to the target time margin sequence of each path in the target time margin sequence, and determining the path corresponding to each selected target time margin as a target path.
9. An integrated circuit timing prediction apparatus, comprising: the device comprises a generating module, a calculating module and a determining module;
the generating module is used for predicting the time margins of a plurality of paths contained in a target integrated circuit by adopting a pre-trained time sequence prediction model and generating a prediction time margin sequence corresponding to the target integrated circuit; the target integrated circuit comprises a plurality of paths formed from a circuit starting point to a circuit terminal point; the prediction time margins of all paths in the prediction time margin sequence are sequentially arranged according to the value; the time sequence prediction model is obtained by training according to the sample graph structure of the sample integrated circuit, the sample graph characteristic information and the real time sequence of the sample integrated circuit;
the calculation module is used for performing path-based time sequence analysis calculation according to the predicted time margin sequence to obtain a target time margin sequence corresponding to the target integrated circuit;
the determining module is configured to determine a target number of target paths from the plurality of paths according to the target time margin sequence.
10. An electronic device, comprising: a processor, a storage medium and a bus, the storage medium storing program instructions executable by the processor, the processor and the storage medium communicating via the bus when the electronic device is running, the processor executing the program instructions to perform the steps of the integrated circuit timing prediction method according to any one of claims 1 to 8.
11. A computer-readable storage medium, having stored thereon a computer program for performing, when executed by a processor, the steps of the integrated circuit timing prediction method according to any one of claims 1 to 8.
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Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160070844A1 (en) * 2014-09-08 2016-03-10 Synopsys Inc. Selectively reducing graph based analysis pessimism
US9875333B1 (en) * 2016-01-19 2018-01-23 Cadence Design Systems, Inc. Comprehensive path based analysis process
CN108804734A (en) * 2017-04-28 2018-11-13 三星电子株式会社 The method and its system of integrated design circuit
US10534878B1 (en) * 2017-10-25 2020-01-14 Avatar Integrated Systems, Inc. Circuit place and route optimization based on path-based timing analysis
US10776547B1 (en) * 2019-10-14 2020-09-15 Cadence Design Systems, Inc. Infinite-depth path-based analysis of operational timing for circuit design
CN112183003A (en) * 2020-11-30 2021-01-05 浙江大学 Step-by-step multi-threshold voltage unit distribution method based on time sequence margin and time sequence path
CN112214097A (en) * 2020-10-20 2021-01-12 天津飞腾信息技术有限公司 Method, device, equipment and storage medium for reducing low threshold unit
CN113486612A (en) * 2021-06-29 2021-10-08 海光信息技术股份有限公司 Integrated circuit design method, device, electronic equipment and readable storage medium
CN114186519A (en) * 2021-11-17 2022-03-15 上海安路信息科技股份有限公司 Time sequence bottleneck probing method and device, terminal equipment and storage medium
CN114967807A (en) * 2022-03-28 2022-08-30 清华大学 Timing detection circuit and adaptive voltage regulation circuit

Patent Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160070844A1 (en) * 2014-09-08 2016-03-10 Synopsys Inc. Selectively reducing graph based analysis pessimism
US9875333B1 (en) * 2016-01-19 2018-01-23 Cadence Design Systems, Inc. Comprehensive path based analysis process
CN108804734A (en) * 2017-04-28 2018-11-13 三星电子株式会社 The method and its system of integrated design circuit
US10534878B1 (en) * 2017-10-25 2020-01-14 Avatar Integrated Systems, Inc. Circuit place and route optimization based on path-based timing analysis
US10776547B1 (en) * 2019-10-14 2020-09-15 Cadence Design Systems, Inc. Infinite-depth path-based analysis of operational timing for circuit design
CN112214097A (en) * 2020-10-20 2021-01-12 天津飞腾信息技术有限公司 Method, device, equipment and storage medium for reducing low threshold unit
CN112183003A (en) * 2020-11-30 2021-01-05 浙江大学 Step-by-step multi-threshold voltage unit distribution method based on time sequence margin and time sequence path
WO2022110815A1 (en) * 2020-11-30 2022-06-02 浙江大学 Step-by-step multi-threshold voltage unit allocation method based on timing margin and timing path
CN113486612A (en) * 2021-06-29 2021-10-08 海光信息技术股份有限公司 Integrated circuit design method, device, electronic equipment and readable storage medium
CN114186519A (en) * 2021-11-17 2022-03-15 上海安路信息科技股份有限公司 Time sequence bottleneck probing method and device, terminal equipment and storage medium
CN114967807A (en) * 2022-03-28 2022-08-30 清华大学 Timing detection circuit and adaptive voltage regulation circuit

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