WO2022109999A1 - 一种电容式指纹识别系统及电子设备及指纹识别方法 - Google Patents

一种电容式指纹识别系统及电子设备及指纹识别方法 Download PDF

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Publication number
WO2022109999A1
WO2022109999A1 PCT/CN2020/132173 CN2020132173W WO2022109999A1 WO 2022109999 A1 WO2022109999 A1 WO 2022109999A1 CN 2020132173 W CN2020132173 W CN 2020132173W WO 2022109999 A1 WO2022109999 A1 WO 2022109999A1
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Prior art keywords
switch
node
voltage
signal
fingerprint identification
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PCT/CN2020/132173
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English (en)
French (fr)
Inventor
蒋新喜
程珍娟
孙天奇
张靖恺
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敦泰电子（深圳）有限公司
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Priority to PCT/CN2020/132173 priority Critical patent/WO2022109999A1/zh
Priority to CN202080097906.3A priority patent/CN115244590A/zh
Publication of WO2022109999A1 publication Critical patent/WO2022109999A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F18/00—Pattern recognition

Definitions

  • the invention relates to the technical field of fingerprint identification, and more particularly, to a capacitive fingerprint identification system, electronic equipment and a fingerprint identification method.
  • Fingerprint Identification Due to its high security and ease of operation, the fingerprint identification system has become the mainstream identification system used in today's electronic equipment. However, the existing fingerprint identification system can only have a single working mode of fingerprint identification.
  • the present application provides a capacitive fingerprint identification system, electronic equipment and fingerprint identification method, and the solutions are as follows:
  • a capacitive fingerprint identification system comprising:
  • the integrating circuit includes: an operational amplifier with a positive-phase input terminal, a negative-phase input terminal, a ground terminal and an output terminal; a feedback branch connected between the negative-phase input terminal and the output terminal; The non-inverting input terminal of the operational amplifier inputs a reference voltage, and the output terminal voltage of the integrating circuit is used for fingerprint identification;
  • a fingerprint information collection circuit connected to the negative-phase input terminal, inputting a reference voltage or a first voltage signal through a switch, and collecting fingerprint information
  • the floating signal generating circuit is connected to the ground terminal for providing the ground terminal with a floating signal VSS adapted to the working mode based on the second voltage signal and the third voltage signal, Selecting and outputting the floating signal as a first ground voltage with a constant amplitude or a second ground voltage with a periodic change in amplitude;
  • the working modes of the capacitive fingerprint identification system include: passive fingerprint detection mode, active fingerprint detection mode, and active combined with passive fingerprint detection mode;
  • the floating signal generating circuit is configured to provide the first ground voltage for the ground terminal
  • the floating signal generating circuit is used for providing the second ground voltage to the ground terminal.
  • the floating signal generating circuit includes:
  • a first switch connecting the port for inputting the third voltage signal with the first node
  • the first node is grounded through the second switch
  • a third switch, and the second node is grounded through the third switch.
  • the first switch is a first transistor
  • the second switch is a second transistor
  • the third switch is a third transistor
  • the gate of the first transistor is connected to the first switch control signal, the source is connected to the third voltage signal, and the drain is connected to the first node;
  • the gate of the second transistor is connected to the second switch control signal, the drain is connected to the first node, and the source is grounded;
  • the gate of the third transistor is connected to the third switch control signal, the source is connected to the second node, and the drain is grounded.
  • the first transistor is a PMOS
  • the second transistor and the third transistor are both NMOS.
  • the above capacitive fingerprint identification system it also includes:
  • the power management unit has a first low dropout regulator, the first low dropout regulator is respectively connected with the fingerprint information acquisition circuit and the floating signal generation circuit to provide the reference voltage and the first voltage signal.
  • the above capacitive fingerprint identification system further comprises: an input and output port and a second low dropout regulator for providing the input and output port with a working voltage;
  • the second low dropout regulator is configured to provide a working voltage for the input and output ports based on the third voltage signal.
  • the fingerprint information collection circuit includes:
  • the port inputting the first voltage signal is connected to the third node through the fifth switch;
  • the detection electrode is connected to the third node and is used for forming a detection capacitance based on the touch operation.
  • the fingerprint information collection circuit further includes:
  • a seventh switch the port inputting the first voltage signal and the fourth node are connected through the seventh switch;
  • the port inputting the reference voltage is connected to the fourth node through the eighth switch
  • the port inputting the first voltage signal is connected to the fifth node through the ninth switch;
  • the port inputting the floating signal is connected to the fifth node through the tenth switch;
  • the fourth node is connected to the third node through a second capacitor, and the fifth node is connected to the third node through a third capacitor.
  • the feedback branch includes:
  • a first reset switch connected between the negative phase input terminal and the output terminal.
  • the feedback capacitor has a first pole plate and a second pole plate
  • the first pole plate is connected to the negative-phase input terminal through a second reset switch, and is connected to a port for inputting a fourth voltage signal through a third reset switch;
  • the second pole plate is connected to the output terminal through a fourth reset switch, and is connected to the port for inputting the first voltage signal through a fifth reset switch.
  • the working modes of the capacitive fingerprint identification system include: passive fingerprint detection mode, active fingerprint detection mode, and active combined with passive fingerprint detection mode;
  • the floating signal generating circuit is configured to provide the first ground voltage for the ground terminal
  • the floating signal generating circuit is used for providing the second ground voltage to the ground terminal.
  • the first ground voltage is 0 potential
  • the second ground voltage is a square wave signal that periodically changes between a zero potential and a preset negative potential.
  • the present invention also provides an electronic device, the capacitive fingerprint identification system described in any one of the above.
  • the present invention also provides a fingerprint identification method of a capacitive fingerprint identification system, comprising:
  • the working mode of the capacitive fingerprint identification system is selected;
  • the working modes of the capacitive fingerprint identification system include: a passive fingerprint detection mode, an active fingerprint detection mode, and an active combined passive fingerprint detection mode;
  • a second ground voltage whose amplitude changes periodically is provided.
  • the capacitive fingerprint identification system includes: an integrating circuit, and the integrating circuit includes: an operational amplifier with a positive phase an input terminal, a negative-phase input terminal, a ground terminal and an output terminal; a feedback branch connected between the negative-phase input terminal and the output terminal; a fingerprint information acquisition circuit, connected to the negative-phase input terminal, for inputting a reference voltage and a first voltage signal, and collecting fingerprint information; a floating signal generating circuit, the floating signal generating circuit is connected to the ground terminal, and is used for generating the signal based on the second voltage signal and the third voltage signal for the The ground terminal provides a floating signal adapted to the working mode, and the floating signal is selected to be output as a first ground voltage with a constant amplitude or a second ground voltage with a periodic change in amplitude.
  • the floating signal generating circuit can provide the ground terminal with a floating signal suitable for the working mode, and the floating signal can be selected to output the first ground voltage with constant amplitude or the amplitude period.
  • the second ground voltage that varies in nature can make the capacitive fingerprint identification system work in different modes based on requirements.
  • Fig. 1 is a floating signal generating circuit of two chips
  • FIG. 2 is a schematic structural diagram of a single chip floating signal generating circuit
  • FIG. 3 is a circuit diagram of a negative pressure charge pump
  • FIG. 4 is a circuit diagram of a capacitive fingerprint identification system according to an embodiment of the present invention.
  • FIG. 5 is a schematic structural diagram of a floating signal generating circuit according to an embodiment of the present invention.
  • FIG. 6 is a schematic structural diagram of another floating signal generating circuit provided by an embodiment of the present invention.
  • Fig. 7 is the timing chart of the switch control signal in the floating signal generating circuit shown in Fig. 6;
  • FIG. 8 is a circuit diagram of a power supply system provided by an embodiment of the present invention.
  • FIG. 9 is a schematic structural diagram of a metal layer layout of a fingerprint detection electrode according to an embodiment of the present invention.
  • FIG. 10 is a circuit diagram of another capacitive fingerprint identification system provided by an embodiment of the present invention.
  • FIG. 11 is a schematic structural diagram of an electronic device according to an embodiment of the present invention.
  • the capacitive fingerprint identification scheme is to judge the fingerprint information of the finger by detecting the capacitance formed by the peaks and valleys in the fingerprint of the finger and the sensing electrodes of the chip.
  • the capacitive fingerprint identification scheme mainly includes: passive identification scheme, active identification scheme, and active and passive identification scheme.
  • Fingerprint detection circuit has three modes: active detection circuit, passive detection circuit and hybrid detection circuit, wherein the hybrid detection circuit is composed of active part circuit and passive part circuit.
  • the active detection circuit loads the ground signal of the detection circuit by adding the driving signal, that is, adding the driving signal to the finger, and the wave valley of the finger fingerprint collects different charges on the capacitance formed by the sensing electrode inside the chip, and integrates it into the output of the integrator.
  • the size of the capacitor is judged by the size of the voltage, so as to reproduce the peaks and valleys of the fingerprint.
  • the passive working principle is different. It uses the influence of the peaks and valleys of the fingerprint on the proportion of the charge distribution of the upper and lower electrodes of the internal capacitance of the chip when the finger is pressed on the surface of the chip to reproduce the fingerprint without adding an additional driving source.
  • the current capacitive fingerprint detection circuit has the following defects: when a passive fingerprint detection circuit with a simple circuit is used, it is easily affected by parasitic capacitance, the dispersion is large, and the data is easily saturated; when the active fingerprint detection circuit with a complex circuit is used, the data consistency is good, but It is generally composed of two chips, and the cost is high; the existing fingerprint detection circuit implemented by a single chip has many off-chip devices, which has requirements on the process, and the cost is still very high.
  • FIG. 1 is an existing active capacitive fingerprint circuit, which uses two chips and has a high cost.
  • the active capacitive fingerprint circuit includes a driving control chip 11 and a fingerprint sensing chip 12, and realizes floating design and active fingerprint collection.
  • the driving control chip 11 provides the VTX level of the fingerprint sensing chip 12 and the required power supply VDD.
  • the fingerprint sensing chip 12 provides the TX signal for the driving control chip, and the fingerprint sensing chip 12 outputs the voltage signal VSS based on the input signal.
  • the drive control chip 11 is connected to the master device 13 through an SPI (Serial Peripheral Interface).
  • the power supply terminal of the driving control chip 11 inputs the voltage signal VDD_SUPPLY, and the ground terminal is grounded.
  • the fingerprint sensing chip 12 outputs a voltage signal VSS in the form of a square wave, the high level of which is VTX and the low level is 0.
  • circuit designs can realize the active identification scheme of a single chip, the circuit design is relatively complex, requiring more off-chip devices, large circuit area, and high process requirements, so the cost improvement is limited, and the manufacturing cost is still high. .
  • FIG. 2 is a schematic structural diagram of a single chip floating signal generating circuit in the prior art.
  • the floating signal generating circuit includes a switch K3, a switch K4 and a switch K5, and one end of the switch K3 inputs a voltage signal VDD_SUPPLY, the other end is connected to the node Q1, one end of the switch K4 is grounded to GND, the other end is connected to the node Q2, a capacitor C1 is connected between the node Q1 and the node Q2, one end of the switch K5 is connected to the negative pressure charge pump, and the other end is connected to the node Q2.
  • Node Q1 provides voltage signal VDD
  • node Q2 provides voltage signal VSS.
  • the fingerprint detection circuit module is connected to the node Q1 and the node Q2 respectively.
  • the node Q1 is connected to the voltage signal VDD_SUPPLY through the switch K3, and the node Q2 is switched between 0 potential and the voltage signal -VTX output by the negative charge pump through the switch K4 and the switch K5.
  • the voltage signal VSS in the form of a square wave can be obtained, and its high level is 0 and its low level is -VTX.
  • the node Q1 is connected to the voltage signal VDD_SUPPLY through the switch K3, and the fingerprint detection circuit module in the fingerprint detection chip is powered by the voltage signal VDD_SUPPLY. At the same time, the voltage signal VDD_SUPPLY supplies power to charge the capacitor C1.
  • the negative voltage charge pump By alternately opening and closing the switch K3, the switch K4 and the switch K5, the periodic change of the voltage signal VSS between 0 and -VTX is realized, and the floating function of the voltage signal VSS is realized.
  • the negative voltage charge pump also needs to provide the voltage signal -VTX required by the voltage signal VSS.
  • the circuit structure of the negative voltage charge pump commonly used in the prior art is shown in FIG. 3 .
  • FIG. 3 is a circuit diagram of a negative pressure charge pump, and the shown negative pressure charge pump includes a switch K6, a switch K7, a switch K8, a switch K9, a capacitor C2 and a capacitor C3.
  • One end of the switch K6 is grounded to GND, and the other end is connected to the node Q3; one end of the switch K7 is connected to the node Q3, and the other end is connected to the voltage signal VDD_SUPPLY; one end of the switch K8 is connected to the node Q4, and the other end is connected to the node Q5; one end of the switch K9 is connected to the node Q4 , the other end is grounded to GND; one plate of capacitor C2 is connected to node Q3, and the other plate is connected to node Q4; one plate of capacitor C3 is connected to node Q5, and the other plate is grounded to GND.
  • the node Q5 outputs the voltage signal -VTX.
  • the negative voltage charge pump shown in Figure 3 requires four switches and two capacitors, and requires a larger circuit area and a logic circuit with a higher load to control the current.
  • the start-up time is related to the size of the capacitor C2 and the capacitor C3 and the size of the start-up current, which will affect the response speed of the system.
  • the technical solutions of the embodiments of the present invention provide a capacitive fingerprint identification system, which adopts a single chip to integrate a passive identification scheme, an active identification scheme, and an active and passive identification scheme, and has three working modes. : Passive fingerprint detection mode, active fingerprint detection mode, and active combined with passive fingerprint detection mode.
  • the technical solution of the embodiment of the present invention requires a simple process, few off-chip devices, low cost, and a working mode that can be flexibly selected according to requirements.
  • FIG. 4 is a circuit diagram of a capacitive fingerprint identification system provided by an embodiment of the present invention, including:
  • Integrating circuit 03 the integrating circuit 03 includes: an operational amplifier OP, which has a positive-phase input terminal, a negative-phase input terminal, a ground terminal, and an output terminal VOUT; an operational amplifier connected between the negative-phase input terminal and the output terminal feedback branch 031;
  • Fingerprint information collection circuit 04 the fingerprint information collection circuit 04 is connected to the negative-phase input terminal for inputting the reference voltage VREF and the first voltage signal VDDA, and collects fingerprint information; the positive-phase input terminal is used for inputting reference voltage VREF.
  • a floating signal generating circuit 05 the floating signal generating circuit 05 is connected to the ground terminal, and is used for providing the ground terminal with a floating signal suitable for the working mode based on the second voltage signal VDD and the third voltage signal VDD_SUPPLY
  • the ground signal VSS is selected to output the floating signal VSS as a first ground voltage with a constant amplitude or a second ground voltage with a periodically varying amplitude.
  • the first ground voltage may be a ground signal GND, which is a zero potential with a fixed amplitude; the second ground voltage may be a square wave signal.
  • the floating signal generation circuit 05 can select and output the floating signal VSS as the first ground voltage or the second ground voltage based on the working mode, so that the capacitive fingerprint identification system In passive fingerprint detection mode, active fingerprint detection mode, and active combined with passive fingerprint detection mode.
  • the system architecture is simple, the fingerprint detection chip area is small, and the off-chip devices are few. Three fingerprint detection modes can be flexibly selected based on requirements.
  • FIG. 5 is a schematic structural diagram of a floating signal generating circuit according to an embodiment of the present invention.
  • the floating signal generating circuit 05 includes:
  • first capacitor C01 one plate is connected to the first node N1, and the first node N1 is used to output the second voltage signal VDD; the other plate is connected to the second node N2, and the second node N2 is used to output the floating signal VSS;
  • the first switch K01 is connected to the port inputting the third voltage signal VDD_SUPPLY and the first node N1;
  • the first node N1 is grounded to GND through the second switch K02;
  • the third switch K03, the second node N2 is grounded to GND through the third switch K03.
  • the first node N1 and the second node N2 are connected to the fingerprint detection circuit module in the fingerprint detection chip, and the fingerprint detection circuit module includes a power supply system, a signal processing part circuit, the above-mentioned integration circuit 03 and a fingerprint information collection circuit 04.
  • the first switch K01 and the third switch K03 are closed and the second switch K02 is open, the first node N1 is connected to the port inputting the third voltage signal VDD_SUPPLY, the second node N2 is grounded, and the floating signal VSS is equal to the ground signal GND.
  • the third voltage signal VDD_SUPPLY provides current for the fingerprint detection circuit module through the first switch K01, and at the same time, the third voltage signal VDD_SUPPLY charges the first capacitor C01.
  • VSS -VDD_SUPPLY
  • the third voltage signal VDD_SUPPLY is the system power supply
  • the floating signal VSS becomes the negative value of the third voltage signal VDD_SUPPLY, that is, the negative voltage of the power supply.
  • the voltage change ⁇ V C across the first capacitor C01 is:
  • I is the discharge current of the first capacitor C01
  • t is the negative pressure working time of the VSS. Based on I and t and the size of the first capacitor C01, the voltage change ⁇ VC across the first capacitor C01 can be calculated.
  • the periodic change of the floating signal VSS between 0 potential and -VDD_SUPPLY is realized, the current and cycle time are well controlled, and the setting is selected.
  • the first capacitor C1 can satisfy that during the period when the current is supplied by the first capacitor C01, the voltage reduction amount does not affect the operation of the detection circuit module in the chip.
  • the floating signal generation circuit 05 shown in FIG. 5 uses three switches and one capacitor to select a ground voltage whose output amplitude is fixed at 0 potential, or a ground voltage whose output amplitude varies periodically between 0 and -VDD_SUPPLY , the circuit structure is simple. Through a single chip, three control schemes of working fingerprint identification working modes are realized, and the floating signal VSS and working mode can be flexibly selected according to the requirements.
  • the active fingerprint identification solution of the technical solution of the present invention uses a single chip to generate a floating signal VSS inside the chip.
  • the second ground voltage is set to change periodically between 0 and -VDD_SUPPLY to ensure reliability and reduce floating loads.
  • the floating signal generating circuit 05 has simple control logic and does not require additional circuits or off-chip devices.
  • the technical solution of the embodiment of the present invention realizes the design of the floating signal generation circuit 05 through a single chip, the circuit control method is simple, the area is small, the off-chip devices are few, the cost is low, and the fingerprint signal collection performance is good, the signal volume is large, and the consistent It has good performance and can penetrate cover plates of different thicknesses, and a level shift circuit is designed through a simple process to perform conversion between different voltage domains.
  • FIG. 6 is a schematic structural diagram of another floating signal generating circuit provided by an embodiment of the present invention.
  • the first switch K01 is a first transistor MP
  • the second switch K01 is a first transistor MP
  • the switch K02 is the second transistor MN1
  • the third switch K03 is the third transistor MN2.
  • the gate of the first transistor MP is connected to the first switch control signal TX1_P
  • the source is connected to the third voltage signal VDD_SUPPLY
  • the drain is connected to the first node N1.
  • the gate of the second transistor MN1 is connected to the second switch control signal TX1_N
  • the drain is connected to the first node N1, and the source is grounded to GND.
  • the gate of the third transistor MN2 is connected to the third switch control signal TX2, the source is connected to the second node N2, and the drain is grounded to GND.
  • the third voltage signal VDD_SUPPLY is provided by the external power supply of the fingerprint detection chip, and the second voltage signal VDD is the internal power supply of the fingerprint detection chip generated by the floating signal generating circuit 05 based on the third voltage signal VDD_SUPPLY.
  • the second voltage signal VDD is switched between VDD_SUPPLY and GND through the first transistor MP and the second transistor MN1.
  • the second node N2 is connected to or disconnected from GND through the third transistor MN2.
  • the first transistor MP is selected to be a PMOS
  • the second transistor MN1 and the third transistor MN2 are both NMOS.
  • the substrate of the PMOS and the substrate of the NMOS may be connected to their respective source terminals.
  • the floating signal generating circuit 05 can be realized by the first capacitor C01 and three MOSs, and the circuit structure is simple.
  • the implementation manner of the three transistors is not limited to that the first transistor MP is a PMOS, and the second transistor MN1 and the third transistor MN2 are both NMOS, which can be based on a switch control signal Set the three transistors as PMOS or NMOS.
  • the choice of the substrate potential of the transistor is not limited to zero for the PN junction.
  • FIG. 7 is a timing diagram of switch control signals in the floating signal generating circuit shown in FIG. 6 , and the three switch control signals are all square wave signals that change periodically.
  • the third switch control signal TX2 is switched from a high level to a low level
  • the first switch control signal TX1_P is switched from a low level to a high level
  • the first switch control signal TX1_P is switched from a low level
  • the second switch control signal TX1_N is switched from low level to high level
  • the third switch control signal TX2 is switched from low level to high level
  • the first switch control signal TX1_P is switched from high level Switch to low level
  • the second switch control signal TX1_N switches from high level to low level.
  • the output port of the second voltage signal VDD passes through the first transistor MP and the input The ports of the three-voltage signal VDD_SUPPLY are connected, and the second node N2 outputting the floating signal VSS is grounded to GND through the third transistor MN2.
  • FIG. 8 is a circuit diagram of a power supply system provided by an embodiment of the present invention.
  • the capacitive fingerprint identification system according to the embodiment of the present invention further includes: a power management unit PMU, the power supply
  • the management single PMU has a first low dropout regulator LDO, and the first low dropout regulator LDO is connected to the fingerprint information acquisition circuit 04, the integration circuit 03 and the floating signal generation circuit 05, respectively, so as to provide all the reference voltage VREF and the first voltage signal VDDA.
  • the port through which the single power management PMU outputs the first voltage signal VDDA may be set to be connected to the second node N2 through a capacitor C3.
  • the floating signal generating circuit 05 can output the second voltage signal VDD and the floating signal VSS based on the input third voltage signal VDD_SUPPLY.
  • the port of the single power management PMU outputting the first voltage signal VDDA is also connected with an analog circuit.
  • the analog circuit is powered by the first voltage signal VDDA generated by the first low dropout regulator LDO in the single power management PMU, and supplies power to the single power management PUM through the second voltage signal VDD.
  • the first node N1 is also connected with a digital circuit.
  • the digital circuit is directly powered by the second voltage signal VDD.
  • the capacitive fingerprint identification system further includes: an input and output port IO and a second low dropout regulator LDO_VDDIO that provides a working voltage for the input and output port IO; wherein the second low dropout regulator LDO_VDDIO is used for A working voltage VDDIO is provided for the input and output ports IO based on the third voltage signal VDD_SUPPLY.
  • the port of the second low dropout regulator LDO_VDDIO to output the voltage VDDIO can be set to be grounded to GND through the capacitor C4.
  • the second low dropout regulator LDO_VDDIO is powered by a third voltage signal VDD_SUPPLY provided by an external power supply.
  • the input and output ports IO are powered by the separately set second low dropout regulator LDO_VDDIO, so as to avoid adverse effects of the input and output ports IO power supply on the fingerprint identification result.
  • the fingerprint information collection circuit 04 includes: a fourth switch K04, the port inputting the reference voltage VREF and the third node N3 are connected to K04 through the fourth switch; a fifth switch K05, which is input to the The port of the first voltage signal VDDA and the third node N3 are connected through the fifth switch K05; the sixth switch K06, the third node N3 and the negative-phase input terminal are connected through the sixth switch K06; A detection electrode 01, which is connected to the third node N3, is used to form a detection capacitance Cf based on a touch operation.
  • the technical scheme of the present invention has a fingerprint detection mode, an active fingerprint detection mode, and an active combined passive fingerprint detection mode, and supports passive fingerprint detection, active fingerprint detection, and active combined passive fingerprint detection.
  • the fifth switch K05 is selected to be turned off, the fourth switch K04 and the sixth switch K06 are switched alternately, and the VSS is periodically switched between GND and -VDD_SUPPLY, which is an active fingerprint detection mode.
  • the technical solution of the present invention can support three fingerprint detection modes, which can be flexibly selected according to requirements.
  • the feedback branch 03 includes: a feedback capacitor CFB connected between the negative-phase input terminal and the output terminal; a feedback capacitor CFB connected between the negative-phase input terminal and the output terminal The first reset switch RST1.
  • FIG. 9 is a schematic structural diagram of a metal layer layout of a fingerprint detection electrode according to an embodiment of the present invention.
  • the capacitive fingerprint identification system according to the embodiment of the present invention includes a first metal layer AA and a second metal layer , the second metal layer includes a first part BB and a second part CC.
  • the first metal layer AA is close to the touch surface of the device relative to the second metal layer.
  • the side of the second metal layer away from the first metal layer AA is provided with a fingerprint detection switch circuit, the fingerprint detection switch circuit includes all switches in the capacitive fingerprint identification system according to the embodiment of the present invention, and the fingerprint is shielded by the second metal layer
  • the crosstalk of the switch circuit to the first metal layer AA is detected to ensure the accuracy of fingerprint identification.
  • the detection electrode 01 of the fingerprint detection sensing unit is located on the patterned first metal layer AA.
  • the first metal layer AA and the finger form a detection capacitor Cf.
  • the first metal layer AA and the first portion BB have a second capacitance C02.
  • Below the first part BB is the fingerprint detection control switch circuit, which prevents the fingerprint detection switch circuit from interfering with the detection capacitor Cf and prevents the detection switch circuit from affecting the fingerprint recognition result.
  • the second portion CC and the first metal layer AA have a third capacitance C03.
  • the first part BB is respectively connected to the first voltage signal VDDA and the reference voltage VREF through two parallel switches; the first metal layer AA is respectively connected to the first voltage signal VDDA and the reference voltage VREF through the two parallel switches; the second The part CC is respectively connected to the first voltage signal VDDA and the floating signal VSS through two switches connected in parallel.
  • FIG. 10 is a circuit diagram of another capacitive fingerprint identification system provided by an embodiment of the present invention.
  • the fingerprint information collection circuit further includes: a seventh switch K07, which is used to input the first The port of a voltage signal VDDA is connected to the fourth node N4 through the seventh switch K07; the eighth switch K08, the port inputting the reference voltage VREF and the fourth node N4 are connected through the eighth switch K08;
  • the ninth switch K09, the port inputting the first voltage signal VDDA and the fifth node N5 are connected through the ninth switch K09;
  • the tenth switch K10 the port inputting the floating signal VSS and the fifth node N5 are connected through the tenth switch K10 is connected;
  • the fourth node N4 is connected to the third node N3 through a second capacitor C02, and the fifth node N5 is connected to the third node N3 through a third capacitor C03.
  • the metal layer layout of the fingerprint information collection circuit 04 can be referred to as shown in FIG. 9 , which will not be repeated here.
  • the feedback capacitor CFB has a first pole plate and a second pole plate; the first pole plate is connected to the non-inverting input terminal through the second reset switch RST2, and The third reset switch RST3 is connected to the port for inputting the fourth voltage signal VDC_OS; the second plate is connected to the output terminal through the fourth reset switch RST4, and the first voltage is input to the fifth reset switch RST5 Port connection for signal VDDA.
  • the reference voltage VREF, the first voltage signal VDDA, and the fourth voltage signal VDC_OS may be any stable voltage values that meet system requirements.
  • the first ground voltage is zero potential; the second ground voltage is a square wave signal that periodically changes between zero potential and a preset negative potential.
  • the second ground voltage is a square wave signal, the high level is 0, and the low level is the preset negative potential -VTX.
  • the working modes of the capacitive fingerprint identification system include: passive fingerprint detection mode, active fingerprint detection mode, and active combined with passive fingerprint detection mode; if in the passive fingerprint detection mode, the The floating signal generation circuit 05 is used to provide the first ground voltage for the ground terminal; if it is in the active fingerprint detection mode or the active and passive fingerprint detection mode, the floating signal generation circuit 05 for providing the second ground voltage to the ground terminal.
  • the passive fingerprint detection mode includes the following three steps:
  • the first step S11 the first reset switch RST1 is closed, the second reset switch RST2 and the fourth reset switch RST4 are open, the third reset switch RST3 and the fifth reset switch RST5 are closed, the sixth switch K06 is open, and the feedback capacitor CFB is two.
  • the terminal power Q RST is:
  • the output voltage signal VOUT of the integrating circuit 03 is:
  • the second step S12 the first reset switch RST1, the third reset switch RST3 and the fifth reset switch RST5 are turned off, the second reset switch RST2 and the fourth reset switch are turned on; the fourth switch K04 is turned off, and the fifth switch K05 is turned on;
  • the seventh switch K07 is closed, the eighth switch K08 is open; the ninth switch K09 is closed, and the tenth switch K10 is open; the sixth switch K06 is open, and the detection capacitor Cf is charged through the fifth switch K05, and the charging power Q1 is:
  • the third step S13 the first reset switch RST1, the third reset switch RST3 and the fifth reset switch RST5 are turned off, the second reset switch RST2 and the fourth reset switch RST4 are turned on, the fifth switch K05 is turned off, and the fourth switch K04 is turned off open; the seventh switch K07 is open, the eighth switch K08 is closed; the ninth switch K09 is open, the tenth switch K10 is closed; the sixth switch K06 is closed, and the charge of the detection capacitor Cf is transferred to the output end of the operational amplifier OP at this time , the charge transfer quantity Q2 is:
  • Different detection capacitors Cf can obtain different output voltage signals VOUT, so as to identify the difference between the detection capacitors and Cf.
  • the second capacitor C02 and the third capacitor C03 are used to compensate the charge amount of the equivalent parasitic capacitor CP at the common node N3 of the fourth switch K04 and the fifth switch K05. Considering the influence of the parasitic capacitance CP from the N3 node to the VSS, the corrected result of the output voltage signal VOUT is:
  • the second step S12 and the third step S13 are repeated. After repeating N times, the output voltage signal VOUT is:
  • the active fingerprint detection mode includes the following three steps:
  • the first step S21 the first reset switch RST1, the third reset switch RST3 and the fifth reset switch RST5 are closed, the second reset switch RST2 and the fourth reset switch RST4 are disconnected, the sixth switch K06 is disconnected, and both ends of the feedback capacitor CFB
  • the power Q RST is:
  • the output voltage signal VOUT of the integrating circuit 03 is:
  • the charge transfer quantity Q2 is:
  • different detection capacitors Cf can obtain different output voltage signals VOUT, and by detecting different detection capacitors Cf, different fingerprint information can be obtained.
  • the equivalent parasitic capacitance of the common node N3 of the fourth switch K04 and the fifth switch K05 has no charge transfer in the active fingerprint detection mode, so the parasitic capacitance has little influence on the output at this time.
  • the output voltage signal VOUT is:
  • the active and passive fingerprint detection mode includes the following three steps:
  • the first step S31 the first reset switch RST1, the third reset switch RST3 and the fifth reset switch RST5 are closed, the second reset switch RST2 and the fourth reset switch RST4 are disconnected, the sixth switch K06 is disconnected, and both ends of the feedback capacitor CFB
  • the power Q RST is:
  • the output voltage signal VOUT of the integrating circuit 03 is:
  • different detection capacitors Cf can obtain different output voltage signals VOUT, and by detecting different detection capacitors Cf, different fingerprint information can be obtained.
  • the second capacitor C02 and the third capacitor C03 are used to compensate the charge amount of the equivalent parasitic capacitor CP at the common node N3 of the fourth switch K04 and the fifth switch K05. Considering the influence of parasitic capacitance CP, the corrected result of the output voltage signal VOUT is:
  • the second step S12 and the third step S13 are repeated, and after the second step S12 and the third step S13 are repeated for N times, the output voltage signal VOUT is:
  • three fingerprint detection modes are implemented in the fingerprint detection circuit of the same fingerprint detection chip, and the desired fingerprint detection mode can be flexibly selected based on the requirements.
  • FIG. 11 is a schematic structural diagram of an electronic device provided by an embodiment of the present invention, and the shown electronic device 100 includes the foregoing implementation.
  • the electronic device 100 may be an electronic device with a fingerprint recognition function, such as a mobile phone, a tablet computer, or a smart wearable device.
  • the electronic device 100 adopts the capacitive fingerprint identification system described in the above-mentioned embodiments, which can realize flexible selection of three fingerprint identification modes through a single chip, with simple circuit structure and low manufacturing cost.
  • another embodiment of the present invention further provides a fingerprint identification method of a capacitive fingerprint identification system, the method comprising:
  • the working mode of the capacitive fingerprint identification system is selected;
  • the working modes of the capacitive fingerprint identification system include: a passive fingerprint detection mode, an active fingerprint detection mode, and an active combined passive fingerprint detection mode;
  • a second ground voltage whose amplitude changes periodically is provided.
  • the working mode can be selected through the control of the switch state in the capacitive fingerprint identification system described in the above embodiment, and the floating signal suitable for the current working mode is provided by the floating signal generating circuit, the control logic is simple, and the circuit structure is simple.

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Abstract

本发明公开了一种电容式指纹识别系统及电子设备及指纹识别方法中，所述电容式指纹识别系统包括：积分电路，包括：运放器，具有正相输入端、负相输入端、接地端和输出端；连接在所述负相输入端和所述输出端之间的反馈支路；指纹信息采集电路，与所述负相输入端连接，用于输入参考电压以及第一电压信号，并采集指纹信息；浮地信号产生电路，与所述接地端连接，用于基于第二电压信号和第三电压信号，为接地端提供与工作模式适配的浮地信号，选择输出浮地信号为幅值恒定的第一接地电压或是幅值周期性变化的第二接地电压。本发明技术方案通过为所述接地端提供与工作模式适配的浮地信号，可以基于需求使得所述电容式指纹识别系统工作在不同的模式。

Description

一种电容式指纹识别系统及电子设备及指纹识别方法 技术领域
本发明涉及指纹识别技术领域，更具体的说，涉及一种电容式指纹识别系统及电子设备及指纹识别方法。
背景技术
随着科学技术的不断发展，越来越多的电子设备被广泛的应用于人们人日常生活以及工作当中，为人们的日常生活以及工作带来了巨大的便利，成为当今人们不可或缺的重要工具。
目前电子设备的功能越来越强度，所存储的信息越来越多，为了保证用户信息的安全性，需要在电子设备中集成身份识别系统。指纹识别由于较高的安全性以及操作方便性，指纹识别系统成为当今电子设备所使用的主流身份识别系统。但是，现有的指纹识别系统仅能具有单一工作模式的指纹识别。
发明内容
有鉴于此，本申请提供了一种电容式指纹识别系统及电子设备及指纹识别方法，方案如下：
一种电容式指纹识别系统，包括：
积分电路，所述积分电路包括：运放器，具有正相输入端、负相输入端、接地端和输出端；连接在所述负相输入端和所述输出端之间的反馈支路；所述运放器的正相输入端输入参考电压，所述积分电路的输出端电压用于指纹识别；
指纹信息采集电路，与所述负相输入端连接，通过切换开关输入参考电压或第一电压信号，并采集指纹信息；
浮地信号产生电路，所述浮地信号产生电路与所述接地端连接，用于基于 第二电压信号和第三电压信号，为所述接地端提供与工作模式适配的浮地信号VSS，选择输出所述浮地信号为幅值恒定的第一接地电压或是幅值周期性变化的第二接地电压；
所述电容式指纹识别系统的工作模式包括：被动式的指纹检测模式、主动式的指纹检测模式、以及主动式结合被动式的指纹检测模式；
如果处于所述被动式的指纹检测模式，所述浮地信号产生电路用于为所述接地端提供所述第一接地电压；
如果处于所述主动式的指纹检测模式或是主动式结合被动式的指纹检测模式，所述浮地信号产生电路用于为所述接地端提供所述第二接地电压。
优选的，在上述电容式指纹识别系统中，所述浮地信号产生电路包括：
第一电容，一个极板连接第一节点，所述第一节点用于输出所述第二电压信号；另一个极板连接第二节点，所述第二节点用于输出所述浮地信号；
第一开关，连接输入所述第三电压信号的端口与所述第一节点；
第二开关，所述第一节点通过所述第二开关接地；
第三开关，所述第二节点通过所述第三开关接地。
优选的，在上述电容式指纹识别系统中，所述第一开关为第一晶体管，所述第二开关为第二晶体管，所述第三开关为第三晶体管；
所述第一晶体管的栅极接入第一开关控制信号，源极接入所述第三电压信号，漏极与所述第一节点连接；
所述第二晶体管的栅极接入第二开关控制信号，漏极与所述第一节点连接，源极接地；
所述第三晶体管的栅极接入第三开关控制信号，源极与所述第二节点连接，漏极接地。
优选的，在上述电容式指纹识别系统中，所述第一晶体管为PMOS，所述第二晶体管和所述第三晶体管均为NMOS。
优选的，在上述电容式指纹识别系统中，还包括：
电源管理单元，所述电源管理单元具有第一低压差调整器，所述第一低压差调整器与所述指纹信息采集电路以及所述浮地信号产生电路分别连接，以提供所述参考电压以及所述第一电压信号。
优选的，在上述电容式指纹识别系统中，还包括：输入输出端口以及为所述输入输出端口提供工作电压的第二低压差调整器；
其中，所述第二低压差调整器用于基于所述第三电压信号为所述输入输出端口提供工作电压。
优选的，在上述电容式指纹识别系统中，所述指纹信息采集电路包括：
第四开关,输入所述参考电压的端口和第三节点通过所述第四开关连接；
第五开关，输入所述第一电压信号的端口和所述第三节点通过所述第五开关连接；
第六开关，所述第三节点和所述负相输入端通过所述第六开关连接；
检测电极，与所述第三节点连接，用于基于触摸操作形成检测电容。
优选的，在上述电容式指纹识别系统中，所述指纹信息采集电路还包括：
第七开关，输入所述第一电压信号的端口和第四节点通过所述第七开关连接；
第八开关，输入所述参考电压的端口和所述第四节点通过所述第八开关连接；
第九开关，输入所述第一电压信号的端口和第五节点通过所述第九开关连接；
第十开关，输入所述浮地信号的端口和所述第五节点通过所述第十开关连接；
其中，所述第四节点通过第二电容与所述第三节点连接，所述第五节点通过第三电容与所述第三节点连接。
优选的，在上述电容式指纹识别系统中，所述反馈支路包括：
连接在所述负相输入端与所述输出端之间的反馈电容；
连接在所述负相输入端与所述输出端之间的第一复位开关。
优选的，在上述电容式指纹识别系统中，所述反馈电容具有第一极板和第二极板；
所述第一极板通过第二复位开关与所述负相输入端连接，且通过第三复位开关与输入第四电压信号的端口连接；
所述第二极板通过第四复位开关与所述输出端连接，且通过第五复位开关 与输入所述第一电压信号的端口连接。
优选的，在上述电容式指纹识别系统中，所述电容式指纹识别系统的工作模式包括：被动式的指纹检测模式、主动式的指纹检测模式、以及主动式结合被动式的指纹检测模式；
如果处于所述被动式的指纹检测模式，所述浮地信号产生电路用于为所述接地端提供所述第一接地电压；
如果处于所述主动式的指纹检测模式或是主动式结合被动式的指纹检测模式，所述浮地信号产生电路用于为所述接地端提供所述第二接地电压。
优选的，在上述电容式指纹识别系统中，所述第一接地电压为0电位；
所述第二接地电压为0电位与预设负电位之间周期变化的方波信号。
本发明还提供了一种电子设备，上述任一项所述的电容式指纹识别系统。
本发明还提供了一种电容式指纹识别系统的指纹识别方法，包括：
基于控制指令，选择电容式指纹识别系统的工作模式；所述电容式指纹识别系统的工作模式包括：被动式的指纹检测模式、主动式的指纹检测模式、以及主动式结合被动式的指纹检测模式；
如果处于所述被动式的指纹检测模式，提供幅值恒定的第一接地电压；
如果处于所述主动式的指纹检测模式或是主动式结合被动式的指纹检测模式，提供幅值周期性变化的第二接地电压。
通过上述描述可知，本发明技术方案提供的电容式指纹识别系统及电子设备及指纹识别方法中，所述电容式指纹识别系统包括：积分电路，所述积分电路包括：运放器，具有正相输入端、负相输入端、接地端和输出端；连接在所述负相输入端和所述输出端之间的反馈支路；指纹信息采集电路，与所述负相输入端连接，用于输入参考电压以及第一电压信号，并采集指纹信息；浮地信号产生电路，所述浮地信号产生电路与所述接地端连接，用于基于第二电压信号和第三电压信号，为所述接地端提供与工作模式适配的浮地信号，选择输出所述浮地信号为幅值恒定的第一接地电压或是幅值周期性变化的第二接地电压。本发明技术方案中通过浮地信号产生电路，能够为所述接地端提供与工作模式适配的浮地信号，选择输出所述浮地信号为幅值恒定的第一接地电压或是幅值周期性变化的第二接地电压，可以基于需求使得所述电容式指纹识别系统 工作在不同的模式。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据提供的附图获得其他的附图。
本说明书附图所绘示的结构、比例、大小等，均仅用以配合说明书所揭示的内容，以供熟悉此技术的人士了解与阅读，并非用以限定本发明可实施的限定条件，故不具技术上的实质意义，任何结构的修饰、比例关系的改变或大小的调整，在不影响本发明所能产生的功效及所能达成的目的下，均应仍落在本发明所揭示的技术内容得能涵盖的范围内。
图1为一种两颗芯片的浮地信号产生电路；
图2为一种单颗芯片浮地信号产生电路的结构示意图；
图3为一种负压电荷泵的电路图；
图4为本发明实施例提供的一种电容式指纹识别系统的电路图；
图5为本发明实施例提供的一种浮地信号产生电路的结构示意图；
图6为本发明实施例提供的另一种浮地信号产生电路的结构示意图；
图7为图6所示浮地信号产生电路中开关控制信号的时序图；
图8为本发明实施例提供的一种电源系统的电路图；
图9为本发明实施例提供的一种指纹检测电极的金属层布局的结构示意图；
图10为本发明实施例提供的另一种电容式指纹识别系统的电路图；
图11为本发明实施例提供的一种电子设备的结构示意图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请中的实施例进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前 提下所获得的所有其他实施例，都属于本申请保护的范围。
电容式指纹识别方案是通过检测手指指纹中波峰波谷与芯片感应电极形成的电容大小，来判断手指的指纹信息。电容式指纹识别方案主要包括：被动式识别方案、主动式识别方案、以及主动式结合被动式的识别方案。
指纹检测电路有主动式检测电路、被动式检测电路和混合式检测电路三种方式，其中混合式检测电路由主动式的部分电路和被动式的部分电路混合构成。
主动式检测电路，通过外加驱动信号加载到检测电路的地信号，即增加驱动信号加载到手指上，手指指纹的波谷对芯片内部感应电极形成的电容搜集不同电荷，积分到积分器的输出端，通过电压大小判断电容的大小，从而重现指纹波峰波谷。
而被动式的工作原理则不同，其是利用手指按在芯片表面时，指纹的波峰波谷对芯片内部电容上下电极电荷分配的比例影响程度来对指纹进行重现指纹，无需额外增加驱动源。
目前的电容式指纹检测电路存在如下缺陷：采用电路简单的被动式指纹检测电路时容易受寄生电容影响，离散性大，数据容易饱和；采用电路复杂的主动式指纹检测电路时数据一致性好，但是一般由两颗芯片组成，成本高；现有的采用单颗芯片实现的指纹检测电路，片外器件多，对工艺有要求，成本依旧很高。
如图1所示，图1为现有的主动式电容指纹电路，采用两颗芯片，成本高。该主动式电容指纹电路包括驱动控制芯片11和指纹感测芯片12，实现浮地设计和主动式的指纹采集。驱动控制芯片11提供指纹感测芯片12的VTX电平及需要的电源VDD。指纹感测芯片12为驱动控制芯片提供TX信号，指纹感测芯片12基于输入信号输出电压信号VSS。驱动控制芯片11通过SPI(串行外围接口)和主设备13连接。驱动控制芯片11电源端输入电压信号VDD_SUPPLY，接地端接地。指纹感测芯片12输出方波形式的电压信号VSS，其高电平为VTX，低电平为0。
虽然一些电路设计能够实现单颗芯片的主动式的识别方案，但是电路设计相对复杂，需要片外器件较多，电路面积大，对工艺要求较高，故对成本改善 有限，制作成本仍旧较高。
如图2所示，图2为现有技术一种单颗芯片浮地信号产生电路的结构示意图，该浮地信号产生电路包括：开关K3、开关K4和开关K5，开关K3的一端输入电压信号VDD_SUPPLY，另一端连接节点Q1，开关K4的一端接地GND，另一端连接节点Q2，节点Q1和节点Q2之间连接有电容C1，开关K5的一端连接负压电荷泵，另一端连接节点Q2。节点Q1提供电压信号VDD，节点Q2提供电压信号VSS。指纹检测电路模块与节点Q1和节点Q2分别连接。
在图2所示电路中，节点Q1通过开关K3和电压信号VDD_SUPPLY连接，节点Q2通过开关K4和开关K5在0电位和负电荷泵输出的电压信号-VTX之间切换。可以获得方波形式的电压信号VSS，其高电平为0，低电平为-VTX。
当开关K3和开关K4闭合，开关K5断开时，节点Q1通过开关K3接入电压信号VDD_SUPPLY，指纹检测芯片中的指纹检测电路模块由电压信号VDD_SUPPLY供电。同时电压信号VDD_SUPPLY供电给电容C1充电。
当开关K3和开关K4断开，开关K5闭合时，节点Q2通过开关K5接入电压信号-VTX，指纹检测芯片中指纹检测电路模块的电流由电容C1提供。故有：
VSS＝-VTX
通过开关K3、开关K4和开关K5的交替断开和闭合，实现了电压信号VSS在0和-VTX之间的周期变化，实现电压信号VSS的浮地功能。但是还需要通过负压电荷泵提供电压信号VSS需要的电压信号-VTX，现有技术中常用的负压电荷泵电路结构如图3所示。
图3为一种负压电荷泵的电路图，所示负压电荷泵包括：开关K6、开关K7、开关K8、开关K9、电容C2和电容C3。开关K6的一端接地GND，另一端连接节点Q3；开关K7的一端连接节点Q3，另一端接入电压信号VDD_SUPPLY；开关K8的一端连接节点Q4，另一端连接节点Q5；开关K9的一端连接节点Q4，另一端接地GND；电容C2的一个极板连接节点Q3，另一个极板连接节点Q4；电容C3的一个极板连接节点Q5，另一个极板接地GND。其中，节点Q5输出电压信号-VTX。
可见，图3所示负压电荷泵需要四个开关以及两个电容，需要更大的电路面积以及更高负载的逻辑电路以控制电流。同时，由于负压电荷泵启动时需要 给电容C2和电容C3充电，启动时间与电容C2和电容C3的大小以及启动电流大小相关，会影响系统的响应速度。
为解决上述问题，本发明实施例技术方案提供了一种电容式指纹识别系统，采用单颗芯片集合了被动式识别方案、主动式识别方案、以及主动式结合被动式的识别方案，具有三种工作模式：被动式的指纹检测模式、主动式的指纹检测模式、以及主动式结合被动式的指纹检测模式。本发明实施例技术方案要求工艺简单，片外器件少，成本低，工作模式可以根据需求灵活选择。
为使本申请的上述目的、特征和优点能够更加明显易懂，下面结合附图和具体实施方式对本申请作进一步详细的说明。
如图4所示，图4为本发明实施例提供的一种电容式指纹识别系统的电路图，包括：
积分电路03，所述积分电路03包括：运放器OP，具有正相输入端、负相输入端、接地端和输出端VOUT；连接在所述负相输入端和所述输出端之间的反馈支路031；
指纹信息采集电路04，所述指纹信息采集电路04与所述负相输入端连接，用于输入参考电压VREF以及第一电压信号VDDA，并采集指纹信息；所述正相输入端用于输入参考电压VREF。
浮地信号产生电路05，所述浮地信号产生电路05与所述接地端连接，用于基于第二电压信号VDD和第三电压信号VDD_SUPPLY，为所述接地端提供与工作模式适配的浮地信号VSS，选择输出所述浮地信号VSS为幅值恒定的第一接地电压或是幅值周期性变化的第二接地电压。其中，所述第一接地电压可以为接地信号GND，为幅值固定的0电位；第二接地电压可以为方波信号。
本发明实施例所述电容式指纹识别系统，所述浮地信号产生电路05能够基于工作模式选择输出所述浮地信号VSS为第一接地电压或是第二接地电压，使得电容式指纹识别系统处于被动式的指纹检测模式、主动式的指纹检测模式、以及主动式结合被动式的指纹检测模式。系统构架简单，指纹检测芯片面积小，片外器件少，三种指纹检测模式可以基于需求灵活选择。
本发明实施例所述电容式指纹识别系统可以通过单颗芯片实现，通过浮地 信号产生电路05为指纹检测芯片接地端提供浮地信号VSS，基于芯片可靠性以及浮动地的负载，浮地信号为第二接地电压时，能够从接地信号GND(0电位)到设定负电位-VTX周期性变化。可以使得-VTX＝-VDD_SUPPLY。
如图5所示，图5为本发明实施例提供的一种浮地信号产生电路的结构示意图，所述浮地信号产生电路05包括：
第一电容C01，一个极板连接第一节点N1，所述第一节点N1用于输出所述第二电压信号VDD；另一个极板连接第二节点N2，所述第二节点N2用于输出所述浮地信号VSS；
第一开关K01，所述第一开关K01连接输入所述第三电压信号VDD_SUPPLY的端口与所述第一节点N1；
第二开关K02，所述第一节点N1通过所述第二开关K02接地GND；
第三开关K03，所述第二节点N2通过所述第三开关K03接地GND。
其中，所述第一节点N1和所述第二节点N2与指纹检测芯片中指纹检测电路模块连接，所述指纹检测电路模块包括电源系统、信号处理部分电路、上述积分电路03以及指纹信息采集电路04。
当第一开关K01和第三开关K03闭合，第二开关K02断开时，第一节点N1与输入第三电压信号VDD_SUPPLY的端口连接，第二节点N2接地，浮地信号VSS等于接地信号GND。第三电压信号VDD_SUPPLY经过第一开关K01，为指纹检测电路模块提供电流，同时第三电压信号VDD_SUPPLY给第一电容C01充电。
当第二开关K02闭合，且第一开关K01和第三开关K03断开时，第一节点N1通过第二开关K02接地GND，第二节点N2与接地端口断开，利用第一电容C01两端的电压不能突变的原理，有如下关系：
V C＝VDD_SUPPLY-0＝0-VSS
VSS＝-VDD_SUPPLY
可见，第三电压信号VDD_SUPPLY为系统电源，浮地信号VSS变为第三电压信号VDD_SUPPLY负值，即为电源的负电压。
第一电容C01两端的电压变化ΔV C为：
Figure PCTCN2020132173-appb-000001
其中，I为第一电容C01放电电流，t为VSS的负压工作时间。基于I和t以及第一电容C01的大小，可以计算出第一电容C01两端的电压变化ΔV C。
通过第一开关K01、第二开关K02和第三开关K03的交替打开和闭合，实现了浮地信号VSS在0电位和-VDD_SUPPLY之间的周期性变化，控制好电流和周期时间，选择设定的第一电容C1，即可以满足由第一电容C01提供电流期间，其电压减小量不影响芯片中检测电路模块的工作。
图5所示浮地信号产生电路05采用三个开关以及一个电容即可选择输出幅值固定位0电位的接地电压，或选择输出幅值在0与-VDD_SUPPLY之间的周期性变化的接地电压，电路结构简单。通过单颗芯片，实现了三种工作指纹识别工作模式的控制方案，可以根据需求灵活选择浮地信号VSS和工作模式。
本发明技术方案的主动式指纹识别方案为采用单颗芯片，在芯片内部产生浮地信号VSS。设置第二接地电压在0和-VDD_SUPPLY之间周期性变化，以保证可靠性以及减小浮地负载。所述浮地信号产生电路05控制逻辑简单，不需要额外电路或者片外器件。
本发明实施例技术方案通过单颗芯片，实现了浮地信号产生电路05的设计，电路控制方式简单，面积小，片外器件少，成本低，同时采集指纹信号性能好，信号量大，一致性好，可以穿透不同厚度的盖板，而且通过简单的工艺设计电平平移电路，进行不同电压域之间的转换。
如图6所示，图6为本发明实施例提供的另一种浮地信号产生电路的结构示意图，基于图5所示方式，所述第一开关K01为第一晶体管MP，所述第二开关K02为第二晶体管MN1，所述第三开关K03为第三晶体管MN2。所述第一晶体管MP的栅极接入第一开关控制信号TX1_P，源极接入所述第三电压信号VDD_SUPPLY，漏极与所述第一节点N1连接。所述第二晶体管MN1的栅极接入第二开关控制信号TX1_N，漏极与所述第一节点连接N1，源极接地GND。所述第三晶体管MN2的栅极接入第三开关控制信号TX2，源极与所述第二节点N2连接，漏极接地GND。
其中，所述第三电压信号VDD_SUPPLY为指纹检测芯片外部供电电源提供，第二电压信号VDD为浮地信号产生电路05基于第三电压信号VDD_SUPPLY产生的指纹检测芯片内部电源。第二电压信号VDD通过第一 晶体管MP和第二晶体管MN1在VDD_SUPPLY和GND之间切换。第二节点N2通过第三晶体管MN2与GND连接或者断开。根据第二电压信号VDD和浮地信号VSS的电压范围，选择所述第一晶体管MP为PMOS，所述第二晶体管MN1和所述第三晶体管MN2均为NMOS。PMOS的衬底和NMOS的衬底连接各自的源端即可。通过第一电容C01以及三个MOS即可实现浮地信号产生电路05，电路结构简单。
需要说明的是，图6所示方式中，三个晶体管实现方式不限于所述第一晶体管MP为PMOS，所述第二晶体管MN1和所述第三晶体管MN2均为NMOS，可以基于开关控制信号设定该三个晶体管为PMOS或是NMOS。晶体管的衬底电位选择不局限于PN结为零。
如图7所示，图7为图6所示浮地信号产生电路中开关控制信号的时序图，三个开关控制信号均为周期性变化的方波信号。同一周期内，在第三开关控制信号TX2由高电平切换为低电平后，第一开关控制信号TX1_P由低电平切换为高电平；在第一开关控制信号TX1_P由低电平切换为高电平后，第二开关控制信号TX1_N由低电平切换为高电平；在第三开关控制信号TX2由低电平切换为高电平前，第一开关控制信号TX1_P由高电平切换为低电平；在第一开关控制信号TX1_P由高电平切换为低电平前，第二开关控制信号TX1_N由高电平切换为低电平。
如果第一开关控制信号TX1_P为低电平，第三开关控制信号TX2为高电平，第二开关控制信号TX1_N为低电平，第二电压信号VDD的输出端口通过第一晶体管MP与输入第三电压信号VDD_SUPPLY的端口连接，输出浮地信号VSS的第二节点N2通过第三晶体管MN2接地GND。
当第一开关控制信号TX1_P高电平，第三开关控制信号TX2为低电平，第二开关控制信号TX1_N高电平，第二电压信号VDD的输出端口通过第二晶体管MN1接地GND，输出浮地信号VSS的第二节点N2与接地端断开。基于第一电容C01两端电容不能突变，VSS＝-VDD_SUPPLY＝-VTX。三个开关控制信号周期性变化，通过简单的电路和控制逻辑实现了浮地信号VSS的选择性输出，相比于传统电路结构，电路结构简单，节省了版图面积，降低了电路功耗，减小了系统响应时间，而且电路结构极其简单。
如图8所示，图8为本发明实施例提供的一种电源系统的电路图，基于上述各个实施例，本发明实施例所述电容式指纹识别系统还包括：电源管理单元PMU，所述电源管理单PMU具有第一低压差调整器LDO，所述第一低压差调整器LDO与所述指纹信息采集电路04、所述积分电路03以及所述浮地信号产生电路05分别连接，以提供所述参考电压VREF以及所述第一电压信号VDDA。其中，可以设置所述电源管理单PMU输出所述第一电压信号VDDA的端口通过电容C3和第二节点N2连接。
所述浮地信号产生电路05能够基于输入的第三电压信号VDD_SUPPLY输出第二电压信号VDD和浮地信号VSS。所述电源管理单PMU输出所述第一电压信号VDDA的端口还连接有模拟电路。模拟电路由所述电源管理单PMU中第一低压差调整器LDO产生的第一电压信号VDDA供电，通过述第二电压信号VDD为所述电源管理单PUM供电。第一节点N1还连接有数字电路。通过第二电压信号VDD为数字电路直接供电。
其他方式中，所述电容式指纹识别系统还包括：输入输出端口IO以及为所述输入输出端口IO提供工作电压的第二低压差调整器LDO_VDDIO；其中，所述第二低压差调整器LDO_VDDIO用于基于所述第三电压信号VDD_SUPPLY为所述输入输出端口IO提供工作电压VDDIO。其中，可以设置所述第二低压差调整器LDO_VDDIO输出电压VDDIO的端口通过电容C4接地GND。第二低压差调整器LDO_VDDIO由外部电源提供的第三电压信号VDD_SUPPLY供电。通过单独设置的第二低压差调整器LDO_VDDIO给输入输出端口IO供电，避免输入输出端口IO供电对指纹识别结果产生不利影响。
如图4所示，所述指纹信息采集电路04包括：第四开关K04,输入所述参考电压VREF的端口和第三节点N3通过所述第四开关连接K04；第五开关K05，输入所述第一电压信号VDDA的端口和所述第三节点N3通过所述第五开关K05连接；第六开关K06，所述第三节点N3和所述负相输入端通过所述第六开关连接K06；检测电极01，所述检测电极01与所述第三节点N3连接，用于基于触摸操作形成检测电容Cf。
本发明技术方案具有指纹检测模式、主动式的指纹检测模式、以及主动式结合被动式的指纹检测模式，支持被动式指纹检测、主动式指纹检测、以及主 动式结合被动式的指纹检测。
选择第四开关K04断开，第五开关K05和第六开关K06交替开关，VSS＝GND＝0，为被动式指纹检测模式。
选择第五开关K05断开，第四开关K04和第六开关K06交替开关，VSS在GND和-VDD_SUPPLY之间周期切换，为主动式指纹检测模式。
选择第四开关K04断开，第五开关K05和第六开关K06交替开关，VSS在GND和-VDD_SUPPLY之间周期切换，为主动式结合被动式的指纹检测模式。
本发明技术方案可以支持三种指纹检测模式，可以根据需求灵活选择。
如图4所示，所述反馈支路03包括：连接在所述负相输入端与所述输出端之间的反馈电容CFB；连接在所述负相输入端与所述输出端之间的第一复位开关RST1。
如图9所示，图9为本发明实施例提供的一种指纹检测电极的金属层布局的结构示意图，本发明实施例所述电容式指纹识别系统包括第一金属层AA与第二金属层，第二金属层包括第一部分BB和第二部分CC。第一金属层AA相对于第二金属层靠近设备触控面。第二金属层远离第一金属层AA的一侧设置有指纹检测开关电路，所述指纹检测开关电路包括本发明实施例所述电容式指纹指纹识别系统中所有开关，通过第二金属层屏蔽指纹检测开关电路对第一金属层AA的串扰，以保证指纹识别的准确性。
具体的，指纹检测感应单元的检测电极01位于图形化的第一金属层AA，在手指触摸识别时，第一金属层AA与手指形成检测电容Cf。第一金属层AA下方具有图形化的第二金属层。第一金属层AA和第一部分BB具有第二电容C02。第一部分BB下方为指纹检测控制开关电路，避免指纹检测开关电路对检测电容Cf造成干扰，避免检测开关电路影响指纹识别结果。第二部分CC和第一金属层AA具有第三电容C03。其中，第一部分BB通过两个并联的开关分别接入第一电压信号VDDA和参考电压VREF；第一金属层AA通过两个并联的开关分别接入第一电压信号VDDA和参考电压VREF；第二部分CC通过两个并联的开关分别接入第一电压信号VDDA和浮地信号VSS。通过设置与检测电容Cf互联的第二电容C02和第三电容C03，并设置对应开关输入 图9所示电压信号，能够增加指纹识别的精度和灵敏度。
如图10所示，图10为本发明实施例提供的另一种电容式指纹识别系统的电路图，基于上述各个实施方式，所述指纹信息采集电路还包括：第七开关K07，输入所述第一电压信号VDDA的端口和第四节点N4通过所述第七开关K07连接；第八开关K08，输入所述参考电压VREF的端口和所述第四节点N4通过所述第八开关K08连接；第九开关K09，输入所述第一电压信号VDDA的端口和第五节点N5通过所述第九开关K09连接；第十开关K10，输入所述浮地信号VSS的端口和所述第五节点N5通过所述第十开关K10连接；
其中，所述第四节点N4通过第二电容C02与所述第三节点N3连接，所述第五节点N5通过第三电容C03与所述第三节点N3连接。指纹信息采集电路04的金属层布局可以参考图9所示，在此不再赘述。
基于图4方式，图10所示方式中，所述反馈电容CFB具有第一极板和第二极板；所述第一极板通过第二复位开关RST2与所述正相输入端连接，且通过第三复位开关RST3与输入第四电压信号VDC_OS的端口连接；所述第二极板通过第四复位开关RST4与所述输出端连接，且通过第五复位开关RST5与输入所述第一电压信号VDDA的端口连接。
本发明实施例中，参考电压VREF、第一电压信号VDDA和第四电压信号VDC_OS可以为任何满足系统需求的稳定电压值。
本发明实施例所述的电容式指纹识别系统中，所述第一接地电压为0电位；所述第二接地电压为0电位与预设负电位之间周期变化的方波信号。第二接地电压为方波信号，高电平为0，低电平为预设负电位-VTX。为了最大化增大信号灵敏度，设置预设负电位-VTX为-VDD_SUPPLY。
如上述，所述电容式指纹识别系统的工作模式包括：被动式的指纹检测模式、主动式的指纹检测模式、以及主动式结合被动式的指纹检测模式；如果处于所述被动式的指纹检测模式，所述浮地信号产生电路05用于为所述接地端提供所述第一接地电压；如果处于所述主动式的指纹检测模式或是主动式结合被动式的指纹检测模式，所述浮地信号产生电路05用于为所述接地端提供所述第二接地电压。
下面结合图9及图10的开关控制方法，对本发明实施例所述电容式指纹 识别系统的三种工作模式进行进一步说明。
反馈电容CFB在复位时，给了一个固定偏置电压VDS_OS-VDDA，以便于根据指纹信息调整输出信号VOUT的电平位置。
被动式指纹检测模式包括如下三个步骤：
第一步S11：第一复位开关RST1闭合，第二复位开关RST2及第四复位开关RST4断开，第三复位开关RST3及第五复位开关RST5闭合，第六开关K06断开，反馈电容CFB两端电量Q RST为：
Q RST＝(VDC_OS-VDDA)*CFB
积分电路03的输出电压信号VOUT为：
VOUT＝VREF
第二步S12：第一复位开关RST1、第三复位开关RST3和第五复位开关RST5断开，第二复位开关RST2和第四复位开关闭合；第四开关K04断开，第五开关K05闭合；第七开关K07闭合，第八开关K08断开；第九开关K09闭合，第十开关K10断开；第六开关K06断开，此时检测电容Cf通过第五开关K05充电，充电电量Q1为：
Q1＝VDDA*Cf+(VDDA-VDDA)*C02+(VDDA-VDDA)*C03
第三步S13：第一复位开关RST1、第三复位开关RST3和第五复位开关RST5断开，第二复位开关RST2和第四复位开关RST4闭合，第五开关K05断开，第四开关K04断开；第七开关K07断开，第八开关K08闭合；第九开关K09断开，第十开关K10闭合；第六开关K06闭合，此时检测电容Cf的电荷转移到运放器OP的输出端，电荷转移量Q2为：
Q2＝VREF*Cf+(VREF-VREF)*C02+VREF*C03+(VREF-VOUT)*CFB
根据电荷守恒原理，有：
Q1+Q RST＝Q2
Figure PCTCN2020132173-appb-000002
不同的检测电容Cf可以得到不同的输出电压信号VOUT，从而识别检测电容你Cf的不同。第二电容C02和第三电容C03用于补偿第四开关K04和第五开关K05公共节点N3等效寄生电容CP的电荷量。考虑N3节点到VSS的 寄生电容CP的影响，输出电压信号VOUT修正后的结果为：
Figure PCTCN2020132173-appb-000003
由于检测电容Cf较小，为了增大输出电压信号VOUT，重复第二步S12和第三步S13，第二步S12和第三步S13重复次数为N，N为正整数，表示积分次数。重复N次之后，输出电压信号VOUT为：
Figure PCTCN2020132173-appb-000004
经过N此积分之后，不仅可以增大检测得到的表示指纹信息的输出电压信号VOUT，还可以移除高频噪声，提高信噪比。
主动式的指纹检测模式包括如下三个步骤：
第一步S21：第一复位开关RST1、第三复位开关RST3和第五复位开关RST5闭合，第二复位开关RST2和第四复位开关RST4断开，第六开关K06断开，反馈电容CFB两端电量Q RST为：
Q RST＝(VDC_OS-VDDA)*CFB
积分电路03的输出电压信号VOUT为：
VOUT＝VREF
第二步S22：第一复位开关RST1、第三复位开关RST3和第五复位开关RST5断开，第二复位开关RST2至和第四复位开关RST4闭合；第五开关K05断开，第四开关K04闭合；第七开关K07断开，第八开关K08闭合；第九开关K09断开，第十开关K10闭合；第六开关K06断开，VSS＝GND＝0，此时，检测电容Cf通过第五开关K05充电，充电电量Q1为：
Q1＝VREF*Cf+(VREF-VREF)*C02+VREF*C03
第三步S23：第一复位开关RST1、第三复位开关RST3和第五复位开关RST5断开，第二复位开关RST2和第四复位开关RST4闭合；第四开关K04断开，第五开关K05断开；第七开关K07断开，第八开关K08闭合；第九开 关K09断开，第十开关K10闭合；第六开关K06闭合，VSS＝-VTX，检测电容Cf的电荷转移到运放器OP的输出端，电荷转移量Q2为：
Q2＝(VREF-VTX)*Cf+(VREF-VREF)*C02+VREF*C03+(VREF-VOUT)*CFB
根据电荷守恒原理，有：
Q1+Q RST＝Q2
Figure PCTCN2020132173-appb-000005
同样，不同的检测电容Cf可以得到不同的输出电压信号VOUT，通过检测不同的检测电容Cf，可以获得不同的指纹信息。
第四开关K04和第五开关K05的公共节点N3等效寄生电容在主动的指纹检测模式没有电荷转移，故此时寄生电容对输出影响小。
重复第二步S22和第三步S23，重复N次之后，输出电压信号VOUT为：
Figure PCTCN2020132173-appb-000006
主动式结合被动式的指纹检测模式包括如下三个步骤：
第一步S31：第一复位开关RST1、第三复位开关RST3和第五复位开关RST5闭合，第二复位开关RST2和第四复位开关RST4断开，第六开关K06断开，反馈电容CFB两端电量Q RST为：
Q RST＝(VDC_OS-VDDA)*CFB
积分电路03的输出电压信号VOUT为：
VOUT＝VREF
第二步S32：第一复位开关RST1、第三复位开关RST3和第五复位开关RST5断开，第二复位开关RST2和第四复位开关RST4闭合；第四开关K04断开，第五开关K05闭合；第七开关K07闭合，第八开关K08断开；第九开关K09闭合，第十开关K10断开；第六开关K06断开，VSS＝GND＝0，此时检测电容通过第五开关K05充电，充电电量Q1为：
Q1＝VDDA*Cf+(VDDA-VDDA)*C02+(VDDA-VDDA)*C03
第三步S33：第一复位开关RST1、第三复位开关RST3和第五复位开关 RST断开，第五开关K05断开，第四开关K04断开；第七开关K07断开，第八开关K08闭合；第九开关K09断开，第十开关K10闭合；第六开关K06闭合，VSS＝-VTX，此时检测电容Cf的电荷转移到运放器OP的输出端，转移的电荷量Q2为：
Q2＝(VREF-VTX)*Cf+(VREF-VREF)*C02+VREF*C03+(VREF-VOUT)*CFB
根据电荷守恒原理，有：
Q1+Q RST＝Q2
Figure PCTCN2020132173-appb-000007
同样，不同的检测电容Cf可以得到不同的输出电压信号VOUT，通过检测不同的检测电容Cf，可以获得不同的指纹信息。第二电容C02和第三电容C03用于补偿第四开关K04和第五开关K05公共节点N3等效寄生电容CP的电荷量。考虑寄生电容CP的影响，输出电压信号VOUT修正后的结果为：
Figure PCTCN2020132173-appb-000008
重复第二步S12和第三步S13，第二步S12和第三步S13重复次数为N之后，输出电压信号VOUT为：
Figure PCTCN2020132173-appb-000009
通过图10所示电容式指纹识别系统，在同一个指纹检测芯片的指纹检测电路中实现了三种指纹检测模式，可以基于需求灵活选择所需指纹检测模式。
基于上述实施例，本发明另一实施例还提供了一种电子设备，如图11所示，图11为本发明实施例提供的一种电子设备的结构示意图，所示电子设备100包括上述实施例所述的电容式指纹识别系统。
所述电子设备100可以为手机、平板电脑或是智能穿戴设备等具有指纹识别功能的电子设备。所述电子设备100采用上述实施例所述的电容式指纹识别系统，能够通过单颗芯片实现三种指纹识别模式的灵活选择，电路结构简单，制作成本低。
基于上述实施例，本发明另一实施例还提供了一种电容式指纹识别系统的指纹识别方法，该方法包括：
基于控制指令，选择电容式指纹识别系统的工作模式；所述电容式指纹识别系统的工作模式包括：被动式的指纹检测模式、主动式的指纹检测模式、以及主动式结合被动式的指纹检测模式；
如果处于所述被动式的指纹检测模式，提供幅值恒定的第一接地电压；
如果处于所述主动式的指纹检测模式或是主动式结合被动式的指纹检测模式，提供幅值周期性变化的第二接地电压。
可以通过上述实施例所述的电容式指纹识别系统中开关状态的控制，选择工作模式，通过浮地信号产生电路提供与当前工作模式适配的浮地信号，控制逻辑简单，电路结构简单。
本说明书中各个实施例采用递进、或并列、或递进和并列结合的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似部分互相参见即可。对于实施例公开的电子设备和指纹识别方法而言，由于其与实施例公开的电容式指纹识别系统相对应，所以描述的比较简单，相关之处参见电容式指纹识别系统对应部分说明即可。
需要说明的是，在本发明的描述中，需要理解的是，术语“上”、“下”、“顶”、“底”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本发明和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本发明的限制。当一个组件被认为是“连接”另一个组件，它可以是直接连接到另一个组件或者可能同时存在居中设置的组件。
还需要说明的是，在本文中，诸如第一和第二等之类的关系术语仅仅用来将一个实体或者操作与另一个实体或操作区分开来，而不一定要求或者暗示这些实体或操作之间存在任何这种实际的关系或者顺序。而且，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的物品或者设备不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种物品或者设备所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括上述要素的物品或者设备中还存在另外的相同要素。
对所公开的实施例的上述说明，使本领域专业技术人员能够实现或使用本申请。对这些实施例的多种修改对本领域的专业技术人员来说将是显而易见的，本文中所定义的一般原理可以在不脱离本申请的精神或范围的情况下，在其它实施例中实现。因此，本申请将不会被限制于本文所示的这些实施例，而是要符合与本文所公开的原理和新颖特点相一致的最宽的范围。

Claims (13)

  1. 一种电容式指纹识别系统，其特征在于，包括：
    积分电路，所述积分电路包括：运放器，具有正相输入端、负相输入端、接地端和输出端；连接在所述负相输入端和所述输出端之间的反馈支路；所述运放器的正相输入端输入参考电压，所述积分电路的输出端电压用于指纹识别；
    指纹信息采集电路，与所述负相输入端连接，通过切换开关输入参考电压或第一电压信号，并采集指纹信息；
    浮地信号产生电路，所述浮地信号产生电路与所述接地端连接，用于基于第二电压信号和第三电压信号，为所述接地端提供与工作模式适配的浮地信号VSS，选择输出所述浮地信号为幅值恒定的第一接地电压或是幅值周期性变化的第二接地电压；
    所述电容式指纹识别系统的工作模式包括：被动式的指纹检测模式、主动式的指纹检测模式、以及主动式结合被动式的指纹检测模式；
    如果处于所述被动式的指纹检测模式，所述浮地信号产生电路用于为所述接地端提供所述第一接地电压；
    如果处于所述主动式的指纹检测模式或是主动式结合被动式的指纹检测模式，所述浮地信号产生电路用于为所述接地端提供所述第二接地电压。
  2. 根据权利要求1所述的电容式指纹识别系统，其特征在于，所述浮地信号产生电路包括：
    第一电容，一个极板连接第一节点，所述第一节点用于输出所述第二电压信号；另一个极板连接第二节点，所述第二节点用于输出所述浮地信号；
    第一开关，连接输入所述第三电压信号的端口与所述第一节点；
    第二开关，所述第一节点通过所述第二开关接地；
    第三开关，所述第二节点通过所述第三开关接地。
  3. 根据权利要求2所述的电容式指纹识别系统，其特征在于，所述第一开关为第一晶体管，所述第二开关为第二晶体管，所述第三开关为第三晶体管；
    所述第一晶体管的栅极接入第一开关控制信号，源极接入所述第三电压信号，漏极与所述第一节点连接；
    所述第二晶体管的栅极接入第二开关控制信号，漏极与所述第一节点连接，源极接地；
    所述第三晶体管的栅极接入第三开关控制信号，源极与所述第二节点连接，漏极接地。
  4. 根据权利要求3所述的电容式指纹识别系统，其特征在于，所述第一晶体管为PMOS，所述第二晶体管和所述第三晶体管均为NMOS。
  5. 根据权利要求1所述的电容式指纹识别系统，其特征在于，还包括：
    电源管理单元，所述电源管理单元具有第一低压差调整器，所述第一低压差调整器与所述指纹信息采集电路以及所述浮地信号产生电路分别连接，以提供所述参考电压以及所述第一电压信号。
  6. 根据权利要求1所述的电容式指纹识别系统，其特征在于，还包括：输入输出端口以及为所述输入输出端口提供工作电压的第二低压差调整器；
    其中，所述第二低压差调整器用于基于所述第三电压信号为所述输入输出端口提供工作电压。
  7. 根据权利要求1所述的电容式指纹识别系统，其特征在于，所述指纹信息采集电路包括：
    第四开关,输入所述参考电压的端口和第三节点通过所述第四开关连接；
    第五开关，输入所述第一电压信号的端口和所述第三节点通过所述第五开关连接；
    第六开关，所述第三节点和所述负相输入端通过所述第六开关连接；
    检测电极，与所述第三节点连接，用于基于触摸操作形成检测电容。
  8. 根据权利要求7所述的电容式指纹识别系统，其特征在于，所述指纹信息采集电路还包括：
    第七开关，输入所述第一电压信号的端口和第四节点通过所述第七开关连接；
    第八开关，输入所述参考电压的端口和所述第四节点通过所述第八开关连接；
    第九开关，输入所述第一电压信号的端口和第五节点通过所述第九开关连接；
    第十开关，输入所述浮地信号的端口和所述第五节点通过所述第十开关连接；
    其中，所述第四节点通过第二电容与所述第三节点连接，所述第五节点通过第三电容与所述第三节点连接。
  9. 根据权利要求1或8所述的电容式指纹识别系统，其特征在于，所述反馈支路包括：
    连接在所述负相输入端与所述输出端之间的反馈电容；
    连接在所述负相输入端与所述输出端之间的第一复位开关；
    所述反馈电容具有第一极板和第二极板；
    所述第一极板通过第二复位开关与所述负相输入端连接，且通过第三复位开关与输入第四电压信号的端口连接；
    所述第二极板通过第四复位开关与所述输出端连接，且通过第五复位开关与输入所述第一电压信号的端口连接。
  10. 根据权利要求1所述的电容式指纹识别系统，其特征在于，所述第一接地电压为0电位；
    所述第二接地电压为0电位与预设负电位之间周期变化的方波信号。
  11. 根据权利要求1所述的电容式指纹识别系统，其特征在于，所述电容式指纹识别系统集成于单颗芯片。
  12. 一种电子设备，其特征在于，包括：如权利要求1-11任一项所述的电容式指纹识别系统。
  13. 一种电容式指纹识别系统的指纹识别方法，其特征在于，包括：
    基于控制指令，选择电容式指纹识别系统的工作模式；所述电容式指纹识别系统的工作模式包括：被动式的指纹检测模式、主动式的指纹检测模式、以及主动式结合被动式的指纹检测模式；
    如果处于所述被动式的指纹检测模式，提供幅值恒定的第一接地电压；
    如果处于所述主动式的指纹检测模式或是主动式结合被动式的指纹检测模式，提供幅值周期性变化的第二接地电压。
PCT/CN2020/132173 2020-11-27 2020-11-27 一种电容式指纹识别系统及电子设备及指纹识别方法 WO2022109999A1 (zh)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115202425A (zh) * 2022-09-15 2022-10-18 成都市易冲半导体有限公司 串行通信总线超低电源电压检测的io设计电路及方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106778672A (zh) * 2016-12-30 2017-05-31 深圳芯启航科技有限公司 一种指纹检测电路和指纹检测传感器
CN206532303U (zh) * 2016-12-30 2017-09-29 深圳芯启航科技有限公司 一种指纹检测电路和指纹检测传感器
US20170323136A1 (en) * 2015-07-27 2017-11-09 Shenzhen GOODIX Technology Co., Ltd. Fingerprint Detecting Circuit and Fingerprint Identification System

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20170323136A1 (en) * 2015-07-27 2017-11-09 Shenzhen GOODIX Technology Co., Ltd. Fingerprint Detecting Circuit and Fingerprint Identification System
CN106778672A (zh) * 2016-12-30 2017-05-31 深圳芯启航科技有限公司 一种指纹检测电路和指纹检测传感器
CN206532303U (zh) * 2016-12-30 2017-09-29 深圳芯启航科技有限公司 一种指纹检测电路和指纹检测传感器

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115202425A (zh) * 2022-09-15 2022-10-18 成都市易冲半导体有限公司 串行通信总线超低电源电压检测的io设计电路及方法
CN115202425B (zh) * 2022-09-15 2022-11-22 成都市易冲半导体有限公司 串行通信总线超低电源电压检测的io设计电路及方法

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