WO2022105704A1 - Circuit tampon, circuit intégré et dispositif électronique - Google Patents

Circuit tampon, circuit intégré et dispositif électronique Download PDF

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Publication number
WO2022105704A1
WO2022105704A1 PCT/CN2021/130568 CN2021130568W WO2022105704A1 WO 2022105704 A1 WO2022105704 A1 WO 2022105704A1 CN 2021130568 W CN2021130568 W CN 2021130568W WO 2022105704 A1 WO2022105704 A1 WO 2022105704A1
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WIPO (PCT)
Prior art keywords
circuit
buffer circuit
switches
driving
driving units
Prior art date
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PCT/CN2021/130568
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English (en)
Chinese (zh)
Inventor
刘广辉
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维沃移动通信有限公司
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Publication of WO2022105704A1 publication Critical patent/WO2022105704A1/fr

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00315—Modifications for increasing the reliability for protection in field-effect transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/0033—Radiation hardening
    • H03K19/00338—In field effect transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00346—Modifications for eliminating interference or parasitic voltages or currents
    • H03K19/00361—Modifications for eliminating interference or parasitic voltages or currents in field effect transistor circuits

Definitions

  • the present application belongs to the field of photography technology, and specifically relates to a buffer circuit, an integrated circuit and an electronic device.
  • a buffer circuit is usually added to the clock module of a display driver integrated circuit (IC) for output waveform shaping, and the output signal of the buffer circuit is used as a reference clock for the back-end frequency division or timing module.
  • IC display driver integrated circuit
  • a traditional snubber circuit In order to ensure that there is no functional risk, a traditional snubber circuit is usually set with a certain driving capability. However, an improper setting of the driving capability often results in strong Electromagnetic Interference (EMI). These EMI interferences will be radiated and coupled to the antenna that is close to it, and the driver IC is usually coupled in parallel with the antenna, resulting in high efficiency of EMI interference radiation coupled to the antenna.
  • EMI Electromagnetic Interference
  • the snubber circuit in the prior art has the problem of poor EMI performance.
  • the purpose of the embodiments of the present application is to provide a buffer circuit, an integrated circuit and an electronic device, which can solve the problem of poor EMI performance in the buffer circuit in the prior art.
  • an embodiment of the present application provides a buffer circuit, including M driving units, M first switches and M second switches, where M is a positive integer greater than 1; wherein,
  • the first terminals of the M driving units are respectively connected to the power supply through the M first switches, and are grounded respectively through the M second switches, and the second terminals of the M driving units are connected to each other as the buffer the input end of the buffer circuit, the third ends of the M driving units are connected to each other as the output end of the buffer circuit;
  • the M first switches and the M second switches are used to control the working modes of the M driving units, and the M driving units are used to perform the signal received at the input end of the buffer circuit. Amplification is performed to output a drive signal of a drive capability corresponding to the working mode at the output end of the buffer circuit, where the working mode is used to represent the drive capability of the M drive units.
  • an embodiment of the present application provides an electronic device, including a clock generator and the buffer circuit described in the first aspect.
  • the M driving units can amplify the signal received by the input end of the buffer circuit, so as to output the driving signal with the driving capability corresponding to the working mode.
  • the driving capability of the output of the buffer circuit can be flexibly adjusted, so that the EMI performance of the buffer circuit can be flexibly adjusted on the premise of ensuring the performance reliability of the buffer circuit.
  • the EMI performance of the snubber circuit can be optimized.
  • FIG. 1 is one of the structural diagrams of a buffer circuit provided by an embodiment of the present application
  • Figure 2 is a schematic diagram of the relationship between a display screen driver IC and an antenna on an electronic device
  • Fig. 3 is the layout realization schematic diagram of M drive units
  • Fig. 4 is the concrete structure diagram of the first drive unit
  • FIG. 5 is a second structural diagram of a buffer circuit provided by an embodiment of the present application.
  • FIG. 6 is a schematic diagram of the relationship between the input voltage V GS of the NMOS tube and the drain current ID;
  • FIG. 7 is a schematic diagram of the control of the input voltage V GS of the NMOS tube to the drain current ID;
  • FIG. 8 is a schematic diagram of a drive signal output by an output end of a buffer circuit
  • FIG. 9 is a schematic diagram of spectrum signals of each driving signal.
  • first, second and the like in the description and claims of the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It is to be understood that the data so used are interchangeable under appropriate circumstances so that the embodiments of the present application can be practiced in sequences other than those illustrated or described herein, and distinguish between “first”, “second”, etc.
  • the objects are usually of one type, and the number of objects is not limited.
  • the first object may be one or more than one.
  • “and/or” in the description and claims indicates at least one of the connected objects, and the character “/" generally indicates that the associated objects are in an "or” relationship.
  • FIG. 1 is a structural diagram of a buffer circuit provided by an embodiment of the present application.
  • the buffer circuit 100 includes M driving units 101, M first switches 102, and M In the second switch 103, M is a positive integer greater than 1; wherein,
  • the first terminals of the M driving units 101 are respectively connected to the power source through the M first switches 102 and grounded through the M second switches 103 respectively, and the second terminals of the M driving units 101 are connected to each other As the input end of the buffer circuit 100, the third ends of the M driving units 101 are connected to each other as the output end of the buffer circuit 100;
  • the M first switches 102 and the M second switches 103 are used to control the working modes of the M driving units 101 , and the M driving units 101 are used for the input terminals of the buffer circuit 100
  • the received signal is amplified to output a drive signal corresponding to the drive capability of the working mode at the output end of the buffer circuit 100 , and the working mode is used to represent the drive capability of the M drive units.
  • the buffer circuit 100 can be set in the driver IC, and the buffer circuit 100 can be added to the clock module of the driver IC to amplify the clock signal and shape the output waveform of the clock signal , to be used as a reference clock for the back-end frequency division or timing module.
  • the driver IC may be a display screen driver IC or a driver IC of other modules, which is not specifically limited here.
  • the buffer circuit 100 may generate strong EMI interference during operation, and the EMI interference will be coupled and radiated to other modules such as antennas that are close to the driver IC, resulting in EMI problems.
  • the buffer circuit 100 is shown below.
  • the screen driver IC is used as an example for detailed description.
  • Figure 2 is a schematic diagram of the relationship between the display driver IC and the antenna on the electronic device.
  • the electronic device product is driven by the appearance of the full screen, and the distance between the display driver IC and the antenna is already sub-millimeters class.
  • the wiring between the modules is relatively long, so that the EMI interference of the display driver IC has a high external radiation efficiency.
  • the display driver IC and the antenna are coupled in parallel, resulting in a relatively high efficiency of EMI interference radiation coupling to the antenna, resulting in EMI problems.
  • the display screen driver IC includes, but is not limited to, driver ICs for display devices such as Active-Matrix Organic Light-Emitting Diode (AMOLED), and liquid crystal thin film transistors (Thin Film Transistor, TFT).
  • AMOLED Active-Matrix Organic Light-Emitting Diode
  • TFT Thin Film Transistor
  • the buffer circuit 100 includes an input terminal and an output terminal.
  • the input terminal of the buffer circuit 100 can be connected to a clock generator, and the clock generator is used for generating a clock signal and passing the clock signal through the buffer circuit 100
  • the input terminal of is input to the buffer circuit 100 .
  • the output end of the buffer circuit 100 outputs a driving signal, and the driving signal can be used as a reference clock for the back-end frequency division or timing module.
  • Each of the M driving units 101 can be connected to the first switch 102 and the second switch 103 , and the first switch 102 and the second switch 103 connected to the driving unit 101 can control the operation of the driving unit 101 Status, the working status of the drive unit 101 includes two types, working and non-working.
  • the clock signal may be shaped, or the clock signal may be amplified when the clock signal is at a high level.
  • the switches connected to the drive unit A are the first switch A and the second switch A. If the first switch A and the second switch A are both disconnected, the drive unit A does not work, and the clock signal is on the rising edge. That is, when the voltage changes from a low level to a high level, the first switch A is closed, and the second switch A is disconnected. At this time, the drive unit A works, amplifies and shapes the clock signal, and when the clock signal falls on the falling edge, the voltage changes from high to high. When the level changes to a low level, the first switch A is turned off, and the second switch A is turned on. At this time, the driving unit A works to shape the clock signal.
  • the driving unit 101 can control the opening and closing of the first switch 102 and the second switch 103 by detecting the rising edge and falling edge of the clock signal, and when detecting the rising edge of the clock signal, control the One switch 102 is closed, and the second switch 103 is open.
  • the second switch 103 is controlled to be closed, and the first switch 102 is opened.
  • the working states of the M driving units 101 can determine the working modes of the M driving units 101, and different M has different types of working modes.
  • M When M is 2, there are three working modes. When it is 3, its working mode includes 7 kinds, and the larger M is, the more kinds of its working mode are.
  • M includes a driving unit A, a driving unit B, and a driving unit C, respectively.
  • the operating modes of the M driving units 101 are shown in Table 1 below.
  • the operating modes are used to represent the driving capabilities of the M driving units, and the driving capabilities of the driving signals output by each operating mode may be different, and the driving capabilities of the M driving units may be driven by a driving current or a driving voltage.
  • the larger the driving current or the driving voltage the larger the driving ability, and the smaller the driving current or the driving voltage, the smaller the driving ability. Since the second terminals of the M driving units 101 are connected to each other as the input terminals of the buffer circuit 100, and the third terminals of the M driving units 101 are connected to each other as the output terminals of the buffer circuit 100, it can be seen that , the M driving units 101 are connected in parallel, and the layout can be implemented as shown in FIG.
  • the driving capability thereof is the superposition of the driving capability of each driving unit 101 .
  • the drive current of drive unit A is 8 milliamps (mA)
  • the drive current of drive unit B is 4 mA
  • the drive current of drive unit C is 2 mA
  • the drive current corresponding to operating mode 1 is 14 mA.
  • the driving signals (the driving signals may be voltage signals) output at the output end of the buffer circuit 100 are also different.
  • each driving unit 101 in the M driving units 101 may be the same or different, and the driving current may depend on the power supply connected through the first switch 102 .
  • the larger the current the smaller the voltage value of the connected power supply, and the smaller the drive current.
  • the first driving unit is any one of the M driving units 101 .
  • FIG. 4 is a specific structural diagram of the first driving unit.
  • the first driving unit includes an N-Metal-Oxide-Semiconductor (NMOS) transistor 1011 and a P-type metal Oxide semiconductor (P-Metal-Oxide-Semiconductor, PMOS) tube 1012;
  • NMOS N-Metal-Oxide-Semiconductor
  • PMOS P-type metal Oxide semiconductor
  • the source of the PMOS transistor 1012 is connected to the voltage through the first target switch 1021, and is grounded through the second target switch 1031, and the source of the NMOS transistor 1011 is grounded; wherein, the first target switch is the Mth Any one of the switches 102, the second target switch is any one of the M second switches 103;
  • the gate of the PMOS transistor 1012 and the gate of the NMOS transistor 1011 are connected to each other as the input terminal of the buffer circuit 100, and the drain of the PMOS transistor 1012 and the drain of the NMOS transistor 1011 are connected to each other as the input terminal of the buffer circuit 100. the output of the buffer circuit 100 .
  • the output of the first driving unit that is, the output of the output terminal of the buffer circuit 100 is the final push-pull output.
  • the source of the PMOS transistor is connected to the power supply, and the voltage between the gate and the source of the NMOS transistor 1011 is turned on when the on condition is reached.
  • the NMOS transistor 1011 is turned on, the greater the voltage value of the connected power supply, the greater the voltage between the drain and the source of the NMOS transistor 1011, and the correspondingly greater the drain current, that is, the driving current.
  • the driving unit 101 outputs a low level, that is, a zero level.
  • the driving current of the driving unit 101 can be set by setting the voltage value of the power supply connected to the driving unit 101 . In this way, by setting different power supplies, the driving current of the M driving units 101 can be flexibly set.
  • the drive capability of each drive unit 101 can be different.
  • the driving current of the driving unit 101 with high driving ability is correspondingly larger than the driving current of other driving units 101, and the driving current of the driving unit 101 with weak driving ability is correspondingly smaller than the driving current of other driving units 101, that is, the driving current of the M driving units 101.
  • the voltage values of the power supplies whose one ends are respectively connected through the M first switches 102 are all different.
  • M driving units 101 , M first switches 102 and M second switches 103 are introduced, and the M driving units are controlled through the M first switches 102 and M second switches 103 101, so that the M driving units 101 can amplify the signal received by the input end of the buffer circuit 100 to output the driving signal with the driving capability corresponding to the operating mode.
  • the driving capability of the output of the buffer circuit 100 can be flexibly adjusted, so that the performance and reliability of the buffer circuit 100 can be flexibly adjusted. Its EMI performance, and then the EMI performance of the snubber circuit 100 can be optimized.
  • the EMI interference of the display driver IC can be reduced, and under the full screen of the electronic device, the efficiency of coupling the EMI interference radiation of the display driver IC to the antenna can be reduced, thereby indirectly Improve the appearance and performance competitiveness of full-screen products with high space requirements.
  • the working modes of the M driving units 101 are adjustable, even if the driving currents of the M driving units 101 are adjustable, the performance reliability of the buffer circuit 100 can be ensured, and the product development and verification cycle can be shortened .
  • the driving capability of the M driving units 101 can be adjusted, which is easy to implement in the semiconductor process, and has a small footprint and low cost .
  • FIG. 5 is a second structural diagram of a buffer circuit provided by an embodiment of the present application.
  • the buffer circuit 100 further includes a first adjustment sub-circuit 104 ; wherein,
  • the input terminal of the first adjustment sub-circuit 104 is connected to the input terminal of the buffer circuit 100 , and the output terminal of the first adjustment sub-circuit 104 is connected to the second terminals of the M driving units 101 .
  • the first adjustment sub-circuit 104 is used to adjust the rising edge time and the falling edge time of the driving signal output by the output end of the buffer circuit 100 .
  • the first adjustment sub-circuit 104 may be a resistance-capacitance (Resistance Capacitance, RC) circuit, the RC circuit is used to delay the rising edge and the falling edge of the driving signal, or may be the output end of the adjustable buffer circuit 100 Other circuits for the rising edge time and falling edge time of the output drive signal are not specifically limited.
  • RC Resistance Capacitance
  • the first adjustment sub-circuit 104 will be described in detail by taking an RC circuit as an example.
  • the RC circuit can be realized by the chip resistor and capacitor layout process, and its layout design is simple.
  • the output end of the RC circuit is connected to the second end of the M driving units 101 , that is, the gate of the NMOS transistor 1011 .
  • an RC circuit is provided between the clock generator and the driving unit 101, which can reduce the gate voltage of the NMOS transistor 1011, and correspondingly, can adjust the input voltage V GS between the gate and the source of the NMOS transistor 1011
  • the change of the current ID between the drain and the source can be controlled, as shown in FIG. 7 , and the rise time of the driving signal output by the output terminal of the buffer circuit 100 can be controlled. and fall time.
  • FIG. 8 is a schematic diagram of the drive signal output by the output end of the buffer circuit.
  • the solid line 801 represents the drive signal before the rise time and fall time are delayed, that is, the buffer of the RC circuit is not set
  • the dashed line 802 represents the drive signal with delayed rise time and fall time, that is, the drive signal output by the output end of the buffer circuit 100 provided with the RC circuit.
  • the time constant of the RC circuit can be set to half the target rising edge time.
  • the buffer circuit 100 may further include a third switch 105 connected in parallel with the first regulating sub-circuit 104, the third switch 105 may bypass the first regulating sub-circuit when closed 104.
  • the buffer circuit 100 further includes a second adjustment sub-circuit 106; wherein,
  • the input terminal of the second adjustment sub-circuit 106 is connected to the third terminals of the M driving units 101 , and the output terminal of the second adjustment sub-circuit 106 serves as the output terminal of the buffer circuit 100 .
  • the second adjustment sub-circuit 106 may be a circuit composed of resistors.
  • a polysilicon resistor may be connected in series with the output ends of the M driving units 101 and the buffer circuit 100, and the resistance value of the polysilicon resistor may be 50 ohms to 100 ohms. In this way, the current from the driving unit 101 to the receiving end can be further reduced, so that the rising edge and the falling edge of the driving signal can be slowed down, and the EMI performance of the buffer circuit 100 can be further improved.
  • the buffer circuit 100 may further include a fourth switch 107, the fourth switch 107 is connected in parallel with the second regulating sub-circuit 106, and the fourth switch 107 may bypass the second regulating sub-circuit when closed 106.
  • the present application also provides an integrated circuit, the integrated circuit includes the buffer circuit in the above embodiment, the buffer circuit includes M driving units, M first switches and M second switches, where M is greater than 1 a positive integer of ; where,
  • the first terminals of the M driving units are respectively connected to the power supply through the M first switches, and are grounded respectively through the M second switches, and the second terminals of the M driving units are connected to each other as the buffer the input end of the buffer circuit, the third ends of the M driving units are connected to each other as the output end of the buffer circuit;
  • the M first switches and the M second switches are used to control the working modes of the M driving units, and the M driving units are used to perform the signal received at the input end of the buffer circuit. Amplification is performed to output a drive signal of a drive capability corresponding to the working mode at the output end of the buffer circuit, where the working mode is used to represent the drive capability of the M drive units.
  • the buffer circuit further includes a first adjustment sub-circuit; wherein,
  • the input end of the first adjustment sub-circuit is connected to the input end of the buffer circuit, and the output end of the first adjustment sub-circuit is connected to the second ends of the M driving units.
  • the first adjustment sub-circuit is a resistance-capacitance circuit, and the resistance-capacitance circuit is used to delay the rising edge and the falling edge of the driving signal.
  • the buffer circuit further includes a third switch, and the third switch is connected in parallel with the first adjustment sub-circuit.
  • the buffer circuit further includes a second adjustment sub-circuit; wherein,
  • the input end of the second adjusting sub-circuit is connected to the third end of the M driving units, and the output end of the second adjusting sub-circuit serves as the output end of the buffer circuit.
  • the second adjustment subcircuit is a circuit composed of resistors.
  • the buffer circuit further includes a fourth switch, and the fourth switch is connected in parallel with the second adjustment sub-circuit.
  • the voltage values of the power supplies respectively connected to the first ends of the M driving units through the M first switches are different.
  • the first driving unit includes a P-type metal-oxide-semiconductor PMOS transistor and an N-type metal-oxide-semiconductor NMOS transistor, and the first driving unit is any one of the M driving units;
  • the source of the PMOS tube is connected to the power supply through the first target switch, and is grounded through the second target switch, and the source of the NMOS tube is grounded; wherein, the first target switch is any one of the M first switches. A switch, the second target switch is any one of the M second switches;
  • the gate of the PMOS transistor and the gate of the NMOS transistor are connected to each other as the input end of the buffer circuit, and the drain of the PMOS transistor and the drain of the NMOS transistor are connected to each other as the buffer circuit 's output.
  • the structure of the buffer circuit in the above integrated circuit is similar to that of the buffer circuit in the above-mentioned embodiment, and has the same beneficial effects as the buffer circuit in the above-mentioned embodiment, so it is not repeated.
  • those skilled in the art should refer to the description of the buffer circuit in the above-mentioned embodiments to understand. To save space, details are not repeated here.
  • a buffer circuit is provided in an integrated circuit, wherein, M driving units, M first switches and M second switches are introduced into the buffer circuit, and the M first switches and M second switches are introduced into the buffer circuit.
  • the second switches control the operating modes of the M driving units, so that the M driving units can amplify the signals received by the input terminals of the buffer circuits to output the driving capability corresponding to the operating modes. drive signal.
  • the driving capability of the output of the buffer circuit can be flexibly adjusted, so that the EMI performance of the buffer circuit can be flexibly adjusted on the premise of ensuring the performance reliability of the buffer circuit.
  • the EMI performance of the snubber circuit is optimized, which in turn can optimize the EMI performance of the integrated circuit.
  • the present application also provides an electronic device, the electronic device includes the buffer circuit and the clock generator in the above embodiments, the output end of the clock generator is connected to the input end of the buffer circuit, and the buffer circuit includes M driving units, M first switches and M second switches, where M is a positive integer greater than 1; wherein,
  • the first terminals of the M driving units are respectively connected to the power supply through the M first switches, and are grounded respectively through the M second switches, and the second terminals of the M driving units are connected to each other as the buffer the input end of the buffer circuit, the third ends of the M driving units are connected to each other as the output end of the buffer circuit;
  • the M first switches and the M second switches are used to control the working modes of the M driving units, and the M driving units are used to perform the signal received at the input end of the buffer circuit. Amplification is performed to output a drive signal with a drive capability corresponding to the working mode at the output end of the buffer circuit, where the working mode is used to represent the drive capability of the M drive units.
  • the buffer circuit further includes a first adjustment sub-circuit; wherein,
  • the input terminal of the first adjustment sub-circuit is connected to the input terminal of the buffer circuit, and the output terminal of the first adjustment sub-circuit is connected to the second terminals of the M driving units.
  • the first adjustment sub-circuit is a resistance-capacitance circuit, and the resistance-capacitance circuit is used to delay the rising edge and the falling edge of the driving signal.
  • the buffer circuit further includes a third switch, and the third switch is connected in parallel with the first adjustment sub-circuit.
  • the buffer circuit further includes a second adjustment sub-circuit; wherein,
  • the input end of the second adjusting sub-circuit is connected to the third end of the M driving units, and the output end of the second adjusting sub-circuit serves as the output end of the buffer circuit.
  • the second adjustment subcircuit is a circuit composed of resistors.
  • the buffer circuit further includes a fourth switch, and the fourth switch is connected in parallel with the second adjustment sub-circuit.
  • the voltage values of the power supplies respectively connected to the first ends of the M driving units through the M first switches are different.
  • the first driving unit includes a P-type metal-oxide-semiconductor PMOS transistor and an N-type metal-oxide-semiconductor NMOS transistor, and the first driving unit is any one of the M driving units;
  • the source of the PMOS tube is connected to the power supply through the first target switch, and is grounded through the second target switch, and the source of the NMOS tube is grounded; wherein, the first target switch is any one of the M first switches. a switch, the second target switch is any one of the M second switches;
  • the gate of the PMOS transistor and the gate of the NMOS transistor are connected to each other as the input end of the buffer circuit, and the drain of the PMOS transistor and the drain of the NMOS transistor are connected to each other as the buffer circuit 's output.
  • the electronic device in this embodiment of the present application may be a mobile electronic device or a non-mobile electronic device.
  • the mobile electronic device may be a mobile phone, a tablet computer, a notebook computer, a palmtop computer, an in-vehicle electronic device, a wearable device, an Ultra-Mobile Personal Computer (UMPC), a netbook, or a personal digital assistant (Personal Digital Assistant).
  • UMPC Ultra-Mobile Personal Computer
  • PDA Personal Digital Assistant
  • non-mobile electronic devices can be servers, network attached storage (Network Attached Storage, NAS), personal computer (Personal Computer, PC), television (Television, TV), teller machine or self-service machine, etc., this application Examples are not specifically limited.
  • the structure of the buffer circuit in the above electronic device is similar to that of the buffer circuit in the above-mentioned embodiment, and has the same beneficial effects as the buffer circuit in the above-mentioned embodiment, so it will not be repeated.
  • those skilled in the art should refer to the description of the buffer circuit in the above-mentioned embodiments to understand. To save space, details are not repeated here.
  • a buffer circuit is set in the integrated circuit of the electronic device, and the buffer circuit introduces M driving units, M first switches and M second switches, and passes the M first switches and M The second switches control the operating modes of the M driving units, so that the M driving units can amplify the signals received by the input terminals of the buffer circuits to output the driving capability corresponding to the operating modes. drive signal.
  • the driving capability of the output of the buffer circuit can be flexibly adjusted, so that the EMI performance of the buffer circuit can be flexibly adjusted on the premise of ensuring the performance reliability of the buffer circuit.
  • the EMI performance of the integrated circuit can be optimized, so as to reduce the interference of the chip in the communication frequency band and improve the network adaptability performance of electronic equipment products.

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Abstract

L'invention concerne un circuit tampon (100), un circuit intégré et un dispositif électronique. Le circuit tampon (100) comprend : M unités d'attaque (101), M premiers commutateurs (102) et M deuxièmes commutateurs (103), M étant un nombre entier positif supérieur à 1. Des premières extrémités des M unités d'attaque (101) sont respectivement connectées à une alimentation électrique au moyen des M premiers commutateurs (102), et sont mises à la terre au moyen des M deuxièmes commutateurs (103) ; des deuxièmes extrémités des M unités d'attaque (101) sont connectées les unes aux autres en tant qu'extrémité d'entrée du circuit tampon (100) ; des troisièmes extrémités des M unités d'attaque (101) sont connectées les unes aux autres en tant qu'extrémité de sortie du circuit tampon (100). Les M premiers commutateurs (102) et les M deuxièmes commutateurs (103) sont utilisés pour commander un mode de fonctionnement des M unités d'attaque (101) ; les M unités d'attaque (101) sont utilisées pour amplifier des signaux reçus par l'extrémité d'entrée du circuit tampon (100), de façon à délivrer en sortie un signal d'attaque de la capacité d'attaque correspondant au mode de fonctionnement à l'extrémité de sortie du circuit tampon (100) ; le mode de fonctionnement est utilisé pour représenter la capacité d'attaque des M unités d'attaque (101).
PCT/CN2021/130568 2020-11-17 2021-11-15 Circuit tampon, circuit intégré et dispositif électronique WO2022105704A1 (fr)

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CN202011284228.XA CN112398467A (zh) 2020-11-17 2020-11-17 缓冲器电路、集成电路及电子设备
CN202011284228.X 2020-11-17

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