WO2022104594A1 - 半导体结构 - Google Patents

半导体结构 Download PDF

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WO2022104594A1
WO2022104594A1 PCT/CN2020/129774 CN2020129774W WO2022104594A1 WO 2022104594 A1 WO2022104594 A1 WO 2022104594A1 CN 2020129774 W CN2020129774 W CN 2020129774W WO 2022104594 A1 WO2022104594 A1 WO 2022104594A1
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layer
stacked
semiconductor structure
semiconductor
island
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PCT/CN2020/129774
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English (en)
French (fr)
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张丽旸
程凯
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苏州晶湛半导体有限公司
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Priority to US18/252,347 priority Critical patent/US20230420434A1/en
Priority to PCT/CN2020/129774 priority patent/WO2022104594A1/zh
Priority to CN202080107205.3A priority patent/CN116547823A/zh
Publication of WO2022104594A1 publication Critical patent/WO2022104594A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/167—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits comprising optoelectronic devices, e.g. LED, photodiodes
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02455—Group 13/15 materials
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
    • H01L21/02496—Layer structure
    • H01L21/02505—Layer structure consisting of more than two layers
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
    • H01L21/02496—Layer structure
    • H01L21/02505—Layer structure consisting of more than two layers
    • H01L21/02507—Alternating layers, e.g. superlattice
    • H—ELECTRICITY
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    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
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    • H—ELECTRICITY
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    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
    • H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
    • H—ELECTRICITY
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    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0093—Wafer bonding; Removal of the growth substrate
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    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/10—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a light reflecting structure, e.g. semiconductor Bragg reflector
    • H—ELECTRICITY
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    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/20—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
    • H—ELECTRICITY
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    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/26—Materials of the light emitting region
    • H01L33/30—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table
    • H01L33/32—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table containing nitrogen
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/44—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
    • H01L33/46—Reflective coating, e.g. dielectric Bragg reflector
    • H—ELECTRICITY
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    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials

Definitions

  • the present application relates to the field of semiconductors, and in particular, to a semiconductor structure.
  • LED optoelectronic devices due to the lack of intrinsic substrates of gallium nitride, LED optoelectronic devices are all fabricated on foreign substrates, such as sapphire, silicon carbide and silicon.
  • the present application provides a semiconductor structure capable of improving the luminous efficiency of a semiconductor device.
  • a semiconductor structure is provided according to an embodiment of the present application, and the semiconductor structure includes:
  • the N-type semiconductor layer, the light-emitting layer, and the P-type semiconductor layer provided on the stacked structure are sequentially stacked.
  • the adjacent stacked structural units when the number of the stacked structural units is multiple, the adjacent stacked structural units partially overlap; or, the adjacent stacked structural units are provided separately from each other.
  • the stacked island includes alternately stacked second semiconductor layers and third semiconductor layers;
  • the material of the second semiconductor layer is Alx1Iny1Ga1 -x1-y1N ; the material of the third semiconductor layer is Alx2Iny2Ga1 -x2-y2N ; wherein, X1, Y1, X2 and The value range of Y2 is 0 ⁇ 1.
  • the layered structure is formed by taking the layered structural unit as the smallest repeating unit;
  • Each of the stacked structural units includes at least three of the stacked islands separated from each other in a horizontal direction.
  • the shape of the cross section of the island in the stack is a circle or a polygon.
  • the diameter of the cross section of the island in the stack is less than or equal to 50um
  • a gap between adjacent islands in the stack there is a gap between adjacent islands in the stack, and a side of the N-type semiconductor layer adjacent to the stack structure is further formed with a recess that is recessed in a direction away from the stack structure, and the recess is is formed corresponding to the gap.
  • the stacked structure, the N-type semiconductor layer, the light-emitting layer and the P-type semiconductor layer are fabricated by an epitaxy process.
  • the nucleation layer is disposed between the substrate and the laminated structure, and the nucleation layer is provided with grooves to form a plurality of islands in the nucleation layer separated from each other in the horizontal direction, Each of the stacked mid-islands corresponds to a mid-island arrangement of each of the nucleation layers.
  • the material of the substrate is sapphire, silicon, silicon carbide or gallium nitride.
  • the semiconductor structure further includes:
  • the reflective layer and the transfer layer are made by a chip process.
  • the material of the metal layer is Ag; or,
  • the reflective layer includes a stacked indium tin oxide layer and/or a DBR layer.
  • the DBR layer is formed by alternately stacking the first material layer of titanium oxide and the second material layer of silicon oxide.
  • a layered structure is provided, and the difference in the arrangement period of the islands in the layered layer is used to achieve selective reflection of light. This is because the island in the lamination makes the lamination structure have a photonic energy band structure, and the color of the reflected light changes with the position of the energy gap, thereby ultimately improving the luminous efficiency of the semiconductor structure.
  • FIG. 1 is a schematic cross-sectional structural diagram of the semiconductor structure of Example 1 of the present application along a vertical direction.
  • FIG. 2( a )- FIG. 2( c ) are schematic cross-sectional structural diagrams along the horizontal direction of the stacked structure of the semiconductor structure of Example 1 of the present application.
  • FIG. 5( a )- FIG. 5( c ) are schematic cross-sectional structural diagrams along the horizontal direction of the stacked structure of the semiconductor structure of Example 2 of the present application.
  • FIG. 6(a)-FIG. 6(b) is a process flow diagram of a method for fabricating a semiconductor structure according to Embodiment 2 of the present application.
  • FIG. 7 is a schematic cross-sectional structural diagram of the semiconductor structure in the third embodiment of the present application along the vertical direction.
  • the laminated structure 30 includes three laminated structural units 31 arranged along the horizontal direction X. As shown in FIG.
  • the stacked structure unit 31 is used as the minimum repeating unit to constitute the stacked structure 30 , that is, the stacked structural unit 31 is the minimum repeatable unit of the stacked structure 30 .
  • the laminated structure 30 may include only one laminated structural unit 31 ; alternatively, the laminated structure 30 may include two laminated structural units 31 , or four laminated structural units 31 , or other numbers of laminated structural units 31 .
  • Each of the stacked structural units 31 includes a plurality of stacked islands 311 separated from each other along the horizontal direction X. As shown in FIG. Preferably, each stacked structural unit 31 includes at least three stacked islands 311 separated from each other along the horizontal direction X.
  • the N-type semiconductor layer 40 , the light-emitting layer 50 and the P-type semiconductor layer 60 are sequentially stacked on the stacked structure 30 .
  • the stacked structure 30 , the N-type semiconductor layer 40 , the light-emitting layer 50 and the P-type semiconductor layer 60 are fabricated by epitaxy process.
  • gaps 312 between adjacent stacked islands 311 there are gaps 312 between adjacent stacked islands 311 , and a recess 41 recessed in a direction away from the stacked structure 30 is formed on the side of the N-type semiconductor layer 40 adjacent to the stacked structure 30 , and the recess 41 is formed corresponding to the gap 312 .
  • the material of the substrate 10 is sapphire, silicon, silicon carbide or gallium nitride.
  • the material of the nucleation layer 20 is AlN.
  • the stacked structure 30 is a stacked structure of multiple layers of materials, that is, the island 311 in the stack includes a buffer layer 313 and a first semiconductor layer 314 that are stacked in sequence.
  • the material of the first semiconductor layer 314 is group III nitride.
  • the cross-sectional shape of the island 311 in the stack may be circular or polygonal. As shown in FIG. 2( a ), the cross-sectional shape of the island 311 in the stack is circular. If the cross section of the island 311 in the stack is circular, the diameter R of the cross section of the island 311 in the stack is less than or equal to 50um. As can be seen from FIG. 2( a ), in this embodiment, the laminated structure 30 includes three laminated structural units 31 ; each laminated structural unit 31 includes three laminated mid-islands 311 , and the three laminated mid-islands 311 are horizontal The directions are set separately from each other.
  • Adjacent stacked structural units 31 may achieve partial overlap by sharing one stacked island 311 , but not limited to this, and may also achieve partial overlap by sharing two stacked central islands 311 ; or, adjacent stacked structural units 31 may not Overlapping, i.e. setting apart from each other.
  • FIG. 2( a )- FIG. 2( c ) are for better showing the structure of the laminated structure 30 , rather than real existence.
  • FIG. 3( a )- FIG. 3( d ) are process flow diagrams of the method for fabricating the semiconductor structure of Embodiment 1 of the present application.
  • the preparation method includes:
  • the nucleation layer 20 is formed on the substrate 10 along the vertical direction Y.
  • the material of the substrate 10 is sapphire, silicon, silicon carbide or gallium nitride.
  • the material of the nucleation layer 20 is AlN.
  • the cross-sectional shape of the island 311 in the stack may be circular or polygonal. If the cross-section of the stacked island 311 is circular, the diameter of the cross-section of the stacked island 311 is less than or equal to 50um; when the shape of the cross-section of the stacked island 311 is a polygon, preferably, the shape of the cross-section of the stacked island 311 is six
  • the shape of the cross-section of the island 311 in the stack can also be other polygons, and the diameter of the smallest circumscribed circle of the cross-section of the island 311 in the stack is less than or equal to 50um.
  • the stacked structure 30 is fabricated by an epitaxial process.
  • a stacked N-type semiconductor layer 40 , a light-emitting layer 50 and a P-type semiconductor layer 60 are formed on the plurality of stacked mid-islands 311 .
  • the N-type semiconductor layer 40 , the light-emitting layer 50 and the P-type semiconductor layer 60 are fabricated by epitaxial process.
  • the selective reflection of light is achieved. This is because the stacked islands 311 make the stacked structure 30 have a photonic energy band structure, and the color of the reflected light changes with the position of the energy gap, thereby ultimately improving the luminous efficiency of the semiconductor structure.
  • this embodiment also provides a semiconductor structure, which is basically the same as the semiconductor structure in Embodiment 1.
  • the stacked islands 311 include alternately stacked second semiconductor layers 315 and The third semiconductor layer 316, wherein the opposite sides of the island 311 in the stack along the vertical direction are the second semiconductor layers 315.
  • the material of the second semiconductor layer 315 is Alx1Iny1Ga1 -x1-y1 ; the material of the third semiconductor layer 316 is Alx2Iny2Ga1 -x2-y2N ; wherein X1, Y1, X2 and Y2 are selected from Values range from 0 to 1.
  • the laminated structure 30 includes three laminated structural units 31 ; each laminated structural unit 31 includes three laminated mid-islands 311 , and the three laminated mid-islands 311 are horizontal The directions are set separately from each other. .
  • Adjacent stacked structural units 31 may achieve partial overlap by sharing one stacked island 311 , but not limited to this, and may also achieve partial overlap by sharing two stacked central islands 311 ; or, adjacent stacked structural units 31 may not Overlapping, i.e. set apart from each other.
  • the laminated structure 30 includes two laminated structural units 31 ; each laminated structural unit 31 includes four laminated mid-islands 311 , and four laminated mid-islands 311 Set apart from each other in the horizontal direction. Adjacent stacked structural units 31 may partially overlap by sharing a stacked island 311 .
  • the embodiment in FIG. 5( c ) is the same as the embodiment in FIG. 5( b ), and will not be repeated here.
  • FIG. 5( a )- FIG. 5( c ) are for better showing the structure of the laminated structure 30 , rather than real existence.
  • another aspect of this embodiment further provides a method for preparing a semiconductor structure, which is used for preparing the above-mentioned semiconductor structure.
  • This preparation method is basically the same as the preparation method of embodiment 1, and its difference is:
  • the stacked island 311 includes alternately stacked second semiconductor layers 315 and third semiconductor layers 316 , wherein opposite sides of the stacked island 311 in the vertical direction are The second semiconductor layer 315 .
  • the material of the second semiconductor layer 315 is Alx1Iny1Ga1 -x1-y1 ; the material of the third semiconductor layer 316 is Alx2Iny2Ga1 -x2-y2N ; wherein X1, Y1, X2 and Y2 are selected from Values range from 0 to 1.
  • step S400 as shown in FIG. 6( b ), a stacked N-type semiconductor layer 40 , a light-emitting layer 50 and a P-type semiconductor layer 60 are formed on the plurality of stacked mid-islands 311 .
  • this embodiment also provides a semiconductor structure, which is basically the same as the semiconductor structure in Embodiment 1, except that the semiconductor structure does not include the substrate 10 and the nucleation layer. 20 , and the semiconductor structure further includes a reflective layer 70 and a transfer layer 80 .
  • another aspect of this embodiment further provides a method for preparing a semiconductor structure, which is used for preparing the above-mentioned semiconductor structure.
  • the preparation method includes all the steps of the preparation method of Example 1, and also includes:
  • Step S600 as shown in FIG. 8( a ), a reflective layer 70 is formed on the P-type semiconductor layer 60 , and the reflective layer 70 is fabricated by a chip process.
  • the reflective layer 70 is a metal layer.
  • the material of the metal layer is Ag; or, the metal layer includes a stacked first metal layer and a second metal layer; the material of the first metal layer is Ni, and the material of the second metal layer for Ag.
  • the reflective layer 70 includes a stacked indium tin oxide layer and a DBR layer. The DBR layer is formed by alternately stacking the first material layer of titanium oxide and the second material layer of silicon oxide.
  • Step S800 as shown in FIG. 8( c ), the nucleation layer 20 and the substrate 10 are peeled off.
  • the stacked structure of the semiconductor structure in this embodiment is not limited to a one-dimensional stacked structure, and may also be a two-dimensional stacked structure or a three-dimensional stacked structure.
  • the above descriptions are only preferred embodiments of the present application, and are not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application shall be included in the present application. within the scope of protection.

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Abstract

一种半导体结构，该半导体结构包括：层叠结构（30），所述层叠结构（30）包括一个层叠结构单元（31），或者多个沿水平方向设置的层叠结构单元（31）；每一所述层叠结构单元（31）包括多个沿水平方向相互分离的层叠中岛（311）；依次层叠设置在所述层叠结构（30）上的N型半导体层（40）、发光层（50）和P型半导体层（60）。通过设置层叠结构（30），能够提高半导体器件发光效率。

Description

半导体结构 技术领域
本申请涉及半导体领域，尤其涉及一种半导体结构。
背景技术
目前，在LED光电器件制造过程中，由于氮化镓本征衬底的缺乏，LED光电器件都是在异质衬底上制成，比如说蓝宝石、碳化硅和硅。
但是，由于氮化镓的高折射率，大部分的光到达LED光电器件的表面时被反射，使大量光线被局限于芯片内部，导致出光效率低。
因此，如何进一步提高LED光电器件的发光效率，仍然是目前亟待解决的难题。
发明内容
本申请提供一种半导体结构，能够提高半导体器件发光效率。
为实现上述目的，根据本申请实施例提供一种半导体结构，所述半导体结构包括：
层叠结构，所述层叠结构包括一个层叠结构单元，或者多个沿水平方向设置的层叠结构单元；每一所述层叠结构单元包括多个沿水平方向相互分离的层叠中岛；
依次层叠设置在所述层叠结构上的N型半导体层、发光层和P型半导体层。
可选的，所述层叠结构为光子晶体结构。
可选的，当所述层叠结构单元的数量为多个时，相邻的所述层叠结构单元部分重叠；或者，相邻的所述层叠结构单元相互分离设置。
可选的，所述层叠中岛包括依次层叠的缓冲层和第一半导体层。
可选的，所述层叠中岛包括交替层叠的第二半导体层和第三半导体层；
所述第二半导体层的材料为Al x1In y1Ga 1-x1-y1N；所述第三半导体层的材料为Al x2In y2Ga 1-x2-y2N；其中，X1、Y1、X2和Y2的取值范围均为0～1。
可选的，以所述层叠结构单元为最小重复单元构成所述层叠结构；
每一所述层叠结构单元中包括至少三个沿水平方向相互分离的所述层叠中岛。
可选的，所述层叠中岛的截面的形状为圆形或者多边形。
可选的，若所述层叠中岛的截面为圆形，所述层叠中岛的截面的直径小于或等于50um；
若所述层叠中岛的截面为多边形，所述层叠中岛的截面的最小外接圆的直径小于或等于50um。
可选的，相邻的所述层叠中岛之间具有间隙，所述N型半导体层与所述层叠结构邻接的一侧还形成有向远离所述层叠结构方向凹进的凹陷，所述凹陷对应于所述间隙形成。
可选的，所述层叠结构、所述N型半导体层、所述发光层和所述P型半导体层为外延工艺制成。
可选的，所述半导体结构还包括衬底和成核层：
沿竖直方向，所述成核层设置在所述衬底和所述层叠结构之间，所述成核层开设有凹槽，以形成多个沿水平方向相互分离的成核层中岛，每 一所述层叠中岛对应于每一所述成核层的中岛设置。
可选的，所述衬底的材料为蓝宝石、硅、碳化硅或者氮化镓。
可选的，所述半导体结构还包括：
反射层，沿竖直方向，所述反射层设置于所述P型半导体层远离所述发光层的一侧；
转移层，沿竖直方向，所述转移层设置于所述反射层远离所述P型半导体层的一侧。
可选的，所述反射层、所述转移层为芯片工艺制成。
可选的，所述反射层为金属层。
可选的，所述金属层的材料为Ag；或者，
所述金属层包括层叠的第一金属层和第二金属层，所述第一金属层的材料为Ni，所述第二金属层的材料为Ag。
可选的，所述反射层包括层叠的铟锡氧化物层和/或DBR层。
可选的，所述DBR层由第一材料层为氧化钛，和第二材料层为氧化硅交替层叠而成。
上述实施例的半导体结构中，设置层叠结构，并利用层叠中岛的排列周期的不同，达到选择性对光进行反射。这是因为，层叠中岛使层叠结构具有光子能带结构，随着能隙位置的不同，反射光的颜色也跟着变化，从而最终达到提高该半导体结构的发光效率。
附图说明
图1是本申请的实施例1的半导体结构的沿垂直方向的截面结构示意图。
图2(a)-图2(c)是本申请的实施例1的半导体结构的层叠结构的沿水平方向的截面结构示意图。
图3(a)-图3(d)是本申请的实施例1的半导体结构的制备方法的工艺流程图。
图4是本申请的实施例2的半导体结构的沿垂直方向的截面结构示意图。
图5(a)-图5(c)是本申请的实施例2的半导体结构的层叠结构的沿水平方向的截面结构示意图。
图6(a)-图6(b)是本申请的实施例2的半导体结构的制备方法的工艺流程图。
图7是本申请的实施例3的半导体结构的沿垂直方向的截面结构示意图。
图8(a)-图8(c)是本申请的实施例3的半导体结构的制备方法的工艺流程图。
具体实施方式
这里将详细地对示例性实施例进行说明，其示例表示在附图中。下面的描述涉及附图时，除非另有表示，不同附图中的相同数字表示相同或相似的要素。以下示例性实施例中所描述的实施方式并不代表与本申请相一致的所有实施方式。相反，它们仅是与如所附权利要求书中所详述的、本申请的一些方面相一致的装置和方法的例子。
在本申请使用的术语是仅仅出于描述特定实施例的目的，而非旨在限制本申请。除非另作定义，本申请使用的技术术语或者科学术语应当为本发明所属领域内具有一般技能的人士所理解的通常意义。本申请说明书 以及权利要求书中使用的“一个”或者“一”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似词语意指出现在“包括”或者“包含”前面的元件或者物件涵盖出现在“包括”或者“包含”后面列举的元件或者物件及其等同，并不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而且可以包括电性的连接，不管是直接的还是间接的。“多个”包括两个，相当于至少两个。在本申请说明书和所附权利要求书中所使用的单数形式的“一种”、“所述”和“该”也旨在包括多数形式，除非上下文清楚地表示其他含义。还应当理解，本文中使用的术语“和/或”是指并包含一个或多个相关联的列出项目的任何或所有可能组合。
实施例1
如图1和图2(a)-图2(c)所示，本实施例提供一种半导体结构。所述半导体结构包括：衬底10；设置在衬底10上的成核层20；设置在成核层20上的层叠结构30。
层叠结构30包括三个沿水平方向X设置的层叠结构单元31。以所述层叠结构单元31为最小重复单元构成所述层叠结构30，即，层叠结构单元31为层叠结构30的可以重复的最小单元。在其他实施例中，层叠结构30可以仅包括一个层叠结构单元31；或者，层叠结构30可以包括两个层叠结构单元31，或者四个层叠结构单元31，或者其他数量的层叠结构单元31。
每一层叠结构单元31包括多个沿水平方向X相互分离的层叠中岛311。较佳的，每一层叠结构单元31包括至少三个沿水平方向X相互分离的层叠中岛311依次层叠设置在层叠结构30上的N型半导体层40、发光层50和P型半导体层60。其中，层叠结构30、N型半导体层40、发光层50和P型半导体层60为外延工艺制成。
成核层20开设有凹槽21，以形成多个沿水平方向X相互分离的成核层中岛，每一层叠中岛311对应于每一成核层中岛设置。
相邻的层叠中岛311之间具有间隙312，N型半导体层40与层叠结构30邻接的一侧还形成有向远离层叠结构30方向凹进的凹陷41，凹陷41对应于间隙312形成。
衬底10的材料为蓝宝石、硅、碳化硅或氮化镓。成核层20的材料为AlN。
在本实施例中，层叠结构30为多层材料的叠层结构，也就是说，层叠中岛311包括依次层叠的缓冲层313和第一半导体层314。第一半导体层314的材料为三族氮化物。
层叠中岛311的截面的形状可以为圆形、或者多边形。如图2(a)所示，层叠中岛311的截面的形状为圆形。若层叠中岛311的截面为圆形，层叠中岛311的截面的直径R小于或等于50um。从图2(a)中可以看出，在该实施方式中，层叠结构30包括三个层叠结构单元31；每一层叠结构单元31包括三个层叠中岛311，三个层叠中岛311沿水平方向相互分离设置。相邻的层叠结构单元31可以通过共用一个层叠中岛311实现部分重叠，但不限于此，也可以通过共用两个层叠中岛311实现部分重叠；或者，相邻的层叠结构单元31也可以不重叠，即相互分离设置。
当层叠中岛311的截面的形状为多边形时，优选的，层叠中岛311的截面的形状为六边形，如图2(b)所示。但不限于此，层叠中岛311的截面的形状也可以为其他的多边形，如图2(c)所示，层叠中岛311的截面的形状为矩形，或者，也可以为其他的多边形形状，如三角形、四边形、六边形等，层叠中岛311的截面的最小外接圆的直径小于或等于50um。
同样，从图2(b)中可以看出，在该实施方式中，层叠结构30包括两个层叠结构单元31；每一层叠结构单元31包括四个层叠中岛311，四 个层叠中岛311沿水平方向相互分离设置。相邻的层叠结构单元31可以通过共用一个层叠中岛311实现部分重叠。图2(c)中的实施方式与图2(b)中实施方式相同，在此不再累述。
需要说明的是，在图2(a)-图2(c)中的虚线是为了更好的展示层叠结构30的结构，而非真实存在。
图3(a)-图3(d)是本申请的实施例1的半导体结构的制备方法的工艺流程图。该制备方法包括：
S100：如图3(a)所示，沿垂直方向Y在衬底10上形成成核层20。衬底10的材料为蓝宝石、硅、碳化硅或氮化镓。成核层20的材料为AlN。
S200：如图3(b)所示，在成核层20上开设凹槽21，以形成多个沿水平方向X相互分离的成核层中岛。
S300：如图3(c)所示，在成核层20上形成多个沿水平方向X相互分离的层叠中岛311；每一层叠中岛311形成于每一成核层中岛之上。其中，层叠中岛311包括依次层叠的缓冲层313和第一半导体层314。第一半导体层314的材料为三族氮化物。
层叠中岛311的截面的形状可以为圆形、或者多边形。若层叠中岛311的截面为圆形，层叠中岛311的截面的直径小于或等于50um；当层叠中岛311的截面的形状为多边形时，优选的，层叠中岛311的截面的形状为六边形，但不限于此，层叠中岛311的截面的形状也可以为其他的多边形，层叠中岛311的截面的最小外接圆的直径小于或等于50um。层叠结构30为外延工艺制成。
S400：如图3(d)所示，在所述多个层叠中岛311上一层形成层叠设置的N型半导体层40、发光层50和P型半导体层60。N型半导体层40、发光层50和P型半导体层60为外延工艺制成。
本实施例中的半导体结构，通过设置层叠结构30，并利用层叠中岛 311的排列周期的不同，达到选择性对光进行反射。这是因为，层叠中岛311使层叠结构30具有光子能带结构，随着能隙位置的不同，反射光的颜色也跟着变化，从而最终达到提高该半导体结构的发光效率。
实施例2
如图4所示，本实施例还提供一种半导体结构，该半导体结构与实施例1中的半导体结构的结构基本相同，本实施例中层叠中岛311包括交替层叠的第二半导体层315和第三半导体层316，其中，层叠中岛311沿竖直方向相对的两侧均为第二半导体层315。
第二半导体层315的材料为Al x1In y1Ga 1-x1-y1；第三半导体层316的材料为Al x2In y2Ga 1-x2-y2N；其中，X1、Y1、X2和Y2的取值范围均为0～1。
层叠中岛311的截面的形状可以为圆形、或者多边形。如图5(a)所示，层叠中岛311的截面的形状为圆形。若层叠中岛311的截面为圆形，层叠中岛311的截面的直径小于或等于50um。
从图5(a)中可以看出，在该实施方式中，层叠结构30包括三个层叠结构单元31；每一层叠结构单元31包括三个层叠中岛311，三个层叠中岛311沿水平方向相互分离设置。。相邻的层叠结构单元31可以通过共用一个层叠中岛311实现部分重叠，但不限于此，也可以通过共用两个层叠中岛311实现部分重叠；或者，相邻的层叠结构单元31也可以不重叠，即相互分离设置。
当层叠中岛311的截面的形状为多边形时，优选的，层叠中岛311的截面的形状为菱形，如图5(b)所示。但不限于此，层叠中岛311的截面的形状也可以为其他的多边形，如图5(c)所示，层叠中岛311的截面的形状为四边形，或者，也可以为其他的多边形形状，如三角形、六边形等，层叠中岛311的截面的最小外接圆的直径小于或等于50um。
同样，从图5(b)中可以看出，在该实施方式中，层叠结构30包括两个层叠结构单元31；每一层叠结构单元31包括四个层叠中岛311，四个层叠中岛311沿水平方向相互分离设置。相邻的层叠结构单元31可以通过共用一个层叠中岛311实现部分重叠。图5(c)中的实施方式与图5(b)中实施方式相同，在此不再累述。
需要说明的是，在图5(a)-图5(c)中的虚线是为了更好的展示层叠结构30的结构，而非真实存在。
如图6(a)-图6(b)所示，本实施例的另一个方面还提供一种半导体结构的制备方法，用于制备上述半导体结构。该制备方法与实施例1的制备方法基本相同，其不同之处在于：
在步骤S300中，如图6(a)所示，层叠中岛311包括交替层叠的第二半导体层315和第三半导体层316，其中，层叠中岛311沿竖直方向相对的两侧均为第二半导体层315。第二半导体层315的材料为Al x1In y1Ga 1-x1-y1；第三半导体层316的材料为Al x2In y2Ga 1-x2-y2N；其中，X1、Y1、X2和Y2的取值范围均为0～1。
在步骤S400中，如图6(b)所示，在所述多个层叠中岛311上一层形成层叠设置的N型半导体层40、发光层50和P型半导体层60。
实施例3
如图7所示，本实施例还提供一种半导体结构，该半导体结构与实施例1中的半导体结构的结构基本相同，其不同之处在于：该半导体结构不包括衬底10及成核层20，且半导体结构还包括反射层70和转移层80。
沿竖直方向Y，反射层70设置于P型半导体层60远离发光层50的一侧。沿竖直方向Y，转移层80设置于反射层70远离P型半导体层60的一侧。反射层70、转移层80为芯片工艺制成。
较佳的，反射层70为金属层。优选的，金属层的材料为Ag；或者，金属层包括层叠的第一金属层和第二金属层；第一金属层的材料为Ni，第二金属层的材料为Ag。但不限于此，在其他实施例中，反射层70包括层叠的铟锡氧化物层和/或DBR层。DBR层由第一材料层为氧化钛，和第二材料层为氧化硅交替层叠而成。
如图8(a)-图8(c)本实施例的另一个方面还提供一种半导体结构的制备方法，用于制备上述半导体结构。该制备方法包括实施例1的制备方法全部步骤，并且还包括：
步骤S600：如图8(a)所示，在P型半导体层60上形成反射层70，反射层70为芯片工艺制成。较佳的，反射层70为金属层。优选的，所述金属层的材料为Ag；或者，所述金属层包括层叠的第一金属层和第二金属层；所述第一金属层的材料为Ni，所述第二金属层的材料为Ag。但不限于此，在其他实施例中，反射层70包括层叠的铟锡氧化物层和DBR层。所述DBR层由第一材料层为氧化钛，和第二材料层为氧化硅交替层叠而成。
步骤S700：如图8(b)所示，在反射层70上形成转移层80。转移层80为芯片工艺制成。
步骤S800：如图8(c)所示，剥离成核层20以及衬底10。
本实施例中的半导体结构的层叠结构不限于一维层叠结构，也可以是二维层叠结构或者三维层叠结构。以上所述仅为本申请的较佳实施例而已，并不用以限制本申请，凡在本申请的精神和原则之内，所做的任何修改、等同替换、改进等，均应包含在本申请保护的范围之内。

Claims (18)

  1. 一种半导体结构，其特征在于，所述半导体结构包括：
    层叠结构(30)，所述层叠结构(30)包括多个沿水平方向设置的层叠结构单元(31)；每一所述层叠结构单元(31)包括多个沿水平方向相互分离的层叠中岛(311)；
    依次层叠设置在所述层叠结构(30)上的N型半导体层(40)、发光层(50)和P型半导体层(60)。
  2. 如权利要求1所述的半导体结构，其特征在于，所述层叠结构(30)为光子晶体结构。
  3. 如权利要求1所述的半导体结构，其特征在于，当所述层叠结构单元(31)的数量为多个时，相邻的所述层叠结构单元(31)部分重叠；或者，相邻的所述层叠结构单元(31)相互分离设置。
  4. 如权利要求1所述的半导体结构，其特征在于，所述层叠中岛(311)包括依次层叠的缓冲层(313)和第一半导体层(314)。
  5. 如权利要求1所述的半导体结构，其特征在于，所述层叠中岛包括交替层叠的第二半导体层(315)和第三半导体层(316)；
    所述第二半导体层(315)的材料为Al x1In y1Ga 1-x1-y1N；所述第三半导体层(316)的材料为Al x2In y2Ga 1-x2-y2N；其中，X1、Y1、X2和Y2的取值范围均为0～1。
  6. 如权利要求1所述的半导体结构，其特征在于，所述层叠结构单元(31)为最小重复单元构成所述层叠结构(30)；
    每一所述层叠结构单元(31)中包括至少三个沿水平方向相互分离的所述层叠中岛(311)。
  7. 如权利要求1所述的半导体结构，其特征在于，所述层叠中岛(311)的截面的形状为圆形、或者多边形。
  8. 如权利要求7所述的半导体结构，其特征在于，
    若所述层叠中岛(311)的截面为圆形，所述层叠中岛(311)的截面的直径小于或等于50um；
    若所述层叠中岛(311)的截面为多边形，所述层叠中岛(311)的截面的最小外接圆的直径小于或等于50um。
  9. 如权利要求1所述的半导体结构，其特征在于，相邻的所述层叠中岛(311)之间具有间隙(312)，所述N型半导体层(40)与所述层叠结构(30)邻接的一侧还形成有向远离所述层叠结构(30)方向凹进的凹陷(41)，所述凹陷(41)对应于所述间隙(312)形成。
  10. 如权利要求1所述的半导体结构，其特征在于，所述层叠结构(30)、N型半导体层(40)、所述发光层(50)和所述P型半导体层(60)为外延工艺制成。
  11. 如权利要求1-10中任意一项所述的半导体结构，其特征在于，所述半导体结构还包括衬底(10)和成核层(20)：
    沿竖直方向，所述成核层(20)设置在所述衬底(10)和所述层叠结构(30)之间，所述成核层(20)开设有凹槽(21)，以形成多个沿水平方向相互分离的成核层中岛，每一所述层叠中岛(311)对应于每一所述成核层中岛设置。
  12. 如权利要求11所述的半导体结构，其特征在于，所述衬底(10)的材料为蓝宝石、硅、碳化硅或者氮化镓。
  13. 如权利要求1-10中任意一项所述的半导体结构，其特征在于，所述半导体结构还包括：
    反射层(70)，沿竖直方向，所述反射层(70)设置于所述P型半导体层(60)远离所述发光层(50)的一侧；
    转移层(80)，沿竖直方向，所述转移层(80)设置于所述反射层(70)远离所述P型半导体层(60)的一侧。
  14. 如权利要求13所述的半导体结构，其特征在于，所述反射层(70)、所述转移层(80)为芯片工艺制成。
  15. 如权利要求13所述的半导体结构，其特征在于，所述反射层(70)为金属层。
  16. 如权利要求15所述的半导体结构，其特征在于，所述金属层的材料为银；或者，所述金属层包括层叠的第一金属层和第二金属层，所述第一金属层的材料为Ni，所述第二金属层的材料为Ag。
  17. 如权利要求13所述的半导体结构，其特征在于，所述反射层(70)包括层叠的铟锡氧化物层和/或DBR层。
  18. 如权利要求17所述的半导体结构，其特征在于，所述DBR层由第一材料层为氧化钛，和第二材料层为氧化硅交替层叠而成。
PCT/CN2020/129774 2020-11-18 2020-11-18 半导体结构 WO2022104594A1 (zh)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050145872A1 (en) * 2003-12-24 2005-07-07 Chao-Yi Fang High performance nitride-based light-emitting diodes
CN101442090A (zh) * 2007-11-21 2009-05-27 财团法人工业技术研究院 发光二极管及其制造方法
CN201773861U (zh) * 2010-03-26 2011-03-23 厦门市三安光电科技有限公司 侧面具有锯齿状孔洞的氮化镓基高亮度发光二极管
CN103035797A (zh) * 2012-12-11 2013-04-10 东南大学 完全禁带光子晶体结构、其制备方法及一种发光二极管

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050145872A1 (en) * 2003-12-24 2005-07-07 Chao-Yi Fang High performance nitride-based light-emitting diodes
CN101442090A (zh) * 2007-11-21 2009-05-27 财团法人工业技术研究院 发光二极管及其制造方法
CN201773861U (zh) * 2010-03-26 2011-03-23 厦门市三安光电科技有限公司 侧面具有锯齿状孔洞的氮化镓基高亮度发光二极管
CN103035797A (zh) * 2012-12-11 2013-04-10 东南大学 完全禁带光子晶体结构、其制备方法及一种发光二极管

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