WO2022102400A1 - Imaging device - Google Patents

Imaging device Download PDF

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Publication number
WO2022102400A1
WO2022102400A1 PCT/JP2021/039570 JP2021039570W WO2022102400A1 WO 2022102400 A1 WO2022102400 A1 WO 2022102400A1 JP 2021039570 W JP2021039570 W JP 2021039570W WO 2022102400 A1 WO2022102400 A1 WO 2022102400A1
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Prior art keywords
pixel
barrier
opb
layer
sensor
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PCT/JP2021/039570
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French (fr)
Japanese (ja)
Inventor
忍 朝山
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ソニーセミコンダクタソリューションズ株式会社
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Publication of WO2022102400A1 publication Critical patent/WO2022102400A1/en

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144Devices controlled by radiation
    • H01L27/146Imager structures
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/60Noise processing, e.g. detecting, correcting, reducing or removing noise
    • H04N25/63Noise processing, e.g. detecting, correcting, reducing or removing noise applied to dark current
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70SSIS architectures; Circuits associated therewith

Definitions

  • This disclosure relates to an image pickup device.
  • an image pickup apparatus includes pixels arranged in a pixel region that receives light from a subject (hereinafter, normal pixels) and pixels arranged in an optical black region in which light from a subject is shielded.
  • a pixel having a photodiode (PD) hereinafter, a pixel with PD
  • a pixel without PD hereinafter, a pixel without PD
  • the dark current component is calculated by subtracting the voltage signal corresponding to the noise component of the none pixel.
  • a contact plug is provided in the pixel without PD, and by applying a positive voltage to the pixel without PD through the contact plug, the dark charge generated in the pixel without PD is discharged. Is disclosed.
  • the PD-less pixel is provided with a contact plug for receiving a positive voltage supply (that is, for charge reset), and there are many layout restrictions. If there is a large difference in layout between the pixels with PD and the pixels without PD, the photoelectric conversion efficiency and wiring capacity will not be equivalent between these pixels, and there is a possibility that an error will occur in the calculation of the dark current component. If this error is large, the image quality may deteriorate.
  • the present disclosure has been made in view of such circumstances, and an object of the present disclosure is to provide an image pickup apparatus capable of suppressing deterioration of image quality.
  • the image pickup apparatus includes a pixel region provided in the semiconductor layer and receiving light from a subject, and an optical black region provided in the semiconductor layer in which the light is shielded.
  • the optical black region has a first pixel having a sensor function of detecting the light and outputting a signal, and a second pixel having no sensor function. Between the first pixel and the second pixel adjacent to each other, there is a first barrier that hinders the movement of electric charges. There is a second barrier that hinders the movement of electric charges between the second pixels that are adjacent to each other. The second barrier has a deeper potential than the first barrier.
  • the second barrier there is one or more regions in which the second barrier exists around the second pixel.
  • the charges exceeding the capacity that can be stored in the second pixel exceed the second barrier and overflow to the other adjacent second pixels.
  • there is a first barrier between the first pixel and the second pixel but there is no second barrier. Since the first barrier has a shallower potential than the second barrier, the transfer of electric charge from the second pixel to the first pixel is suppressed. Thereby, the image pickup apparatus can suppress the occurrence of a defect (for example, whitening) in the output of the first pixel due to the overflow of the electric charge from the second pixel.
  • a defect for example, whitening
  • the image pickup apparatus can reduce the difference in layout between the first pixel and the second pixel, and can make the photoelectric conversion efficiency and the wiring capacity equivalently close to each other between the first pixel and the second pixel. .. As a result, the image pickup apparatus can reduce the possibility of an error in the calculation of the dark current component, and thus can suppress the deterioration of the image quality.
  • FIG. 1 is a block diagram showing a configuration example of the image pickup apparatus according to the first embodiment of the present disclosure.
  • FIG. 2 is a plan view showing a configuration example of the pixel array unit according to the first embodiment of the present disclosure.
  • FIG. 3 is a cross-sectional view showing a configuration example of an OPB region of the pixel array unit according to the first embodiment of the present disclosure.
  • FIG. 4 is a diagram showing an example of the potential distribution of the OPB region according to the first embodiment of the present disclosure.
  • FIG. 5 is a diagram showing an example of the potential distribution of the OPB region according to the first embodiment of the present disclosure.
  • FIG. 6 is a diagram showing an image quality image of the OPB region according to the first embodiment of the present disclosure.
  • FIG. 1 is a block diagram showing a configuration example of the image pickup apparatus according to the first embodiment of the present disclosure.
  • FIG. 2 is a plan view showing a configuration example of the pixel array unit according to the first embodiment of the present disclosure.
  • FIG. 7A is a cross-sectional view showing a configuration example of an OPB pixel with a sensor according to the first embodiment of the present disclosure.
  • FIG. 7B is a plan view showing a configuration example of the N + layer and the P + layer of the OPB pixel with a sensor according to the first embodiment of the present disclosure.
  • FIG. 8A is a cross-sectional view showing a configuration example of a sensorless OPB pixel according to the first embodiment of the present disclosure.
  • FIG. 8B is a plan view showing a configuration example of the N + layer and the P + layer of the OPB pixel without a sensor according to the first embodiment of the present disclosure.
  • FIG. 9 is a cross-sectional view showing a configuration example of the OPB region according to the first embodiment of the present disclosure.
  • FIG. 10 is a diagram showing the potential distribution of the OPB region according to the comparative example of the present disclosure.
  • FIG. 11 is a diagram showing an image quality image of the OPB region according to the comparative example of the present disclosure.
  • FIG. 12 is a cross-sectional view showing the configuration of an OPB pixel with a sensor according to a modification of the first embodiment of the present disclosure.
  • FIG. 13 is a cross-sectional view showing the configuration of the OPB pixel without a sensor according to the modified example of the first embodiment of the present disclosure.
  • FIG. 14A is a cross-sectional view showing a configuration example of an OPB pixel with a sensor according to the second embodiment of the present disclosure.
  • FIG. 14B is a plan view showing a configuration example of the N + layer and the DTI layer of the OPB pixel with a sensor according to the second embodiment of the present disclosure.
  • FIG. 15A is a cross-sectional view showing a configuration example of a sensorless OPB pixel according to the second embodiment of the present disclosure.
  • FIG. 15B is a plan view showing a configuration example of the N + layer and the DTI layer of the OPB pixel without a sensor according to the second embodiment of the present disclosure.
  • FIG. 16 is a cross-sectional view showing the configuration of an OPB pixel with a sensor according to a modification of the second embodiment of the present disclosure.
  • FIG. 17 is a cross-sectional view showing the configuration of the OPB pixel without a sensor according to the modified example of the second embodiment of the present disclosure.
  • FIG. 18 is a cross-sectional view showing a configuration example of the OPB region according to the third embodiment of the present disclosure.
  • the direction may be explained using the words in the X-axis direction, the Y-axis direction, and the Z-axis direction.
  • the X-axis direction and the Y-axis direction are directions parallel to one surface 10a of the semiconductor layer 10, which will be described later.
  • the X-axis direction and the Y-axis direction are also referred to as horizontal directions.
  • the Z-axis direction is the normal direction of one surface 10a.
  • the X-axis direction, the Y-axis direction, and the Z-axis direction are orthogonal to each other.
  • the first conductive type is P type and the second conductive type is N type will be exemplified.
  • the conductive type may be selected in the opposite relationship, the first conductive type may be N type, and the second conductive type may be P type.
  • + (or-) attached to P or N is a semiconductor layer having a relatively high (or low) impurity concentration as compared with the semiconductor layer not marked with + (or-). Means. However, even if the semiconductor layers have the same P and P (or the same N and N), it does not mean that the impurity concentrations of the respective semiconductor layers are exactly the same.
  • FIG. 1 is a block diagram showing a configuration example of the image pickup apparatus 1 according to the first embodiment of the present disclosure.
  • the image pickup device 1 shown in FIG. 1 is, for example, a back-illuminated solid-state image pickup device.
  • the image pickup apparatus 1 includes a pixel array unit 12, a vertical drive circuit 13, a column signal processing circuit 14, a horizontal drive circuit 15, an output circuit 16, and a control circuit 17.
  • the pixel array unit 12 has a normal pixel area R0 (an example of the “pixel area” of the present disclosure) and an optical black (hereinafter, OPB) area arranged around the normal pixel area R0. It has R1 and.
  • the normal pixel region R0 is a light receiving region that receives light collected by an optical system (not shown), and has a plurality of pixels 21.
  • the plurality of pixels 21 are arranged in a matrix.
  • the plurality of pixels 21 are connected to the vertical drive circuit 13 row by row via the horizontal signal line 22, and are connected to the column signal processing circuit 14 column by column via the vertical signal line 23.
  • Each of the plurality of pixels 21 outputs a pixel signal at a level corresponding to the amount of light received.
  • An image of the subject is constructed from those pixel signals.
  • the vertical drive circuit 13 sequentially supplies drive signals for driving (transfer, selection, reset, etc.) of each pixel 21 to the pixels 21 via the horizontal signal line 22 for each row of the plurality of pixels 21. ..
  • the column signal processing circuit 14 performs AD conversion of the pixel signal by performing CDS (Correlated Double Sampling) processing on the pixel signal output from the plurality of pixels 21 via the vertical signal line 23. At the same time, remove the reset noise.
  • the horizontal drive circuit 15 sequentially supplies a drive signal for outputting a pixel signal from the column signal processing circuit 14 to the data output signal line 24 to the column signal processing circuit 14 for each row of the plurality of pixels 21.
  • the output circuit 16 amplifies the pixel signal supplied from the column signal processing circuit 14 via the data output signal line 24 at the timing according to the drive signal of the horizontal drive circuit 15, and outputs the pixel signal to the signal processing circuit in the subsequent stage.
  • the control circuit 17 controls the drive of each block inside the image pickup apparatus 1. For example, the control circuit 17 generates a clock signal according to the drive cycle of each block and supplies it to each block.
  • the pixel 21 includes a photodiode 31, a transfer transistor 32, a floating diffusion FD, an amplification transistor 34, a selection transistor 35, and a reset transistor 36.
  • the transfer transistor 32, the floating diffusion FD, the amplification transistor 34, the selection transistor 35, and the reset transistor 36 constitute a read circuit 30 that reads out the charge (pixel signal) photoelectrically converted by the photodiode 31.
  • the photodiode 31 is a photoelectric conversion unit that converts incident light into electric charges by photoelectric conversion and stores them.
  • the anode terminal is grounded and the cathode terminal is connected to the transfer transistor 32.
  • a transfer signal TRG is supplied from the vertical drive circuit 13 to the gate electrode TG of the transfer transistor 32.
  • the transfer transistor 32 is driven according to the transfer signal TRG supplied to the gate electrode TG.
  • the transfer transistor 32 is turned on, the charge stored in the photodiode 31 is transferred to the floating diffusion FD.
  • the floating diffusion FD is a floating diffusion region having a predetermined storage capacity connected to the gate electrode of the amplification transistor 34, and temporarily stores the charge transferred from the photodiode 31.
  • the amplification transistor 34 outputs a pixel signal at a level corresponding to the electric charge stored in the floating diffusion FD (that is, the potential of the floating diffusion FD) to the vertical signal line 23 via the selection transistor 35. That is, due to the configuration in which the floating diffusion FD is connected to the gate electrode of the amplification transistor 34, the floating diffusion FD and the amplification transistor 34 amplify the electric charge generated in the photodiode 31 and convert it into a pixel signal at a level corresponding to the electric charge. Functions as a conversion unit.
  • the selection transistor 35 is driven according to the selection signal SEL supplied from the vertical drive circuit 13, and when the selection transistor 35 is turned on, the pixel signal output from the amplification transistor 34 can be output to the vertical signal line 23.
  • the reset transistor 36 is driven according to the reset signal RST supplied from the vertical drive circuit 13, and when the reset transistor 36 is turned on, the electric charge accumulated in the floating diffusion FD is discharged to the power supply line Vdd, and the floating diffusion FD becomes the floating diffusion FD. It will be reset.
  • FIG. 2 is a plan view showing a configuration example of the pixel array unit 12 according to the first embodiment of the present disclosure.
  • the OPB region R1 is shown larger than the normal pixel region R0.
  • the OPB area R1 is usually arranged around the pixel area R0.
  • the OPB region R1 has a plurality of light-shielded pixels, and the signal output from these pixels is used as a reference for the black level of the pixels of the normal pixel region.
  • the OPB region R1 is symmetrically arranged vertically and horizontally in the normal pixel region R0 in a plan view in order to realize, for example, a vertical inversion that inverts the captured image up and down and a left-right inversion drive that inverts the left and right. ing.
  • the OPB region R1 has an OPB pixel region R11 with a sensor, an OPB pixel region R12 without a sensor, and an overflow drain pixel region R13.
  • the overflow / drain pixel area R13, the OPB pixel area R11 with the sensor, the OPB pixel area R12 without the sensor, and the overflow / drain pixel area R13 are arranged in this order from the normal pixel area R0 toward the outside of the normal pixel area R0. ..
  • the charge e- for example, the dark current component
  • FIG. 3 is a cross-sectional view showing a configuration example of the OPB region R1 of the pixel array unit 12 according to the first embodiment of the present disclosure.
  • the cross-sectional view shown in FIG. 3 corresponds to a cross-sectional view obtained by cutting the plan view shown in FIG. 2 along the AA'line.
  • the pixel array unit 12 includes a semiconductor layer 10 having a normal pixel region R0 (see FIG. 2) and an OPB region R1, and a light-shielding metal 90 provided on one surface 10a of the semiconductor layer 10. And a color filter CF provided on the light-shielding metal 90, and a microlens ML provided on the color filter CF.
  • one surface 10a side of the semiconductor layer 10 is the back surface side of the image pickup apparatus 1.
  • the semiconductor layer 10 is made of, for example, silicon (Si).
  • the semiconductor layer 10 may be composed of a single crystal silicon substrate, or may be a silicon layer formed on the silicon substrate by an epitaxial growth method.
  • the semiconductor layer 10 is provided with an OPB pixel region R11 with a sensor, an OPB pixel region R12 without a sensor, and an overflow drain pixel region R13, respectively.
  • the light-shielding metal 90 is provided, for example, in a part of the normal pixel region R0 (for example, between one adjacent pixel 21 and the other pixel 21) and in the entire OPB region R1.
  • the color filter CF and the microlens ML are provided continuously, for example, from the normal pixel region R0 to the OPB region R1.
  • the light-shielding metal 90 is continuously provided above the OPB pixel region R11 with a sensor, above the OPB pixel region R12 without a sensor, and above the overflow drain pixel region R13.
  • a color filter CF and a microlens ML are provided above the OPB pixel region R11 with a sensor, above the OPB pixel region R12 without a sensor, and above the overflow drain pixel region R13 via a light-shielding metal 90.
  • the OPB pixel region R11 with a sensor, the OPB pixel region R12 without a sensor, and the overflow drain pixel region R13 are shielded from light by a light-shielding metal 90.
  • the sensor-equipped OPB pixel region R11 has a sensor-equipped OPB pixel 50 (an example of the “first pixel” of the present disclosure).
  • the OPB pixel region R11 with a sensor has a plurality of sensors arranged side by side in the X-axis direction and the Y-axis direction (that is, the horizontal direction), respectively. It may have the present OPB pixel 50.
  • the OPB pixel 50 with a sensor has the same configuration as the pixel 21 provided in the normal pixel region R0, except that the upper part thereof is shielded from light by the light-shielding metal 90.
  • the sensorless OPB pixel region R12 has a sensorless OPB pixel 60 (an example of the "second pixel" of the present disclosure). In FIG. 3, four sensorless OPB pixels 60 arranged in the Y-axis direction are shown, but this is merely an example.
  • the sensorless OPB pixel region R12 may have a plurality of sensorless OPB pixels 60 arranged side by side in the X-axis direction and the Y-axis direction, respectively.
  • the overflow-drain pixel region R13 has an overflow-drain pixel 70 (an example of the "third pixel" of the present disclosure). Although only one overflow / drain pixel 70 is shown in FIG. 3, the overflow / drain pixel region R13 may have a plurality of overflow / drain pixels 70 arranged side by side in the X-axis direction and the Y-axis direction, respectively. ..
  • a barrier ⁇ BA1 (an example of the “first barrier” of the present disclosure) that hinders the movement of the electric charge e ⁇ exists between the OPB pixel 50 with a sensor and the OPB pixel 60 without a sensor adjacent to each other. do.
  • a barrier ⁇ BA2 (an example of the “second barrier” of the present disclosure) that hinders the movement of the electric charge e ⁇ .
  • a barrier ⁇ BA3 (an example of the “third barrier” of the present disclosure) that hinders the movement of the electric charge e ⁇ .
  • the space between one adjacent pixel and the other pixel is also referred to as "between adjacent pixels”.
  • FIG. 4 and 5 are diagrams showing an example of the potential distribution of the OPB region R1 according to the first embodiment of the present disclosure.
  • the barrier ⁇ BA2 existing between the adjacent pixels of the OPB pixels 60 without the sensor has a deeper potential than the barrier ⁇ BA1 existing between the adjacent pixels of the OPB pixel 50 with the sensor and the OPB pixel 60 without the sensor. .. ⁇ BA2- ⁇ BA1> 0.
  • deep potential may be paraphrased as “high potential” or “high potential”, or may be paraphrased as “low barrier height” in view of the electric charge e-.
  • shallow potential may be paraphrased as “low potential” or “low potential”, or may be paraphrased as "high barrier height” in view of the electric charge e ⁇ .
  • the barrier ⁇ BA3 existing between the adjacent pixels of the OPB pixel 60 without the sensor and the overflow drain pixel 70 has a deeper potential than the barrier ⁇ BA1.
  • the potential of the barrier ⁇ BA2 and the potential of the barrier ⁇ BA3 are, for example, the same depth as each other.
  • ⁇ BA2 ⁇ BA3.
  • the potential ⁇ Sens1 of the OPB pixel 50 with a sensor has a deeper potential than the barriers ⁇ BA1 and ⁇ BA2, respectively.
  • the potential ⁇ Sens1 of the OPB pixel 50 with a sensor is, for example, the potential of the N + layer 110 (see FIG. 7A described later) in the OPB pixel 50 with a sensor.
  • the sensor-equipped OPB pixel 50 has a gate electrode TG1 (an example of the "first gate electrode” of the present disclosure) for transferring the electric charge generated by the sensor-equipped OPB pixel 50.
  • the OPB pixel 50 with a sensor is connected to the floating diffusion FD via a transfer transistor 32 (see FIG. 1) having a gate electrode TG1.
  • a transfer transistor 32 (see FIG. 1) having a gate electrode TG1.
  • the transfer gate is turned on and the charge e- accumulated in the OPB pixel 50 with a sensor becomes. Transferred to the floating diffusion FD.
  • the potential ⁇ Sens2 of the OPB pixel 60 without a sensor has a deeper potential than each of the barriers ⁇ BA1 and ⁇ BA2.
  • the potential ⁇ Sens2 of the OPB pixel 60 without a sensor is, for example, the potential of the N + layer 110 (see FIG. 8A described later) in the OPB pixel 60 without a sensor.
  • the potential ⁇ Sens3 of the overflow / drain pixel 70 has a deeper potential than each of the barriers ⁇ BA1, ⁇ BA2, and ⁇ BA3.
  • the potential ⁇ Sens3 of the overflow drain pixel 70 is, for example, the potential of the N + layer 110 (see FIG. 9 described later) in the overflow drain pixel 70.
  • the charge e- (for example, the dark current component) generated in the OPB pixel 60 without a sensor
  • the charge e- overflowing in the OPB pixel 60 without a sensor is larger than exceeding the barrier ⁇ BA1 due to the magnitude relationship of the barrier height described above. , It is easier to exceed the barriers ⁇ BA2 and ⁇ BA3.
  • the charge e-overflowing in the OPB pixel 60 without the sensor is suppressed from moving to the OPB pixel 50 with the sensor by the barrier ⁇ BA1 and moves to the OPB pixel 60 without the sensor or the adjacent overflow drain pixel 70. ..
  • the overflow / drain pixel 70 is connected to the floating diffusion FD via, for example, a transfer transistor 32 (see FIG. 1) having a gate electrode TG3.
  • the floating diffusion FD is connected to a positive power line Vdd (an example of the "preset positive potential" of the present disclosure), for example, via a reset transistor 36 (see FIG. 1).
  • the transfer gate is turned on and the charge e- accumulated in the overflow drain pixel 70 is a floating diffusion. It is discharged to the positive power line Vdd via the FD.
  • the transfer gate of the overflow / drain pixel 70 may be on (that is, always on) in a state where no voltage is applied to the third gate electrode. As a result, the overflow / drain pixel 70 is constantly discharged to the positive power supply line Vdd.
  • the OPB pixel 60 without a sensor has a gate electrode TG2 (an example of the “second gate electrode” of the present disclosure) having the same structure as the gate electrode TG1 (see FIG. 4).
  • a gate electrode TG2 an example of the “second gate electrode” of the present disclosure
  • the barrier ⁇ BA2 has a deeper potential (that is, the barrier height is lower) than the barrier ⁇ TG2.
  • the potential of the barrier ⁇ TG2 is the same depth when a voltage is applied to the gate electrode TG2 and when a voltage is not applied to the gate electrode TG.
  • the potential of the barrier ⁇ TG2 has a constant depth regardless of whether a voltage is applied to the gate electrode TG2 or not.
  • the charge e-overflowing in the sensorless OPB pixel 60 is suppressed from moving to the floating diffusion FD by the barrier ⁇ TG2, and moves to the adjacent sensorless OPB pixel 60 or the adjacent overflow drain pixel 70.
  • FIG. 6 is a diagram showing an image quality image of the OPB region R1 according to the first embodiment of the present disclosure.
  • the charge e-overflowing in the OPB pixel 60 without the sensor is suppressed from moving to the OPB pixel 50 with the sensor by the barrier ⁇ BA1, and the movement to the floating diffusion FD is suppressed by the barrier ⁇ TG2.
  • the OPB pixel region R11 with a sensor has a defect in the output of the OPB pixel 50 with a sensor adjacent to the OPB pixel region R12 without a sensor (for example, whitening as shown in FIG. 6 described later). ) Can be suppressed.
  • FIG. 7A is a cross-sectional view showing a configuration example of the OPB pixel 50 with a sensor according to the first embodiment of the present disclosure.
  • FIG. 7B is a plan view showing a configuration example of the N + layer 110 and the P + layer 120 of the OPB pixel 50 with a sensor according to the first embodiment of the present disclosure. Note that FIG. 7A includes a cross section of the plan view shown in FIG. 7B cut along the YZ plane passing through the BB'line.
  • the OPB pixel 50 with a sensor has an N + layer 110 provided on the semiconductor layer 10 (an example of the “second impurity diffusion layer” of the present disclosure) and a P + provided around the N + layer 110.
  • a layer 120 and a gate electrode TG1 provided on the P + layer 120 via a gate insulating film (not shown) are provided.
  • the P + layer 120 is a first P + layer 121 (an example of the “first impurity diffusion layer” of the present disclosure) located on one surface 110a (upper surface in FIG. 7A) side of the N + layer 110, and the N + layer 110.
  • a second P + layer 122 located on the side of the other surface 110b (lower surface in FIG.
  • the third P + layer 123 is provided around each of the OPB pixel 50 with a sensor and the OPB pixel 60 without a sensor.
  • a photodiode is composed of an N + layer 110 and a first P + layer 121.
  • the charge e ⁇ generated by the photodiode is stored in the N + layer 110.
  • the N + layer 110 functions as a charge storage layer.
  • the charge e ⁇ stored in the N + layer 110 is output as a signal to the floating diffusion FD (see, for example, FIG. 4) when the transfer transistor having the gate electrode TG1 is turned on.
  • the third P + layer 123 constitutes an inter-pixel separation portion of the OPB pixel 50 with a sensor. As shown in FIG. 7B, the third P + layer 123 surrounds the N + layer 110 in the X-axis direction and the Y-axis direction.
  • the OPB pixel 50 with a sensor can be placed between adjacent pixels (for example, between an adjacent OPB pixel 50 with a sensor, between an adjacent OPB pixel 50 without a sensor, or an adjacent overflow drain pixel.
  • a barrier ⁇ BA1 (see, for example, FIGS. 3 and 4) can be formed (between 70 and 70).
  • FIG. 8A is a cross-sectional view showing a configuration example of the OPB pixel 60 without a sensor according to the first embodiment of the present disclosure.
  • FIG. 8B is a plan view showing a configuration example of the N + layer 110 and the P + layer 120 of the sensorless OPB pixel 60 according to the first embodiment of the present disclosure. Note that FIG. 8A includes a cross section of the plan view shown in FIG. 8B cut along the YZ plane passing through the CC'line.
  • the sensorless OPB pixel 60 has an N + layer 110 provided on the semiconductor layer 10, a P + layer 120 provided around the N + layer 110, and a gate insulating film on the P + layer 120 (FIG. 8A).
  • a gate electrode TG2 provided via (not shown) is provided.
  • the P + layer 120 is located on the first P + layer 121A located on one surface 110a (upper surface in FIG. 8A) side of the N + layer 110 and on the other surface 110b (lower surface in FIG. 8A) side of the N + layer 110. It has a second P + layer 122 and a third P + layer 123 located on the side surface 110c of the N + layer 110.
  • a photodiode is composed of an N + layer 110 and a first P + layer 121A.
  • the charge e ⁇ generated by the photodiode is stored in the N + layer 110.
  • the N + layer 110 functions as a charge storage layer.
  • the P + layer 121A of the OPB pixel 60 without a sensor has a larger thickness than, for example, the P + layer 121 of the OPB pixel 50 with a sensor.
  • the transfer transistor having the gate electrode TG2 is not turned on.
  • the charge stored in the N + layer 110 is not output as a signal to the floating diffusion FD (see, for example, FIG. 4) via the transfer transistor having the gate electrode TG2.
  • the photodiode composed of the N + layer 110 and the first P + layer 121A does not output a signal to the floating diffusion FD, and therefore does not function as a sensor.
  • the third P + layer 123 constitutes an inter-pixel separation portion of the OPB pixel 60 without a sensor. As shown in FIG. 8B, in the X-axis direction and the Y-axis direction, the third P + layer 123 surrounds the N + layer 110 except for a part of the region R121 (an example of the “non-separable region” of the present disclosure). I'm out.
  • the third P + layer 123 allows the sensorless OPB pixel 60 to form a barrier ⁇ BA1 with the adjacent sensored OPB pixel 50.
  • one or more regions R121 in which the third P + layer 123 is not arranged are provided.
  • One sensorless OPB pixel 60 and the other sensorless OPB pixel 60 adjacent to each other in the Y-axis direction (or the X-axis direction, or the X-axis direction and the Y-axis direction) are the regions R121 in which the third P + layer 123 is not arranged.
  • N + layers 110 are connected to each other.
  • the sensorless OPB pixel 60 has a deeper potential than the barrier ⁇ BA1 between the sensorless OPB pixel 60 and the other sensorless OPB pixels 60 adjacent in the Y-axis direction (or the X-axis direction, or the X-axis direction and the Y-axis direction).
  • the barrier ⁇ BA2 can be formed.
  • FIG. 9 is a cross-sectional view showing a configuration example of the OPB region R1 according to the first embodiment of the present disclosure.
  • the sensorless OPB pixel 60 has the above-mentioned region R121 together with the N + layer 110 of the overflow drain pixels 70 adjacent to each other in the Y-axis direction (or the X-axis direction, or the X-axis direction and the Y-axis direction). Connecting via.
  • the OPB pixel 60 without a sensor has a barrier ⁇ BA3 having a deeper potential than the barrier ⁇ BA1 between the overflow and drain pixels 70 adjacent to each other in the Y-axis direction (or the X-axis direction, or the X-axis direction and the Y-axis direction). Can be formed.
  • the gate electrode TG1 of the OPB pixel 50 with a sensor is driven in the same manner as the pixel in the normal pixel region R0 (see, for example, FIG. 1).
  • the transfer transistor having the gate electrode TG1 is turned on, the charge e ⁇ stored in the N + layer 110 is output as a signal to the floating diffusion FD (see, for example, FIG. 4).
  • the gate electrode TG2 of the OPB pixel 60 without a sensor is also driven in the same manner as the gate electrode TG1 of the OPB pixel 50 with a sensor. Even when driven in this way, the transfer transistor having the gate electrode TG2 is not turned on, so that the charge e ⁇ stored in the N + layer 110 is not output as a signal to the floating diffusion FD.
  • the region where the channel under the gate electrode TG3 is formed is not the first P + layer 121 but the N + layer 110.
  • the transfer transistor having the gate electrode TG3 is always on, and the N + layer 110 of the overflow drain pixel 70 can be constantly connected to the floating diffusion FD (see, for example, FIG. 4).
  • the reset transistor connected in series with the transfer transistor having the gate electrode TG3 may also be always on.
  • the N + layer 110 of the overflow drain pixel 70 can be constantly connected to the power supply line Vdd (for example, see FIG. 4) via the floating diffusion FD and the reset transistor.
  • the electric charge e ⁇ overflowing in the OPB pixel 60 without a sensor exceeds the barriers ⁇ BA2 and ⁇ BA3 and is constantly discharged to the power supply line Vdd.
  • FIG. 10 is a diagram showing the potential distribution of the OPB region R1 ′ according to the comparative example of the present disclosure.
  • FIG. 11 is a diagram showing an image quality image of the OPB region R1 ′ according to the comparative example of the present disclosure.
  • ⁇ BA1 ′ between the adjacent pixels of the OPB pixel 50 ′ with the sensor and the OPB pixel 60 ′ without the sensor.
  • ⁇ BA2 ′ between adjacent pixels of the OPB pixels 60 ′ without a sensor.
  • the barrier ⁇ BA2 ′ has the same potential depth as the barrier ⁇ BA1 ′.
  • ⁇ BA2' ⁇ BA1'.
  • ⁇ BA3 ′ there is a barrier ⁇ BA3 ′ between the adjacent pixels of the OPB pixel 60 ′ without the sensor and the overflow drain pixel 70 ′.
  • the barrier ⁇ BA3 ′ has the same potential depth as the barrier ⁇ BA1 ′.
  • ⁇ BA3' ⁇ BA1'.
  • the sensored OPB pixel adjacent to the sensorless OPB pixel area R12' Whitening may occur in the output of 50.
  • the image pickup apparatus 1 is provided in the semiconductor layer 10, a normal pixel region R0 that receives light from a subject, and is provided in the semiconductor layer 10 to block light.
  • the OPB region R1 is provided.
  • the OPB region R1 has an OPB pixel 50 with a sensor having a sensor function of detecting light and outputting a signal, and an OPB pixel 60 without a sensor having no sensor function.
  • ⁇ BA1 that hinders the movement of the electric charge e ⁇ .
  • ⁇ BA2 between the sensorless OPB pixels 60 adjacent to each other, which hinders the movement of the electric charge e ⁇ .
  • ⁇ BA2 has a deeper potential than ⁇ BA1.
  • ⁇ BA2 there is one or more regions R121 in which ⁇ BA2 exists around the OPB pixel 60 without a sensor.
  • the charge e-that exceeds the capacity that can be stored in the sensorless OPB pixel 60 exceeds the barrier ⁇ BA2 and is adjacent to the other sensorless OPB pixel 60.
  • ⁇ BA1 exists, but the barrier ⁇ BA2 does not exist.
  • the barrier ⁇ BA1 has a shallower potential than the barrier ⁇ BA2, it is possible to suppress the movement of the charge e-from the OPB pixel 60 without the sensor to the OPB pixel 50 with the sensor. As a result, the image pickup apparatus 1 can suppress the occurrence of defects (for example, whitening) in the output of the OPB pixel 50 with the sensor due to the overflow of the charge e ⁇ from the OPB pixel 60 without the sensor.
  • the image pickup apparatus 1 can reduce the difference in layout between the OPB pixel 50 with a sensor and the OPB pixel 60 without a sensor, and the photoelectric conversion efficiency and wiring between the OPB pixel 50 with a sensor and the OPB pixel 60 without a sensor.
  • the capacity etc. can be made close to the equivalent.
  • the image pickup apparatus 1 can reduce the possibility that an error occurs in the calculation of the dark current component, and thus can suppress the deterioration of the image quality.
  • each of the gate electrodes TG1, TG2, and TG3 of the OPB pixel 50 with a sensor, the OPB pixel 60 without a sensor, and the overflow drain pixel 70 has a planar structure. Indicated. However, the embodiments of the present disclosure are not limited to this. In the embodiments of the present disclosure, at least one or more of the gate electrodes TG1, TG2, and TG3 may have a trench gate structure.
  • FIG. 12 is a cross-sectional view showing the configuration of the OPB pixel 50A with a sensor according to the modified example of the first embodiment of the present disclosure.
  • the gate electrode TG1 of the OPB pixel 50A with a sensor has a trench gate structure.
  • the semiconductor layer 10 is provided with a hole H1 that opens on one surface 10a side and reaches the N + layer 110.
  • the gate electrode TG1 is arranged in the hole H1 via a gate insulating film (not shown), and has a vertical gate electrode VG1 extending in the vertical direction (for example, the Z-axis direction) and a gate insulating film (not shown). It has a horizontal gate electrode HG1 provided on one 10a of the semiconductor layer 10 via the above.
  • the vertical gate electrode VG1 and the horizontal gate electrode HG1 are connected to each other and are integrally formed.
  • the sensor-equipped OPB pixel 50A shown in FIG. 12 functions in the same manner as the sensor-equipped OPB pixel 50 shown in FIG. 7A, for example.
  • FIG. 13 is a cross-sectional view showing the configuration of the sensorless OPB pixel 60A according to the modified example of the first embodiment of the present disclosure.
  • the gate electrode TG2 of the OPB pixel 60A without a sensor has a trench gate structure.
  • the semiconductor layer 10 is provided with a hole H2 that opens on one side of 10a and does not reach the N + layer 110.
  • the bottom of the hole H2 is located within the P + layer 121A.
  • the gate electrode TG2 is arranged in the hole H2 via a gate insulating film (not shown), and has a vertical gate electrode VG2 extending in the vertical direction (for example, the Z-axis direction) and a gate insulating film (not shown).
  • the sensorless OPB pixel 60A shown in FIG. 13 functions in the same manner as the sensorless OPB pixel 60 shown in FIG. 8A, for example.
  • the third P + layer 123 is exemplified as a pixel-to-pixel separation unit that separates adjacent pixels.
  • the pixel-to-pixel separation section that separates adjacent pixels is not limited to the P-type impurity diffusion layer.
  • the inter-pixel separation unit may have, for example, trench isolation.
  • FIG. 14A is a cross-sectional view showing a configuration example of the OPB pixel 50B with a sensor according to the second embodiment of the present disclosure.
  • FIG. 14B is a plan view showing a configuration example of the N + layer 110 and the DTI layer 133 of the OPB pixel 50B with a sensor according to the second embodiment of the present disclosure. Note that FIG. 14A includes a cross section of the plan view shown in FIG. 14B cut along the YZ plane passing through the DD'line.
  • the OPB pixel 50B with a sensor has an STI (shallow Trench Isolation) layer 131 and a DTI (Deep Trench Isolation) layer 133 as inter-pixel separation portions.
  • the STI layer 131 has, for example, a structure in which an insulating film such as silicon oxide (SiO2) or polysilicon is embedded in a groove portion that opens on one surface (upper surface in FIG. 14) 10a side of the semiconductor layer 10.
  • the DTI layer 133 has, for example, a structure in which an insulating film such as SiO2 or polysilicon is embedded in a groove that opens on the other surface (lower surface in FIG. 14) side opposite to one surface 10a of the semiconductor layer 10.
  • the STI layer 131 and the DTI layer 133 are in contact with each other.
  • the STI layer 131 and the DTI layer 133 are arranged so as to overlap each other in a plan view from the normal direction (for example, the Z-axis direction) of one surface 10a of the semiconductor layer 10.
  • the DTI layer 133 surrounds the N + layer 110 in the X-axis direction and the Y-axis direction. Due to the DTI layer 133, the OPB pixel 50B with a sensor is placed between adjacent pixels (for example, between an OPB pixel 50B with another sensor adjacent to it, between an OPB pixel 50B without an adjacent sensor, or an adjacent overflow drain pixel 70.
  • a barrier ⁇ BA1 can be formed between the two.
  • FIG. 15A is a cross-sectional view showing a configuration example of the OPB pixel 60B without a sensor according to the second embodiment of the present disclosure.
  • FIG. 15B is a plan view showing a configuration example of the N + layer 110 and the DTI layer 133 of the sensorless OPB pixel 60B according to the second embodiment of the present disclosure. Note that FIG. 15A includes a cross section of the plan view shown in FIG. 15B cut along the YZ plane passing through the DD'line.
  • the sensorless OPB pixel 60B has an N + layer 110 provided on the semiconductor layer 10, a P + layer 120 provided around the N + layer 110, and a gate insulating film on the P + layer 120 (FIG. 15A).
  • a gate electrode TG2 provided via (not shown) is provided.
  • the P + layer 120 is located on the first P + layer 121A located on one surface 110a (upper surface in FIG. 15A) side of the N + layer 110 and on the other surface 110b (lower surface in FIG. 15A) side of the N + layer 110. It has a second P + layer 122 and a third P + layer 123 located on the side surface 110c of the N + layer 110.
  • the OPB pixel 60B without a sensor has an STI layer 131 and a DTI layer 133 as inter-pixel separation portions.
  • the DTI layer 133 surrounds the N + layer 110 except for a part of the region R121.
  • the DTI layer 133 allows the sensorless OPB pixel 60B to form a barrier ⁇ BA1 with the adjacent sensored OPB pixel 50B.
  • the N + layers 110 of the OPB pixels 60B without sensors adjacent to each other in the Y-axis direction (or the X-axis direction, or the X-axis direction and the Y-axis direction) are connected to each other via the above-mentioned region R121. Due to the above region R121, the sensorless OPB pixel 60B forms a barrier ⁇ BA2 with another sensorless OPB pixel 60B adjacent in the Y-axis direction (or X-axis direction, or X-axis direction and Y-axis direction). can do.
  • the image pickup apparatus 1 has a defect (for example, whitening) in the output of the OPB pixel 50B with the sensor due to the overflow of the charge e-from the OPB pixel 60B without the sensor. It can be suppressed from occurring. Further, the image pickup apparatus 1 can reduce the difference in layout between the OPB pixel 50B with a sensor and the OPB pixel 60B without a sensor, and the photoelectric conversion efficiency and wiring capacity between the OPB pixel 50B with a sensor and the OPB pixel 60B without a sensor. Etc. can be brought close to the equivalent. As a result, the image pickup apparatus 1 can reduce the possibility that an error occurs in the calculation of the dark current component, and thus can suppress the deterioration of the image quality.
  • a defect for example, whitening
  • the STI layer 131 may be omitted.
  • the inter-pixel separation unit may be composed of a DTI layer 133 and a P-type impurity diffusion layer, or may be composed of only the DTI layer 133.
  • FIG. 16 is a cross-sectional view showing the configuration of the OPB pixel 50C with a sensor according to the modified example of the second embodiment of the present disclosure.
  • FIG. 17 is a cross-sectional view showing the configuration of the OPB pixel 60C without a sensor according to the modified example of the second embodiment of the present disclosure.
  • the inter-pixel separation portion is composed of a DTI layer and a third P + layer 123. Even with such a configuration, the same effect as that of the second embodiment can be obtained.
  • the third P + layer 123 which is a pixel-to-pixel separation unit, is located between adjacent pixels of the sensorless OPB pixels 60 (or between adjacent pixels of the sensorless OPB pixel 60 and the overflow drain pixel 70). It has been described that there is a region R121 in which a part is removed, and the N + layers 110 of both pixels are connected to each other via this region R121. Further, it has been explained that the barrier ⁇ BA2 (or the barrier ⁇ BA3) is formed between the adjacent pixels by this configuration. However, in the embodiment of the present disclosure, an impurity diffusion layer other than the N + layer 110 is interposed between one N + layer 110 connected via the above region R121 and the other N + layer 120. The barrier ⁇ BA2 (or the barrier ⁇ BA3) may be formed by another impurity diffusion layer.
  • FIG. 18 is a cross-sectional view showing a configuration example of the OPB region R1A according to the third embodiment of the present disclosure.
  • an N-type or N-type impurity diffusion layer 130 having a lower N-type impurity concentration than the N + layer between adjacent pixels of the sensorless OPB pixels 60 (the present disclosure).
  • An example of a "fourth impurity diffusion layer" is provided.
  • the N-type or N-type impurity diffusion layer 130 forms a barrier ⁇ BA2 between adjacent pixels of the sensorless OPB pixels 60.
  • an N-type or N-type impurity diffusion layer 130 is also provided between the adjacent pixels of the OPB pixel 60 without a sensor and the overflow / drain pixel 70.
  • the N-type or N-type impurity diffusion layer 130 forms a barrier ⁇ BA3 between the adjacent pixels of the OPB pixel 60 without a sensor and the overflow drain pixel 70.
  • the image pickup apparatus 1 has the same effect as that of the first and second embodiments. Further, in the third embodiment, the potential of the barrier ⁇ BA2 can be controlled to a desired value by adjusting the concentration of the N-type impurity in the impurity diffusion layer 130 and the horizontal thickness of the impurity diffusion layer 130. ..
  • the present disclosure may also have the following structure.
  • a pixel area provided on the semiconductor layer that receives light from the subject An optical black region provided on the semiconductor layer and shielded from the light is provided.
  • the optical black region is The first pixel having a sensor function of detecting the light and outputting a signal, There is a first barrier that hinders the movement of electric charges between the second pixel that does not have the sensor function and the first pixel that has and is adjacent to each other and the second pixel. There is a second barrier that hinders the movement of electric charges between the second pixels that are adjacent to each other.
  • the second barrier is an image pickup device having a deeper potential than the first barrier.
  • the optical black region further comprises a third pixel, which is connected to a preset positive potential.
  • the image pickup apparatus There is a third barrier that hinders the transfer of electric charge between the second pixel and the third pixel that are adjacent to each other.
  • the image pickup apparatus according to (1), wherein the third barrier has a deeper potential than the first barrier.
  • the first pixel has a first gate electrode for transferring the charge generated by the first pixel.
  • the second pixel has a second gate electrode having the same structure as the first gate electrode.
  • Around the second gate electrode there is a fourth barrier that hinders the transfer of electric charge.
  • the imaging device according to any one of (1) to (3), wherein the second barrier has a deeper potential than the fourth barrier.
  • the potential of the fourth barrier is The image pickup apparatus according to (4) above, wherein the depth is the same when a voltage is applied to the second gate electrode and when the voltage is not applied to the second gate electrode.
  • the third pixel has a third gate electrode and has a third gate electrode. Around the third gate electrode, there is a fifth barrier that hinders the transfer of electric charge.
  • the optical black region is Further, an inter-pixel separation unit provided around each of the first pixel and the second pixel is provided.
  • the inter-pixel separation portion forms the first barrier, and the inter-pixel separation portion forms the first barrier.
  • the image pickup apparatus according to any one of (1) to (7) above, wherein one or more non-separable regions in which the inter-pixel separation portion is not arranged are provided around the second pixel. .. (9)
  • Each of the first pixel and the second pixel The first conductive type first impurity diffusion layer and It has a second conductive type second impurity diffusion layer bonded to the first impurity diffusion layer.
  • Image pickup device 10 Semiconductor layer 10a, 110a One side 12 Pixel array unit 13 Vertical drive circuit 14 Column signal processing circuit 15 Horizontal drive circuit 16 Output circuit 17 Control circuit 21 Pixel 22 Horizontal signal line 23 Vertical signal line 24 Data output signal line 30 Read circuit 31 Photodiode 32 Transfer transistor 34 Amplification transistor 35 Selective transistor 36 Reset transistor 50, 50A, 50B, 50C OPB pixel 60, 60A, 60B, 60C without sensor OPB pixel 70 Overflow drain pixel 90 Light-shielding metal 110 N + layer 110b The other surface 120 P + layer 121, 121A 1st P + layer 122 2nd P + layer 123 3rd P + layer 130 impurity diffusion layer 131 STI layer 133 DTI layer CF color filter FD floating diffusion H1, H2 hole HG1, HG2 horizontal gate electrode ML micro Lens PD photodiode R0 normal pixel area R1, R1A OPB area R11 with sensor OPB pixel area R12 without sensor OPB pixel area R13 overflow drain pixel area

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Abstract

Provided is an imaging device that makes it possible to suppress any reduction in image quality. This imaging device comprises a pixel region that is provided to a semiconductor layer and that receives light from a subject, and an optical black region that is provided to the semiconductor layer and that is shielded from light. The optical black region has a first pixel having a sensor function for detecting light and outputting a signal, and a second pixel that does not have a sensor function. A first barrier wall that prevents the movement of charge is present between mutually adjacent first and second pixels. A second barrier wall that prevents the movement of charge is present between mutually adjacent second pixels. The second barrier wall has a deeper potential than the first barrier wall.

Description

撮像装置Imaging device
 本開示は、撮像装置に関する。 This disclosure relates to an image pickup device.
 撮像装置は、被写体からの光を受光する画素領域に配置された画素(以下、通常画素)と、被写体からの光が遮光されるオプティカルブラック領域に配置された画素とを備えることが知られている(例えば、特許文献1参照)。特許文献1には、フォトダイオード(PD)有する画素(以下、PD有り画素)と、PDが無い画素(以下、PD無し画素)とがオプティカルブラック領域に配置され、PD有り画素の電圧信号からPD無し画素のノイズ成分に対応した電圧信号を減算することで、暗電流成分を算出することが開示されている。また、特許文献1には、PD無し画素にコンタクトプラグが設けられており、コンタクトプラグを介してPD無し画素に正の電圧を印加することによって、PD無し画素で生じた暗電荷を排出することが開示されている。 It is known that an image pickup apparatus includes pixels arranged in a pixel region that receives light from a subject (hereinafter, normal pixels) and pixels arranged in an optical black region in which light from a subject is shielded. (For example, see Patent Document 1). In Patent Document 1, a pixel having a photodiode (PD) (hereinafter, a pixel with PD) and a pixel without PD (hereinafter, a pixel without PD) are arranged in an optical black region, and a PD is obtained from a voltage signal of a pixel with PD. It is disclosed that the dark current component is calculated by subtracting the voltage signal corresponding to the noise component of the none pixel. Further, in Patent Document 1, a contact plug is provided in the pixel without PD, and by applying a positive voltage to the pixel without PD through the contact plug, the dark charge generated in the pixel without PD is discharged. Is disclosed.
特開2019-96914号公報Japanese Unexamined Patent Publication No. 2019-96914
 特許文献1に開示された技術では、PD無し画素は、正の電圧の供給を受けるための(すなわち、電荷リセット用の)コンタクトプラグが設けられており、レイアウトの制限が多い。PD有り画素とPD無し画素との間でレイアウトの違いが大きいと、これら両画素間で光電変換効率や配線容量などが等価にならず、暗電流成分の算出に誤差が生じる可能性がある。この誤差が大きいと、画質が低下する可能性がある。 In the technique disclosed in Patent Document 1, the PD-less pixel is provided with a contact plug for receiving a positive voltage supply (that is, for charge reset), and there are many layout restrictions. If there is a large difference in layout between the pixels with PD and the pixels without PD, the photoelectric conversion efficiency and wiring capacity will not be equivalent between these pixels, and there is a possibility that an error will occur in the calculation of the dark current component. If this error is large, the image quality may deteriorate.
 本開示はこのような事情に鑑みてなされたもので、画質の低下を抑制できるようにした撮像装置を提供することを目的とする。 The present disclosure has been made in view of such circumstances, and an object of the present disclosure is to provide an image pickup apparatus capable of suppressing deterioration of image quality.
 本開示の一態様に係る撮像装置は、半導体層に設けられ、被写体からの光を受光する画素領域と、前記半導体層に設けられ、前記光が遮光されるオプティカルブラック領域と、を備える。前記オプティカルブラック領域は、前記光を検出して信号を出力するセンサ機能を有する第1画素と、前記センサ機能がない第2画素と、を有する。互いに隣接する前記第1画素と前記第2画素との間には、電荷の移動を妨げる第1障壁が存在する。互いに隣接する前記第2画素同士の間には電荷の移動を妨げる第2障壁が存在する。前記第2障壁は、前記第1障壁よりもポテンシャルが深い。 The image pickup apparatus according to one aspect of the present disclosure includes a pixel region provided in the semiconductor layer and receiving light from a subject, and an optical black region provided in the semiconductor layer in which the light is shielded. The optical black region has a first pixel having a sensor function of detecting the light and outputting a signal, and a second pixel having no sensor function. Between the first pixel and the second pixel adjacent to each other, there is a first barrier that hinders the movement of electric charges. There is a second barrier that hinders the movement of electric charges between the second pixels that are adjacent to each other. The second barrier has a deeper potential than the first barrier.
 これによれば、第2画素の周囲には、第2障壁が存在する領域が1つ以上存在する。第2画素に蓄積された電荷のうち、第2画素で蓄積可能な容量を超えた分の電荷は、第2障壁を超えて、隣接する他の第2画素へオーバーフローする。一方、第1画素と第2画素との間には、第1障壁は存在するが、第2障壁は存在しない。第1障壁は第2障壁よりもポテンシャル深さが浅いため、第2画素から第1画素へ電荷が移動することが抑制される。これにより、撮像装置は、第2画素からの電荷のオーバーフローに起因して第1画素の出力に不具合(例えば、白浮き)が生じることを抑制することができる。 According to this, there is one or more regions in which the second barrier exists around the second pixel. Of the charges stored in the second pixel, the charges exceeding the capacity that can be stored in the second pixel exceed the second barrier and overflow to the other adjacent second pixels. On the other hand, there is a first barrier between the first pixel and the second pixel, but there is no second barrier. Since the first barrier has a shallower potential than the second barrier, the transfer of electric charge from the second pixel to the first pixel is suppressed. Thereby, the image pickup apparatus can suppress the occurrence of a defect (for example, whitening) in the output of the first pixel due to the overflow of the electric charge from the second pixel.
 また、第2画素からの電荷の排出は、第2障壁が存在する領域を介して行われるため、第2画素に電荷リセット用のコンタクトプラグを設ける必要はない。これにより、撮像装置は、第1画素と第2画素との間でレイアウトの違いを小さくでき、第1画素と第2画素との間で光電変換効率や配線容量などを等価に近づけることができる。これにより、撮像装置は、暗電流成分の算出に誤差が生じる可能性を低減できるため、画質の低下を抑制することができる。 Further, since the charge is discharged from the second pixel through the region where the second barrier exists, it is not necessary to provide a contact plug for charge reset in the second pixel. As a result, the image pickup apparatus can reduce the difference in layout between the first pixel and the second pixel, and can make the photoelectric conversion efficiency and the wiring capacity equivalently close to each other between the first pixel and the second pixel. .. As a result, the image pickup apparatus can reduce the possibility of an error in the calculation of the dark current component, and thus can suppress the deterioration of the image quality.
図1は、本開示の実施形態1に係る撮像装置の構成例を示すブロック図である。FIG. 1 is a block diagram showing a configuration example of the image pickup apparatus according to the first embodiment of the present disclosure. 図2は、本開示の実施形態1に係る画素アレイ部の構成例を示す平面図である。FIG. 2 is a plan view showing a configuration example of the pixel array unit according to the first embodiment of the present disclosure. 図3は、本開示の実施形態1に係る画素アレイ部のOPB領域の構成例を示す断面図である。FIG. 3 is a cross-sectional view showing a configuration example of an OPB region of the pixel array unit according to the first embodiment of the present disclosure. 図4は、本開示の実施形態1に係るOPB領域のポテンシャル分布の一例を示す図である。FIG. 4 is a diagram showing an example of the potential distribution of the OPB region according to the first embodiment of the present disclosure. 図5は、本開示の実施形態1に係るOPB領域のポテンシャル分布の一例を示す図である。FIG. 5 is a diagram showing an example of the potential distribution of the OPB region according to the first embodiment of the present disclosure. 図6は、本開示の実施形態1に係るOPB領域の画質イメージを示す図である。FIG. 6 is a diagram showing an image quality image of the OPB region according to the first embodiment of the present disclosure. 図7Aは、本開示の実施形態1に係るセンサ有りOPB画素の構成例を示す断面図である。FIG. 7A is a cross-sectional view showing a configuration example of an OPB pixel with a sensor according to the first embodiment of the present disclosure. 図7Bは、本開示の実施形態1に係るセンサ有りOPB画素のN+層及びP+層の構成例を示す平面図である。FIG. 7B is a plan view showing a configuration example of the N + layer and the P + layer of the OPB pixel with a sensor according to the first embodiment of the present disclosure. 図8Aは、本開示の実施形態1に係るセンサ無しOPB画素の構成例を示す断面図である。FIG. 8A is a cross-sectional view showing a configuration example of a sensorless OPB pixel according to the first embodiment of the present disclosure. 図8Bは、本開示の実施形態1に係るセンサ無しOPB画素のN+層及びP+層の構成例を示す平面図である。FIG. 8B is a plan view showing a configuration example of the N + layer and the P + layer of the OPB pixel without a sensor according to the first embodiment of the present disclosure. 図9は、本開示の実施形態1に係るOPB領域の構成例を示す断面図である。FIG. 9 is a cross-sectional view showing a configuration example of the OPB region according to the first embodiment of the present disclosure. 図10は、本開示の比較例に係るOPB領域のポテンシャル分布を示す図である。FIG. 10 is a diagram showing the potential distribution of the OPB region according to the comparative example of the present disclosure. 図11は、本開示の比較例に係るOPB領域の画質イメージを示す図である。FIG. 11 is a diagram showing an image quality image of the OPB region according to the comparative example of the present disclosure. 図12は、本開示の実施形態1の変形例に係るセンサ有りOPB画素の構成を示す断面図である。FIG. 12 is a cross-sectional view showing the configuration of an OPB pixel with a sensor according to a modification of the first embodiment of the present disclosure. 図13は、本開示の実施形態1の変形例に係るセンサ無しOPB画素の構成を示す断面図である。FIG. 13 is a cross-sectional view showing the configuration of the OPB pixel without a sensor according to the modified example of the first embodiment of the present disclosure. 図14Aは、本開示の実施形態2に係るセンサ有りOPB画素の構成例を示す断面図である。FIG. 14A is a cross-sectional view showing a configuration example of an OPB pixel with a sensor according to the second embodiment of the present disclosure. 図14Bは、本開示の実施形態2に係るセンサ有りOPB画素のN+層及びDTI層の構成例を示す平面図である。FIG. 14B is a plan view showing a configuration example of the N + layer and the DTI layer of the OPB pixel with a sensor according to the second embodiment of the present disclosure. 図15Aは、本開示の実施形態2に係るセンサ無しOPB画素の構成例を示す断面図である。FIG. 15A is a cross-sectional view showing a configuration example of a sensorless OPB pixel according to the second embodiment of the present disclosure. 図15Bは、本開示の実施形態2に係るセンサ無しOPB画素のN+層及びDTI層の構成例を示す平面図である。FIG. 15B is a plan view showing a configuration example of the N + layer and the DTI layer of the OPB pixel without a sensor according to the second embodiment of the present disclosure. 図16は、本開示の実施形態2の変形例に係るセンサ有りOPB画素の構成を示す断面図である。FIG. 16 is a cross-sectional view showing the configuration of an OPB pixel with a sensor according to a modification of the second embodiment of the present disclosure. 図17は、本開示の実施形態2の変形例に係るセンサ無しOPB画素の構成を示す断面図である。FIG. 17 is a cross-sectional view showing the configuration of the OPB pixel without a sensor according to the modified example of the second embodiment of the present disclosure. 図18は、本開示の実施形態3に係るOPB領域の構成例を示す断面図である。FIG. 18 is a cross-sectional view showing a configuration example of the OPB region according to the third embodiment of the present disclosure.
 以下において、図面を参照して本開示の実施形態を説明する。以下の説明で参照する図面の記載において、同一又は類似の部分には同一又は類似の符号を付している。ただし、図面は模式的なものであり、厚みと平面寸法との関係、各層の厚みの比率等は現実のものとは異なることに留意すべきである。したがって、具体的な厚みや寸法は以下の説明を参酌して判断すべきものである。また、図面相互間においても互いの寸法の関係や比率が異なる部分が含まれていることは勿論である。 Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. In the description of the drawings referred to in the following description, the same or similar parts are designated by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between the thickness and the plane dimensions, the ratio of the thickness of each layer, etc. are different from the actual ones. Therefore, the specific thickness and dimensions should be determined in consideration of the following explanation. In addition, it goes without saying that parts having different dimensional relationships and ratios are included between the drawings.
 以下の説明における上下等の方向の定義は、単に説明の便宜上の定義であって、本開示の技術的思想を限定するものではない。例えば、対象を90°回転して観察すれば上下は左右に変換して読まれ、180°回転して観察すれば上下は反転して読まれることは勿論である。 The definition of directions such as up and down in the following description is merely a definition for convenience of explanation, and does not limit the technical idea of the present disclosure. For example, if the object is rotated by 90 ° and observed, the top and bottom are converted to left and right and read, and if the object is rotated by 180 ° and observed, the top and bottom are reversed and read.
 以下の説明では、X軸方向、Y軸方向及びZ軸方向の文言を用いて、方向を説明する場合がある。例えば、X軸方向及びY軸方向は、後述する半導体層10の一方の面10aに平行な方向である。X軸方向及びY軸方向を水平方向ともいう。Z軸方向は、一方の面10aの法線方向である。X軸方向、Y軸方向及びZ軸方向は、互いに直交する。 In the following explanation, the direction may be explained using the words in the X-axis direction, the Y-axis direction, and the Z-axis direction. For example, the X-axis direction and the Y-axis direction are directions parallel to one surface 10a of the semiconductor layer 10, which will be described later. The X-axis direction and the Y-axis direction are also referred to as horizontal directions. The Z-axis direction is the normal direction of one surface 10a. The X-axis direction, the Y-axis direction, and the Z-axis direction are orthogonal to each other.
 以下の説明では、第1導電型がP型、第2導電型がN型の場合について例示的に説明する。しかし、導電型を逆の関係に選択して、第1導電型をN型、第2導電型をP型としても構わない。またPやNに付す+(または、-)は、+(または、-)が付記されていない半導体層に比して、それぞれ相対的に不純物濃度が高い(または、低い)半導体層であることを意味する。ただし同じPとP(または、同じNとN)とが付された半導体層であっても、それぞれの半導体層の不純物濃度が厳密に同じであることを意味するものではない。 In the following description, the case where the first conductive type is P type and the second conductive type is N type will be exemplified. However, the conductive type may be selected in the opposite relationship, the first conductive type may be N type, and the second conductive type may be P type. Further, + (or-) attached to P or N is a semiconductor layer having a relatively high (or low) impurity concentration as compared with the semiconductor layer not marked with + (or-). Means. However, even if the semiconductor layers have the same P and P (or the same N and N), it does not mean that the impurity concentrations of the respective semiconductor layers are exactly the same.
<実施形態1>
(撮像装置の構成例)
 図1は、本開示の実施形態1に係る撮像装置1の構成例を示すブロック図である。図1に示す撮像装置1は、例えば裏面照射型の固体撮像装置である。図1に示すように、撮像装置1は、画素アレイ部12、垂直駆動回路13、カラム信号処理回路14、水平駆動回路15、出力回路16、および制御回路17を備える。
<Embodiment 1>
(Configuration example of image pickup device)
FIG. 1 is a block diagram showing a configuration example of the image pickup apparatus 1 according to the first embodiment of the present disclosure. The image pickup device 1 shown in FIG. 1 is, for example, a back-illuminated solid-state image pickup device. As shown in FIG. 1, the image pickup apparatus 1 includes a pixel array unit 12, a vertical drive circuit 13, a column signal processing circuit 14, a horizontal drive circuit 15, an output circuit 16, and a control circuit 17.
 画素アレイ部12は、後述の図2に示すように、通常画素領域R0(本開示の「画素領域」の一例)と、通常画素領域R0の周囲に配置されたオプティカルブラック(以下、OPB)領域R1とを有する。通常画素領域R0は、図示しない光学系により集光される光を受光する受光領域であり、複数の画素21を有する。 As shown in FIG. 2 described later, the pixel array unit 12 has a normal pixel area R0 (an example of the “pixel area” of the present disclosure) and an optical black (hereinafter, OPB) area arranged around the normal pixel area R0. It has R1 and. The normal pixel region R0 is a light receiving region that receives light collected by an optical system (not shown), and has a plurality of pixels 21.
 複数の画素21は、行列状に配置されている。複数の画素21は、水平信号線22を介して行ごとに垂直駆動回路13に接続されるとともに、垂直信号線23を介して列ごとにカラム信号処理回路14に接続される。複数の画素21は、それぞれ受光する光の光量に応じたレベルの画素信号をそれぞれ出力する。それらの画素信号から、被写体の画像が構築される。 The plurality of pixels 21 are arranged in a matrix. The plurality of pixels 21 are connected to the vertical drive circuit 13 row by row via the horizontal signal line 22, and are connected to the column signal processing circuit 14 column by column via the vertical signal line 23. Each of the plurality of pixels 21 outputs a pixel signal at a level corresponding to the amount of light received. An image of the subject is constructed from those pixel signals.
 垂直駆動回路13は、複数の画素21の行ごとに順次、それぞれの画素21を駆動(転送や、選択、リセットなど)するための駆動信号を、水平信号線22を介して画素21に供給する。カラム信号処理回路14は、複数の画素21から垂直信号線23を介して出力される画素信号に対してCDS(Correlated Double Sampling:相関2重サンプリング)処理を施すことにより、画素信号のAD変換を行うとともにリセットノイズを除去する。 The vertical drive circuit 13 sequentially supplies drive signals for driving (transfer, selection, reset, etc.) of each pixel 21 to the pixels 21 via the horizontal signal line 22 for each row of the plurality of pixels 21. .. The column signal processing circuit 14 performs AD conversion of the pixel signal by performing CDS (Correlated Double Sampling) processing on the pixel signal output from the plurality of pixels 21 via the vertical signal line 23. At the same time, remove the reset noise.
 水平駆動回路15は、複数の画素21の列ごとに順次、カラム信号処理回路14から画素信号をデータ出力信号線24に出力させるための駆動信号を、カラム信号処理回路14に供給する。出力回路16は、水平駆動回路15の駆動信号に従ったタイミングでカラム信号処理回路14からデータ出力信号線24を介して供給される画素信号を増幅し、後段の信号処理回路に出力する。制御回路17は、撮像装置1の内部の各ブロックの駆動を制御する。例えば、制御回路17は、各ブロックの駆動周期に従ったクロック信号を生成して、それぞれのブロックに供給する。 The horizontal drive circuit 15 sequentially supplies a drive signal for outputting a pixel signal from the column signal processing circuit 14 to the data output signal line 24 to the column signal processing circuit 14 for each row of the plurality of pixels 21. The output circuit 16 amplifies the pixel signal supplied from the column signal processing circuit 14 via the data output signal line 24 at the timing according to the drive signal of the horizontal drive circuit 15, and outputs the pixel signal to the signal processing circuit in the subsequent stage. The control circuit 17 controls the drive of each block inside the image pickup apparatus 1. For example, the control circuit 17 generates a clock signal according to the drive cycle of each block and supplies it to each block.
 画素21は、フォトダイオード31、転送トランジスタ32、フローティングディフュージョンFD、増幅トランジスタ34、選択トランジスタ35、およびリセットトランジスタ36を備える。転送トランジスタ32、フローティングディフュージョンFD、増幅トランジスタ34、選択トランジスタ35、およびリセットトランジスタ36は、フォトダイオード31で光電変換された電荷(画素信号)の読み出しを行う読出回路30を構成している。 The pixel 21 includes a photodiode 31, a transfer transistor 32, a floating diffusion FD, an amplification transistor 34, a selection transistor 35, and a reset transistor 36. The transfer transistor 32, the floating diffusion FD, the amplification transistor 34, the selection transistor 35, and the reset transistor 36 constitute a read circuit 30 that reads out the charge (pixel signal) photoelectrically converted by the photodiode 31.
 フォトダイオード31は、入射した光を光電変換により電荷に変換して蓄積する光電変換部であり、アノード端子が接地されているとともに、カソード端子が転送トランジスタ32に接続されている。転送トランジスタ32のゲート電極TGには、垂直駆動回路13から転送信号TRGが供給される。転送トランジスタ32は、ゲート電極TGに供給される転送信号TRGに従って駆動する。転送トランジスタ32がオンになると、フォトダイオード31に蓄積されている電荷がフローティングディフュージョンFDに転送される。フローティングディフュージョンFDは、増幅トランジスタ34のゲート電極に接続された所定の蓄積容量を有する浮遊拡散領域であり、フォトダイオード31から転送される電荷を一時的に蓄積する。 The photodiode 31 is a photoelectric conversion unit that converts incident light into electric charges by photoelectric conversion and stores them. The anode terminal is grounded and the cathode terminal is connected to the transfer transistor 32. A transfer signal TRG is supplied from the vertical drive circuit 13 to the gate electrode TG of the transfer transistor 32. The transfer transistor 32 is driven according to the transfer signal TRG supplied to the gate electrode TG. When the transfer transistor 32 is turned on, the charge stored in the photodiode 31 is transferred to the floating diffusion FD. The floating diffusion FD is a floating diffusion region having a predetermined storage capacity connected to the gate electrode of the amplification transistor 34, and temporarily stores the charge transferred from the photodiode 31.
 増幅トランジスタ34は、フローティングディフュージョンFDに蓄積されている電荷に応じたレベル(即ち、フローティングディフュージョンFDの電位)の画素信号を、選択トランジスタ35を介して垂直信号線23に出力する。すなわち、フローティングディフュージョンFDが増幅トランジスタ34のゲート電極に接続される構成により、フローティングディフュージョンFDおよび増幅トランジスタ34は、フォトダイオード31において発生した電荷を増幅し、その電荷に応じたレベルの画素信号に変換する変換部として機能する。 The amplification transistor 34 outputs a pixel signal at a level corresponding to the electric charge stored in the floating diffusion FD (that is, the potential of the floating diffusion FD) to the vertical signal line 23 via the selection transistor 35. That is, due to the configuration in which the floating diffusion FD is connected to the gate electrode of the amplification transistor 34, the floating diffusion FD and the amplification transistor 34 amplify the electric charge generated in the photodiode 31 and convert it into a pixel signal at a level corresponding to the electric charge. Functions as a conversion unit.
 選択トランジスタ35は、垂直駆動回路13から供給される選択信号SELに従って駆動し、選択トランジスタ35がオンになると、増幅トランジスタ34から出力される画素信号が垂直信号線23に出力可能な状態となる。リセットトランジスタ36は、垂直駆動回路13から供給されるリセット信号RSTに従って駆動し、リセットトランジスタ36がオンになると、フローティングディフュージョンFDに蓄積されている電荷が電源線Vddに排出されて、フローティングディフュージョンFDがリセットされる。 The selection transistor 35 is driven according to the selection signal SEL supplied from the vertical drive circuit 13, and when the selection transistor 35 is turned on, the pixel signal output from the amplification transistor 34 can be output to the vertical signal line 23. The reset transistor 36 is driven according to the reset signal RST supplied from the vertical drive circuit 13, and when the reset transistor 36 is turned on, the electric charge accumulated in the floating diffusion FD is discharged to the power supply line Vdd, and the floating diffusion FD becomes the floating diffusion FD. It will be reset.
(OPB領域の構成例)
 図2は、本開示の実施形態1に係る画素アレイ部12の構成例を示す平面図である。なお、図2では、OPB領域R1を詳細に説明するために、通常画素領域R0に対してOPB領域R1を大きく示している。
(Example of OPB area configuration)
FIG. 2 is a plan view showing a configuration example of the pixel array unit 12 according to the first embodiment of the present disclosure. In FIG. 2, in order to explain the OPB region R1 in detail, the OPB region R1 is shown larger than the normal pixel region R0.
 図2に示すように、OPB領域R1は、通常画素領域R0の周囲に配置されている。OPB領域R1は遮光された複数の画素を有し、これらの画素から出力される信号が、通常画素領域が有する画素の黒レベルの基準として用いられる。OPB領域R1は、例えば、撮像画像の上下を反転させる上下反転や、左右を反転させる左右反転の駆動を実現するために、平面視で、通常画素領域R0の上下、左右に対称的に配されている。 As shown in FIG. 2, the OPB area R1 is usually arranged around the pixel area R0. The OPB region R1 has a plurality of light-shielded pixels, and the signal output from these pixels is used as a reference for the black level of the pixels of the normal pixel region. The OPB region R1 is symmetrically arranged vertically and horizontally in the normal pixel region R0 in a plan view in order to realize, for example, a vertical inversion that inverts the captured image up and down and a left-right inversion drive that inverts the left and right. ing.
 図2に示すように、OPB領域R1は、センサ有りOPB画素領域R11と、センサ無しOPB画素領域R12と、オーバーフロードレイン画素領域R13とを有する。通常画素領域R0から、通常画素領域R0の外側へ向けて、オーバーフロードレイン画素領域R13、センサ有りOPB画素領域R11、センサ無しOPB画素領域R12、オーバーフロードレイン画素領域R13が、この順で配置されている。図2の矢印で示すように、センサ無しOPB画素領域R12で生じた電荷e-(例えば、暗電流成分)のうち、センサ無しOPB画素領域R12で蓄積可能な容量を超えた分の電荷e-は、オーバーフローして、オーバーフロードレイン画素領域R13へ移動する。 As shown in FIG. 2, the OPB region R1 has an OPB pixel region R11 with a sensor, an OPB pixel region R12 without a sensor, and an overflow drain pixel region R13. The overflow / drain pixel area R13, the OPB pixel area R11 with the sensor, the OPB pixel area R12 without the sensor, and the overflow / drain pixel area R13 are arranged in this order from the normal pixel area R0 toward the outside of the normal pixel area R0. .. As shown by the arrow in FIG. 2, of the charge e- (for example, the dark current component) generated in the sensorless OPB pixel region R12, the charge e-that exceeds the capacity that can be stored in the sensorless OPB pixel region R12. Overflows and moves to the overflow drain pixel area R13.
 図3は、本開示の実施形態1に係る画素アレイ部12のOPB領域R1の構成例を示す断面図である。図3に示す断面図は、図2に示した平面図をA-A´線で切断した断面に対応している。図3に示すように、画素アレイ部12は、通常画素領域R0(図2参照)とOPB領域R1とを備える半導体層10と、半導体層10の一方の面10a上に設けられた遮光メタル90と、遮光メタル90上に設けられたカラーフィルタCFと、カラーフィルタCF上に設けられたマイクロレンズMLと、を備える。例えば、半導体層10の一方の面10a側が、撮像装置1の裏面側である。 FIG. 3 is a cross-sectional view showing a configuration example of the OPB region R1 of the pixel array unit 12 according to the first embodiment of the present disclosure. The cross-sectional view shown in FIG. 3 corresponds to a cross-sectional view obtained by cutting the plan view shown in FIG. 2 along the AA'line. As shown in FIG. 3, the pixel array unit 12 includes a semiconductor layer 10 having a normal pixel region R0 (see FIG. 2) and an OPB region R1, and a light-shielding metal 90 provided on one surface 10a of the semiconductor layer 10. And a color filter CF provided on the light-shielding metal 90, and a microlens ML provided on the color filter CF. For example, one surface 10a side of the semiconductor layer 10 is the back surface side of the image pickup apparatus 1.
 半導体層10は、例えばシリコン(Si)で構成されている。半導体層10は、単結晶のシリコン基板で構成されていてもよいし、シリコン基板上にエピタキシャル成長法で形成されたシリコン層であってもよい。半導体層10に、センサ有りOPB画素領域R11、センサ無しOPB画素領域R12、オーバーフロードレイン画素領域R13がそれぞれ設けられている。 The semiconductor layer 10 is made of, for example, silicon (Si). The semiconductor layer 10 may be composed of a single crystal silicon substrate, or may be a silicon layer formed on the silicon substrate by an epitaxial growth method. The semiconductor layer 10 is provided with an OPB pixel region R11 with a sensor, an OPB pixel region R12 without a sensor, and an overflow drain pixel region R13, respectively.
 遮光メタル90は、例えば、通常画素領域R0の一部(例えば、隣接する一方の画素21と他方の画素21との間)と、OPB領域R1の全域とに設けられている。カラーフィルタCFとマイクロレンズMLはそれぞれ、例えば、通常画素領域R0からOPB領域R1まで連続して設けられている。例えば、センサ有りOPB画素領域R11の上方と、センサ無しOPB画素領域R12の上方及びオーバーフロードレイン画素領域R13の上方に、遮光メタル90が連続して設けられている。また、センサ有りOPB画素領域R11の上方と、センサ無しOPB画素領域R12の上方及びオーバーフロードレイン画素領域R13の上方には、遮光メタル90を介して、カラーフィルタCFとマイクロレンズMLとが設けられている。センサ有りOPB画素領域R11と、センサ無しOPB画素領域R12及びオーバーフロードレイン画素領域R13は、遮光メタル90によって遮光されている。 The light-shielding metal 90 is provided, for example, in a part of the normal pixel region R0 (for example, between one adjacent pixel 21 and the other pixel 21) and in the entire OPB region R1. The color filter CF and the microlens ML are provided continuously, for example, from the normal pixel region R0 to the OPB region R1. For example, the light-shielding metal 90 is continuously provided above the OPB pixel region R11 with a sensor, above the OPB pixel region R12 without a sensor, and above the overflow drain pixel region R13. Further, a color filter CF and a microlens ML are provided above the OPB pixel region R11 with a sensor, above the OPB pixel region R12 without a sensor, and above the overflow drain pixel region R13 via a light-shielding metal 90. There is. The OPB pixel region R11 with a sensor, the OPB pixel region R12 without a sensor, and the overflow drain pixel region R13 are shielded from light by a light-shielding metal 90.
 図3に示すように、センサ有りOPB画素領域R11は、センサ有りOPB画素50(本開示の「第1画素」の一例)を有する。図3では、センサ有りOPB画素50を1つしか記載していないが、センサ有りOPB画素領域R11は、X軸方向及びY軸方向(すなわち、水平方向)にそれぞれ並んで配置された複数のセンサ有りOPB画素50を有してよい。センサ有りOPB画素50は、その上方が遮光メタル90で遮光されている点を除いて、通常画素領域R0に設けられた画素21と同様の構成を有する。 As shown in FIG. 3, the sensor-equipped OPB pixel region R11 has a sensor-equipped OPB pixel 50 (an example of the “first pixel” of the present disclosure). Although only one OPB pixel 50 with a sensor is shown in FIG. 3, the OPB pixel region R11 with a sensor has a plurality of sensors arranged side by side in the X-axis direction and the Y-axis direction (that is, the horizontal direction), respectively. It may have the present OPB pixel 50. The OPB pixel 50 with a sensor has the same configuration as the pixel 21 provided in the normal pixel region R0, except that the upper part thereof is shielded from light by the light-shielding metal 90.
 センサ無しOPB画素領域R12は、センサ無しOPB画素60(本開示の「第2画素」の一例)を有する。図3では、Y軸方向に並ぶ4つのセンサ無しOPB画素60を記載しているが、これはあくまで例示である。センサ無しOPB画素領域R12は、X軸方向及びY軸方向にそれぞれ並んで配置された複数のセンサ無しOPB画素60を有してよい。 The sensorless OPB pixel region R12 has a sensorless OPB pixel 60 (an example of the "second pixel" of the present disclosure). In FIG. 3, four sensorless OPB pixels 60 arranged in the Y-axis direction are shown, but this is merely an example. The sensorless OPB pixel region R12 may have a plurality of sensorless OPB pixels 60 arranged side by side in the X-axis direction and the Y-axis direction, respectively.
 オーバーフロードレイン画素領域R13は、オーバーフロードレイン画素70(本開示の「第3画素」の一例)を有する。図3では、オーバーフロードレイン画素70を1つしか記載していないが、オーバーフロードレイン画素領域R13は、X軸方向及びY軸方向にそれぞれ並んで配置された複数のオーバーフロードレイン画素70を有してよい。 The overflow-drain pixel region R13 has an overflow-drain pixel 70 (an example of the "third pixel" of the present disclosure). Although only one overflow / drain pixel 70 is shown in FIG. 3, the overflow / drain pixel region R13 may have a plurality of overflow / drain pixels 70 arranged side by side in the X-axis direction and the Y-axis direction, respectively. ..
 図3に示すように、互いに隣接するセンサ有りOPB画素50とセンサ無しOPB画素60との間には、電荷e-の移動を妨げる障壁φBA1(本開示の「第1障壁」の一例)が存在する。また、互いに隣接するセンサ無しOPB画素60同士の間には、電荷e-の移動を妨げる障壁φBA2(本開示の「第2障壁」の一例」)が存在する。また、互いに隣接するセンサ無しOPB画素60とオーバーフロードレイン画素70との間には、電荷e-の移動を妨げる障壁φBA3(本開示の「第3障壁」の一例」)が存在する。なお、以下の説明では、隣接する一方の画素と他方の画素との間を、「隣接画素間」ともいう。 As shown in FIG. 3, a barrier φBA1 (an example of the “first barrier” of the present disclosure) that hinders the movement of the electric charge e− exists between the OPB pixel 50 with a sensor and the OPB pixel 60 without a sensor adjacent to each other. do. Further, between the sensorless OPB pixels 60 adjacent to each other, there is a barrier φBA2 (an example of the “second barrier” of the present disclosure) that hinders the movement of the electric charge e−. Further, between the OPB pixel 60 without a sensor and the overflow drain pixel 70 adjacent to each other, there is a barrier φBA3 (an example of the “third barrier” of the present disclosure) that hinders the movement of the electric charge e−. In the following description, the space between one adjacent pixel and the other pixel is also referred to as "between adjacent pixels".
 図4及び図5は、本開示の実施形態1に係るOPB領域R1のポテンシャル分布の一例を示す図である。図4に示すように、センサ無しOPB画素60同士の隣接画素間に存在する障壁φBA2は、センサ有りOPB画素50とセンサ無しOPB画素60との隣接画素間に存在する障壁φBA1よりもポテンシャルが深い。ΦBA2-ΦBA1>0である。 4 and 5 are diagrams showing an example of the potential distribution of the OPB region R1 according to the first embodiment of the present disclosure. As shown in FIG. 4, the barrier φBA2 existing between the adjacent pixels of the OPB pixels 60 without the sensor has a deeper potential than the barrier φBA1 existing between the adjacent pixels of the OPB pixel 50 with the sensor and the OPB pixel 60 without the sensor. .. ΦBA2-ΦBA1> 0.
 なお、本明細書において、「ポテンシャルが深い」は、「ポテンシャルが高い」又は「電位が高い」と言い換えてもよく、電荷e-から見て「障壁高さが低い」と言い換えてもよい。本明細書において、「ポテンシャルが浅い」は、「ポテンシャルが低い」又は「電位が低い」と言い換えてもよく、電荷e-から見て「障壁高さが高い」と言い換えてもよい。 In the present specification, "deep potential" may be paraphrased as "high potential" or "high potential", or may be paraphrased as "low barrier height" in view of the electric charge e-. In the present specification, "shallow potential" may be paraphrased as "low potential" or "low potential", or may be paraphrased as "high barrier height" in view of the electric charge e−.
 センサ無しOPB画素60とオーバーフロードレイン画素70との隣接画素間に存在する障壁φBA3は、障壁φBA1よりもポテンシャルが深い。ΦBA3-ΦBA1>0である。また、障壁φBA2のポテンシャルと障壁φBA3のポテンシャルは、例えば、互いに同じ深さである。φBA2=φBA3である。 The barrier φBA3 existing between the adjacent pixels of the OPB pixel 60 without the sensor and the overflow drain pixel 70 has a deeper potential than the barrier φBA1. ΦBA3-ΦBA1> 0. Further, the potential of the barrier φBA2 and the potential of the barrier φBA3 are, for example, the same depth as each other. φBA2 = φBA3.
 センサ有りOPB画素50のポテンシャルφSens1は、障壁φBA1、φBA2よりもそれぞれポテンシャルが深い。センサ有りOPB画素50のポテンシャルφSens1とは、例えば、センサ有りOPB画素50におけるN+層110(後述の図7A参照)のポテンシャルである。 The potential φSens1 of the OPB pixel 50 with a sensor has a deeper potential than the barriers φBA1 and φBA2, respectively. The potential φSens1 of the OPB pixel 50 with a sensor is, for example, the potential of the N + layer 110 (see FIG. 7A described later) in the OPB pixel 50 with a sensor.
 センサ有りOPB画素50は、センサ有りOPB画素50で生成された電荷を転送するためのゲート電極TG1(本開示の「第1ゲート電極」の一例)を有する。センサ有りOPB画素50は、ゲート電極TG1を有する転送トランジスタ32(図1参照)を介して、フローティングディフュージョンFDに接続されている。ゲート電極TG1の周囲には、電荷の移動を妨げる障壁φTG1が存在する。ゲート電極TG1に電圧が印加されて、障壁φTG1のポテンシャルがセンサ有りOPB画素50のポテンシャルφSens1よりも深くなると、転送ゲートがオンになり、センサ有りOPB画素50に蓄積されていた電荷e-が、フローティングディフュージョンFDに転送される。 The sensor-equipped OPB pixel 50 has a gate electrode TG1 (an example of the "first gate electrode" of the present disclosure) for transferring the electric charge generated by the sensor-equipped OPB pixel 50. The OPB pixel 50 with a sensor is connected to the floating diffusion FD via a transfer transistor 32 (see FIG. 1) having a gate electrode TG1. Around the gate electrode TG1, there is a barrier φTG1 that hinders the movement of electric charges. When a voltage is applied to the gate electrode TG1 and the potential of the barrier φTG1 becomes deeper than the potential φSens1 of the OPB pixel 50 with a sensor, the transfer gate is turned on and the charge e- accumulated in the OPB pixel 50 with a sensor becomes. Transferred to the floating diffusion FD.
 センサ無しOPB画素60のポテンシャルφSens2は、障壁φBA1、φBA2の各々よりもポテンシャルが深い。センサ無しOPB画素60のポテンシャルφSens2とは、例えば、センサ無しOPB画素60におけるN+層110(後述の図8A参照)のポテンシャルである。同様に、オーバーフロードレイン画素70のポテンシャルφSens3は、障壁φBA1、φBA2、φBA3の各々よりもポテンシャルが深い。オーバーフロードレイン画素70のポテンシャルφSens3とは、例えば、オーバーフロードレイン画素70におけるN+層110(後述の図9参照)のポテンシャルである。 The potential φSens2 of the OPB pixel 60 without a sensor has a deeper potential than each of the barriers φBA1 and φBA2. The potential φSens2 of the OPB pixel 60 without a sensor is, for example, the potential of the N + layer 110 (see FIG. 8A described later) in the OPB pixel 60 without a sensor. Similarly, the potential φSens3 of the overflow / drain pixel 70 has a deeper potential than each of the barriers φBA1, φBA2, and φBA3. The potential φSens3 of the overflow drain pixel 70 is, for example, the potential of the N + layer 110 (see FIG. 9 described later) in the overflow drain pixel 70.
 センサ無しOPB画素60で生じた電荷e-(例えば、暗電流成分)のうち、センサ無しOPB画素60でオーバーフローした電荷e-は、上記した障壁高さの大小関係により、障壁ΦBA1を超えるよりも、障壁ΦBA2、ΦBA3を超える方が容易となっている。これにより、センサ無しOPB画素60でオーバーフローした電荷e-は、障壁φBA1によってセンサ有りOPB画素50への移動が抑制され、隣接するセンサ無しOPB画素60、又は、隣接するオーバーフロードレイン画素70へ移動する。 Of the charge e- (for example, the dark current component) generated in the OPB pixel 60 without a sensor, the charge e- overflowing in the OPB pixel 60 without a sensor is larger than exceeding the barrier ΦBA1 due to the magnitude relationship of the barrier height described above. , It is easier to exceed the barriers ΦBA2 and ΦBA3. As a result, the charge e-overflowing in the OPB pixel 60 without the sensor is suppressed from moving to the OPB pixel 50 with the sensor by the barrier φBA1 and moves to the OPB pixel 60 without the sensor or the adjacent overflow drain pixel 70. ..
 オーバーフロードレイン画素70は、例えばゲート電極TG3を有する転送トランジスタ32(図1参照)を介して、フローティングディフュージョンFDに接続されている。フローティングディフュージョンFDは、例えばリセットトランジスタ36(図1参照)を介して、正の電源線Vdd(本開示の「予め設定された正電位」の一例)に接続される。 The overflow / drain pixel 70 is connected to the floating diffusion FD via, for example, a transfer transistor 32 (see FIG. 1) having a gate electrode TG3. The floating diffusion FD is connected to a positive power line Vdd (an example of the "preset positive potential" of the present disclosure), for example, via a reset transistor 36 (see FIG. 1).
 ゲート電極TG3の周囲には、電荷の移動を妨げる障壁φTG3(本開示の「第5障壁」の一例)が存在する。ゲート電極TG3に電圧が印加されて、障壁φTG3のポテンシャルがオーバーフロードレイン画素70のポテンシャルφSens3よりも深くなると、転送ゲートがオンになり、オーバーフロードレイン画素70に蓄積されていた電荷e-は、フローティングディフュージョンFDを経由して、正の電源線Vddに排出される。なお、オーバーフロードレイン画素70の転送ゲートは、第3ゲート電極に電圧が印加されていない状態でオン(すなわち、常時オン)であってもよい。これにより、オーバーフロードレイン画素70は、正の電源線Vddに常時排出される。 Around the gate electrode TG3, there is a barrier φTG3 (an example of the “fifth barrier” of the present disclosure) that hinders the movement of electric charges. When a voltage is applied to the gate electrode TG3 and the potential of the barrier φTG3 becomes deeper than the potential φSens3 of the overflow drain pixel 70, the transfer gate is turned on and the charge e- accumulated in the overflow drain pixel 70 is a floating diffusion. It is discharged to the positive power line Vdd via the FD. The transfer gate of the overflow / drain pixel 70 may be on (that is, always on) in a state where no voltage is applied to the third gate electrode. As a result, the overflow / drain pixel 70 is constantly discharged to the positive power supply line Vdd.
 また、図5に示すように、センサ無しOPB画素60は、ゲート電極TG1(図4参照)と同じ構造を有するゲート電極TG2(本開示の「第2ゲート電極」の一例)を有する。ゲート電極TG2の周囲には、電荷の移動を妨げる障壁φTG2(本開示の「第4障壁」の一例)が存在する。障壁φBA2は、障壁φTG2よりもポテンシャルが深い(すなわち、障壁高さが低い)。ΦBA2-ΦTG2>0である。障壁φTG2のポテンシャルは、ゲート電極TG2に電圧が印加されているときと、ゲート電極TGに電圧が印加されてないときとで、互いに同じ深さである。すなわち、障壁φTG2のポテンシャルは、ゲート電極TG2への電圧の印加、非印加に関わりなく、一定の深さである。これにより、センサ無しOPB画素60でオーバーフローした電荷e-は、障壁φTG2によってフローティングディフュージョンFDへの移動が抑制され、隣接するセンサ無しOPB画素60、又は、隣接するオーバーフロードレイン画素70へ移動する。 Further, as shown in FIG. 5, the OPB pixel 60 without a sensor has a gate electrode TG2 (an example of the “second gate electrode” of the present disclosure) having the same structure as the gate electrode TG1 (see FIG. 4). Around the gate electrode TG2, there is a barrier φTG2 (an example of the “fourth barrier” of the present disclosure) that hinders the movement of electric charges. The barrier φBA2 has a deeper potential (that is, the barrier height is lower) than the barrier φTG2. ΦBA2-ΦTG2> 0. The potential of the barrier φTG2 is the same depth when a voltage is applied to the gate electrode TG2 and when a voltage is not applied to the gate electrode TG. That is, the potential of the barrier φTG2 has a constant depth regardless of whether a voltage is applied to the gate electrode TG2 or not. As a result, the charge e-overflowing in the sensorless OPB pixel 60 is suppressed from moving to the floating diffusion FD by the barrier φTG2, and moves to the adjacent sensorless OPB pixel 60 or the adjacent overflow drain pixel 70.
 図6は、本開示の実施形態1に係るOPB領域R1の画質イメージを示す図である。上述したように、センサ無しOPB画素60でオーバーフローした電荷e-は、障壁φBA1によってセンサ有りOPB画素50への移動が抑制され、障壁φTG2によってフローティングディフュージョンFDへの移動が抑制される。これにより、図6に示すように、センサ有りOPB画素領域R11は、センサ無しOPB画素領域R12に隣接するセンサ有りOPB画素50の出力に不具合(例えば、後述の図6に示すような、白浮き)が生じることを抑制することができる。 FIG. 6 is a diagram showing an image quality image of the OPB region R1 according to the first embodiment of the present disclosure. As described above, the charge e-overflowing in the OPB pixel 60 without the sensor is suppressed from moving to the OPB pixel 50 with the sensor by the barrier φBA1, and the movement to the floating diffusion FD is suppressed by the barrier φTG2. As a result, as shown in FIG. 6, the OPB pixel region R11 with a sensor has a defect in the output of the OPB pixel 50 with a sensor adjacent to the OPB pixel region R12 without a sensor (for example, whitening as shown in FIG. 6 described later). ) Can be suppressed.
 図7Aは、本開示の実施形態1に係るセンサ有りOPB画素50の構成例を示す断面図である。図7Bは、本開示の実施形態1に係るセンサ有りOPB画素50のN+層110及びP+層120の構成例を示す平面図である。なお、図7Aは、図7Bに示す平面図をB-B´線を通るYZ平面で切断した断面を含んでいる。 FIG. 7A is a cross-sectional view showing a configuration example of the OPB pixel 50 with a sensor according to the first embodiment of the present disclosure. FIG. 7B is a plan view showing a configuration example of the N + layer 110 and the P + layer 120 of the OPB pixel 50 with a sensor according to the first embodiment of the present disclosure. Note that FIG. 7A includes a cross section of the plan view shown in FIG. 7B cut along the YZ plane passing through the BB'line.
 図7Aに示すように、センサ有りOPB画素50は、半導体層10に設けられたN+層110(本開示の「第2不純物拡散層」の一例)と、N+層110の周囲に設けられたP+層120と、P+層120上にゲート絶縁膜(図示せず)を介して設けられたゲート電極TG1と、を備える。例えば、P+層120は、N+層110の一方の面110a(図7Aでは、上面)側に位置する第1P+層121(本開示の「第1不純物拡散層」の一例)と、N+層110の他方の面110b(図7Aでは、下面)側に位置する第2P+層122と、N+層110の側面110cの側に位置する第3P+層123(本開示の「第3不純物拡散層」の一例)と、を有する。第3P+層123は、センサ有りOPB画素50及びセンサ無しOPB画素60の各々の周囲に設けられている。 As shown in FIG. 7A, the OPB pixel 50 with a sensor has an N + layer 110 provided on the semiconductor layer 10 (an example of the “second impurity diffusion layer” of the present disclosure) and a P + provided around the N + layer 110. A layer 120 and a gate electrode TG1 provided on the P + layer 120 via a gate insulating film (not shown) are provided. For example, the P + layer 120 is a first P + layer 121 (an example of the “first impurity diffusion layer” of the present disclosure) located on one surface 110a (upper surface in FIG. 7A) side of the N + layer 110, and the N + layer 110. A second P + layer 122 located on the side of the other surface 110b (lower surface in FIG. 7A) and a third P + layer 123 located on the side of the side surface 110c of the N + layer 110 (an example of the "third impurity diffusion layer" of the present disclosure). And have. The third P + layer 123 is provided around each of the OPB pixel 50 with a sensor and the OPB pixel 60 without a sensor.
 センサ有りOPB画素50では、例えば、N+層110と第1P+層121とによってフォトダイオードが構成されている。フォトダイオードで生じた電荷e-は、N+層110で蓄積される。センサ有りOPB画素50において、N+層110は電荷蓄積層として機能する。N+層110に蓄積された電荷e-は、ゲート電極TG1を有する転送トランジスタがオンすることによって、フローティングディフュージョンFD(例えば、図4参照)に信号として出力される。 In the OPB pixel 50 with a sensor, for example, a photodiode is composed of an N + layer 110 and a first P + layer 121. The charge e− generated by the photodiode is stored in the N + layer 110. In the OPB pixel 50 with a sensor, the N + layer 110 functions as a charge storage layer. The charge e− stored in the N + layer 110 is output as a signal to the floating diffusion FD (see, for example, FIG. 4) when the transfer transistor having the gate electrode TG1 is turned on.
 第3P+層123によって、センサ有りOPB画素50の画素間分離部が構成されている。図7Bに示すように、X軸方向及びY軸方向において、第3P+層123は、N+層110の周囲を囲んでいる。第3P+層123によって、センサ有りOPB画素50は、隣接画素間(例えば、隣接する他のセンサ有りOPB画素50との間、隣接するセンサ無しOPB画素50との間、又は、隣接するオーバーフロードレイン画素70との間)に障壁φBA1(例えば、図3、図4参照)を形成することができる。 The third P + layer 123 constitutes an inter-pixel separation portion of the OPB pixel 50 with a sensor. As shown in FIG. 7B, the third P + layer 123 surrounds the N + layer 110 in the X-axis direction and the Y-axis direction. By the third P + layer 123, the OPB pixel 50 with a sensor can be placed between adjacent pixels (for example, between an adjacent OPB pixel 50 with a sensor, between an adjacent OPB pixel 50 without a sensor, or an adjacent overflow drain pixel. A barrier φBA1 (see, for example, FIGS. 3 and 4) can be formed (between 70 and 70).
 図8Aは、本開示の実施形態1に係るセンサ無しOPB画素60の構成例を示す断面図である。図8Bは、本開示の実施形態1に係るセンサ無しOPB画素60のN+層110及びP+層120の構成例を示す平面図である。なお、図8Aは、図8Bに示す平面図をC-C´線を通るYZ平面で切断した断面を含んでいる。 FIG. 8A is a cross-sectional view showing a configuration example of the OPB pixel 60 without a sensor according to the first embodiment of the present disclosure. FIG. 8B is a plan view showing a configuration example of the N + layer 110 and the P + layer 120 of the sensorless OPB pixel 60 according to the first embodiment of the present disclosure. Note that FIG. 8A includes a cross section of the plan view shown in FIG. 8B cut along the YZ plane passing through the CC'line.
 図8Aに示すように、センサ無しOPB画素60は、半導体層10に設けられたN+層110と、N+層110の周囲に設けられたP+層120と、P+層120上にゲート絶縁膜(図示せず)を介して設けられたゲート電極TG2と、を備える。例えば、P+層120は、N+層110の一方の面110a(図8Aでは、上面)側に位置する第1P+層121Aと、N+層110の他方の面110b(図8Aでは、下面)側に位置する第2P+層122と、N+層110の側面110cの側に位置する第3P+層123と、を有する。 As shown in FIG. 8A, the sensorless OPB pixel 60 has an N + layer 110 provided on the semiconductor layer 10, a P + layer 120 provided around the N + layer 110, and a gate insulating film on the P + layer 120 (FIG. 8A). A gate electrode TG2 provided via (not shown) is provided. For example, the P + layer 120 is located on the first P + layer 121A located on one surface 110a (upper surface in FIG. 8A) side of the N + layer 110 and on the other surface 110b (lower surface in FIG. 8A) side of the N + layer 110. It has a second P + layer 122 and a third P + layer 123 located on the side surface 110c of the N + layer 110.
 センサ無しOPB画素60では、例えば、N+層110と第1P+層121Aとによってフォトダイオードが構成されている。フォトダイオードで生じた電荷e-は、N+層110で蓄積される。センサ無しOPB画素60においても、N+層110は電荷蓄積層として機能する。 In the OPB pixel 60 without a sensor, for example, a photodiode is composed of an N + layer 110 and a first P + layer 121A. The charge e− generated by the photodiode is stored in the N + layer 110. Even in the OPB pixel 60 without a sensor, the N + layer 110 functions as a charge storage layer.
 センサ無しOPB画素60が有するP+層121Aは、例えば、センサ有りOPB画素50が有するP+層121と比べて、厚さが大きい。これにより、センサ無しOPB画素60では、ゲート電極TG2を有する転送トランジスタがオンしないようになっている。N+層110で蓄積された電荷は、ゲート電極TG2を有する転送トランジスタを介してフローティングディフュージョンFD(例えば、図4参照)に信号として出力されることはない。N+層110と第1P+層121Aとで構成されるフォトダイオードは、信号をフローティングディフュージョンFDに出力しないため、センサとして機能しない。 The P + layer 121A of the OPB pixel 60 without a sensor has a larger thickness than, for example, the P + layer 121 of the OPB pixel 50 with a sensor. As a result, in the OPB pixel 60 without a sensor, the transfer transistor having the gate electrode TG2 is not turned on. The charge stored in the N + layer 110 is not output as a signal to the floating diffusion FD (see, for example, FIG. 4) via the transfer transistor having the gate electrode TG2. The photodiode composed of the N + layer 110 and the first P + layer 121A does not output a signal to the floating diffusion FD, and therefore does not function as a sensor.
 第3P+層123によって、センサ無しOPB画素60の画素間分離部が構成されている。図8Bに示すように、X軸方向及びY軸方向において、第3P+層123は、一部の領域R121(本開示の「非分離領域」の一例)を除いて、N+層110の周囲を囲んでいる。第3P+層123によって、センサ無しOPB画素60は、隣接するセンサ有りOPB画素50との間には、障壁φBA1を形成することができる。 The third P + layer 123 constitutes an inter-pixel separation portion of the OPB pixel 60 without a sensor. As shown in FIG. 8B, in the X-axis direction and the Y-axis direction, the third P + layer 123 surrounds the N + layer 110 except for a part of the region R121 (an example of the “non-separable region” of the present disclosure). I'm out. The third P + layer 123 allows the sensorless OPB pixel 60 to form a barrier φBA1 with the adjacent sensored OPB pixel 50.
 センサ無しOPB画素60の周囲には、第3P+層123が配置されない領域R121が1つ以上設けられている。Y軸方向(またはX軸方向、若しくはX軸方向及びY軸方向)で互いに隣接する一方のセンサ無しOPB画素60と他方のセンサ無しOPB画素60は、第3P+層123が配置されていない領域R121を通して、N+層110同士が接続している。これにより、センサ無しOPB画素60は、Y軸方向(またはX軸方向、若しくはX軸方向及びY軸方向)で隣接する他のセンサ無しOPB画素60との間に、障壁φBA1よりもポテンシャルが深い障壁φBA2を形成することができる。 Around the OPB pixel 60 without a sensor, one or more regions R121 in which the third P + layer 123 is not arranged are provided. One sensorless OPB pixel 60 and the other sensorless OPB pixel 60 adjacent to each other in the Y-axis direction (or the X-axis direction, or the X-axis direction and the Y-axis direction) are the regions R121 in which the third P + layer 123 is not arranged. Through, N + layers 110 are connected to each other. As a result, the sensorless OPB pixel 60 has a deeper potential than the barrier φBA1 between the sensorless OPB pixel 60 and the other sensorless OPB pixels 60 adjacent in the Y-axis direction (or the X-axis direction, or the X-axis direction and the Y-axis direction). The barrier φBA2 can be formed.
 図9は、本開示の実施形態1に係るOPB領域R1の構成例を示す断面図である。図9に示すように、センサ無しOPB画素60は、Y軸方向(またはX軸方向、若しくはX軸方向及びY軸方向)で隣接するオーバーフロードレイン画素70のN+層110とも、上記の領域R121を介して接続している。これにより、センサ無しOPB画素60は、Y軸方向(またはX軸方向、若しくはX軸方向及びY軸方向)で隣接するオーバーフロードレイン画素70との間に、障壁φBA1よりもポテンシャルが深い障壁φBA3を形成することができる。 FIG. 9 is a cross-sectional view showing a configuration example of the OPB region R1 according to the first embodiment of the present disclosure. As shown in FIG. 9, the sensorless OPB pixel 60 has the above-mentioned region R121 together with the N + layer 110 of the overflow drain pixels 70 adjacent to each other in the Y-axis direction (or the X-axis direction, or the X-axis direction and the Y-axis direction). Connecting via. As a result, the OPB pixel 60 without a sensor has a barrier φBA3 having a deeper potential than the barrier φBA1 between the overflow and drain pixels 70 adjacent to each other in the Y-axis direction (or the X-axis direction, or the X-axis direction and the Y-axis direction). Can be formed.
 図9において、センサ有りOPB画素50のゲート電極TG1は、通常画素領域R0(例えば、図1参照)の画素と同様に駆動される。ゲート電極TG1を有する転送トランジスタがオンすることによって、N+層110に蓄積された電荷e-は、フローティングディフュージョンFD(例えば、図4参照)に信号として出力される。 In FIG. 9, the gate electrode TG1 of the OPB pixel 50 with a sensor is driven in the same manner as the pixel in the normal pixel region R0 (see, for example, FIG. 1). When the transfer transistor having the gate electrode TG1 is turned on, the charge e− stored in the N + layer 110 is output as a signal to the floating diffusion FD (see, for example, FIG. 4).
 センサ無しOPB画素60のゲート電極TG2も、センサ有りOPB画素50のゲート電極TG1と同様に駆動される。このように駆動される場合でも、ゲート電極TG2を有する転送トランジスタはオンしないので、N+層110に蓄積された電荷e-がフローティングディフュージョンFDに信号として出力されることはない。 The gate electrode TG2 of the OPB pixel 60 without a sensor is also driven in the same manner as the gate electrode TG1 of the OPB pixel 50 with a sensor. Even when driven in this way, the transfer transistor having the gate electrode TG2 is not turned on, so that the charge e− stored in the N + layer 110 is not output as a signal to the floating diffusion FD.
 オーバーフロードレイン画素70において、ゲート電極TG3下のチャネルが形成される領域は、第1P+層121ではなく、N+層110となっている。これにより、ゲート電極TG3を有する転送トランジスタは常時オンとなり、オーバーフロードレイン画素70のN+層110を、フローティングディフュージョンFD(例えば、図4参照)に常時接続することができる。 In the overflow / drain pixel 70, the region where the channel under the gate electrode TG3 is formed is not the first P + layer 121 but the N + layer 110. As a result, the transfer transistor having the gate electrode TG3 is always on, and the N + layer 110 of the overflow drain pixel 70 can be constantly connected to the floating diffusion FD (see, for example, FIG. 4).
 また、ゲート電極TG3を有する転送トランジスタに直列に接続されるリセットトランジスタも、常時オンであってよい。これにより、オーバーフロードレイン画素70のN+層110を、フローティングディフュージョンFDを及びリセットトランジスタを介して電源線Vdd(例えば、図4参照)に常時接続することができる。センサ無しOPB画素60でオーバーフローした電荷e-は、障壁φBA2、φBA3を超えて、電源線Vddに常時排出される。 Further, the reset transistor connected in series with the transfer transistor having the gate electrode TG3 may also be always on. Thereby, the N + layer 110 of the overflow drain pixel 70 can be constantly connected to the power supply line Vdd (for example, see FIG. 4) via the floating diffusion FD and the reset transistor. The electric charge e− overflowing in the OPB pixel 60 without a sensor exceeds the barriers φBA2 and φBA3 and is constantly discharged to the power supply line Vdd.
(比較例)
 図10は、本開示の比較例に係るOPB領域R1´のポテンシャル分布を示す図である。図11は、本開示の比較例に係るOPB領域R1´の画質イメージを示す図である。図10に示すように、比較例に係るOPB領域R1´では、センサ有りOPB画素50´とセンサ無しOPB画素60´との隣接画素間に障壁φBA1´が存在する。また、センサ無しOPB画素60´同士の隣接画素間に障壁φBA2´が存在する。障壁φBA2´は、障壁φBA1´とポテンシャル深さが同じである。ΦBA2´=ΦBA1´である。また、センサ無しOPB画素60´とオーバーフロードレイン画素70´との隣接画素間には、障壁φBA3´が存在する。障壁φBA3´は、障壁φBA1´とポテンシャル深さが同じである。ΦBA3´=ΦBA1´である。
(Comparative example)
FIG. 10 is a diagram showing the potential distribution of the OPB region R1 ′ according to the comparative example of the present disclosure. FIG. 11 is a diagram showing an image quality image of the OPB region R1 ′ according to the comparative example of the present disclosure. As shown in FIG. 10, in the OPB region R1 ′ according to the comparative example, there is a barrier φBA1 ′ between the adjacent pixels of the OPB pixel 50 ′ with the sensor and the OPB pixel 60 ′ without the sensor. Further, there is a barrier φBA2 ′ between adjacent pixels of the OPB pixels 60 ′ without a sensor. The barrier φBA2 ′ has the same potential depth as the barrier φBA1 ′. ΦBA2'= ΦBA1'. Further, there is a barrier φBA3 ′ between the adjacent pixels of the OPB pixel 60 ′ without the sensor and the overflow drain pixel 70 ′. The barrier φBA3 ′ has the same potential depth as the barrier φBA1 ′. ΦBA3'= ΦBA1'.
 比較例に係るOPB領域R1´では、ΦBA3´=φBA2´=ΦBA1´の関係により、センサ無しOPB画素60´でオーバーフローした電荷e-は、障壁ΦBA1´を超え易くなっている。センサ無しOPB画素60´でオーバーフローした電荷e-が、障壁φBA1´を超えてセンサ有りOPB画素50へ移動すると、図11に示すように、センサ無しOPB画素領域R12´に隣接するセンサ有りOPB画素50の出力に、白浮きが生じる可能性がある。 In the OPB region R1 ′ according to the comparative example, the charge e-overflowing in the OPB pixel 60 ′ without the sensor tends to exceed the barrier ΦBA1 ′ due to the relationship of ΦBA3 ′ = φBA2 ′ = ΦBA1 ′. When the charge e-overflowing in the sensorless OPB pixel 60'moves to the sensored OPB pixel 50 beyond the barrier φBA1', as shown in FIG. 11, the sensored OPB pixel adjacent to the sensorless OPB pixel area R12' Whitening may occur in the output of 50.
(実施形態1の効果)
 以上説明したように、本開示の実施形態1に係る撮像装置1は、半導体層10に設けられ、被写体からの光を受光する通常画素領域R0と、半導体層10に設けられ、光が遮光されるOPB領域R1と、を備える。OPB領域R1は、光を検出して信号を出力するセンサ機能を有するセンサ有りOPB画素50と、センサ機能がないセンサ無しOPB画素60と、を有する。互いに隣接するセンサ有りOPB画素50とセンサ無しOPB画素60との間には、電荷e-の移動を妨げる障壁φBA1が存在する。互いに隣接するセンサ無しOPB画素60同士の間には電荷e-の移動を妨げるφBA2が存在する。φBA2は、φBA1よりもポテンシャルが深い。
(Effect of Embodiment 1)
As described above, the image pickup apparatus 1 according to the first embodiment of the present disclosure is provided in the semiconductor layer 10, a normal pixel region R0 that receives light from a subject, and is provided in the semiconductor layer 10 to block light. The OPB region R1 is provided. The OPB region R1 has an OPB pixel 50 with a sensor having a sensor function of detecting light and outputting a signal, and an OPB pixel 60 without a sensor having no sensor function. Between the OPB pixel 50 with a sensor and the OPB pixel 60 without a sensor adjacent to each other, there is a barrier φBA1 that hinders the movement of the electric charge e−. There is φBA2 between the sensorless OPB pixels 60 adjacent to each other, which hinders the movement of the electric charge e−. φBA2 has a deeper potential than φBA1.
 これによれば、センサ無しOPB画素60の周囲には、φBA2が存在する領域R121が1つ以上存在する。センサ無しOPB画素60に蓄積された電荷e-のうち、センサ無しOPB画素60で蓄積可能な容量を超えた分の電荷e-は、障壁φBA2を超えて、隣接する他のセンサ無しOPB画素60へオーバーフローする。一方、センサ有りOPB画素50とセンサ無しOPB画素60との間には、φBA1は存在するが、障壁φBA2は存在しない。障壁φBA1は、障壁φBA2よりもポテンシャル深さが浅いため、センサ無しOPB画素60からセンサ有りOPB画素50へ電荷e-が移動することが抑制される。これにより、撮像装置1は、センサ無しOPB画素60からの電荷e-のオーバーフローに起因してセンサ有りOPB画素50の出力に不具合(例えば、白浮き)が生じることを抑制することができる。 According to this, there is one or more regions R121 in which φBA2 exists around the OPB pixel 60 without a sensor. Of the charges e-stored in the sensorless OPB pixel 60, the charge e-that exceeds the capacity that can be stored in the sensorless OPB pixel 60 exceeds the barrier φBA2 and is adjacent to the other sensorless OPB pixel 60. Overflow to. On the other hand, between the OPB pixel 50 with the sensor and the OPB pixel 60 without the sensor, φBA1 exists, but the barrier φBA2 does not exist. Since the barrier φBA1 has a shallower potential than the barrier φBA2, it is possible to suppress the movement of the charge e-from the OPB pixel 60 without the sensor to the OPB pixel 50 with the sensor. As a result, the image pickup apparatus 1 can suppress the occurrence of defects (for example, whitening) in the output of the OPB pixel 50 with the sensor due to the overflow of the charge e− from the OPB pixel 60 without the sensor.
 また、センサ無しOPB画素60からの電荷e-の排出は、障壁φBA2が存在する領域R121を介して行われるため、センサ無しOPB画素60に電荷e-リセット用のコンタクトプラグを設ける必要はない。これにより、撮像装置1は、センサ有りOPB画素50とセンサ無しOPB画素60との間でレイアウトの違いを小さくでき、センサ有りOPB画素50とセンサ無しOPB画素60との間で光電変換効率や配線容量などを等価に近づけることができる。これにより、撮像装置1は、暗電流成分の算出に誤差が生じる可能性を低減できるため、画質の低下を抑制することができる。 Further, since the charge e- is discharged from the sensorless OPB pixel 60 via the region R121 in which the barrier φBA2 exists, it is not necessary to provide the sensorless OPB pixel 60 with a contact plug for charge e-reset. As a result, the image pickup apparatus 1 can reduce the difference in layout between the OPB pixel 50 with a sensor and the OPB pixel 60 without a sensor, and the photoelectric conversion efficiency and wiring between the OPB pixel 50 with a sensor and the OPB pixel 60 without a sensor. The capacity etc. can be made close to the equivalent. As a result, the image pickup apparatus 1 can reduce the possibility that an error occurs in the calculation of the dark current component, and thus can suppress the deterioration of the image quality.
(変形例)
 上記の実施形態1では、例えば図9に示したように、センサ有りOPB画素50、センサ無しOPB画素60、オーバーフロードレイン画素70の各ゲート電極TG1、TG2、TG3が、それぞれプレーナ構造を有する場合を示した。しかしながら、本開示の実施形態はこれに限定されない。本開示の実施形態では、各ゲート電極TG1、TG2、TG3の少なくとも1つ以上が、トレンチゲート構造を有してもよい。
(Modification example)
In the first embodiment, for example, as shown in FIG. 9, each of the gate electrodes TG1, TG2, and TG3 of the OPB pixel 50 with a sensor, the OPB pixel 60 without a sensor, and the overflow drain pixel 70 has a planar structure. Indicated. However, the embodiments of the present disclosure are not limited to this. In the embodiments of the present disclosure, at least one or more of the gate electrodes TG1, TG2, and TG3 may have a trench gate structure.
 図12は、本開示の実施形態1の変形例に係るセンサ有りOPB画素50Aの構成を示す断面図である。図12に示すように、センサ有りOPB画素50Aのゲート電極TG1は、トレンチゲート構造を有する。例えば、半導体層10には、一方の面10a側に開口し、N+層110に至る孔部H1が設けられている。ゲート電極TG1は、ゲート絶縁膜(図示せず)を介して孔部H1内に配置され、縦方向(例えば、Z軸方向)に延設された垂直ゲート電極VG1と、ゲート絶縁膜(図示せず)を介して半導体層10の一方の10a上に設けられた水平ゲート電極HG1と、を有する。垂直ゲート電極VG1と水平ゲート電極HG1は、互いに接続しており、一体に形成されている。図12に示すセンサ有りOPB画素50Aは、例えば図7Aに示したセンサ有りOPB画素50と同様に機能する。 FIG. 12 is a cross-sectional view showing the configuration of the OPB pixel 50A with a sensor according to the modified example of the first embodiment of the present disclosure. As shown in FIG. 12, the gate electrode TG1 of the OPB pixel 50A with a sensor has a trench gate structure. For example, the semiconductor layer 10 is provided with a hole H1 that opens on one surface 10a side and reaches the N + layer 110. The gate electrode TG1 is arranged in the hole H1 via a gate insulating film (not shown), and has a vertical gate electrode VG1 extending in the vertical direction (for example, the Z-axis direction) and a gate insulating film (not shown). It has a horizontal gate electrode HG1 provided on one 10a of the semiconductor layer 10 via the above. The vertical gate electrode VG1 and the horizontal gate electrode HG1 are connected to each other and are integrally formed. The sensor-equipped OPB pixel 50A shown in FIG. 12 functions in the same manner as the sensor-equipped OPB pixel 50 shown in FIG. 7A, for example.
 図13は、本開示の実施形態1の変形例に係るセンサ無しOPB画素60Aの構成を示す断面図である。図13に示すように、センサ無しOPB画素60Aのゲート電極TG2は、トレンチゲート構造を有する。例えば、半導体層10には、一方の10a側に開口し、N+層110に到達しない孔部H2が設けられている。孔部H2の底部は、P+層121A内に位置する。ゲート電極TG2は、ゲート絶縁膜(図示せず)を介して孔部H2内に配置され、縦方向(例えば、Z軸方向)に延設された垂直ゲート電極VG2と、ゲート絶縁膜(図示せず)を介して半導体層10の一方の面10a上に設けられた水平ゲート電極HG2と、を有する。垂直ゲート電極VG1と水平ゲート電極HG2は、互いに接続しており、一体に形成されている。図13に示すセンサ無しOPB画素60Aは、例えば図8Aに示したセンサ無しOPB画素60と同様に機能する。 FIG. 13 is a cross-sectional view showing the configuration of the sensorless OPB pixel 60A according to the modified example of the first embodiment of the present disclosure. As shown in FIG. 13, the gate electrode TG2 of the OPB pixel 60A without a sensor has a trench gate structure. For example, the semiconductor layer 10 is provided with a hole H2 that opens on one side of 10a and does not reach the N + layer 110. The bottom of the hole H2 is located within the P + layer 121A. The gate electrode TG2 is arranged in the hole H2 via a gate insulating film (not shown), and has a vertical gate electrode VG2 extending in the vertical direction (for example, the Z-axis direction) and a gate insulating film (not shown). It has a horizontal gate electrode HG2 provided on one surface 10a of the semiconductor layer 10 via the above. The vertical gate electrode VG1 and the horizontal gate electrode HG2 are connected to each other and are integrally formed. The sensorless OPB pixel 60A shown in FIG. 13 functions in the same manner as the sensorless OPB pixel 60 shown in FIG. 8A, for example.
<実施形態2>
 上記の実施形態では、隣接する画素間を分離する画素間分離部として、第3P+層123を例示した。しかしながら、本開示の実施形態において、隣接する画素間を分離する画素間分離部は、P型の不純物拡散層に限定されない。画素間分離部は、例えば、トレンチアイソレーションを有してもよい。
<Embodiment 2>
In the above embodiment, the third P + layer 123 is exemplified as a pixel-to-pixel separation unit that separates adjacent pixels. However, in the embodiment of the present disclosure, the pixel-to-pixel separation section that separates adjacent pixels is not limited to the P-type impurity diffusion layer. The inter-pixel separation unit may have, for example, trench isolation.
 図14Aは、本開示の実施形態2に係るセンサ有りOPB画素50Bの構成例を示す断面図である。図14Bは、本開示の実施形態2に係るセンサ有りOPB画素50BのN+層110及びDTI層133の構成例を示す平面図である。なお、図14Aは、図14Bに示す平面図をD-D´線を通るYZ平面で切断した断面を含んでいる。 FIG. 14A is a cross-sectional view showing a configuration example of the OPB pixel 50B with a sensor according to the second embodiment of the present disclosure. FIG. 14B is a plan view showing a configuration example of the N + layer 110 and the DTI layer 133 of the OPB pixel 50B with a sensor according to the second embodiment of the present disclosure. Note that FIG. 14A includes a cross section of the plan view shown in FIG. 14B cut along the YZ plane passing through the DD'line.
 図14Aに示すように、センサ有りOPB画素50Bは、画素間分離部として、STI(shallow Trench Isolation)層131と、DTI(Deep Trench Isolation)層133と、を有する。STI層131は、例えば、半導体層10の一方の面(図14では、上面)10a側に開口する溝部に、酸化シリコン(SiO2)等の絶縁膜又はポリシリコンが埋め込まれた構造を有する。DTI層133は、例えば、半導体層10の一方の面10aの反対側である他方の面(図14では、下面)側に開口する溝部に、SiO2等の絶縁膜又はポリシリコンが埋め込まれた構造を有する。図14Aに示すように、STI層131とDTI層133は互いに接している。半導体層10の一方の面10aの法線方向(例えば、Z軸方向)からの平面視で、STI層131とDTI層133は互いに重なるように配置されている。 As shown in FIG. 14A, the OPB pixel 50B with a sensor has an STI (shallow Trench Isolation) layer 131 and a DTI (Deep Trench Isolation) layer 133 as inter-pixel separation portions. The STI layer 131 has, for example, a structure in which an insulating film such as silicon oxide (SiO2) or polysilicon is embedded in a groove portion that opens on one surface (upper surface in FIG. 14) 10a side of the semiconductor layer 10. The DTI layer 133 has, for example, a structure in which an insulating film such as SiO2 or polysilicon is embedded in a groove that opens on the other surface (lower surface in FIG. 14) side opposite to one surface 10a of the semiconductor layer 10. Has. As shown in FIG. 14A, the STI layer 131 and the DTI layer 133 are in contact with each other. The STI layer 131 and the DTI layer 133 are arranged so as to overlap each other in a plan view from the normal direction (for example, the Z-axis direction) of one surface 10a of the semiconductor layer 10.
 図14Bに示すように、X軸方向及びY軸方向において、DTI層133は、N+層110の周囲を囲んでいる。DTI層133によって、センサ有りOPB画素50Bは、隣接画素間(例えば、隣接する他のセンサ有りOPB画素50Bとの間、隣接するセンサ無しOPB画素50Bとの間、又は、隣接するオーバーフロードレイン画素70との間)に障壁φBA1(例えば、図3、図4参照)を形成することができる。 As shown in FIG. 14B, the DTI layer 133 surrounds the N + layer 110 in the X-axis direction and the Y-axis direction. Due to the DTI layer 133, the OPB pixel 50B with a sensor is placed between adjacent pixels (for example, between an OPB pixel 50B with another sensor adjacent to it, between an OPB pixel 50B without an adjacent sensor, or an adjacent overflow drain pixel 70. A barrier φBA1 (see, for example, FIGS. 3 and 4) can be formed between the two.
 図15Aは、本開示の実施形態2に係るセンサ無しOPB画素60Bの構成例を示す断面図である。図15Bは、本開示の実施形態2に係るセンサ無しOPB画素60BのN+層110及びDTI層133の構成例を示す平面図である。なお、図15Aは、図15Bに示す平面図をD-D´線を通るYZ平面で切断した断面を含んでいる。 FIG. 15A is a cross-sectional view showing a configuration example of the OPB pixel 60B without a sensor according to the second embodiment of the present disclosure. FIG. 15B is a plan view showing a configuration example of the N + layer 110 and the DTI layer 133 of the sensorless OPB pixel 60B according to the second embodiment of the present disclosure. Note that FIG. 15A includes a cross section of the plan view shown in FIG. 15B cut along the YZ plane passing through the DD'line.
 図15Aに示すように、センサ無しOPB画素60Bは、半導体層10に設けられたN+層110と、N+層110の周囲に設けられたP+層120と、P+層120上にゲート絶縁膜(図示せず)を介して設けられたゲート電極TG2と、を備える。例えば、P+層120は、N+層110の一方の面110a(図15Aでは、上面)側に位置する第1P+層121Aと、N+層110の他方の面110b(図15Aでは、下面)側に位置する第2P+層122と、N+層110の側面110cの側に位置する第3P+層123と、を有する。 As shown in FIG. 15A, the sensorless OPB pixel 60B has an N + layer 110 provided on the semiconductor layer 10, a P + layer 120 provided around the N + layer 110, and a gate insulating film on the P + layer 120 (FIG. 15A). A gate electrode TG2 provided via (not shown) is provided. For example, the P + layer 120 is located on the first P + layer 121A located on one surface 110a (upper surface in FIG. 15A) side of the N + layer 110 and on the other surface 110b (lower surface in FIG. 15A) side of the N + layer 110. It has a second P + layer 122 and a third P + layer 123 located on the side surface 110c of the N + layer 110.
 図15Aに示すように、センサ無しOPB画素60Bは、画素間分離部として、STI層131と、DTI層133と、を有する。図15Bに示すように、X軸方向及びY軸方向において、DTI層133は、一部の領域R121を除いて、N+層110の周囲を囲んでいる。DTI層133によって、センサ無しOPB画素60Bは、隣接するセンサ有りOPB画素50Bとの間に、障壁φBA1を形成することができる。 As shown in FIG. 15A, the OPB pixel 60B without a sensor has an STI layer 131 and a DTI layer 133 as inter-pixel separation portions. As shown in FIG. 15B, in the X-axis direction and the Y-axis direction, the DTI layer 133 surrounds the N + layer 110 except for a part of the region R121. The DTI layer 133 allows the sensorless OPB pixel 60B to form a barrier φBA1 with the adjacent sensored OPB pixel 50B.
 また、Y軸方向(またはX軸方向、若しくはX軸方向及びY軸方向)で互いに隣接するセンサ無しOPB画素60BのN+層110同士は、上記の領域R121を介して接続している。上記の領域R121によって、センサ無しOPB画素60Bは、Y軸方向(またはX軸方向、若しくはX軸方向及びY軸方向)で隣接する他のセンサ無しOPB画素60Bとの間に、障壁φBA2を形成することができる。 Further, the N + layers 110 of the OPB pixels 60B without sensors adjacent to each other in the Y-axis direction (or the X-axis direction, or the X-axis direction and the Y-axis direction) are connected to each other via the above-mentioned region R121. Due to the above region R121, the sensorless OPB pixel 60B forms a barrier φBA2 with another sensorless OPB pixel 60B adjacent in the Y-axis direction (or X-axis direction, or X-axis direction and Y-axis direction). can do.
 実施形態1と同様に、実施形態2においても、撮像装置1は、センサ無しOPB画素60Bからの電荷e-のオーバーフローに起因してセンサ有りOPB画素50Bの出力に不具合(例えば、白浮き)が生じることを抑制することができる。また、撮像装置1は、センサ有りOPB画素50Bとセンサ無しOPB画素60Bとの間でレイアウトの違いを小さくでき、センサ有りOPB画素50Bとセンサ無しOPB画素60Bとの間で光電変換効率や配線容量などを等価に近づけることができる。これにより、撮像装置1は、暗電流成分の算出に誤差が生じる可能性を低減できるため、画質の低下を抑制することができる。 Similar to the first embodiment, in the second embodiment, the image pickup apparatus 1 has a defect (for example, whitening) in the output of the OPB pixel 50B with the sensor due to the overflow of the charge e-from the OPB pixel 60B without the sensor. It can be suppressed from occurring. Further, the image pickup apparatus 1 can reduce the difference in layout between the OPB pixel 50B with a sensor and the OPB pixel 60B without a sensor, and the photoelectric conversion efficiency and wiring capacity between the OPB pixel 50B with a sensor and the OPB pixel 60B without a sensor. Etc. can be brought close to the equivalent. As a result, the image pickup apparatus 1 can reduce the possibility that an error occurs in the calculation of the dark current component, and thus can suppress the deterioration of the image quality.
(変形例)
 本開示の実施形態2では、STI層131は無くてもよい。画素間分離部は、DTI層133とP型の不純物拡散層とで構成されていてもよいし、DTI層133のみで構成されていてもよい。
(Modification example)
In the second embodiment of the present disclosure, the STI layer 131 may be omitted. The inter-pixel separation unit may be composed of a DTI layer 133 and a P-type impurity diffusion layer, or may be composed of only the DTI layer 133.
 図16は、本開示の実施形態2の変形例に係るセンサ有りOPB画素50Cの構成を示す断面図である。図17は、本開示の実施形態2の変形例に係るセンサ無しOPB画素60Cの構成を示す断面図である。図16及び図17に示すように、この変形例では、画素間分離部がDTI層と第3P+層123とで構成されている。このような構成であっても、上記の実施形態2と同様の効果を奏する。 FIG. 16 is a cross-sectional view showing the configuration of the OPB pixel 50C with a sensor according to the modified example of the second embodiment of the present disclosure. FIG. 17 is a cross-sectional view showing the configuration of the OPB pixel 60C without a sensor according to the modified example of the second embodiment of the present disclosure. As shown in FIGS. 16 and 17, in this modification, the inter-pixel separation portion is composed of a DTI layer and a third P + layer 123. Even with such a configuration, the same effect as that of the second embodiment can be obtained.
<実施形態3>
 上記の実施形態1では、センサ無しOPB画素60同士の隣接画素間(または、センサ無しOPB画素60とオーバーフロードレイン画素70との隣接画素間)には、画素間分離部である第3P+層123の一部が除去された領域R121があり、この領域R121を介して、両画素のN+層110同士が接続することを説明した。また、この構成により、隣接画素間に障壁φBA2(または、障壁φBA3)が形成されることを説明した。しかしながら、本開示の実施形態において、上記の領域R121を介して接続する一方のN+層110と、他方のN+層120との間には、N+層110以外の他の不純物拡散層が介在していてもよく、他の不純物拡散層によって障壁φBA2(または、障壁φBA3)が形成されていてもよい。
<Embodiment 3>
In the first embodiment, the third P + layer 123, which is a pixel-to-pixel separation unit, is located between adjacent pixels of the sensorless OPB pixels 60 (or between adjacent pixels of the sensorless OPB pixel 60 and the overflow drain pixel 70). It has been described that there is a region R121 in which a part is removed, and the N + layers 110 of both pixels are connected to each other via this region R121. Further, it has been explained that the barrier φBA2 (or the barrier φBA3) is formed between the adjacent pixels by this configuration. However, in the embodiment of the present disclosure, an impurity diffusion layer other than the N + layer 110 is interposed between one N + layer 110 connected via the above region R121 and the other N + layer 120. The barrier φBA2 (or the barrier φBA3) may be formed by another impurity diffusion layer.
 図18は、本開示の実施形態3に係るOPB領域R1Aの構成例を示す断面図である。図18に示すように、OPB領域R1Aでは、センサ無しOPB画素60同士の隣接画素間に、N+層よりもN型不純物濃度が低い、N型又はN-型の不純物拡散層130(本開示の「第4不純物拡散層」の一例)が設けられている。N型又はN-型の不純物拡散層130によって、センサ無しOPB画素60同士の隣接画素間に障壁φBA2が形成されている。また、センサ無しOPB画素60とオーバーフロードレイン画素70との隣接画素間にも、N型又はN-型の不純物拡散層130が設けられている。N型又はN-型の不純物拡散層130によって、センサ無しOPB画素60とオーバーフロードレイン画素70との隣接画素間に障壁φBA3が形成されている。 FIG. 18 is a cross-sectional view showing a configuration example of the OPB region R1A according to the third embodiment of the present disclosure. As shown in FIG. 18, in the OPB region R1A, an N-type or N-type impurity diffusion layer 130 having a lower N-type impurity concentration than the N + layer between adjacent pixels of the sensorless OPB pixels 60 (the present disclosure). An example of a "fourth impurity diffusion layer") is provided. The N-type or N-type impurity diffusion layer 130 forms a barrier φBA2 between adjacent pixels of the sensorless OPB pixels 60. Further, an N-type or N-type impurity diffusion layer 130 is also provided between the adjacent pixels of the OPB pixel 60 without a sensor and the overflow / drain pixel 70. The N-type or N-type impurity diffusion layer 130 forms a barrier φBA3 between the adjacent pixels of the OPB pixel 60 without a sensor and the overflow drain pixel 70.
 実施形態3においても、撮像装置1は、実施形態1、2と同様の効果を奏する。また、実施形態3では、不純物拡散層130におけるN型不純物の濃度や、不純物拡散層130の水平方向の厚みを調整することにより、障壁φBA2のポテンシャルを所望の値に制御することが可能である。 Also in the third embodiment, the image pickup apparatus 1 has the same effect as that of the first and second embodiments. Further, in the third embodiment, the potential of the barrier φBA2 can be controlled to a desired value by adjusting the concentration of the N-type impurity in the impurity diffusion layer 130 and the horizontal thickness of the impurity diffusion layer 130. ..
<その他の実施形態>
 上記のように、本開示は実施形態及び変形例によって記載したが、この開示の一部をなす論述及び図面は本開示を限定するものであると理解すべきではない。この開示から当業者には様々な代替実施の形態、実施例及び運用技術が明らかとなろう。例えば、実施形態1から実施形態3の各構成を任意に組み合わせて、本開示の実施形態の構成としてもよい。また、上記の実施形態において、第1P+層121、第2P+層122、第3P+層123を、互いに異なる濃度としてもよい。このように、本技術はここでは記載していない様々な実施形態等を含むことは勿論である。上述した実施形態及び変形例の要旨を逸脱しない範囲で、構成要素の種々の省略、置換及び変更のうち少なくとも1つを行うことができる。また、本明細書に記載された効果はあくまでも例示であって限定されるものでは無く、また他の効果があってもよい。
<Other embodiments>
As mentioned above, this disclosure has been described by embodiments and variations, but the statements and drawings that form part of this disclosure should not be understood to limit this disclosure. This disclosure will reveal to those skilled in the art various alternative embodiments, examples and operational techniques. For example, the configurations of the first to third embodiments may be arbitrarily combined to form the configurations of the embodiments of the present disclosure. Further, in the above embodiment, the first P + layer 121, the second P + layer 122, and the third P + layer 123 may have different concentrations from each other. As described above, it goes without saying that the present technique includes various embodiments not described here. At least one of the various omissions, substitutions and modifications of the components may be made without departing from the gist of the embodiments and modifications described above. Further, the effects described in the present specification are merely exemplary and not limited, and other effects may be obtained.
 なお、本開示は以下のような構成も取ることができる。
(1)
 半導体層に設けられ、被写体からの光を受光する画素領域と、
 前記半導体層に設けられ、前記光が遮光されるオプティカルブラック領域と、を備え、
 前記オプティカルブラック領域は、
 前記光を検出して信号を出力するセンサ機能を有する第1画素と、
 前記センサ機能がない第2画素と、を有し
 互いに隣接する前記第1画素と前記第2画素との間には、電荷の移動を妨げる第1障壁が存在し、
 互いに隣接する前記第2画素同士の間には電荷の移動を妨げる第2障壁が存在し、
 前記第2障壁は、前記第1障壁よりもポテンシャルが深い、撮像装置。
(2)
 前記オプティカルブラック領域は、予め設定された正電位に接続される第3画素、をさらに有し、
 互いに隣接する前記第2画素と前記第3画素との間には電荷の移動を妨げる第3障壁が存在し、
 前記第3障壁は、前記第1障壁よりもポテンシャルが深い、前記(1)に記載の撮像装置。
(3)
 前記第3画素は、前記第3障壁よりもポテンシャルが深い、前記(2)に記載の撮像装置。
(4)
 前記第1画素は、前記第1画素で生成された電荷を転送するための第1ゲート電極を有し、
 前記第2画素は、前記第1ゲート電極と同じ構造を有する第2ゲート電極を有し、
 前記第2ゲート電極の周囲には、電荷の移動を妨げる第4障壁が存在し、
 前記第2障壁は、前記第4障壁よりもポテンシャルが深い、前記(1)から(3)のいずれか1項に記載の撮像装置。
(5)
 前記第4障壁のポテンシャルは、
 前記第2ゲート電極に電圧が印加されているときと、前記第2ゲート電極に前記電圧が印加されてないときとで、互いに同じ深さである、前記(4)に記載の撮像装置。
(6)
 前記第3画素は第3ゲート電極を有し、
 前記第3ゲート電極の周囲には、電荷の移動を妨げる第5障壁が存在し、
 前記第5障壁は、前記第3障壁よりもポテンシャルが深い、前記(2)に記載の撮像装置。
(7)
 前記第3ゲート電極による前記正電位との接続は常時オンである、前記(6)に記載の撮像装置。
(8)
 前記オプティカルブラック領域は、
 前記第1画素及び前記第2画素の各々の周囲に設けられた画素間分離部、をさらに備え、
 前記画素間分離部が前記第1障壁を形成し、
 前記第2画素の周囲には、前記画素間分離部が配置されていない非分離領域が1つ以上設けられている、前記(1)から前記(7)のいずれか1項に記載の撮像装置。
(9)
 前記第1画素及び前記第2画素の各々は、
 第1導電型の第1不純物拡散層と、
 前記第1不純物拡散層に接合された第2導電型の第2不純物拡散層と、を有し、
 互いに隣接する一方の前記第2画素と他方の前記第2画素は、前記非分離領域を通して、前記第2不純物拡散層同士が接続している前記(8)に記載の撮像装置。
(10)
 前記画素間分離部は、第1導電型の第3不純物拡散層を有する、前記(8)又は(9)に記載の撮像装置。
(11)
 前記画素間分離部は、トレンチアイソレーションを有する、前記(8)から(10)のいずれか1項に記載の撮像装置。
(12)
 前記非分離領域に配置された第2導電型の第4不純物拡散層、をさらに備え、
 前記第4不純物拡散層は、前記第2不純物拡散層よりも第2導電型の濃度が低い、前記(9)に記載の撮像装置。
The present disclosure may also have the following structure.
(1)
A pixel area provided on the semiconductor layer that receives light from the subject,
An optical black region provided on the semiconductor layer and shielded from the light is provided.
The optical black region is
The first pixel having a sensor function of detecting the light and outputting a signal,
There is a first barrier that hinders the movement of electric charges between the second pixel that does not have the sensor function and the first pixel that has and is adjacent to each other and the second pixel.
There is a second barrier that hinders the movement of electric charges between the second pixels that are adjacent to each other.
The second barrier is an image pickup device having a deeper potential than the first barrier.
(2)
The optical black region further comprises a third pixel, which is connected to a preset positive potential.
There is a third barrier that hinders the transfer of electric charge between the second pixel and the third pixel that are adjacent to each other.
The image pickup apparatus according to (1), wherein the third barrier has a deeper potential than the first barrier.
(3)
The image pickup apparatus according to (2), wherein the third pixel has a deeper potential than the third barrier.
(4)
The first pixel has a first gate electrode for transferring the charge generated by the first pixel.
The second pixel has a second gate electrode having the same structure as the first gate electrode.
Around the second gate electrode, there is a fourth barrier that hinders the transfer of electric charge.
The imaging device according to any one of (1) to (3), wherein the second barrier has a deeper potential than the fourth barrier.
(5)
The potential of the fourth barrier is
The image pickup apparatus according to (4) above, wherein the depth is the same when a voltage is applied to the second gate electrode and when the voltage is not applied to the second gate electrode.
(6)
The third pixel has a third gate electrode and has a third gate electrode.
Around the third gate electrode, there is a fifth barrier that hinders the transfer of electric charge.
The imaging device according to (2) above, wherein the fifth barrier has a deeper potential than the third barrier.
(7)
The image pickup apparatus according to (6) above, wherein the connection with the positive potential by the third gate electrode is always on.
(8)
The optical black region is
Further, an inter-pixel separation unit provided around each of the first pixel and the second pixel is provided.
The inter-pixel separation portion forms the first barrier, and the inter-pixel separation portion forms the first barrier.
The image pickup apparatus according to any one of (1) to (7) above, wherein one or more non-separable regions in which the inter-pixel separation portion is not arranged are provided around the second pixel. ..
(9)
Each of the first pixel and the second pixel
The first conductive type first impurity diffusion layer and
It has a second conductive type second impurity diffusion layer bonded to the first impurity diffusion layer.
The image pickup apparatus according to (8), wherein the second pixel on one side adjacent to each other and the second pixel on the other side are connected to each other through the non-separable region.
(10)
The image pickup apparatus according to (8) or (9) above, wherein the inter-pixel separation unit has a first conductive type third impurity diffusion layer.
(11)
The image pickup apparatus according to any one of (8) to (10) above, wherein the inter-pixel separation unit has trench isolation.
(12)
A second conductive type fourth impurity diffusion layer, which is arranged in the non-separable region, is further provided.
The image pickup apparatus according to (9) above, wherein the fourth impurity diffusion layer has a lower concentration of the second conductive type than the second impurity diffusion layer.
1 撮像装置
10 半導体層
10a、110a 一方の面
12 画素アレイ部
13 垂直駆動回路
14 カラム信号処理回路
15 水平駆動回路
16 出力回路
17 制御回路
21 画素
22 水平信号線
23 垂直信号線
24 データ出力信号線
30 読出回路
31 フォトダイオード
32 転送トランジスタ
34 増幅トランジスタ
35 選択トランジスタ
36 リセットトランジスタ
50、50A、50B、50C センサ有りOPB画素
60、60A、60B、60C センサ無しOPB画素
70 オーバーフロードレイン画素
90 遮光メタル
110 N+層
110b 他方の面
120 P+層
121、121A 第1P+層
122 第2P+層
123 第3P+層
130 不純物拡散層
131 STI層
133 DTI層
CF カラーフィルタ
FD フローティングディフュージョン
H1、H2 孔部
HG1、HG2 水平ゲート電極
ML マイクロレンズ
PD フォトダイオード
R0 通常画素領域
R1、R1A OPB領域
R11 センサ有りOPB画素領域
R12 センサ無しOPB画素領域
R13 オーバーフロードレイン画素領域
R121 領域
RST リセット信号
SEL 選択信号
TG、TG1、TG2、TG3 ゲート電極
TRG 転送信号
Vdd 電源線
VG1、VG2 垂直ゲート電極
φBA1、φBA2、ΦBA3、φTG1、φTG2、φTG3 障壁
φSens1、φSens2、φSens3 ポテンシャル
1 Image pickup device 10 Semiconductor layer 10a, 110a One side 12 Pixel array unit 13 Vertical drive circuit 14 Column signal processing circuit 15 Horizontal drive circuit 16 Output circuit 17 Control circuit 21 Pixel 22 Horizontal signal line 23 Vertical signal line 24 Data output signal line 30 Read circuit 31 Photodiode 32 Transfer transistor 34 Amplification transistor 35 Selective transistor 36 Reset transistor 50, 50A, 50B, 50C OPB pixel 60, 60A, 60B, 60C without sensor OPB pixel 70 Overflow drain pixel 90 Light-shielding metal 110 N + layer 110b The other surface 120 P + layer 121, 121A 1st P + layer 122 2nd P + layer 123 3rd P + layer 130 impurity diffusion layer 131 STI layer 133 DTI layer CF color filter FD floating diffusion H1, H2 hole HG1, HG2 horizontal gate electrode ML micro Lens PD photodiode R0 normal pixel area R1, R1A OPB area R11 with sensor OPB pixel area R12 without sensor OPB pixel area R13 overflow drain pixel area R121 area RST reset signal SEL selection signal TG, TG1, TG2, TG3 gate electrode TRG transfer signal Vdd power supply line VG1, VG2 vertical gate electrodes φBA1, φBA2, ΦBA3, φTG1, φTG2, φTG3 barrier φSens1, φSens2, φSens3 potential

Claims (12)

  1.  半導体層に設けられ、被写体からの光を受光する画素領域と、
     前記半導体層に設けられ、前記光が遮光されるオプティカルブラック領域と、を備え、
     前記オプティカルブラック領域は、
     前記光を検出して信号を出力するセンサ機能を有する第1画素と、
     前記センサ機能がない第2画素と、を有し
     互いに隣接する前記第1画素と前記第2画素との間には、電荷の移動を妨げる第1障壁が存在し、
     互いに隣接する前記第2画素同士の間には電荷の移動を妨げる第2障壁が存在し、
     前記第2障壁は、前記第1障壁よりもポテンシャルが深い、撮像装置。
    A pixel area provided on the semiconductor layer that receives light from the subject,
    An optical black region provided on the semiconductor layer and shielded from the light is provided.
    The optical black region is
    The first pixel having a sensor function of detecting the light and outputting a signal,
    There is a first barrier that hinders the movement of electric charge between the second pixel that does not have the sensor function and the first pixel that has and is adjacent to each other and the second pixel.
    There is a second barrier that hinders the movement of electric charges between the second pixels that are adjacent to each other.
    The second barrier is an image pickup device having a deeper potential than the first barrier.
  2.  前記オプティカルブラック領域は、予め設定された正電位に接続される第3画素、をさらに有し、
     互いに隣接する前記第2画素と前記第3画素との間には電荷の移動を妨げる第3障壁が存在し、
     前記第3障壁は、前記第1障壁よりもポテンシャルが深い、請求項1に記載の撮像装置。
    The optical black region further comprises a third pixel, which is connected to a preset positive potential.
    There is a third barrier that hinders the transfer of electric charge between the second pixel and the third pixel that are adjacent to each other.
    The imaging device according to claim 1, wherein the third barrier has a deeper potential than the first barrier.
  3.  前記第3画素は、前記第3障壁よりもポテンシャルが深い、請求項2に記載の撮像装置。 The imaging device according to claim 2, wherein the third pixel has a deeper potential than the third barrier.
  4.  前記第1画素は、前記第1画素で生成された電荷を転送するための第1ゲート電極を有し、
     前記第2画素は、前記第1ゲート電極と同じ構造を有する第2ゲート電極を有し、
     前記第2ゲート電極の周囲には、電荷の移動を妨げる第4障壁が存在し、
     前記第2障壁は、前記第4障壁よりもポテンシャルが深い、請求項1に記載の撮像装置。
    The first pixel has a first gate electrode for transferring the charge generated by the first pixel.
    The second pixel has a second gate electrode having the same structure as the first gate electrode.
    Around the second gate electrode, there is a fourth barrier that hinders the transfer of electric charge.
    The imaging device according to claim 1, wherein the second barrier has a deeper potential than the fourth barrier.
  5.  前記第4障壁のポテンシャルは、
     前記第2ゲート電極に電圧が印加されているときと、前記第2ゲート電極に前記電圧が印加されてないときとで、互いに同じ深さである、請求項4に記載の撮像装置。
    The potential of the fourth barrier is
    The image pickup apparatus according to claim 4, wherein the depth is the same when the voltage is applied to the second gate electrode and when the voltage is not applied to the second gate electrode.
  6.  前記第3画素は第3ゲート電極を有し、
     前記第3ゲート電極の周囲には、電荷の移動を妨げる第5障壁が存在し、
     前記第5障壁は、前記第3障壁よりもポテンシャルが深い、請求項2に記載の撮像装置。
    The third pixel has a third gate electrode and has a third gate electrode.
    Around the third gate electrode, there is a fifth barrier that hinders the transfer of electric charge.
    The imaging device according to claim 2, wherein the fifth barrier has a deeper potential than the third barrier.
  7.  前記第3ゲート電極による前記正電位との接続は常時オンである、請求項6に記載の撮像装置。 The imaging device according to claim 6, wherein the connection with the positive potential by the third gate electrode is always on.
  8.  前記オプティカルブラック領域は、
     前記第1画素及び前記第2画素の各々の周囲に設けられた画素間分離部、をさらに備え、
     前記画素間分離部が前記第1障壁を形成し、
     前記第2画素の周囲には、前記画素間分離部が配置されていない非分離領域が1つ以上設けられている、請求項1に記載の撮像装置。
    The optical black region is
    Further, an inter-pixel separation unit provided around each of the first pixel and the second pixel is provided.
    The inter-pixel separation portion forms the first barrier, and the inter-pixel separation portion forms the first barrier.
    The image pickup apparatus according to claim 1, wherein one or more non-separable regions in which the inter-pixel separation portion is not arranged are provided around the second pixel.
  9.  前記第1画素及び前記第2画素の各々は、
     第1導電型の第1不純物拡散層と、
     前記第1不純物拡散層に接合された第2導電型の第2不純物拡散層と、を有し、
     互いに隣接する一方の前記第2画素と他方の前記第2画素は、前記非分離領域を通して、前記第2不純物拡散層同士が接続している請求項8に記載の撮像装置。
    Each of the first pixel and the second pixel
    The first conductive type first impurity diffusion layer and
    It has a second conductive type second impurity diffusion layer bonded to the first impurity diffusion layer.
    The image pickup apparatus according to claim 8, wherein the second pixel on one side adjacent to each other and the second pixel on the other side are connected to each other through the non-separable region.
  10.  前記画素間分離部は、第1導電型の第3不純物拡散層を有する、請求項8に記載の撮像装置。 The image pickup apparatus according to claim 8, wherein the inter-pixel separation unit has a first conductive type third impurity diffusion layer.
  11.  前記画素間分離部は、トレンチアイソレーションを有する、請求項8に記載の撮像装置。 The image pickup apparatus according to claim 8, wherein the inter-pixel separation portion has trench isolation.
  12.  前記非分離領域に配置された第2導電型の第4不純物拡散層、をさらに備え、
     前記第4不純物拡散層は、前記第2不純物拡散層よりも第2導電型の濃度が低い、請求項9に記載の撮像装置。
     
    A second conductive type fourth impurity diffusion layer, which is arranged in the non-separable region, is further provided.
    The image pickup apparatus according to claim 9, wherein the fourth impurity diffusion layer has a lower concentration of the second conductive type than the second impurity diffusion layer.
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008205905A (en) * 2007-02-21 2008-09-04 Sony Corp Solid-state imaging apparatus and imaging apparatus
JP2013069958A (en) * 2011-09-26 2013-04-18 Sony Corp Imaging element, image pickup apparatus, manufacturing apparatus and manufacturing method
JP2013118573A (en) * 2011-12-05 2013-06-13 Nikon Corp Imaging apparatus
JP2019096914A (en) * 2019-03-18 2019-06-20 株式会社東芝 Solid state imaging device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008205905A (en) * 2007-02-21 2008-09-04 Sony Corp Solid-state imaging apparatus and imaging apparatus
JP2013069958A (en) * 2011-09-26 2013-04-18 Sony Corp Imaging element, image pickup apparatus, manufacturing apparatus and manufacturing method
JP2013118573A (en) * 2011-12-05 2013-06-13 Nikon Corp Imaging apparatus
JP2019096914A (en) * 2019-03-18 2019-06-20 株式会社東芝 Solid state imaging device

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