WO2022095786A1 - 存储器及神经形态芯片、数据处理方法 - Google Patents

存储器及神经形态芯片、数据处理方法 Download PDF

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Publication number
WO2022095786A1
WO2022095786A1 PCT/CN2021/127080 CN2021127080W WO2022095786A1 WO 2022095786 A1 WO2022095786 A1 WO 2022095786A1 CN 2021127080 W CN2021127080 W CN 2021127080W WO 2022095786 A1 WO2022095786 A1 WO 2022095786A1
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data
memory
volatile storage
read
storage unit
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PCT/CN2021/127080
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English (en)
French (fr)
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何伟
沈杨书
祝夭龙
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北京灵汐科技有限公司
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Priority claimed from CN202011212421.2A external-priority patent/CN112365912A/zh
Priority claimed from CN202011211266.2A external-priority patent/CN112365910A/zh
Application filed by 北京灵汐科技有限公司 filed Critical 北京灵汐科技有限公司
Publication of WO2022095786A1 publication Critical patent/WO2022095786A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
    • G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/402—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration individual to each memory cell, i.e. internal refresh

Definitions

  • the embodiments of the present disclosure relate to the field of chip technology, and in particular, to a memory, a neuromorphic chip, and a data processing method.
  • memory can be divided into volatile memory (Random Access Memory, RAM) and non-volatile memory (Non-Volatile memory, abbreviated as NVM).
  • RAM Random Access Memory
  • NVM Non-Volatile memory
  • the data in the volatile memory cannot be retained for a long time after the power is off, and the data in the non-volatile memory can be retained for a long time after the power is off.
  • non-volatile memory is scaled down to tens of nanometers or even smaller, its non-volatility is greatly challenged, and non-volatile memory often requires a compromise between storage density and data retention time.
  • the embodiments of the present disclosure provide a memory, a neuromorphic chip, and a data processing method, which can flexibly adjust the data storage duration according to actual application conditions, and realize long-term data storage by means of circuit compensation.
  • an embodiment of the present disclosure provides a memory, the memory includes: a non-volatile storage module, the non-volatile storage module includes a connected non-volatile storage unit and a refresh circuit; wherein, the The refresh circuit is used to read the stored data in the non-volatile storage unit, and write the stored data back to the non-volatile storage unit.
  • the non-volatile memory module further includes: a control unit; the control unit is connected to the refresh circuit, and is used to control a working state of the refresh circuit; wherein the working state at least includes a refresh frequency .
  • the non-volatile storage module further includes: a timer, the timer is connected to the control unit and the refresh circuit; the control unit is further configured to control the timing period of the timer , triggering the refresh circuit to read the storage data in the non-volatile storage unit at a refresh frequency matching the timing period, and write the storage data back to the non-volatile storage unit.
  • control unit is further configured to control the refresh circuit to read the storage data in the target storage area in the non-volatile storage unit, and write the storage data in the target storage area back to the The target storage area in the non-volatile storage unit.
  • the non-volatile storage unit includes a non-volatile memory array and a preset type controller; wherein the preset type controller is used to provide an interface of a preset protocol type for interfacing with an external device.
  • the preset protocol types include at least one of the following: a static random access memory interface protocol and an enhanced dynamic random access memory interface protocol.
  • the memory further includes: a volatile storage module and a preload circuit connected between the nonvolatile storage unit and the volatile storage module; wherein the preload circuit is used for The storage data in the non-volatile storage unit is read for preloading, and the volatile storage module is configured to read the storage data preloaded in the preload circuit and transmit it to the neuron computing core.
  • the memory further includes a receiving module; the receiving module is configured to receive a data reading instruction, and the data reading instruction includes information of the target storage data to be preloaded; the volatile storage module, for reading the preloaded storage data in the preload circuit before the receiving module receives the data reading instruction according to the data reading instruction, and transmitting the preloaded storage data Give the neuron a computing core; the preload circuit is configured to read the target storage data in the non-volatile storage unit for preloading according to the information of the target storage data.
  • the non-volatile memory module further includes: an arbiter; the arbiter is connected between the non-volatile memory unit and the refresh circuit, and is connected to the non-volatile memory between the unit and the preload circuit; the arbiter is used to determine whether the read stored data needs to be written through the refresh circuit after the stored data in the non-volatile storage unit is read Back to the non-volatile storage unit, it is still necessary to write to the preload circuit for preloading.
  • an arbiter is connected between the non-volatile memory unit and the refresh circuit, and is connected to the non-volatile memory between the unit and the preload circuit; the arbiter is used to determine whether the read stored data needs to be written through the refresh circuit after the stored data in the non-volatile storage unit is read Back to the non-volatile storage unit, it is still necessary to write to the preload circuit for preloading.
  • the volatile memory module includes: static random access memory.
  • the non-volatile storage unit includes: a magnetic memory.
  • the refresh frequency of the refresh circuit is a minute level or an hour level.
  • an embodiment of the present disclosure further provides a neuromorphic chip, where the neuromorphic chip includes: at least one memory provided in the first aspect above and at least one neuron computing core.
  • the memory is connected to each neuron computing core in the chip in the form of bus connection.
  • the memories are connected in a distributed correspondence with one or more neuron computing cores in the chip.
  • one of the memories is embedded in one or a plurality of designated neuron computing core areas.
  • an embodiment of the present disclosure further provides a data processing method, where the data processing method is applied to the memory according to the first aspect, and the data processing method includes: reading the nonvolatile memory through a preload circuit The stored data in the volatile storage module is preloaded for reading by the volatile storage module; the stored data preloaded in the preload circuit is read through the volatile storage module and transmitted to the neuron computing core.
  • the data processing method further includes: receiving a data reading instruction, where the data reading instruction includes information of target storage data to be preloaded;
  • the storage data preloaded in the preload circuit and transmitted to the neuron computing core includes: reading the preloaded storage data in the preload circuit according to the data reading instruction through the volatile storage module and transmitting giving the neuron computing core; the preloading by reading the stored data in the non-volatile storage module by the preloading circuit for reading by the volatile storage module, comprising: using the preloading circuit according to the data
  • the read instruction reads the target storage data in the non-volatile storage module for preloading.
  • the data processing method further includes: reading the stored data in the non-volatile storage unit through a refresh circuit, and writing the stored data back to the non-volatile storage unit.
  • the data processing method further includes: after the stored data in the non-volatile storage unit is read by an arbiter, judging whether the stored data needs to be written back to the non-volatile storage unit through the refresh circuit. Volatile memory cells still need to be written into the preload circuit for preloading.
  • the memory provided by the embodiments of the present disclosure includes a non-volatile storage module, and the non-volatile storage module includes a connected non-volatile storage unit and a refresh circuit.
  • the refresh circuit reads the stored data in the non-volatile storage unit and write the stored data back to the non-volatile storage unit, in the case of a fixed area of the non-volatile storage unit, the storage time of the data stored in the non-volatile storage unit is increased, and the flexible adjustment of data storage is achieved. Technical effect of time.
  • FIG. 1 is a schematic structural diagram of a memory in an embodiment of the present disclosure.
  • FIG. 2 is a schematic structural diagram of a non-volatile memory module in an embodiment of the present disclosure.
  • FIG. 3 is a schematic structural diagram of a nonvolatile memory cell in an embodiment of the present disclosure.
  • FIG. 4 is a schematic structural diagram of a memory in an embodiment of the present disclosure.
  • FIG. 5 is a schematic structural diagram of a memory in an embodiment of the present disclosure.
  • FIG. 6 is a schematic structural diagram of a neuromorphic chip in an embodiment of the present disclosure.
  • FIG. 7 is a schematic structural diagram of a neuromorphic chip in an embodiment of the present disclosure.
  • FIG. 8 is a schematic structural diagram of a neuromorphic chip in an embodiment of the present disclosure.
  • FIG. 9 is a schematic structural diagram of a neuromorphic chip in an embodiment of the present disclosure.
  • FIG. 10 is a flowchart of a data processing method in an embodiment of the present disclosure.
  • FIG. 1 is a schematic structural diagram of a memory in an embodiment of the present disclosure, which can be applied to any device, for example, a neuromorphic chip, a conventional chip, and the like.
  • the memory 10 provided by the embodiment of the present disclosure includes: a non-volatile storage module 100 , and the non-volatile storage module 100 includes a connected non-volatile storage unit 101 and a refresh circuit 102 .
  • the refresh circuit 102 is used to read the stored data in the non-volatile storage unit 101 and write the stored data back to the non-volatile storage unit 101 .
  • the non-volatile storage unit 101 may include: FLASH flash memory, phase change memory, ferroelectric memory (FRAM), resistive change memory (RRAM), magnetic memory (MRAM), spin memory (STT- RAM) and one or more of optical memory.
  • the non-volatile memory unit 101 may be a magnetic memory (MRAM).
  • MRAM magnetic memory
  • the specific implementation form of the nonvolatile storage unit 101 is not particularly limited in this embodiment of the present disclosure, and the nonvolatile storage unit 101 may also be implemented by using other nonvolatile memories.
  • the refresh circuit 102 is configured to refresh the stored data in the non-volatile storage unit 101, read the storage data in the non-volatile storage unit 101, and write the read storage data back In the non-volatile storage unit 101, the storage duration of the non-volatile storage unit 101 for storing the stored data is extended.
  • the stored data in the non-volatile storage unit is read through a refresh circuit, the stored data is written back to the non-volatile storage unit, and long-term data storage is realized by means of circuit compensation,
  • the data storage duration can be flexibly adjusted according to the actual application situation, and the flexibility of the use of the memory can be improved.
  • the memory of the embodiment of the present disclosure can ensure that when it is scaled down to tens of nanometers or even smaller, it still has good non-volatility, and can be applied to any scenario, and the memory of the embodiment of the present disclosure can be used to store any type of data .
  • the non-volatile storage unit 101 can be used to store relatively stable data of the neuron computing core, for example, can store the connection weight of the neuron computing core of the neuromorphic chip, network One or more of connection methods, neuron activation functions, and initialization information. Relatively stable data can be stored in the memory for a longer period of time through the refresh circuit.
  • the memory of the embodiment of the present disclosure may also be used to store relatively dynamic data, for example, input data to be processed.
  • the memory can also store relatively stable data and dynamic data at the same time.
  • part of the storage space can be used to store relatively stable data
  • the rest of the storage space can be used to store dynamic data
  • the refresh circuit can be used to store dynamic data.
  • the relatively stable stored data is read, and the read stored data is written back, which is not limited in this embodiment of the present disclosure.
  • the embodiment of the present disclosure does not limit the specific implementation form of the refresh circuit 102 , as long as it can refresh the stored data in the nonvolatile memory unit 101 .
  • the refresh frequency of the refresh circuit 102 is at the minute level or the hour level, that is, the data stored in the nonvolatile memory unit 101 is refreshed once every few minutes or every few hours.
  • the data storage duration of the MARM is related to its material and area. Assuming that the data storage duration of the MRAM is 10 minutes, the refresh frequency of the refresh circuit 102 can be set to once every 10 minutes, and the refresh circuit 102 performs the following operations every 10 minutes: read out, and write the read storage data back into the non-volatile storage unit 101 .
  • the refresh frequency of the refresh circuit 102 may also be set to the second level or the day level, which may be determined according to the data storage duration of the non-volatile storage unit 101 , which is not specifically limited in the embodiments of the present disclosure. .
  • the memory provided by the embodiment of the present disclosure consumes lower power due to data refresh.
  • a non-volatile storage module includes a connected non-volatile storage unit and a refresh circuit, and the refresh circuit reads the stored data in the non-volatile storage unit and writes the stored data back In the non-volatile storage unit, when the area of the non-volatile storage unit is fixed, the storage duration of the data stored in the non-volatile storage unit is effectively increased, and the technical effect of flexibly adjusting the data storage duration is achieved.
  • the storage time of the non-volatile memory cell is also fixed, for example, several minutes or several hours.
  • the data in the non-volatile storage unit is refreshed by the refresh circuit, which flexibly adjusts the storage duration of the data stored in the non-volatile storage unit, thereby achieving a longer storage effect with a smaller storage area and improving the memory.” non-volatile" effect.
  • the stored data of the non-volatile storage unit is refreshed by the refresh circuit, it is not permanently stored for a long time, and may also be "volatile” to a certain extent, that is, the memory provided by the embodiments of the present disclosure Based on the “non-volatile unit” and the refresh circuit to achieve the “volatile” effect, the “non-volatile” effect can also be achieved, and the use of the memory is highly flexible.
  • the non-volatile storage unit 101 of the memory can store for a duration of 10 minutes. If the storage duration of the memory is required to be longer than 10 minutes, the refresh circuit 102 can perform reading of the storage in the non-volatile storage unit 101 data, and write the stored data back to the refresh operation of the non-volatile storage unit 101 .
  • the refresh circuit 102 may perform at least one refresh operation according to the refresh frequency. For example, it may be refreshed every 8 minutes to ensure that the memory does not lose the stored data.
  • the refresh frequency of the refresh circuit is 0, and the memory can be stored for 10 minutes to achieve the effect of "volatility".
  • the memory of the embodiment of the present disclosure can be flexibly applied to various storage scenarios.
  • the area size and storage duration of the non-volatile storage unit may be flexibly set according to factors such as area constraints, customization requirements, and cost considerations of applicable scenarios, which are not limited in the embodiments of the present disclosure.
  • the non-volatile memory module 100 further includes: a control unit 103, the control unit 103 is connected to the refresh circuit 102, and is used for controlling the working state of the refresh circuit 102, wherein, The working state includes at least a refresh rate.
  • the refresh frequency of the refresh circuit 102 can be controlled by the control unit 103 .
  • the control unit 103 is implemented in the form of software and/or hardware, which is not specifically limited in this embodiment of the present disclosure.
  • the refresh frequency may be determined by an external system and sent to the control unit 103, or may be determined by the control unit 103 according to the storage duration of the non-volatile storage unit 101 and the duration to be stored.
  • the refresh frequency can be determined to be 0.
  • the storage duration to be stored is greater than or equal to the storage duration of the non-volatile storage unit 101, the The storage duration is determined by the refresh frequency. For example, the storage duration of a non-volatile storage unit is 1 hour, and the refresh frequency can be refreshed every 55 minutes to ensure that data can be stored for a long time, which is not specifically limited in this embodiment of the present disclosure.
  • the refresh circuit 102 stops working, that is, the data stored in the nonvolatile memory unit 101 will not be updated.
  • the refresh circuit 102 starts to work, and updates the stored data in the nonvolatile memory unit 101 according to the refresh frequency.
  • the chip where the memory is located is used to run a simple neural network.
  • the refresh frequency of the refresh circuit 102 can be set to zero by the control unit 103 , the refresh circuit stops working.
  • the read circuit in the chip reads the updated data in the off-chip DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory, double data rate synchronous dynamic random access memory). and write the weight to the non-volatile storage unit 101.
  • DDR SDRAM Double Data Rate Synchronous Dynamic Random Access Memory, double data rate synchronous dynamic random access memory
  • the working state may further include the number of refreshes.
  • the number of refreshes may be determined by an external system and sent to the control unit 103, or determined by the control unit 103 according to the duration to be stored and the refresh frequency. The disclosed embodiments do not limit this.
  • the non-volatile memory module 100 further includes: a timer 104, and the timer 104 is connected to the control unit 103 and the refresh circuit 102; correspondingly, the control unit 103 also uses In controlling the timing period of the timer 104, the refresh circuit 102 is triggered to read the stored data in the non-volatile storage unit 101 at a refresh frequency matching the timing period, and the storage data is written back to the non-volatile storage unit 101.
  • the control unit 103 can adjust the timing period of the timer 104 to realize the adjustment of the refresh frequency of the refresh circuit 102 . For example, when the control unit 103 sets the timing period of the timer 104 to 2 minutes, the refresh frequency of the refresh circuit 102 is refreshed every 2 minutes.
  • the timer 104 sends a refresh trigger signal to the refresh circuit 102 every time the timer 104 times the set timing period, and after the refresh circuit 102 receives the refresh trigger signal, executes the data stored in the non-volatile storage unit 101. Perform the update operation.
  • control unit 103 is further configured to control the refresh circuit 102 to read the storage data in the target storage area in the non-volatile storage unit 101 and write the storage data in the target storage area back The target storage area described in the non-volatile storage unit 101 .
  • the control command sent by the control unit 103 to the refresh circuit 102 may include a target addressing address, so that the refresh circuit 102 reads the stored data in the nonvolatile storage unit 101 according to the target addressing address, that is, reads the nonvolatile memory. store data in the storage area corresponding to the target addressing address in the volatile storage unit 101 , and write the read storage data back into the corresponding storage area in the non-volatile storage unit 101 .
  • the target addressing address in the control instruction sent by the control unit 103 to the refresh circuit 102 can be dynamically set.
  • the refresh circuit can select part of the stored data in the non-volatile storage unit to update, so as to increase the storage time of this part of the stored data.
  • the update processing is highly flexible, and the refresh power consumption is also reduced to a certain extent.
  • the non-volatile storage unit 101 includes a non-volatile memory array 1011 and a preset type controller 1012; wherein the preset type controller 1012 is used to provide For connecting to an interface of a preset protocol type of an external device, the external device is, for example, other devices of the chip where the memory 10 is located.
  • the preset protocol type includes at least one of the following: a static random access memory (Static Random-Access Memory, SRAM) interface protocol and an enhanced dynamic random access memory (EDRAM, enhanced dynamic memory) random access memory) interface protocol.
  • SRAM static random access memory
  • EDRAM enhanced dynamic random access memory
  • the external interface of the non-volatile storage unit 101 is realized by including a preset type controller 1012, which is used to realize the connection between the memory 10 and other devices in the chip.
  • the preset type controller 1012 included in the non-volatile storage unit 101 is an SRAM-like controller, and the SRAM-like controller provides the external interface of the non-volatile storage unit 101 , that is, the non-volatile storage unit 101
  • the external interface is the SRAM interface.
  • the preset type controller 1012 included in the non-volatile storage unit 101 is an EDRAM-like controller, and the EDRAM-like controller provides the external interface of the non-volatile storage unit 101, that is, the non-volatile storage unit
  • the external interface of 101 is the EDRAM interface.
  • the interface provided by the preset type controller 1012 is usually a general-purpose interface
  • the protocol of the external interface of the non-volatile storage unit 100 is a general interface protocol, such as the SRAM interface protocol or the EDRAM interface protocol, etc.
  • the memory 10 may further include a volatile storage module 200 , and a preload connected between the non-volatile storage module 100 and the volatile storage module 200 circuit 300.
  • the preload circuit 300 is used for reading the stored data in the non-volatile storage module 100 for preloading
  • the volatile storage module 200 is used for reading the stored data preloaded in the preload circuit 300 and transmitting it to the neuron Compute core 400.
  • the non-volatile memory module 100 is composed of a non-volatile memory array, and the read and write rate of its interface is usually relatively low, while the data read and write rate of the neuron computing core 400 is usually relatively high.
  • the embodiment of the present disclosure may connect the preload circuit 300 and the volatile memory module 200 between the non-volatile memory module 100 and the neuron computing core 400 .
  • the volatile memory module 200 is composed of a volatile memory array, and the read/write rate of its interface is usually relatively high, which can match the data read/write rate of the neuron computing core 400 , and thus can provide the neuron computing core 400 in time. Data is transmitted, thereby improving the processing efficiency of the neuron computing core 400 and the power consumption of the neuromorphic chip.
  • the volatile memory module 200 may be a static random access memory (SRAM).
  • the preload circuit 300 first stores the stored data after reading the non-volatile memory module 100, and waits for the volatile memory module 200 to read it.
  • the volatile memory module 200 reads the preload in advance in the preload circuit 300.
  • the loaded storage data is then transmitted to the neuron computing core 400 .
  • the embodiments of the present disclosure do not specifically limit the specific implementation form of the preload circuit, as long as it can read the stored data in the nonvolatile memory module 100 and perform the preload function.
  • the preload circuit is used to read the stored data in the non-volatile storage module for preloading, and the volatile storage module reads the preloaded storage data in the preload circuit and transmits it to the neuron computing core It solves the problem that the read and write rates of the non-volatile memory module and the neuron computing core do not match, and reduces the impact on the processing efficiency of the neuron computing core, resulting in increased chip power consumption and other problems.
  • the memory 10 further includes a receiving module (not shown in the figure), the receiving module is configured to receive a data reading instruction, and the data reading instruction includes the target storage data to be preloaded. information.
  • the volatile storage module 200 is configured to read, according to the data read command, the preloaded storage data in the preload circuit 300 before the receiving module receives the data read command, and store data that has been preloaded in the preload circuit 300. This preloaded storage data is passed to the neuron computing core 400 .
  • the preload circuit 300 is configured to read the target storage data in the non-volatile storage module 100 to perform preloading according to the information of the target storage data.
  • the volatile storage module 200 reads the data reading instruction received by the receiving module according to the data reading instruction
  • the data preloaded in the preload circuit 300 before is transmitted to the neuron computing core 400, and the preload circuit 300 reads the non-volatile storage module 100 according to the information of the target storage data to be preloaded in the data read instruction.
  • the target storage data in is preloaded.
  • the preloaded data read in the preload circuit 300 by the volatile memory module 200 is the data preloaded by the preload circuit at the previous moment.
  • the data read instruction sent by the neuron computing core 400 not only instructs the volatile memory module 200 to read the preloaded data in the preload circuit 300 and transmits it to the neuron computing core 400, but also instructs the preload circuit 300 to read the non-volatile data.
  • the target storage data in the volatile memory module 100 is preloaded.
  • the data read instruction sent by the neuron computing core 400 may include a first addressing address for instructing the volatile memory module 200 to read the preloaded data in the preload circuit 300, and a first addressing address for The second addressing address that instructs the preload circuit 300 to read the target storage data in the nonvolatile memory module 100 for preloading.
  • the preloading circuit 300 reads the stored data in the non-volatile memory module 100 for the first time to perform the preloading operation, which can be triggered and executed by power-on of the chip, which is not specifically limited in this embodiment of the present disclosure.
  • the preloading circuit 300 as long as the data is preloaded before the volatile storage module 200 reads it.
  • the non-volatile memory module 100 further includes: an arbiter 105 .
  • the arbiter 105 is connected between the nonvolatile memory unit 101 and the refresh circuit 102 , and between the nonvolatile memory unit 101 and the preload circuit 300 .
  • the arbiter 105 is used to determine after the stored data in the non-volatile storage unit 101 is read, whether the read storage data needs to be written back to the non-volatile storage unit 101 through the refresh circuit 102 or needs to be written into the preload circuit 300 for preloading.
  • the refresh circuit 102 and the preload circuit 300 in the non-volatile memory module 100 may share the same read circuit, and read the non-volatile memory cell 101 through the read circuit data stored in .
  • the arbiter 105 can determine that the read data should be written back into the non-volatile storage unit 101 to realize the non-volatile storage unit 101 The data refreshed should still be written into the preload circuit 300 for preloading.
  • the embodiments of the present disclosure do not specifically limit the specific implementation form of the read circuit, as long as the data stored in the nonvolatile storage unit 101 can be read.
  • the arbiter 105 can determine whether the read data should be written back to the non-volatile storage unit 101 to refresh the data of the non-volatile storage unit 101 according to the addressing address of the read circuit, or should be The preload circuit 300 is written to perform preload. For example, if the addressing address of the read circuit is the same as the second search address in the data read instruction sent by the neuron computing core 400 for instructing the preload circuit 300 to read the stored data in the non-volatile memory module 100 for preloading, If the address is the same, it is determined that the read data should be written into the preload circuit for preload.
  • the arbiter 105 may also determine, according to the control instruction received by the read circuit, whether the read data should be written back to the non-volatile storage unit 101 to refresh the data of the non-volatile storage unit 101, or should It is written into the preload circuit 300 for preload. For example, if the control command received by the read circuit is triggered by the refresh circuit 102 , it is determined that the read data should be written back into the non-volatile storage unit 101 .
  • an arbiter is set to judge the data flow of the stored data read in the non-volatile storage unit, assist the refresh circuit to refresh the stored data in the non-volatile storage unit, and assist in preloading The circuit preloads the stored data in the non-volatile memory cells to ensure the accuracy of the data flow.
  • FIG. 6 is a schematic structural diagram of a neuromorphic chip in an embodiment of the present disclosure, which is applicable to the case of neural network computing.
  • a neuromorphic chip 1 provided by an embodiment of the present disclosure includes: at least one memory 10 described in any embodiment of the present disclosure (one memory 10 is shown in the figure) and a many-core array, and the many-core array includes At least one neuron computing core 50 .
  • the many-core array may be an APU (Accelerated Processing Unit, accelerated processor) many-core array.
  • APU Accelerated Processing Unit, accelerated processor
  • the neuromorphic chip shown in FIG. 6 is merely illustrative to show that the neuromorphic chip 1 includes the memory 10 and the neuron computing core 50, and does not specifically limit the structure of the neuromorphic chip 1.
  • one or more memories 10 may be included in a neuromorphic chip 1 .
  • the stored data in the memory 10 can be used jointly by multiple neuron computing cores 50;
  • the stored data in each memory 10 can be used by one neuron computing core 50 alone.
  • a plurality of neuron computing cores 50 are commonly used, or the stored data of a part of the memories of the plurality of memories 10 may be used by one neuron computing core 50 .
  • the memory 10 is connected to each neuron in the neuromorphic chip 1 in the form of a bus to calculate Core 50 connections.
  • the number of the memory 10 is only one, so the data stored therein is global to the chip and shared by all the neuron computing cores 50 (many cores) in the neuromorphic chip 1 . Furthermore, the data that needs to be used by each neuron computing core 50 does not need to be repeatedly stored for many times, thereby reducing the data storage area in the neuromorphic chip and also reducing the size of the neuromorphic chip. In addition, when the storage area of the memory 10 is small, the memory interface will also occupy a considerable proportion of the area, which reduces the number of the memory 10, which reduces the number of memory interfaces, and relatively increases the area of the data storage area in the total area of the memory. , which in turn increases the effective area of memory used in neuromorphic chips.
  • the neuromorphic chip 1 may further include other types of processors, such as ARM (Advanced RISC Machine) processors or CPU (Central Processing Unit, central processing unit), other types of processors can communicate and interact with other devices in chip 1 through the bus.
  • processors such as ARM (Advanced RISC Machine) processors or CPU (Central Processing Unit, central processing unit), other types of processors can communicate and interact with other devices in chip 1 through the bus.
  • ARM Advanced RISC Machine
  • CPU Central Processing Unit, central processing unit
  • the neuromorphic chip 1 may include an interface, and the interface may include: UART (Universal Asynchronous Receiver/Transmitter), I2C (Inter Integrated Circuit), One or more of the interfaces such as GPIO (General-Purpose Input/Output), DDR (Double Data Rate Synchronous Dynamic Random Access Memory, double-rate synchronous dynamic random access memory), etc.
  • the interface is used to connect the chip External devices, devices outside the chip can communicate and interact with other devices in the chip 1 through the interface of the chip 1 .
  • the neuromorphic chip 1 may further include a volatile memory 60 , and the volatile memory 60 may also be connected to each nerve in the neuromorphic chip 1 in the form of a bus connection.
  • the metacomputing core 50 is connected.
  • the volatile memory 60 and the memory 10 are used to store the data of the neuron computing core 50 in different operation stages.
  • the operation process will not only generate intermediate data with a large amount of data and frequent data changes but do not need to be stored for a long time, but also generate infrequent data changes and need to be stored for a long time. , Key data saved when power off.
  • Each neuron computing core 50 needs not only the volatile memory 60 as a memory buffer to calculate intermediate variables, but also the memory 10 as a hard disk to store data that needs to be stored for a long time, such as neuron connection mode and connection weight, so as to ensure that the chip can be stored after power failure. Save important network model data, and can quickly load data work after power-on.
  • the memory 10 may be used to store relatively stable data of the neuron computing core 50
  • the volatile memory 60 may be used to store relatively dynamic data of the neuron computing core 50
  • relatively stable data can be defined as data that needs to be reused, such as one or more of connection weights, network connection methods, neuron activation functions and initialization information
  • relatively dynamic data can be defined as data that does not need to be reused, For example, the data input by an external data source (host computer or external read-only memory) or the intermediate value calculated by the network, etc.
  • memory 10 may be used to store relatively stable and relatively dynamic data. For example, when there is one memory 10, part of the storage space of the memory may be used to store relatively stable data, and the remaining storage space may be used to store relatively dynamic data. When there are multiple memories 10, some of the memories 10 may be used to store relatively stable data, and the rest of the memories 10 may be used to store relatively dynamic data.
  • the memory 10 and one or more neuron computing cores 50 in the neuromorphic chip 1 Distributed corresponding connections. It can be understood that the neuron computing core 50 includes a computing unit 51 for data processing.
  • the memory 10 is distributed into the neuromorphic chip 1 and can be used as a functional unit of the neuron computing core 50 to realize the distributed embedded distribution of the memory 10 .
  • the embedded distributed memory 10 is connected to a plurality of neuron computing cores 50 of the neuromorphic chip architecture in a distributed correspondence to form an independent correspondence. That is, it is ensured that each distributed memory 10 is only connected to one or a limited number of neuron computing cores 50 .
  • the data may also be stored in one or more distributed memories 10 correspondingly.
  • each neuron computing core 50 is correspondingly connected to one or a limited plurality of distributed memories 10 .
  • the memory 10 may be of small capacity, built in the neuron computing core 50 as an independent non-volatile memory, so that each (or a limited number of) neuron computing cores contain both independent
  • the volatile memory also includes independent non-volatile memory, which can effectively alleviate the limitation of data communication bandwidth and improve the stability, reliability and processing efficiency of the system.
  • FIG. 8 exemplarily shows a situation in which each neuron computing core 50 is connected to a memory 10 correspondingly, and the memory 10 is embedded in the corresponding neuron computing core 50 , and embodiments of the present disclosure include but are not limited to this situation.
  • a memory 10 is embedded in one or a plurality of designated neuron computing core 50 regions.
  • FIG. 9 the case where one memory 10 is embedded in one, two, three and four designated areas of the neuron computing core 50 is exemplarily shown respectively.
  • the form of embedded distribution of the memory 10 in the chip architecture may be, based on multiple neuron computing cores in the chip architecture, according to each memory 10 Embedding distribution is performed corresponding to one or at the same time corresponding to multiple nearby neuron computing cores. That is, in a system with massively parallel computing or functional cores, each embedded distributed memory 10 is shared by a single or several neuron computing cores 50 .
  • the memory 10 is distributed into the neuromorphic chip 1 as a functional unit of the internal neuron computing core 50, so that each neuron computing core 50 and the corresponding memory 10 have independent
  • the data channel solves the data communication bottleneck problem caused by frequent updating of weights during online learning.
  • the chip architecture further includes a volatile memory 60 corresponding to each of the neuron computing cores 50 , wherein the volatile memory 60 and the memory 10 It is used to store the data of the neuron computing core 50 in different operation stages.
  • Each neuron computing core 50 uses a single memory 10 to store different data for the operation of that single neuron computing core 50 (or several neuron computing cores 50). Meanwhile, for each neuron computing core 50 , a volatile memory 60 needs to be included inside, and the volatile memory 60 includes but is not limited to static random access memory, registers, etc., and cooperates with the memory 10 .
  • volatile memory 60 is used to store one or more of a computational cache of neuron computational core 50 and the current neuron state.
  • the neuron computing core 50 will store the intermediate variables generated during operation such as its calculation cache, the current neuron state (membrane potential), etc., which is characterized by a large amount of data, Data changes frequently but does not need to be kept for long periods of time.
  • the above neuromorphic chip includes one or more memories provided by any embodiment of the present disclosure, and has effective effects corresponding to the memories.
  • the above neuromorphic chip includes one or more memories provided by any embodiment of the present disclosure, and has effective effects corresponding to the memories.
  • FIG. 10 is a flow chart of a data processing method in an embodiment of the present disclosure, and the method is applicable to a situation where a neuron computing core reads data in a memory to perform corresponding data processing.
  • the data processing method provided by the embodiment of the present disclosure includes a non-volatile storage module, a volatile storage module, and a non-volatile storage module connected to the non-volatile storage module.
  • the method includes the following steps S310 and S320.
  • Step S310 Read the stored data in the non-volatile storage module through the preload circuit to perform preloading, so as to be read by the volatile storage module.
  • Step S320 Read the preloaded storage data in the preload circuit through the volatile storage module and transmit it to the neuron computing core.
  • the preload circuit first stores the stored data after reading the non-volatile storage module, and waits for the volatile storage module to read, and the volatile storage module is stored in the preload circuit Read the preloaded data and send it to the neuron computing core.
  • the above technical solution solves the problem that the read and write rates of the non-volatile memory module and the neuron computing core do not match, and effectively improves the problems that affect the processing efficiency of the neuron computing core and increase the power consumption of the chip.
  • the above data processing method further includes: receiving a data read instruction, where the data read instruction includes information of target storage data to be preloaded.
  • step S320 may further include: through the volatile storage module According to the data read instruction, the preloaded storage data in the preload circuit is read and sent to the neuron computing core.
  • step S310 may further include:
  • the data read instruction reads the stored data in the non-volatile storage module for preloading.
  • the volatile storage module reads the data preloaded in the preload circuit according to the data read instruction and transmits it to the neuron computing core, and at the same time,
  • the preload circuit reads the stored data in the non-volatile memory module according to the data read instruction to perform preload.
  • the data read in the preload circuit by the volatile memory module is the data preloaded by the preload circuit at the previous moment.
  • the data read instruction sent by the neuron computing core not only instructs the volatile memory module to read data in the preload circuit and transmit it to the neuron computing core, but also instructs the preload circuit to read the non-volatile memory
  • the storage data in the storage module is preloaded.
  • the data read instruction sent by the neuron computing core includes a first addressing address for instructing the volatile memory module to read data in the preload circuit, and a first addressing address for instructing the preload circuit to read the non-volatile memory. The second addressing address for preloading the stored data in the volatile memory module.
  • the preloading circuit reads the stored data in the non-volatile memory module for the first time to perform the preloading operation, which can be triggered by power-on of the chip, which is not specifically limited in the embodiment of the present disclosure.
  • the volatile memory module can be preloaded before reading.
  • the above data processing method may further include the following steps: reading stored data in the non-volatile storage unit through a refresh circuit, and writing the stored data back to the non-volatile storage unit unit.
  • the refresh circuit periodically reads the stored data in the non-volatile storage unit, and writes the read storage data back into the non-volatile storage unit, so as to prolong the storage of the storage data in the non-volatile storage unit duration.
  • the refresh frequency of the refresh circuit is at the minute level or the hour level, that is, the data stored in the non-volatile storage unit is refreshed once every few minutes or every few hours.
  • the memory provided by the embodiments of the present disclosure consumes lower power due to data refresh.
  • the above data processing method further includes the following steps: after the stored data in the non-volatile storage unit is read by an arbiter, it is determined that the stored data needs to be written back to the non-volatile storage unit through the refresh circuit. Volatile memory cells still need to be written into the preload circuit for preloading.
  • the refresh circuit and the preload circuit in the non-volatile memory module may share the same read circuit, and the stored data in the non-volatile memory cell is read through the read circuit. After the data is read in the non-volatile memory cell through the read circuit, the arbiter can determine that the read data should be written back to the non-volatile memory cell to refresh the data of the non-volatile memory cell, Still should be written to the preload circuit for preload.
  • an arbiter is set to judge the data flow of the stored data read in the non-volatile storage unit, assist the refresh circuit to refresh the stored data in the non-volatile storage unit, and assist in preloading The circuit preloads the stored data in the non-volatile memory cells to ensure the accuracy of the data flow.

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Abstract

一种存储器及神经形态芯片、数据处理方法。该存储器（10）包括非易失性存储模块（100），非易失性存储模块（100）包括：相连的非易失性存储单元（101）和刷新电路（102）；其中，所述刷新电路（102）用于读取所述非易失性存储单元（101）中的存储数据，并将所述存储数据写回所述非易失性存储单元（101）。在非易失性存储单元面积固定的情况下，上述存储器增加了非易失性存储单元中存储数据的存储时长，达到了灵活调整数据存储时长的技术效果。

Description

存储器及神经形态芯片、数据处理方法 技术领域
本公开实施例涉及芯片技术领域，尤其涉及一种存储器及神经形态芯片、数据处理方法。
背景技术
按照数据存储时长，存储器可以分为易失性存储器(Random Access Memory，RAM)和非易失性存储器(Non-Volatile memory，缩写为NVM)。其中，易失性存储器中的数据在掉电后无法长时间保留，非易失性存储器中的数据在掉电后能够长时间保留。然而，当非易失性存储器微缩到几十纳米甚至更小的时候，其非易失性受到极大的挑战，非易失性存储器往往需在存储密度和数据保存时间之间进行折中。
发明内容
本公开实施例提供一种存储器及神经形态芯片、数据处理方法，可以根据实际应用情况灵活地调整数据存储时长，利用电路补偿的方式实现长期的数据保存。
第一方面，本公开实施例提供了一种存储器，该存储器包括：非易失性存储模块，所述非易失性存储模块包括相连的非易失性存储单元和刷新电路；其中，所述刷新电路用于读取所述非易失性存储单元中的存储数据，并将所述存储数据写回所述非易失性存储单元。
可选地，所述非易失性存储模块还包括：控制单元；所述控制单元与所述刷新电路相连，用于控制所述刷新电路的工作状态；其中，所述工作状态至少包括刷新频率。
可选地，所述非易失性存储模块还包括：计时器，所述计时器与所述控制单元、所述刷新电路相连；所述控制单元，还用于控制所述计时器的计时周期，以触发所述刷新电路以与所述计时周期匹配的刷新频率读取所述非易失性存储单元中的存储数据，并将所述存储数据写回所述非易失性存储单元。
可选地，所述控制单元还用于控制所述刷新电路读取所述非易失性存储单元中目标存储区域中的存储数据，并将所述目标存储区域中的存储数据写回所述非易失性存储单元中所述目标存储区域。
可选地，所述非易失性存储单元包括非易失性存储器阵列和预设类型控制器；其中，所述预设类型控制器用于提供用于对接外部器件的预设协议类型的接口。
可选地，所述预设协议类型至少包括下述之一：静态随机存取存储器接口协议和增强 动态随机存取存储器接口协议。
可选地，所述存储器还包括：易失性存储模块以及连接于所述非易失性存储单元与所述易失性存储模块之间的预载电路；其中，所述预载电路用于读取所述非易失性存储单元中的存储数据进行预载，所述易失性存储模块用于读取所述预载电路中预载的存储数据并传送给神经元计算核心。
可选地，所述存储器还包括接收模块；所述接收模块，用于接收数据读取指令，所述数据读取指令包括待预载的目标存储数据的信息；所述易失性存储模块，用于根据所述数据读取指令，读取在所述接收模块接收到所述数据读取指令之前所述预载电路中已预载的存储数据，并将所述已预载的存储数据传送给神经元计算核心；所述预载电路，用于根据所述目标存储数据的信息，读取所述非易失性存储单元中的目标存储数据进行预载。
可选地，所述非易失性存储模块还包括：仲裁器；所述仲裁器连接于所述非易失性存储单元和所述刷新电路之间，以及连接于所述非易失性存储单元和所述预载电路之间；所述仲裁器用于在所述非易失性存储单元中的存储数据被读取之后，判断被读取的所述存储数据是需要通过所述刷新电路写回所述非易失性存储单元，还是需要写入所述预载电路进行预载。
可选地，所述易失性存储模块包括：静态随机存取存储器。
可选地，所述非易失性存储单元包括：磁存储器。
可选地，所述刷新电路的刷新频率为分钟级别或者小时级别。
第二方面，本公开实施例还提供了一种神经形态芯片，该神经形态芯片包括：至少一个上述第一方面提供的存储器和至少一个神经元计算核心。
可选地，当所述存储器的数量为一个时，所述存储器以总线连接形式与所述芯片中的每个神经元计算核心连接。
可选地，当所述存储器的数量为多个时，所述存储器与所述芯片中的一个或多个神经元计算核心呈分布式对应连接。
可选地，一个所述存储器嵌入式地分布在一个或者指定的多个所述神经元计算核心区域。
第三方面，本公开实施例还提供了一种数据处理方法，该数据处理方法应用于上述第一方面所述的存储器，所述数据处理方法包括：通过预载电路读取所述非易失性存储模块中的存储数据进行预载，以供易失性存储模块读取；通过所述易失性存储模块读取所述预载电路中预载的存储数据并传送给神经元计算核心。
可选地，所述数据处理方法还包括：接收数据读取指令，所述数据读取指令包括待预载的目标存储数据的信息；所述通过所述易失性存储模块读取所述预载电路中预载的存储数据并传送给神经元计算核心，包括：通过所述易失性存储模块根据所述数据读取指令， 读取所述预载电路中已预载的存储数据并传送给神经元计算核心；所述通过预载电路读取所述非易失性存储模块中的存储数据进行预载，以供易失性存储模块读取，包括：通过预载电路根据所述数据读取指令，读取所述非易失性存储模块中的目标存储数据进行预载。
可选地，所述数据处理方法还包括：通过刷新电路读取非易失性存储单元中的存储数据，并将所述存储数据写回所述非易失性存储单元。
可选地，所述数据处理方法还包括：通过仲裁器在所述非易失性存储单元中的存储数据被读取之后，判断所述存储数据是需要通过所述刷新电路写回所述非易失性存储单元，还是需要写入所述预载电路进行预载。
本公开实施例提供的存储器，包括非易失性存储模块，非易失性存储模块包括相连的非易失性存储单元和刷新电路，刷新电路读取非易失性存储单元中的存储数据之后并将所述存储数据写回非易失性存储单元中，在非易失性存储单元面积固定的情况下，增加了非易失性存储单元中存储数据的存储时长，达到了灵活调整数据存储时长的技术效果。
附图说明
附图用来提供对本公开实施例的进一步理解，并且构成说明书的一部分，与本公开的实施例一起用于解释本公开，并不构成对本公开的限制。通过参考附图对详细示例实施例进行描述，以上和其它特征和优点对本领域技术人员将变得更加显而易见，在附图中：
图1是本公开实施例中的一种存储器的结构示意图。
图2是本公开实施例中的一种非易失性存储模块的结构示意图。
图3是本公开实施例中的一种非易失性存储单元的结构示意图。
图4是本公开实施例中的一种存储器的结构示意图。
图5是本公开实施例中的一种存储器的结构示意图。
图6是本公开实施例中的一种神经形态芯片的结构示意图。
图7是本公开实施例中的一种神经形态芯片的结构示意图。
图8是本公开实施例中的一种神经形态芯片的结构示意图。
图9是本公开实施例中的一种神经形态芯片的结构示意图。
图10是本公开实施例中的一种数据处理方法的流程图。
具体实施方式
下面结合附图和实施例对本公开作进一步的详细说明。可以理解的是，此处所描述的具体实施例仅仅用于解释本公开，而非对本公开的限定。另外还需要说明的是，为了便于描述，附图中仅示出了与本公开相关的部分而非全部结构。
图1是本公开实施例中的一种存储器的结构示意图，可适用于任意装置中，例如，神 经形态芯片、传统芯片等。如图1所示，本公开实施例提供的存储器10，包括：非易失性存储模块100，非易失性存储模块100包括相连的非易失性存储单元101和刷新电路102。其中，刷新电路102用于读取非易失性存储单元101中的存储数据，并将所述存储数据写回非易失性存储单元101。
在本公开实施例中，非易失性存储单元101可以包括：FLASH闪存、相变存储器、铁电存储器(FRAM)、阻变存储器(RRAM)、磁存储器(MRAM)、自旋存储器(STT-RAM)及光存储器中的一种或多种。示例性的，非易失性存储单元101可以为磁存储器(MRAM)。本公开实施例对于非易失性存储单元101的具体实现形式不作特殊限制，非易失性存储单元101还可以采用其他非易失性存储器实现。
在本公开实施例中，刷新电路102用于对非易失性存储单元101中的存储数据进行刷新，读取非易失性存储单元101中的存储数据，并将读取的存储数据写回非易失性存储单元101中，以延长非易失性存储单元101存储所述存储数据的存储时长。
本公开实施例提供的存储器，通过刷新电路读取非易失性存储单元中的存储数据，并将所述存储数据写回非易失性存储单元，利用电路补偿的方式实现长期的数据保存，能够实现根据实际应用情况灵活地调整数据存储时长，提高存储器的使用灵活性。本公开实施例的存储器可以保证在微缩到几十纳米甚至更小的时候，仍具备较好的非易失性，可以适用于任意场景，且本公开实施例的存储器可用于存储任意类型的数据。
举例来说，在一种神经网络计算场景中，非易失性存储单元101中可以用于存储神经元计算核心的相对稳定数据，例如可以存储神经形态芯片的神经元计算核心的连接权重、网络连接方式、神经元激活函数和初始化信息等中的一种或多种。可以通过刷新电路保证相对稳定数据得以较长时间存储在存储器中。在另一种神经网络计算场景中，本公开实施例的存储器还可以用于存储相对动态的数据，例如，输入的待处理数据等。在另一种神经网络计算场景中，存储器还可以同时存储相对稳定的数据以及动态数据，例如，可以部分存储空间用于存储相对稳定的数据，其余存储空间用于存储动态数据，刷新电路用于读取相对稳定的存储数据，并将读取的存储数据写回，本公开实施例对此不做限制。
需要说明的是，本公开实施例对于刷新电路102的具体实现形式不作具体限制，只要能够实现对非易失性存储单元101中的存储数据进行刷新即可。
在本公开的一些实施例中，刷新电路102的刷新频率为分钟级别或者小时级别，也即每几分钟或每几小时将非易失性存储单元101中存储数据的刷新一次。
以非易失性存储单元101为MRAM为例，MARM的数据存储时长与其材料和面积有关。假设，MRAM的数据存储时长为10分钟，那么可以将刷新电路102的刷新频率设置为每10分钟一次，刷新电路102每10分钟执行一次如下操作：将非易失性存储单元101中的存储数据读取出来，并将读取的存储数据写回非易失性存储单元101中。
在本公开的一些实施例中，刷新电路102的刷新频率也可以设置为秒级别或者天级别，具体可根据非易失性存储单元101的数据存储时长确定，本公开实施例对此不作具体限定。
相比较于刷新频率为毫秒级别的DRAM(Dynamic Random Access Memory，动态随机存取存储器)，本公开实施例提供的存储器由于数据刷新消耗的功率会更低。
本公开实施例提供的存储器，非易失性存储模块包括相连的非易失性存储单元和刷新电路，刷新电路读取非易失性存储单元中的存储数据之后并将所述存储数据写回非易失性存储单元中，在非易失性存储单元面积固定的情况下，有效增加了非易失性存储单元中存储数据的存储时长，达到了灵活调整数据存储时长的技术效果。
在实际应用中，当非易失性存储单元的面积固定时，非易失性存储单元的存储时长也是固定的，例如是几分钟或者几小时。通过刷新电路对非易失性存储单元中数据进行刷新，灵活调整了非易失性存储单元中存储数据的存储时长，进而能够以较小的存储面积实现较长的存储效果，提升了存储器“非易失”的效果。同时，鉴于非易失性存储单元的存储数据是通过刷新电路进行刷新的，并非一成不变地长期存储，在一定程度上来讲也可以是“易失”的，也即本公开实施例提供的存储器可以基于“非易失性单元”和刷新电路来实现“易失性”的效果，也可以实现“非易失”的效果，存储器的使用灵活度较高。
举例来说，存储器的非易失性存储单元101能够存储的时长为10分钟，若需要存储器存储的时长大于10分钟，则可以通过刷新电路102执行读取非易失性存储单元101中的存储数据，并将所述存储数据写回非易失性存储单元101的刷新操作。可选的，刷新电路102可以按照刷新频率，执行至少一次刷新操作。例如，可以是每8分钟刷新一次，以保证存储器不丢失该存储数据。
在本公开的一些实施例中，若需要存储器存储的时长小于或者等于10分钟，则刷新电路的刷新频率为0，存储器可以存储10分钟，实现“易失性”的效果。
这样，本公开实施例的存储器可以灵活适用于各类存储场景。其中，非易失性存储单元的面积大小、能够存储的时长可以根据适用场景的面积约束、定制需求、成本考虑等因素灵活设置，本公开实施例对此不做限制。
在本公开的一些实施例中，如图2所示，非易失性存储模块100还包括：控制单元103，控制单元103与刷新电路102相连，用于控制刷新电路102的工作状态，其中，所述工作状态至少包括刷新频率。
在本公开的一些实施例中，可以通过控制单元103对刷新电路102的刷新频率进行控制。可选的，控制单元103以软件和/或硬件的形式实现，本公开实施例对此不作具体限制。刷新频率可以是通过外部系统确定并发送给控制单元103的，也可以是控制单元103根据非易失性存储单元101的存储时长以及待存储的时长确定的，例如，在待存储的时长 小于非易失性存储单元101的存储时长时，则可以确定刷新频率为0，在待存储的时长大于或等于非易失性存储单元101的存储时长时，则可以根据非易失性存储单元101的存储时长，确定刷新频率，例如，非易失性存储单元的存储时长为1小时，刷新频率可以是每55分钟刷新一次，以保证数据可以长期保存，本公开实施例对此不做具体限制。
当控制刷新电路102的刷新频率为零时，刷新电路102停止工作，也即不会对非易失性存储单元101中的存储数据进行更新。当控制刷新电路102的刷新频率非零时，刷新电路102开始工作，按照刷新频率对非易失性存储单元101中的存储数据进行更新。
在一些可选的应用场景中，存储器所在芯片用于运行简单的神经网络，神经网络的权重数据量较小或者权重更新比较频繁时，可以通过控制单元103将刷新电路102的刷新频率设置为零，刷新电路停止工作。此种情况下，当权重数据需要更新时，通过芯片中的读电路在芯片外的DDR SDRAM(Double Data Rate Synchronous Dynamic Random Access Memory，双倍数据率同步动态随机存取存储器)中读取更新后的权重并写入非易失性存储单元101即可。
在本公开的一些实施例中，工作状态还可以包括刷新次数，刷新次数可以是外部系统确定并发送给控制单元103的，也可以是控制单元103根据待存储的时长以及刷新频率确定的，本公开实施例对此不做限制。
在本公开的一些实施例中，如图2所示，非易失性存储模块100还包括：计时器104，计时器104与控制单元103、刷新电路102相连；相应的，控制单元103还用于控制计时器104的计时周期，以触发刷新电路102以与计时周期匹配的刷新频率读取非易失性存储单元101中的存储数据，并将所述存储数据写回非易失性存储单元101。
控制单元103可以调整计时器104的计时周期，以实现对刷新电路102的刷新频率的调整。例如，当控制单元103将计时器104的计时周期设置为2分钟时，则刷新电路102的刷新频率为每2分钟刷新一下。
可选的，计时器104每次计时到设置的计时周期时，向刷新电路102发送刷新触发信号，刷新电路102接收到该刷新触发信号之后，执行对非易失性存储单元101中的存储数据进行更新的操作。
在本公开的一些实施例中，控制单元103还用于控制刷新电路102读取非易失性存储单元101中目标存储区域中的存储数据，并将所述目标存储区域中的存储数据写回非易失性存储单元101中所述目标存储区域。
控制单元103发送给刷新电路102的控制指令中可以包括目标寻址地址，以使刷新电路102根据该目标寻址地址读取非易失性存储单元101中的存储数据，也即读取非易失性存储单元101中与该目标寻址地址对应的存储区域中的存储数据，并将读取到的存储数据写回非易失性存储单元101中对应的存储区域中。其中，控制单元103发送给刷新电路 102的控制指令中的目标寻址地址可以动态设置。
在上述实施方式中，根据控制单元的控制，刷新电路可以选取非易失性存储单元中的部分存储数据进行更新，以提升这部分存储数据的存储时长，对于不需要长时存储的数据则不进行更新处理，灵活性较高，也在一定程度上降低了刷新功耗。
在本公开的一些实施例中，如图3所示，非易失性存储单元101包括非易失性存储器阵列1011和预设类型控制器1012；其中，预设类型控制器1012用于提供用于对接外部器件的预设协议类型的接口，外部器件例如是存储器10所在芯片的其他器件。
在本公开的一些实施例中，所述预设协议类型至少包括下述之一：静态随机存取存储器(Static Random-Access Memory，SRAM)接口协议和增强动态随机存取存储器(EDRAM，enhanced dynamic random access memory)接口协议。
在本公开的一些实施例中，非易失性存储单元101的对外接口是通过其包括预设类型控制器1012实现的，用于实现存储器10与所在芯片内的其他器件的对接。
例如，非易失性存储单元101中包括的预设类型控制器1012为类SRAM控制器，由类SRAM控制器提供非易失性存储单元101的对外接口，也即非易失性存储单元101的对外接口为SRAM接口。
又例如，非易失性存储单元101中包括的预设类型控制器1012为类EDRAM控制器，由类EDRAM控制器提供非易失性存储单元101的对外接口，也即非易失性存储单元101的对外接口为EDRAM接口。
鉴于预设类型控制器1012提供的接口通常为通用型接口，进而非易失性存储单元100的对外接口的协议为通用的接口协议，如SRAM接口协议或EDRAM接口协议等，因此，开发人员在进行芯片开发时无需对非易失性存储单元101的接口进行特殊处理，以此降低了开发人员在芯片进行功能性开发时的工作复杂度。
在本公开的一些实施例中，如图4所示，存储器10还可以进一步包括易失性存储模块200，以及连接于非易失性存储模块100与易失性存储模块200之间的预载电路300。
其中，预载电路300用于读取非易失性存储模块100中的存储数据进行预载，易失性存储模块200用于读取预载电路300中预载的存储数据并传送给神经元计算核心400。
非易失性存储模块100是由非易失性存储器阵列组成的，其接口的读写速率通常比较低，而神经元计算核心400的数据读写速率通常比较高，将非易失性存储模块100应用于神经形态芯片中，与神经元计算核心400直接对接时，会存在读写速度不匹配的现象，无法为神经元计算核心400及时传送数据，进而影响神经元计算核心的处理效率，导致神经形态芯片出现功耗增加等问题。为有效解决该问题，本公开实施例可以在非易失性存储模块100与神经元计算核心400之间连接预载电路300和易失性存储模块200。
易失性存储模块200是由易失性存储器阵列组成的，其接口的读写速率通常比较高， 能够与神经元计算核心400的数据读写速率相匹配，进而能够为神经元计算核心400及时传送数据，从而改善神经元计算核心400的处理效率以及神经形态芯片的功耗。示例性的，易失性存储模块200可以为静态随机存取存储器(SRAM)。
预载电路300在读取非易失性存储模块100中的存储数据后首先存储起来，等待易失性存储模块200来读取，易失性存储模块200在预载电路300中读取提前预载好的存储数据再传送给神经元计算核心400。
需要说明的是，本公开实施例对于预载电路的具体实现形式不作具体限制，只要能够实现读取非易失性存储模块100中的存储数据，并进行预载功能即可。
本公开实施例提供的存储器，通过预载电路读取非易失性存储模块中的存储数据进行预载，易失性存储模块读取预载电路中预载的存储数据传送给神经元计算核心的技术手段，解决了非易失性存储模块与神经元计算核心的读写速率不匹配的问题，减少对神经元计算核心的处理效率产生影响、导致芯片功耗增加等问题。
在本公开的一些实施例中，存储器10还包括接收模块(图中未示出)，所述接收模块用于接收数据读取指令，所述数据读取指令包括待预载的目标存储数据的信息。所述易失性存储模块200用于根据所述数据读取指令，读取在所述接收模块接收到所述数据读取指令之前所述预载电路300中已预载的存储数据，并将该已预载的存储数据传送给神经元计算核心400。所述预载电路300用于根据所述目标存储数据的信息，读取所述非易失性存储模块100中的目标存储数据进行预载。
举例来说，存储器10的接收模块接收来自神经元计算核心400的数据读取指令之后，易失性存储模块200根据该数据读取指令读取在所述接收模块接收到所述数据读取指令之前预载电路300中已预载的数据传送给神经元计算核心400，预载电路300根据该数据读取指令中的待预载的目标存储数据的信息，读取非易失性存储模块100中的目标存储数据进行预载。其中，易失性存储模块200在预载电路300中读取的已预载的数据是预载电路在前一时刻预载的数据。
神经元计算核心400发送的数据读取指令既指示易失性存储模块200在预载电路300中读取已预载的数据并传送给神经元计算核心400，又指示预载电路300读取非易失性存储模块100中的目标存储数据进行预载。可选地，神经元计算核心400发送的数据读取指令中可以包括用于指示易失性存储模块200在预载电路300中读取已预载的数据的第一寻址地址，以及用于指示预载电路300读取非易失性存储模块100中的目标存储数据进行预载的第二寻址地址。
需要指出的是，预载电路300首次读取非易失性存储模块100中的存储数据进行预载的操作可以由芯片上电触发执行的，本公开实施例对此不作具体限定，预载电路300只要在易失性存储模块200读取前预载好数据即可。
在本公开的一些实施例中，如图5所示，非易失性存储模块100中还包括：仲裁器105。仲裁器105连接于非易失性存储单元101和刷新电路102之间，以及连接于非易失性存储单元101和预载电路300之间。
仲裁器105用于在非易失性存储单元101中的存储数据被读取之后，判断被读取的所述存储数据是需要通过刷新电路102写回非易失性存储单元101，还是需要写入预载电路300进行预载。
在本公开的一些实施例中，非易失性存储模块100中的刷新电路102和预载电路300可以共用同一个读(read)电路，并通过该读电路读取非易失性存储单元101中的存储数据。当通过该读电路在非易失性存储单元101中读取数据之后，仲裁器105可以判定读出的数据是应当被写回非易失性存储单元101中实现对非易失性存储单元101的数据刷新，还是应当被写入预载电路300进行预载。本公开实施例对于读电路的具体实现形式不作具体限制，只要能够实现读取非易失性存储单元101中的存储数据即可。
示例性的，仲裁器105可以根据该读电路的寻址地址判断读出的数据是应当被写回非易失性存储单元101中实现对非易失性存储单元101的数据刷新，还是应当被写入预载电路300进行预载。例如，若该读电路的寻址地址与神经元计算核心400发送的数据读取指令中用于指示预载电路300读取非易失性存储模块100中的存储数据进行预载的第二寻址地址相同，则确定读出的数据应当被写入预载电路进行预载。
示例性的，仲裁器105还可以根据该读电路接收的控制指令判断读出的数据是应当被写回非易失性存储单元101中实现对非易失性存储单元101的数据刷新，还是应当被写入预载电路300进行预载。例如，若该读电路接收的控制指令是由刷新电路102触发的，则确定读出的数据应当被写回非易失性存储单元101中。
在上述实施方式中，设置仲裁器对在非易失性存储单元中读取的存储数据的数据流向进行判断，协助刷新电路对非易失性存储单元中的存储数据进行刷新，以及协助预载电路对非易失性存储单元中的存储数据进行预载，以确保数据流的准确性。
图6是本公开实施例中的一种神经形态芯片的结构示意图，适用于神经网络计算的情况。如图6所示，本公开实施例提供的神经形态芯片1，包括：至少一个本公开任意实施例所述的存储器10(图中以一个存储器10示出)以及众核阵列，众核阵列包括至少一个神经元计算核心50。
关于该存储器10的具体描述可参见上述本公开任意实施例所述的存储器10的相关描述，此处不再赘述。
在本公开的一些实施例中，众核阵列可以是APU(Accelerated Processing Unit，加速处理器)众核阵列。
需要注意的是，图6所示的神经形态芯片仅是示例性地示出神经形态芯片1包括存储 器10和神经元计算核心50，并非是对神经形态芯片1的结构进行具体限定。
在本公开的一些实施例中，一个神经形态芯片1中可以包括一个或多个存储器10。可选的，当一个神经形态芯片1中只包括一个本公开实施例的存储器10时，该存储器10中的存储数据可以被多个神经元计算核心50共同使用；可选的，当一个神经形态芯片1中包括多个存储器10时，每个存储器10中的存储数据可以被一个神经元计算核心50单独使用，例如，存储器10与神经元计算核心50一一对应设置，一个存储器10也可以被多个神经元计算核心50共同使用，也可以是多个存储器10中部分存储器的存储数据被一个神经元计算核心50使用。
在一种可选的实施方式中，如图7所示，当神经形态芯片1中包括的存储器10的数量为一个时，存储器10以总线连接形式与神经形态芯片1中的每个神经元计算核心50连接。
在上述实施方式中，存储器10的数量只有一个，故其存储数据是芯片全局性的，供神经形态芯片1中的所有神经元计算核心50(众核)共用。进而，针对各神经元计算核心50都需要使用的数据无需多次重复存储，以此减小了神经形态芯片中的数据存储面积，也减小了神经形态芯片的尺寸。另外，在存储器10的存储面积较小时，存储器接口也会占用相当大比例的面积，减少了存储器10的数量，也就减小了存储器接口的数量，相对提高了数据存储区域面积占存储器总面积的比例，进而提升了神经形态芯片中存储器的有效使用面积。
在本公开的一些实施例中，如图7所示，神经形态芯片1中还可以包括其他类型处理器，其他类型处理器例如是ARM(Advanced RISC Machine，进阶精简指令集机器)处理器或CPU(Central Processing Unit，中央处理器)，其他类型处理器可以通过总线与芯片1内的其他器件进行通信交互。
在本公开的一些实施例中，如图7所示，神经形态芯片1中可以包括接口，接口可以包括：UART(Universal Asynchronous Receiver/Transmitter，通用异步收发传输器)、I2C(Inter Integrated Circuit)、GPIO(General-Purpose Input/Output，通用输入/输出口)、DDR(Double Data Rate Synchronous Dynamic Random Access Memory，双倍速率同步动态随机存储器)等接口中的一种或多种，接口用于连接芯片外部器件，芯片外部器件可以通过芯片1的接口与芯片1内的其他器件进行通信交互。
在本公开的一些实施例中，如图7所示，神经形态芯片1中还可以包括易失性存储器60，易失性存储器60也可以以总线连接形式与神经形态芯片1中的每个神经元计算核心50连接。其中，易失性存储器60和存储器10用于存储神经元计算核心50在不同运算阶段的数据。
可以理解的是，在多个并行神经元计算核心50下，运算过程既会产生数据量大、数 据频繁变化但不需要长时间保存的中间数据，也会产生数据变化不频繁、需要长时间保存、掉电保存的关键数据。
每个神经元计算核心50既需要易失性存储器60作为内存缓冲计算中间变量，也需要存储器10作为硬盘存储神经元连接模式、连接权重等需要长久保存的数据，以保证芯片在掉电后能保存重要的网络模型数据，以及在上电后能够迅速加载数据工作。
在本公开的一些实施例中，存储器10可以用于存储神经元计算核心50的相对稳定数据，易失性存储器60用于存储神经元计算核心50的相对动态数据。其中，相对稳定数据可以定义为需要重复使用的数据，例如连接权重、网络连接方式、神经元激活函数和初始化信息中的一种或多种；相对动态数据可以定义为不需要重复使用的数据，例如外部数据源(上位机或者外部只读存储器)输入的数据或网络计算的中间值等。
在本公开的一些实施例中，存储器10可以用于存储相对稳定和相对动态的数据。例如，当存储器10为一个时，可以是该存储器的部分存储空间用于存储相对稳定的数据，其余存储空间用于存储相对动态的数据。当存储器10为多个时，可以是部分存储器10用于存储相对稳定的数据，其余存储器10用于存储相对动态的数据。
在本公开的一些实施例中，如图8所示，当神经形态芯片1中包括的存储器10的数量为多个时，存储器10与神经形态芯片1中的一个或多个神经元计算核心50呈分布式对应连接。可以理解的是，神经元计算核心50中包括用于数据处理的计算单元51。
在本公开的一些实施例中，存储器10分布式地引入到神经形态芯片1内部，可以作为神经元计算核心50的功能单元，以实现存储器10的分布式嵌入分布。嵌入的分布式存储器10与神经形态芯片架构的多个神经元计算核心50分布式对应连接，形成独立的对应关系。即，保证每个分布式的存储器10仅对应连接一个或者有限的多个神经元计算核心50。
对于计算量较大的神经元计算核心50，也可以将数据对应存储在一个或者多个分布式的存储器10中。相应的，使每个神经元计算核心50对应连接一个或者有限的多个分布式的存储器10。
在上述实施方式中，存储器10可以是小容量的，内置于神经元计算核心50中，作为独立的非易失性存储器，以使每个(或者有限多个)神经元计算核心内部既包含独立的易失性存储器，也包含独立的非易失性存储器，能够有效缓解数据通信带宽的限制问题，提高系统的稳定性、可靠性和处理效率。
需要说明的是，图8示例性示出了每个神经元计算核心50对应连接一个存储器10，存储器10嵌入对应的神经元计算核心50的情形，本公开实施例包括但不限于此种情形。
在本公开的一些实施例中，如图9所示，一个存储器10嵌入式地分布在一个或者指定的多个神经元计算核心50区域。其中，在如图9中，示例性地分别示出了一个存储器 10嵌入式地分布在一个、两个、三个以及四个指定的神经元计算核心50区域的情形。
在本公开的一些实施例提供的神经形态芯片架构中，存储器10在芯片架构中进行嵌入式分布的形式可以为，以芯片架构中的多个神经元计算核心为基础，按照每个存储器10分别对应一个，或者同时对应附近指定多个神经元计算核心进行嵌入分布。即在具有大规模并行计算或功能核的系统中，每个嵌入分布式的存储器10供单个或者若干个神经元计算核心50共用。
其中，每个存储器10和与之连接的神经元计算核心50之间具有独立的数据通道。
在本公开的一些实施例中，将存储器10分布式地引入到神经形态芯片1中，作为内部神经元计算核心50的功能单元，使每个神经元计算核心50与对应的存储器10具有独立的数据通道，以此解决了在线学习时频繁更新权重带来的数据通信瓶颈问题。
在本公开的一些实施例中，如图9所示，所述芯片构架还包括分别与每个所述神经元计算核心50对应的易失性存储器60，其中，易失性存储器60和存储器10用于存储神经元计算核心50在不同运算阶段的数据。
每个神经元计算核心50(或若干个神经元计算核心50)使用单个存储器10存储不同的数据，用于该单个神经元计算核心50(或若干个神经元计算核心50)的运行。同时，对于每个神经元计算核心50，内部还需包含有易失性存储器60，易失性存储器60包括但不限于静态随机存取存储器、寄存器等，与存储器10配合。
在本公开的一些实施例中，易失性存储器60用于存储神经元计算核心50的计算缓存和当前神经元状态中的一种或多种。为了进行合理地数据分配，对于内部的易失性存储器60，神经元计算核心50会存储其计算缓存、当前神经元状态(膜电位)等运行时产生的中间变量，其特点是数据量大、数据频繁变化但不需要长时间保存。
上述神经形态芯片中，包括一个或多个本公开任意实施例所提供的存储器，具备与该存储器相应的有效效果。未在本公开实施例中关于神经形态芯片的详尽描述的技术细节，可参见前述相关实施例的相关描述，此处不再赘述。
图10是本公开实施例中的一种数据处理方法的流程图，该方法适用于神经元计算核心在存储器中读取数据以进行相应数据处理的情况。
如图10所示，本公开实施例提供的数据处理方法，应用于本公开任意实施例所述的包括非易失性存储模块、易失性存储模块，以及连接于所述非易失性存储模块与所述易失性存储模块之间的预载电路的存储器中，该方法包括：以下步骤S310和步骤S320。
步骤S310、通过预载电路读取非易失性存储模块中的存储数据进行预载，以供易失性存储模块读取。
步骤S320、通过易失性存储模块读取预载电路中预载的存储数据并传送给神经元计算核心。
在本公开的一些实施例中，预载电路在读取非易失性存储模块中的存储数据后首先存储起来，等待易失性存储模块进行读取，易失性存储模块在预载电路中读取提前预载好的数据再传送给神经元计算核心。
上述技术方案解决了非易失性存储模块与神经元计算核心的读写速率不匹配的问题，有效改善了对神经元计算核心的处理效率产生影响、导致芯片功耗增加等问题。
作为一种可选的实施方式，上述数据处理方法还包括：接收数据读取指令，数据读取指令包括待预载的目标存储数据的信息。
相应的，通过所述易失性存储模块读取所述预载电路中预载的存储数据并传送给神经元计算核心的步骤，即步骤S320，可以进一步包括：通过所述易失性存储模块根据所述数据读取指令，读取所述预载电路中预载的存储数据并传送给神经元计算核心。
相应的，通过预载电路读取所述非易失性存储模块中的存储数据进行预载，以供易失性存储模块读取的步骤，即步骤S310，可以进一步包括：通过预载电路根据所述数据读取指令，读取所述非易失性存储模块中的存储数据进行预载。
在该实施方式中，存储器接收来自神经元计算核心的数据读取指令之后，易失性存储模块根据该数据读取指令读取预载电路中预载的数据传送给神经元计算核心，同时，预载电路根据该数据读取指令读取非易失性存储模块中的存储数据进行预载。其中，易失性存储模块在预载电路中读取的数据是预载电路在前一时刻预载的数据。
在该实施方式中，神经元计算核心发送的数据读取指令既指示易失性存储模块在预载电路中读取数据并传送给神经元计算核心，又指示预载电路读取非易失性存储模块中的存储数据进行预载。可选地，神经元计算核心发送的数据读取指令中包括用于指示易失性存储模块在预载电路中读取数据的第一寻址地址，以及用于指示预载电路读取非易失性存储模块中的存储数据进行预载的第二寻址地址。
需要指出的是，预载电路首次读取非易失性存储模块中的存储数据进行预载的操作可以由芯片上电触发执行的，本公开实施例对此不作具体限定，预载电路只要在易失性存储模块读取前预载好即可。
在本公开的一些实施例中，上述数据处理方法还可以包括以下步骤：通过刷新电路读取非易失性存储单元中的存储数据，并将所述存储数据写回所述非易失性存储单元。
其中，刷新电路定时读取非易失性存储单元中的存储数据，并将读取的存储数据写回非易失性存储单元中，以延长非易失性存储单元存储所述存储数据的存储时长。
可选的，刷新电路的刷新频率为分钟级别或者小时级别，也即每几分钟或每几小时将非易失性存储单元中存储数据的刷新一次。相比较于刷新频率为毫秒级别的DRAM，本公开实施例提供的存储器由于数据刷新而消耗的功率会更低。
进一步的，上述数据处理方法还包括以下步骤：通过仲裁器在所述非易失性存储单元 中的存储数据被读取之后，判断所述存储数据是需要通过所述刷新电路写回所述非易失性存储单元，还是需要写入所述预载电路进行预载。
在本公开的一些实施例中，非易失性存储模块中的刷新电路和预载电路可以共用同一个读电路，并通过这个读电路读取非易失性存储单元中的存储数据。当通过该读电路在非易失性存储单元中读取数据之后，仲裁器可以判定读出的数据是应当被写回非易失性存储单元中实现对非易失性存储单元的数据刷新，还是应当被写入预载电路进行预载。
在上述实施方式中，设置仲裁器对在非易失性存储单元中读取的存储数据的数据流向进行判断，协助刷新电路对非易失性存储单元中的存储数据进行刷新，以及协助预载电路对非易失性存储单元中的存储数据进行预载，以确保数据流的准确性。
在本公开实施例关于数据处理方法的描述中，未尽详细解释之处可以参见前述相关实施例的相关描述，在此不再赘述。
注意，上述仅为本公开的较佳实施例及所运用技术原理。本领域技术人员会理解，本公开不限于这里所述的特定实施例，对本领域技术人员来说能够进行各种明显的变化、重新调整和替代而不会脱离本公开的保护范围。因此，虽然通过以上实施例对本公开进行了较为详细的说明，但是本公开不仅仅限于以上实施例，在不脱离本公开构思的情况下，还可以包括更多其他等效实施例，而本公开的范围由所附的权利要求范围决定。

Claims (20)

  1. 一种存储器，其特征在于，所述存储器包括：非易失性存储模块，所述非易失性存储模块包括相连的非易失性存储单元和刷新电路；
    其中，所述刷新电路用于读取所述非易失性存储单元中的存储数据，并将所述存储数据写回所述非易失性存储单元。
  2. 根据权利要求1所述的存储器，其特征在于，所述非易失性存储模块还包括：控制单元；
    所述控制单元与所述刷新电路相连，用于控制所述刷新电路的工作状态；
    其中，所述工作状态至少包括刷新频率。
  3. 根据权利要求2所述的存储器，其特征在于，所述非易失性存储模块还包括：计时器，所述计时器与所述控制单元、所述刷新电路相连；
    所述控制单元，还用于控制所述计时器的计时周期，以触发所述刷新电路以与所述计时周期匹配的刷新频率读取所述非易失性存储单元中的存储数据，并将所述存储数据写回所述非易失性存储单元。
  4. 根据权利要求2所述的存储器，其特征在于，所述控制单元还用于控制所述刷新电路读取所述非易失性存储单元中目标存储区域中的存储数据，并将所述目标存储区域中的存储数据写回所述非易失性存储单元中所述目标存储区域。
  5. 根据权利要求1所述的存储器，其特征在于，所述非易失性存储单元包括非易失性存储器阵列和预设类型控制器；其中，所述预设类型控制器用于提供用于对接外部器件的预设协议类型的接口。
  6. 根据权利要求5所述的存储器，其特征在于，所述预设协议类型至少包括下述之一：静态随机存取存储器接口协议和增强动态随机存取存储器接口协议。
  7. 根据权利要求1所述的存储器，其特征在于，所述存储器还包括：易失性存储模块以及连接于所述非易失性存储单元与所述易失性存储模块之间的预载电路；
    其中，所述预载电路用于读取所述非易失性存储单元中的存储数据进行预载，所述易失性存储模块用于读取所述预载电路中预载的存储数据并传送给神经元计算核心。
  8. 根据权利要求7所述的存储器，其特征在于，所述存储器还包括接收模块；
    所述接收模块，用于接收数据读取指令，所述数据读取指令包括待预载的目标存储数据的信息；
    所述易失性存储模块，用于根据所述数据读取指令，读取在所述接收模块接收到所述数据读取指令之前所述预载电路中已预载的存储数据，并将所述已预载的存储数据传送给神经元计算核心；
    所述预载电路，用于根据所述目标存储数据的信息，读取所述非易失性存储单元中 的目标存储数据进行预载。
  9. 根据权利要求7所述的存储器，其特征在于，所述非易失性存储模块还包括：仲裁器；所述仲裁器连接于所述非易失性存储单元和所述刷新电路之间，以及连接于所述非易失性存储单元和所述预载电路之间；
    所述仲裁器用于在所述非易失性存储单元中的存储数据被读取之后，判断被读取的所述存储数据是需要通过所述刷新电路写回所述非易失性存储单元，还是需要写入所述预载电路进行预载。
  10. 根据权利要求7所述的存储器，其特征在于，所述易失性存储模块包括：静态随机存取存储器。
  11. 根据权利要求1所述的存储器，其特征在于，所述非易失性存储单元包括：磁存储器。
  12. 根据权利要求1-11中任意一项所述的存储器，其特征在于，所述刷新电路的刷新频率为分钟级别或者小时级别。
  13. 一种神经形态芯片，其特征在于，包括：至少一个如权利要求1-12任一项所述的存储器和至少一个神经元计算核心。
  14. 根据权利要求13所述的芯片，其特征在于，当所述存储器的数量为一个时，所述存储器以总线连接形式与所述芯片中的每个神经元计算核心连接。
  15. 根据权利要求13所述的芯片，其特征在于，当所述存储器的数量为多个时，所述存储器与所述芯片中的一个或多个神经元计算核心呈分布式对应连接。
  16. 根据权利要求15所述的芯片，其特征在于，一个所述存储器嵌入式地分布在一个或者指定的多个所述神经元计算核心区域。
  17. 一种数据处理方法，其特征在于，应用于如权利要求7-10中任一项所述的存储器，所述数据处理方法包括：
    通过预载电路读取所述非易失性存储模块中的存储数据进行预载，以供易失性存储模块读取；
    通过所述易失性存储模块读取所述预载电路中预载的存储数据并传送给神经元计算核心。
  18. 根据权利要求17所述的方法，其特征在于，所述数据处理方法还包括：接收数据读取指令，所述数据读取指令包括待预载的目标存储数据的信息；
    所述通过所述易失性存储模块读取所述预载电路中预载的存储数据并传送给神经元计算核心，包括：通过所述易失性存储模块根据所述数据读取指令，读取所述预载电路中已预载的存储数据并传送给神经元计算核心；
    所述通过预载电路读取所述非易失性存储模块中的存储数据进行预载，以供易失性存储模块读取，包括：通过预载电路根据所述数据读取指令，读取所述非易失性存储模 块中的目标存储数据进行预载。
  19. 根据权利要求17所述的方法，其特征在于，所述数据处理方法还包括：
    通过刷新电路读取非易失性存储单元中的存储数据，并将所述存储数据写回所述非易失性存储单元。
  20. 根据权利要求19所述的方法，其特征在于，所述数据处理方法还包括：
    通过仲裁器在所述非易失性存储单元中的存储数据被读取之后，判断所述存储数据是需要通过所述刷新电路写回所述非易失性存储单元，还是需要写入所述预载电路进行预载。
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