WO2022095512A1 - 失效位元修补方法、装置、设备及存储介质 - Google Patents

失效位元修补方法、装置、设备及存储介质 Download PDF

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Publication number
WO2022095512A1
WO2022095512A1 PCT/CN2021/108195 CN2021108195W WO2022095512A1 WO 2022095512 A1 WO2022095512 A1 WO 2022095512A1 CN 2021108195 W CN2021108195 W CN 2021108195W WO 2022095512 A1 WO2022095512 A1 WO 2022095512A1
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Prior art keywords
repair
standardized
circuit
range
failed bit
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PCT/CN2021/108195
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English (en)
French (fr)
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陈予郎
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长鑫存储技术有限公司
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Priority to US17/449,590 priority Critical patent/US20220139490A1/en
Publication of WO2022095512A1 publication Critical patent/WO2022095512A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/394—Routing
    • G06F30/3953—Routing detailed
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2119/00—Details relating to the type or aim of the analysis or the optimisation
    • G06F2119/02—Reliability analysis or reliability optimisation; Failure analysis, e.g. worst case scenario performance, failure mode and effects analysis [FMEA]

Definitions

  • the present disclosure relates to the field of semiconductor technology, and in particular, to a method, apparatus, device, and readable storage medium for repairing a failed bit.
  • the Repair Algorithm is a method that can effectively allocate spare circuits to repair the lines where the above-mentioned failed bits are located.
  • the RA can obtain the locations allocated for the spare circuits, where there is a high probability of being replaced by locations that may cover all failed bits on the chip.
  • the higher the probability that an RA assignment position covers all the failed bits on a specific chip the more difficult it is for the RA to be applied to chips of different product specifications, and the redevelopment of RAs for chips of different product specifications takes a long time and is costly. Therefore, improving the versatility of RA has become an urgent problem to be solved.
  • the purpose of the present disclosure is to provide a method, apparatus, device and readable storage medium for repairing a failed bit, so as to improve the versatility of the repair algorithm.
  • a first aspect of the present application provides a method for repairing a failed bit, including: obtaining a repair specification of a spare circuit of a chip where a failed bit is located; standardizing the repair specification of the spare circuit to obtain a standardized repair specification; obtain the position of the failed bit on the chip; process the position of the failed bit on the chip according to the standardized repair specification to obtain the standardized position of the failed bit; The circuit allocation algorithm allocates the spare circuit according to the standardized position of the failed bit and the standardized repair specification to obtain the standardized repair position of the spare circuit; restores the standardized repair position of the spare circuit according to the standardized repair specification Repairing the failed bit for the repair location on the chip for the spare circuit.
  • a second aspect of the present application provides an apparatus for repairing a failed bit, including: a parameter acquisition module configured to obtain a repair specification of a spare circuit of a chip where the failed bit is located; The position on the chip; the specification conversion module is used to standardize the repair specification of the spare circuit to obtain a standardized repair specification; according to the standardized repair specification, the position of the failed bit on the chip is processed, obtaining the normalized position of the failed bit; a circuit allocation module, configured to use a spare circuit allocation algorithm to allocate the spare circuit according to the standardized position of the failed bit and the standardized repair specification, and obtain the standardized repair of the spare circuit a position; a position restoration module, configured to restore the standardized repair position of the spare circuit to the repair position of the spare circuit on the chip according to the standardized repair specification, so as to repair the failed bit.
  • a third aspect of the present application provides an apparatus comprising: a memory, a processor, and executable instructions stored in the memory and executable in the processor, the processor executing the Any of the methods described above are implemented when the instructions are executable.
  • a fourth aspect of the present application provides a computer-readable storage medium on which computer-executable instructions are stored, and when the executable instructions are executed by a processor, implement any of the above methods.
  • the embodiment of the present disclosure may have the following advantages: by obtaining the repair specification of the spare circuit of the chip where the failed bit is located and the position of the failed bit on the chip, and standardizing the repair specification of the spare circuit to obtain the standardized repair specification, according to the standardized repair specification
  • the position of the failed bit on the chip is processed to obtain the standardized position of the failed bit, and then the spare circuit allocation algorithm is used to allocate the spare circuit according to the standardized position of the failed bit and the standardized repair specification, and the standardized repair position of the spare circuit is obtained.
  • the standardized patching specification restores the standardized patching position of the spare circuit to the patching position of the spare circuit on the chip to patch the failed bits, thereby improving the generality of the patching algorithm.
  • FIG. 1 shows a schematic diagram of a system structure in an embodiment of the present disclosure.
  • FIG. 2 shows a flowchart of a method for repairing a failed bit in an embodiment of the present disclosure.
  • FIG. 3 is a schematic diagram of data flow according to an alternate circuit analysis system shown in FIG. 2 .
  • FIG. 4A is a block diagram of a product unit shown in FIG. 3 .
  • FIG. 4B is a schematic diagram illustrating data segmentation using an alternate circuit analysis system according to an exemplary embodiment.
  • FIG. 5A is a flowchart illustrating a method for converting a specification of a standby circuit according to an exemplary embodiment.
  • FIG. 5B is a schematic diagram showing area division according to an exemplary embodiment.
  • FIG. 6A is a flow chart of another method for converting a specification of a standby circuit according to an exemplary embodiment.
  • FIG. 6B is a schematic diagram illustrating the division of normalized sub-domains according to an exemplary embodiment.
  • FIG. 6C is a schematic diagram of in-situ patching according to an exemplary embodiment.
  • FIG. 7 is a schematic diagram of unified specification data according to an exemplary embodiment.
  • FIG. 8 is a flowchart illustrating another method for repairing a failed bit according to an exemplary embodiment.
  • FIG. 9 is a schematic diagram of data flow according to yet another standby circuit analysis system shown in FIG. 8 .
  • FIG. 10 is a schematic diagram of data flow according to yet another standby circuit analysis system shown in FIGS. 8 and 9 .
  • FIG. 11 shows a schematic structural diagram of an electronic device in an embodiment of the present disclosure.
  • Example embodiments will now be described more fully with reference to the accompanying drawings.
  • Example embodiments can be embodied in various forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art.
  • the drawings are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale.
  • the same reference numerals in the drawings denote the same or similar parts, and thus their repeated descriptions will be omitted.
  • first, second, etc. are used for descriptive purposes only, and should not be construed as indicating or implying relative importance or implying the number of indicated technical features. Thus, a feature defined as “first” or “second” may expressly or implicitly include one or more of that feature.
  • plural means at least two, such as two, three, etc., unless expressly and specifically defined otherwise.
  • the symbol “/” generally indicates that the related objects are an “or” relationship.
  • connection should be interpreted in a broad sense, for example, it may be an electrical connection or may communicate with each other; it may be directly connected or indirectly connected through an intermediate medium.
  • connection should be interpreted in a broad sense, for example, it may be an electrical connection or may communicate with each other; it may be directly connected or indirectly connected through an intermediate medium.
  • a chip containing failed bits is provided with spare circuits, the chip includes spare circuits extending in a predetermined direction, and these spare circuits are used to repair the chip by replacing the failed bits within a predetermined repair range.
  • the number of spare circuits is limited, so the RA needs to be designed to assign the spare circuits.
  • the RA can obtain the locations assigned for various spare circuits, where there is a high probability of being replaced by locations that may cover all failed bits on the chip. But the higher the probability that an RA assignment location covers all the failed bits, the more difficult it is for this RA to become a general algorithm.
  • a general algorithm means that it can be easily applied to most (or even all) product specifications.
  • the development of RA is time-consuming and costly. Therefore, improving the versatility of RA has become an urgent problem to be solved.
  • the present disclosure provides a method for repairing a failed bit.
  • the repairing specification of the spare circuit is standardized to obtain the standardized repairing specification.
  • FIG. 1 illustrates an exemplary system architecture 10 to which the failed bit repair method or alternate circuit analysis system of the present disclosure may be applied.
  • the system architecture 10 may include terminal devices 102 , a network 104 , a server 106 and a database 108 .
  • the terminal device 102 may be various electronic devices having a display screen and supporting input and output, including but not limited to smart phones, tablet computers, laptop computers, desktop computers, chip patching devices, and the like.
  • the network 104 is the medium used to provide the communication link between the terminal device 102 and the server 106 .
  • the network 104 may include various connection types, such as wired, wireless communication links, or fiber optic cables, among others.
  • the server 106 may be a server or server cluster or the like that provides various services.
  • the database 108 can be a large database software placed on a server or a small database software installed on a computer for storing data.
  • the terminal device 102 may be used to interact with the server 106 and the database 108 through the network 104 to receive or transmit data and the like.
  • the terminal device 102 may be a chip repair device, uploads chip failure bit position data and spare circuit repair specifications to the server 106 through the network 104 , and obtains the allocated spare circuit repair position from the server 106 through the network 104 .
  • the server 106 may also receive data from the database 108 or send data to the database 108 through the network 104, or the like.
  • the server 106 can be a background processing server, which is used to obtain the chip failure bit position data and the spare circuit repair specification from the database 108 through the network 104, and allocate the spare circuit, and then feed back the assigned spare circuit repair position to the chip through the network 104. Repair equipment 102 .
  • terminal devices, networks, servers and databases in FIG. 1 are merely illustrative. There can be any number of terminal devices, networks, servers and databases according to implementation needs.
  • Fig. 2 is a flow chart of a method for repairing a failed bit according to an exemplary embodiment.
  • the method shown in FIG. 2 can be applied to, for example, the server side of the above-mentioned system, and can also be applied to the terminal device of the above-mentioned system.
  • the method 20 provided by the embodiment of the present disclosure may include the following steps.
  • step S202 the repair specification of the spare circuit of the chip where the failed bit is located is obtained.
  • the repair specification of the spare circuit may include the line width of the spare circuit, the preset repair range of the spare circuit, and may also include the number of spare circuits, and so on. Different chip products may have different spare circuit repair specifications.
  • step S204 the repair specification of the backup circuit is standardized to obtain a standardized repair specification.
  • Standardized repair specifications can include standardized line width and standardized repair range.
  • the line width of the spare circuit can be standardized according to the number of bits, and the repair range can be re-divided into the repair range according to parameters such as the length and quantity of the spare circuit to obtain the standardized repair range.
  • Embodiments may refer to FIGS. 5A to 5B .
  • the spare circuit repair specifications of various products are converted into unified standard specifications, which can be used for subsequent spare circuit assignment algorithms.
  • step S206 the position of the failed bit on the chip is obtained.
  • Position data for all failed bits in a chip is available.
  • Different chip products arrange positions differently. It is usually counted in multiples of 2 on the chip.
  • a certain chip product consists of 22 array groups (Bank Group, BG), each BG is divided into 22 arrays (Bank), the positioning of the bit position in the Bank can be X15-0, D0-2 , Y0-3... etc. 2 metadata.
  • the position of a bit in a chip can be represented by 32 binary digits.
  • step S208 the position of the failed bit on the chip is processed according to the standardized repair specification to obtain the standardized position of the failed bit.
  • the position of the failed bit on the chip is scaled according to the line width of the standby circuit and the normalized line width to obtain the normalized position of the failed bit.
  • the available scaling parameter is the normalized line width/alternate circuit original line width.
  • a backup circuit allocation algorithm is used to allocate the backup circuit according to the standardized position of the failed bit and the standardized repair specification, so as to obtain the standardized repair position of the backup circuit.
  • the standardized line width of the spare circuit, the normalized repair range and the number of spare circuits any algorithm that can effectively assign the spare circuit to completely cover all the failed bit positions on the chip can be used to allocate the spare circuit, and obtain the spare circuit for standardized The normalized patch location for the patch range.
  • step S212 the standardized repairing position of the spare circuit is restored to the repairing position of the spare circuit on the chip according to the standardized repairing specification to repair the failed bit.
  • the standardized repair position of the spare circuit can be restored to the repair position of the spare circuit on the chip to repair the failed bit.
  • the repairing position of the spare circuit on the chip can be reversely restored according to the scaling parameter, and the data can be provided to the chip repairing device for repairing.
  • the repairing specification of the spare circuit is standardized to obtain the standardized repairing specification
  • the position of the failed bit on the chip is processed according to the standardized repair specification to obtain the standardized position of the failed bit, and then the spare circuit allocation algorithm is used to allocate the spare circuit according to the standardized position of the failed bit and the standardized repair specification, and the standardized repair of the spare circuit is obtained.
  • the standardized repairing position of the spare circuit is restored to the repairing position of the spare circuit on the chip to repair the failed bit, thereby improving the versatility of the repairing algorithm.
  • FIG. 3 is a schematic diagram of data flow according to an alternate circuit analysis system shown in FIG. 2 .
  • the source data input to the backup circuit analysis system includes position data 302 of the failed bit on the original chip and product specification parameters 304 , which can be repair specifications of the backup circuit.
  • the solid line connecting arrows in FIG. 3 indicate the processing flow, and the dotted line connecting arrows indicate input/output.
  • the alternate circuit analysis system may include a production unit 306 and a common unit 308, which are described in detail below.
  • the product unit 306 can standardize specifications for various product specifications, and configure a unified specification data conversion method and specification definition, so that any product specification (such as new product specification) data can be standardized through product specification parameters. Convert to uniform specification data.
  • the product unit 306 may be used to implement steps S202 to S208 in FIG. 2 .
  • the common unit 308 can be embedded with any spare circuit assignment algorithm, so that various spare circuit assignment algorithms can follow the process of the unified specification data, and control the unified specification data to perform arithmetic operations to obtain the final spare circuit assignment repair position data 310 .
  • Patch location data 310 may assign location data for patch failed bits to all spare circuits in a chip.
  • the product unit 306 may be used to implement steps S210 to S212 in FIG. 2 .
  • FIG. 4A is a data interaction diagram for data segmentation using an alternate circuit analysis system shown in FIG. 3 .
  • the solid line connecting arrows in FIG. 4A indicate the processing flow, and the dotted line connecting arrows indicate input/output.
  • the product unit 306 may include a data segmentation module 3062 and a specification conversion module 3064, which are described in detail below.
  • the data splitting module 3062 can be used to split the data of one chip into several independently processable ranges of data that will not affect each other when the standby circuit is dispatched.
  • the data splitting module 3062 can split the data in the chip according to the product specification parameters 304 .
  • FIG. 4B is a schematic diagram of data division according to an exemplary embodiment. As shown in Figure 4B, the data in one chip is divided into several Banks 30722 data, each bank data, based on the maximum range that can be allocated by the Global Redundancy (GR) in the product specification (this range is called the global range), the Each bank data is divided into several global areas 30724 and stored as global data 3072 .
  • the global data 3072 can be sent to the specification conversion module 3064.
  • the specification conversion module 3064 can be used to convert the global data 3072 into unified specification data 3074 and transmit it to the common unit 308 without affecting the known invalid bit position information. In addition, scaling parameters for all bit positions before and after normalization are provided in the data, so that the original position can be calculated for each normalized position.
  • the specific processing flow of the specification conversion module 3064 can be referred to FIG. 5A to FIG. 6C .
  • the sharing unit 308 provides an algorithm for the allocation of spare circuits, and specifies which spare circuit is used for repairing each failed bit. It is not necessary to provide different algorithms for a certain product. In an orderly process flow, the final spare circuit assignment patch position data 310 is obtained.
  • FIG. 5A is a flowchart illustrating a method for converting a specification of a standby circuit according to an exemplary embodiment.
  • the method shown in FIG. 5A may be the specific processing procedure of steps S204 to S208 in FIG. 2 .
  • the method shown in FIG. 5A can be applied to the server side of the above-mentioned system, and can also be applied to the terminal device of the above-mentioned system.
  • step S502 the line width of the standby circuit is normalized according to the bit element to obtain the normalized line width.
  • the line widths of the spare circuits can be standardized according to bits, for example, 1, or 2, or 3 bits.
  • step S504 the chip is divided into a plurality of unified regions according to a preset repair range, and the range of each unified region is obtained.
  • the length of the range of each unified area can be obtained as the length of the corresponding preset repair range in the extension direction of the backup circuit, or the width of the range of each unified area can be obtained as the length of the corresponding preset repair range in the extension direction of the backup circuit.
  • the backup circuit may include a global backup circuit (GR) and a sub-region backup circuit (Local Redundancy, LR).
  • the extension direction of the global backup circuit is orthogonal to the extension direction of the sub-region backup circuit, and the repair range is preset. It can include a global repair range and a sub-field repair range.
  • the global repair range includes multiple sub-field repair ranges, wherein the global backup circuit is used to repair the defective bits in the global repair range on the chip, and the sub-field backup circuit is used to repair the sub-field on the chip. Stale bits in the domain patch range.
  • the length of the range of each unified area can be obtained as the length of the corresponding global repair range in the extension direction of the global backup circuit, and the width of the range of each unified area and the length of the corresponding sub-field repair range in the extension direction of the sub-field backup circuit are obtained. same.
  • FIG. 5B is a schematic diagram showing area division according to an exemplary embodiment. As shown in FIG. 5B , after the chip is divided into a plurality of regions according to FIG. 4B , each region can be divided into several regions 5002 , and the GR and LR assignment processing of any region will not affect other regions, such as one region
  • the GR or LR assigned by A is unlikely to overlap or overlap with the assignment positions of GR or LR in other regions than A.
  • the range of a region 5002 can be defined as follows: the GR extension direction range is a length range 50024 of a GR dispatchable repair, and the LR extension direction range is a LR dispatchable repair length range 50022, wherein the GR dispatch fix example 50026 is the GR in FIG. 5B .
  • Directional dotted line, LR dispatch patch example 50028 is the LR direction solid line in Figure 5B.
  • step S506 standardize the preset repair range according to the range of each unified area to obtain a standardized repair range of the backup circuit. Divide the chip or a whole area into the scope of each unified area, and correspond the repair scope of the spare circuit to the scope of each unified area. For example, the normalized patch range corresponding to each GR or LR can be obtained.
  • step S508 the position of the failed bit on the chip is processed according to the normalized line width, and the normalized position of the failed bit is obtained as the position of the failed bit in the corresponding unified area.
  • the position of each bit on the chip can be normalized to its position on a uniform area, and a bit value matrix can be used to indicate whether the bit at the position on the chip or the area is invalid.
  • the normalized line width can be performed by the OR operation.
  • RWL line width is 2 (bits)
  • RBL line width is also 2
  • the original subfield is 2 (bits)
  • the chip partition may be refined, for example, a chip (chip) may be divided into multiple banks (banks), the length of GR and LR will not exceed the range of 1 bank, and the length of GR>length of LR.
  • the size of the bank and the whole domain will be the same, but the segment, subdomain, and DQ may have different sizes.
  • the specification conversion method of the spare circuit provided by the embodiment of the present disclosure, by converting the spare circuit repair specifications of various products into a unified standard specification, standardized repair data of products with different spare circuit repair specifications are obtained, wherein different spare circuit repair specifications are obtained. Products will have different processing procedures to make the final output standardized repair data meet the requirements of the input specifications of the common unit, so that any circuit allocation algorithm can allocate the spare circuits of the standardized repair specifications in the common unit, and improve the repair algorithm. generality of the law.
  • FIG. 6A is a flow chart of another method for converting a specification of a standby circuit according to an exemplary embodiment.
  • the method shown in FIG. 6A may be the specific processing procedure of step S506 in FIG. 6A .
  • the method shown in FIG. 6A can be applied to, for example, the server side of the above-mentioned system, and can also be applied to the terminal device of the above-mentioned system.
  • the normalized patching range includes a standardized global patching scope and a standardized sub-domain patching scope.
  • step S602 the normalized global repair range is obtained as the range of the corresponding unified region.
  • step S604 when the sub-field backup circuit is used for co-location repair, standardize the sub-field repair range corresponding to the sub-field backup circuit to obtain a standardized sub-field repair range, and the normalized sub-field repair range is in the extension direction of the global backup circuit.
  • the length is one data grid (DQ).
  • the LR linewidth can be normalized as
  • the vertical axis uses DQ as the basic unit for OR operation or addition operation. For example, if the vertical DQ in each original subfield is regarded as a matrix, then
  • d ijk represents the value of the k-th bit in the i-th row and j-th column DQ in the original subfield; Represents the value of the kth bit in the jth column DQ in the normalized subfield, and the bit has the value 0 or 1 as described above.
  • FIG. 6B is a schematic diagram illustrating the division of normalized sub-domains according to an exemplary embodiment.
  • the original subfield 6002 is normalized to obtain a normalized subfield 6004, that is, the range of the original subfield 6002 is normalized in the GR direction to be acceptable
  • the minimum range of usually 1DQ, allows uniform specification data to be used without in-place patching.
  • FIG. 6C is a schematic diagram of in-situ patching according to an exemplary embodiment.
  • the left picture shows a bit of a failed bit in the original subfield
  • the right picture shows the LR repair circuit allocated in the LR direction.
  • An LR is just a spare circuit, not multiple spare circuits, it looks like multiple (or rows) are the reason behind the design of the lines, they are all considered the same.
  • When repairing only a certain LR position is specified to replace the line position that originally had a failed bit, so as to achieve the purpose of repairing the failed bit.
  • FIG. 7 is a schematic diagram of unified specification data according to an exemplary embodiment.
  • one chip may include multiple populations 6008 , one population 6008 may be divided into multiple regions 6006 , and one region 6006 may be divided into multiple normalized sub-regions 6004 in the GR direction.
  • FIG. 8 is a flowchart illustrating another method for repairing a failed bit according to an exemplary embodiment.
  • the method shown in FIG. 8 may be the processing procedure of repairing the defective bits performed after step S508 in FIG. 5A .
  • the method shown in FIG. 8 can be applied to, for example, the server side of the above-mentioned system, and can also be applied to the terminal device of the above-mentioned system.
  • step S802 in each unified area, a backup circuit allocation algorithm is used to allocate a backup circuit according to the position of the failed bit in the corresponding unified area and the standardized repair range, and the standardized repair position is obtained as the repair position of the backup circuit in the corresponding unified area.
  • Any alternate circuit allocation algorithm that effectively assigns the spare circuit to completely cover the position of the failed bit can be used, and the position and result of the assignment of the spare circuit can be output. Overwrite repair, if successful, it is a valid universe, otherwise it is an invalid universe.
  • step S804 the repairing position of the spare circuit in the corresponding unified area is restored to the repairing position of the spare circuit on the chip according to the standardized line width to repair the failed bit.
  • the normalized line width is obtained when the line width is normalized in bits, for example, normalized to 1, or 2, or 3 bits, and the corresponding GR direction is reduced to 1/original GR line width, or 2/original GR Line width, or 2/original GR line width, and the LR direction is reduced to 1/original LR line width, or 2/original LR line width, or 2/original LR line width.
  • the position is zoomed back in for restoration.
  • FIG. 9 is a schematic diagram of data flow according to yet another standby circuit analysis system shown in FIG. 8 .
  • the solid line connecting arrows in FIG. 9 indicate the processing flow, and the broken line connecting arrows indicate input/output.
  • the sharing unit 308 can include an input control module 3082, which can be used to input a large number of unified specification data 3074 that have been divided into data, so that the GR and LR assignment processing in any one area will not affect other areas, and each area can be A region sequentially enters the assignment algorithm module 3084 independently for standby circuit assignment processing. When each region enters the allocation algorithm module 3084, additional auxiliary parameters can be given, such as the available number of GR in the current global region and LR in the region, and so on.
  • the assignment algorithm module 3084 provides any algorithm that can effectively assign the spare circuit to completely cover the position of the failed bit, and outputs the position and result of the assignment of the spare circuit, that is, the assignment data 3088.
  • the result is whether the failed bit in the whole field can be successfully completed. It is completely covered and repaired by limited spare circuits, if successful, it is a valid population, otherwise it is a failed population.
  • the Bank to which the invalidated universe belongs will also be designated as the invalidated bank.
  • the position restoration module 3086 restores the spare circuit assignment repair position (the normalized position) in the assignment data 3088 to the original position by using the scaling parameter provided in the unified specification data 3074 , and outputs all the assignment repair original positions to the patch position data 310 .
  • FIG. 10 is a schematic diagram of data flow according to yet another standby circuit analysis system shown in FIGS. 8 and 9 .
  • the solid line connecting arrows in FIG. 10 indicate the processing flow, and the dotted line connecting arrows indicate input/output.
  • modules with the same meanings as those in FIG. 3 , FIG. 4A and FIG. 9 have the same reference numerals, and will not be repeated here.
  • the input control module 3082 receives the unified specification data 3074, it first reads the entire area in the chip in sequence (S3002), and then sequentially reads the area in the entire area (S30010), and then enters the Algorithm module 3084 is dispatched.
  • the allocation algorithm module 3084 allocates the backup circuit, it determines whether the allocation result is that the failed bits in the region can be successfully completely covered and repaired by the limited backup circuit (S3008).
  • Unprocessed area (S3004), if there is an unprocessed area, return to step S30010 to read, if there is no unprocessed area, determine whether there is an unprocessed whole area (S3006), if there is an unprocessed whole area, return to step S3002 to read, If there is no unprocessed universe, enter the position restoration module 3086 , restore the spare circuit dispatched patch positions in the dispatch data 3088 to the original positions, and output all dispatched patch original positions to the patch position data 310 .
  • FIG. 11 shows a schematic structural diagram of an electronic device in an embodiment of the present disclosure. It should be noted that the device shown in FIG. 11 is only an example of a computer system, and should not impose any limitations on the functions and scope of use of the embodiments of the present disclosure.
  • the apparatus 1100 includes a central processing unit (CPU) 1101, which can be processed according to a program stored in a read only memory (ROM) 1102 or a program loaded from a storage section 1108 into a random access memory (RAM) 1103 Various appropriate actions and processes are performed.
  • ROM read only memory
  • RAM random access memory
  • various programs and data necessary for the operation of the device 1100 are also stored.
  • the CPU 1101, the ROM 1102, and the RAM 1103 are connected to each other through a bus 1104.
  • An input/output (I/O) interface 1105 is also connected to the bus 1104 .
  • the following components are connected to the I/O interface 1105: an input section 1106 including a keyboard, a mouse, etc.; an output section 1107 including a cathode ray tube (CRT), a liquid crystal display (LCD), etc., and a speaker, etc.; a storage section 1108 including a hard disk, etc. ; and a communication section 1109 including a network interface card such as a LAN card, a modem, and the like.
  • the communication section 1109 performs communication processing via a network such as the Internet.
  • Drivers 1110 are also connected to I/O interface 1105 as needed.
  • a removable medium 1111 such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, etc., is mounted on the drive 1110 as needed so that a computer program read therefrom is installed into the storage section 1108 as needed.
  • embodiments of the present disclosure include a computer program product comprising a computer program carried on a computer-readable medium, the computer program containing program code for performing the method illustrated in the flowchart.
  • the computer program may be downloaded and installed from the network via the communication portion 1109, and/or installed from the removable medium 1111.
  • CPU central processing unit
  • the computer-readable medium shown in the present disclosure may be a computer-readable signal medium or a computer-readable storage medium, or any combination of the above two.
  • the computer-readable storage medium can be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus or device, or a combination of any of the above. More specific examples of computer readable storage media may include, but are not limited to, electrical connections with one or more wires, portable computer disks, hard disks, random access memory (RAM), read only memory (ROM), erasable Programmable read only memory (EPROM or flash memory), fiber optics, portable compact disk read only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.
  • a computer-readable storage medium may be any tangible medium that contains or stores a program that can be used by or in conjunction with an instruction execution system, apparatus, or device.
  • a computer-readable signal medium may include a data signal propagated in baseband or as part of a carrier wave, carrying computer-readable program code therein. Such propagated data signals may take a variety of forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the foregoing.
  • a computer-readable signal medium can also be any computer-readable medium other than a computer-readable storage medium that can transmit, propagate, or transport the program for use by or in connection with the instruction execution system, apparatus, or device .
  • Program code embodied on a computer readable medium may be transmitted using any suitable medium including, but not limited to, wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing.
  • each block in the flowchart or block diagrams may represent a module, segment, or portion of code that contains one or more logical functions for implementing the specified functions executable instructions.
  • the functions noted in the blocks may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved.
  • the modules involved in the embodiments of the present disclosure may be implemented in software or hardware.
  • the described modules can also be provided in the processor, for example, it can be described as: a processor includes a parameter acquisition module, a specification conversion module, a circuit allocation module and a position restoration module. Wherein, the names of these modules do not constitute a limitation on the module itself under certain circumstances.
  • the parameter acquisition module can also be described as "a module for acquiring chip parameters from a connected terminal".
  • the present disclosure also provides a computer-readable medium.
  • the computer-readable medium may be included in the device described in the above-mentioned embodiments, or it may exist alone without being assembled into the device.
  • the above-mentioned computer-readable medium carries one or more programs, and when the above-mentioned one or more programs are executed by a device, the device includes: obtaining the repair specification of the spare circuit of the chip where the failed bit is located; Standardize the specifications to obtain standardized repair specifications; obtain the position of the failed bit on the chip; process the position of the failed bit on the chip according to the standardized repair specifications to obtain the standardized position of the failed bit; use an alternate circuit allocation algorithm according to The standardized position of the failed bit and the standardized repair specification are allocated to the spare circuit to obtain the standardized repair position of the spare circuit; according to the standardized repair specification, the standardized repair position of the spare circuit is restored to the repair position of the spare circuit on the chip to repair the failed bit.

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Abstract

一种失效位元修补方法、装置、设备及存储介质，涉及半导体技术领域。该方法包括：获取失效位元所在芯片的备用电路的修补规格（S202）；将所述备用电路的修补规格进行标准化处理，获得标准化修补规格（S204）；获取所述失效位元在所述芯片上的位置（S206）；根据所述标准化修补规格对所述失效位元在所述芯片上的位置进行处理，获得所述失效位元的标准化位置（S208）；采用备用电路分配算法根据所述失效位元的标准化位置和所述标准化修补规格分配所述备用电路，获得所述备用电路的标准化修补位置（S210）；根据所述标准化修补规格将所述备用电路的标准化修补位置还原为所述备用电路在芯片上的修补位置以修补所述失效位元（S212）。该方法实现了提高修补演算法的通用性。

Description

失效位元修补方法、装置、设备及存储介质
本公开基于申请号为202011225125.6、申请日为2020年11月05日、发明名称为《失效位元修补方法、装置、设备及存储介质》的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本公开作为参考。
技术领域
本公开涉及半导体技术领域，具体而言，涉及一种失效位元修补方法、装置、设备及可读存储介质。
背景技术
随着计算机技术的快速发展，集成电路芯片在人们的生产生活中发挥的作用越来越大。然而，芯片在研制、生产和使用过程中产生的失效问题不可避免，通常可以采用备用电路对芯片中的失效位元进行修补处理。
修补演算法(Repair Algorithm,RA)是一种能有效分派备用电路，以修补上述失效位元所在的线路的方法。RA能获取为备用电路分派的位置，在这些位置具有高概率的可能覆盖到芯片上所有失效位元的位置取代。但是一个RA分派位置覆盖特定芯片上所有失效位元的概率越高，这个RA越难适用不同产品规格的芯片，而对不同产品规格芯片重新开发RA耗费时间长、成本高。因此，提高RA的通用性成为亟待解决的问题。
在所述背景技术部分公开的上述信息仅用于加强对本公开的背景的理解，因此它可以包括不构成对本领域普通技术人员已知的现有技术的信息。
发明内容
本公开的目的在于提供一种失效位元修补方法、装置、设备及可读存储介质，以提高修补演算法的通用性。
本公开的其他特性和优点将通过下面的详细描述变得显然，或部分 地通过本公开的实践而习得。
根据一些实施例，本申请第一方面提供了一种失效位元修补方法，包括：获取失效位元所在芯片的备用电路的修补规格；将所述备用电路的修补规格进行标准化处理，获得标准化修补规格；获取所述失效位元在所述芯片上的位置；根据所述标准化修补规格对所述失效位元在所述芯片上的位置进行处理，获得所述失效位元的标准化位置；采用备用电路分配算法根据所述失效位元的标准化位置和所述标准化修补规格分配所述备用电路，获得所述备用电路的标准化修补位置；根据所述标准化修补规格将所述备用电路的标准化修补位置还原为所述备用电路在芯片上的修补位置以修补所述失效位元。
根据一些实施例，本申请第二方面提供了一种失效位元修补装置，包括：参数获取模块，用于获取失效位元所在芯片的备用电路的修补规格；获取所述失效位元在所述芯片上的位置；规格转换模块，用于将所述备用电路的修补规格进行标准化处理，获得标准化修补规格；根据所述标准化修补规格对所述失效位元在所述芯片上的位置进行处理，获得所述失效位元的标准化位置；电路分配模块，用于采用备用电路分配算法根据所述失效位元的标准化位置和所述标准化修补规格分配所述备用电路，获得所述备用电路的标准化修补位置；位置还原模块，用于根据所述标准化修补规格将所述备用电路的标准化修补位置还原为所述备用电路在芯片上的修补位置以修补所述失效位元。
根据一些实施例，本申请第三方面提供了一种设备，包括：存储器、处理器及存储在所述存储器中并可在所述处理器中运行的可执行指令，所述处理器执行所述可执行指令时实现如上述任一种方法。
根据一些实施例，本申请第四方面提供了一种计算机可读存储介质，其上存储有计算机可执行指令，所述可执行指令被处理器执行时实现如上述任一种方法。
本公开实施例可以具有以下优点，通过获取失效位元所在芯片的备用电路的修补规格和失效位元在芯片上的位置，将备用电路的修补规格进行标准化处理获得标准化修补规格，根据标准化修补规格对失效位元在芯片上的位置进行处理获得失效位元的标准化位置，然后采用备用电路 分配算法根据失效位元的标准化位置和标准化修补规格分配备用电路，获得备用电路的标准化修补位置，再根据标准化修补规格将备用电路的标准化修补位置还原为备用电路在芯片上的修补位置以修补失效位元，从而可实现提高修补演算法的通用性。
应当理解的是，本申请的一个或多个实施例的细节在下面的附图和描述中提出，以上的一般描述和后文的细节描述仅是示例性的，并不能限制本公开。本申请的其它特征和优点将从说明书.附图以及权利要求书变得明显。
附图说明
为了更清楚地说明本申请实施例或传统技术中的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。通过参照附图详细描述其示例实施例，本公开的上述和其它目标、特征及优点将变得更加显而易见。
图1示出本公开实施例中一种系统结构的示意图。
图2示出本公开实施例中一种失效位元修补方法的流程图。
图3是根据图2示出的一种备用电路分析系统的数据流转示意图。
图4A是根据图3示出的一种产品单元的框图。
图4B是根据一示例性实施例示出的一种采用备用电路分析系统进行数据分割的示意图。
图5A是根据一示例性实施例示出的一种备用电路的规格转换方法的流程图。
图5B是根据一示例性实施例示出的区域划分示意图。
图6A是根据一示例性实施例示出的另一种备用电路的规格转换方法的流程图。
图6B是根据一示例性实施例示出的标准化子域划分示意图。
图6C是根据一示例性实施例示出的同位修补示意图。
图7是根据一示例性实施例示出的统一规格数据示意图。
图8是根据一示例性实施例示出的另一种失效位元修补方法的流程图。
图9是根据图8示出的再一种备用电路分析系统的数据流转示意图。
图10是根据图8和图9示出的又一种备用电路分析系统的数据流转示意图。
图11示出本公开实施例中一种电子设备的结构示意图。
具体实施方式
现在将参考附图更全面地描述示例实施例。然而，示例实施例能够以多种形式实施，且不应被理解为限于在此阐述的范例；相反，提供这些实施例使得本公开将更加全面和完整，并将示例实施例的构思全面地传达给本领域的技术人员。附图仅为本公开的示意性图解，并非一定是按比例绘制。图中相同的附图标记表示相同或类似的部分，因而将省略对它们的重复描述。
此外，所描述的特征、结构或特性可以以任何合适的方式结合在一个或更多实施例中。在下面的描述中，提供许多具体细节从而给出对本公开的实施例的充分理解。然而，本领域技术人员将意识到，可以实践本公开的技术方案而省略所述特定细节中的一个或更多，或者可以采用其它的方法、装置、步骤等。在其它情况下，不详细示出或描述公知结构、方法、装置、实现或者操作以避免喧宾夺主而使得本公开的各方面变得模糊。
此外，术语“第一”、“第二”等仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本公开的描述中，“多个”的含义是至少两个，例如两个，三个等，除非另有明确具体的限定。符号“/”一般表示前后关联对象是一种“或”的关系。
在本公开中，除非另有明确的规定和限定，“连接”等术语应做广义理解，例如，可以是电连接或可以互相通讯；可以是直接相连，也可以通过中间媒介间接相连。对于本领域的普通技术人员而言，可以根据具体情 况理解上述术语在本公开中的具体含义。
如上所述，含有失效位元的芯片上设有备用电路，芯片包括沿预定方向延伸的备用电路，这些备用电路用于通过取代预设修补范围内失效的位元来修补芯片。备用电路的数量有限，因此需要设计RA来对备用电路进行分派。RA能获取为各种备用电路分派的位置，在这些位置具有高概率的可能覆盖到芯片上所有失效位元的位置取代。但是一个RA分派位置覆盖所有失效位元的概率越高，这个RA越难以成为通用算法。通用算法指的是可以容易的被应用到大多数(甚至所有的)产品规格上。而RA开发耗费时间长、成本高。因此提高RA的通用性成为亟待解决的问题。
因此，本公开提供了一种失效位元修补方法，通过获取失效位元所在芯片的备用电路的修补规格和失效位元在芯片上的位置，将备用电路的修补规格进行标准化处理获得标准化修补规格，根据标准化修补规格对失效位元在芯片上的位置进行处理获得失效位元的标准化位置，然后采用备用电路分配算法根据失效位元的标准化位置和标准化修补规格分配备用电路，获得备用电路的标准化修补位置，再根据标准化修补规格将备用电路的标准化修补位置还原为备用电路在芯片上的修补位置以修补失效位元，从而可实现提高修补演算法的通用性。
图1示出了可以应用本公开的失效位元修补方法或备用电路分析系统的示例性系统架构10。
如图1所示，系统架构10可以包括终端设备102、网络104、服务器106和数据库108。终端设备102可以是具有显示屏并且支持输入、输出的各种电子设备，包括但不限于智能手机、平板电脑、膝上型便携计算机、台式计算机、芯片修补设备等等。网络104用以在终端设备102和服务器106之间提供通信链路的介质。网络104可以包括各种连接类型，例如有线、无线通信链路或者光纤电缆等等。服务器106可以是提供各种服务的服务器或服务器集群等。数据库108可以为置于服务器上的大型数据库软件，也可以为安装在计算机上的小型数据库软件，用于存储数据。
可以使用终端设备102通过网络104与服务器106和数据库108交互，以接收或发送数据等。例如，终端设备102例如可以是芯片修补设备，通过网络104向服务器106上传芯片失效位元位置数据和备用电路修补规格， 又通过网络104从服务器106中获取分配的备用电路修补位置。在服务器106也可通过网络104从数据库108接收数据或向数据库108发送数据等。例如服务器106可为后台处理服务器，用于通过网络104从数据库108获取芯片失效位元位置数据和备用电路修补规格，并进行备用电路分配，然后将分配的备用电路修补位置通过网络104反馈给芯片修补设备102。
应该理解，图1中的终端设备、网络、服务器和数据库的数目仅仅是示意性的。根据实现需要，可以具有任意数目的终端设备、网络、服务器和数据库。
图2是根据一示例性实施例示出的一种失效位元修补方法的流程图。如图2所示的方法例如可以应用于上述系统的服务器端，也可以应用于上述系统的终端设备。
参考图2，本公开实施例提供的方法20可以包括以下步骤。
在步骤S202中，获取失效位元所在芯片的备用电路的修补规格。备用电路的修补规格可包括备用电路的线宽和备用电路的预设修补范围，还可包括备用电路的数量等等。不同的芯片产品可有不同的备用电路修补规格。
在步骤S204中，将备用电路的修补规格进行标准化处理，获得标准化修补规格。标准化修补规格可包括标准化线宽和标准化修补范围，可将备用电路的线宽按照位元数量进行标准化，将修补范围根据备用电路的长度、数量等参数重新划分修补范围，获得标准化修补范围，具体实施方式可参照图5A至图5B。通过将备用电路的修补规格进行标准化处理，将各种产品的备用电路修补规格转换为统一的标准规格，可用于后续的备用电路分派算法。
在步骤S206中，获取失效位元在芯片上的位置。可获得一个芯片中的所有失效位元的位置数据。不同的芯片产品对位置的编排方法不同。在芯片上通常要以2的倍数的方式来计数。例如某一个芯片产品，由2 2个阵列组(Bank Group，BG)组成，每一个BG又分为2 2个阵列(Bank)，Bank中对于位元位置的定位可以X15-0,D0-2,Y0-3……等2元数据组成。换句话说，一个位元在一个芯片中的位置可以32个2进位数值来表示。
在步骤S208中，根据标准化修补规格对失效位元在芯片上的位置进 行处理，获得失效位元的标准化位置。根据备用电路的线宽和标准化线宽对失效位元在芯片上的位置进行缩放处理，获得失效位元的标准化位置。
在一些实施例中，例如，可获得缩放比例参数为标准化线宽/备用电路原线宽。
在步骤S210中，采用备用电路分配算法根据失效位元的标准化位置和标准化修补规格分配备用电路，获得备用电路的标准化修补位置。根据备用电路的标准化线宽、标准化修补范围和备用电路的数量，可采用任何可有效分派备用电路使其完全覆盖芯片上所有失效位元位置的算法，对备用电路进行分配，获得备用电路对于标准化修补范围的标准化修补位置。
在步骤S212中，根据标准化修补规格将备用电路的标准化修补位置还原为备用电路在芯片上的修补位置以修补失效位元。可根据备用电路的线宽和标准化线宽将备用电路的标准化修补位置还原为备用电路在芯片上的修补位置以修补失效位元。例如可根据上述缩放比例参数逆向还原备用电路在芯片上的修补位置，并将该数据提供至芯片修补设备进行修补。
根据本公开实施例提供的失效位元修补方法，通过获取失效位元所在芯片的备用电路的修补规格和失效位元在芯片上的位置，将备用电路的修补规格进行标准化处理获得标准化修补规格，根据标准化修补规格对失效位元在芯片上的位置进行处理获得失效位元的标准化位置，然后采用备用电路分配算法根据失效位元的标准化位置和标准化修补规格分配备用电路，获得备用电路的标准化修补位置，再根据标准化修补规格将备用电路的标准化修补位置还原为备用电路在芯片上的修补位置以修补失效位元，从而可实现提高修补演算法的通用性。
图3是根据图2示出的一种备用电路分析系统的数据流转示意图。如图3所示，输入备用电路分析系统的来源数据包括失效位元在原芯片上的位置数据302和产品规格参数304，产品规格参数304可为备用电路的修补规格。图3中实线连接箭头表示处理流程，虚线连接箭头表示输入/输出。备用电路分析系统可包括产品单元306和共用单元308，具体描述如下。
产品单元306可针对各式不同产品规格进行规格标准化，配置统一规格数据的转换方法与规格定义，使任意产品规格(如新产品规格)数据， 可经由产品规格参数的标准化方法，将新产品规格转换为统一规格数据。产品单元306可用于实施图2中的步骤S202至步骤S208。
共用单元308可嵌入任意备用电路分派算法，使各种备用电路分派算法承接统一规格数据的流程，并控制统一规格数据进行算法运算，获取最终的备用电路分派修补位置数据310。修补位置数据310可为一个芯片中所有备用电路分派修补失效位元的位置数据。产品单元306可用于实施图2中的步骤S210至步骤S212。
图4A是根据图3示出的采用备用电路分析系统进行数据分割的数据交互图。图4A中实线连接箭头表示处理流程，虚线连接箭头表示输入/输出。如图4A所示，产品单元306可包括数据分割模块3062和规格转换模块3064，具体描述如下。
数据分割模块3062可用于将一个芯片的数据进行分割，使其成为数个在备用电路分派时不会相互影响的可独立处理之范围数据。数据分割模块3062可根据产品规格参数304，对芯片中的数据进行分割。图4B是根据一示例性实施例示出的一种数据分割示意图。如图4B所示，将一个芯片中数据分割为数个Banks 30722数据，每一个Bank数据，基于产品规格中全域备用电路(Global Redundancy,GR)可分派的最大范围(此范围称为全域)，将每一个Bank数据进行分割成为数个全域30724，存储成全域数据3072。可将全域数据3072发送至规格转换模块3064。
规格转换模块3064可用于将全域数据3072转换为统一规格数据3074并传输至共用单元308，且不影响已知的失效位元位置信息。此外，数据中提供标准化前与标准化后所有位元位置的缩放比例参数，使每一个标准化后的位置皆可计算出原始位置。规格转换模块3064的具体处理流程可参照图5A至图6C。
共用单元308提供备用电路分派的算法，指定了每一个失效位元由哪种备用电路进行修补，无需针对某产品的提供不同的算法，提供一个能将众多已进行数据分割的统一规格数据3074实现有秩序的处理流程，获取最终的备用电路分派修补位置数据310。
图5A是根据一示例性实施例示出的一种备用电路的规格转换方法的流程图。如图5A所示的方法可为图2中步骤S204至步骤S208的具体处 理过程。如图5A所示的方法例如可以应用于上述系统的服务器端，也可以应用于上述系统的终端设备。
在步骤S502中，将备用电路的线宽按照位元进行标准化处理，获得标准化线宽。针对各式产品中，各种备用电路之线宽大小不一的问题，可将备用电路的线宽按照位元进行标准化，例如标准化为1个、或2个、或3个位元。
在步骤S504中，根据预设修补范围将芯片划分为多个统一区域，获得各个统一区域的范围。可获得各个统一区域的范围的长度为对应的预设修补范围在备用电路的延伸方向的长度，或获得各个统一区域的范围的宽度为对应的预设修补范围在备用电路的延伸方向的长度。
在一些实施例中，例如，备用电路可包括全域备用电路(GR)和子域备用电路(Local Redundancy,LR)，全域备用电路的延伸方向与子域备用电路的延伸方向正交，预设修补范围可包括全域修补范围和子域修补范围，全域修补范围包括多个子域修补范围，其中全域备用电路用于修补芯片上的全域修补范围内的失效位元，子域备用电路用于修补芯片上的子域修补范围内的失效位元。可获得各个统一区域的范围的长度为对应的全域修补范围在全域备用电路的延伸方向的长度，获得各个统一区域的范围的宽度与对应的子域修补范围在子域备用电路的延伸方向的长度相同。
图5B是根据一示例性实施例示出的区域划分示意图。如图5B所示，可在根据图4B将芯片划分出多个全域之后，可将每个全域分割为数个区域5002，任一个区域的GR与LR分派处理过程不会影响其他区域，例如一个区域A分派的GR或LR不可能与除A以外的其他区域的GR或LR分派位置呈现交叉或重迭的情况。可定义一个区域5002的范围为：GR延伸方向范围为一条GR可分派修补的长度范围50024，LR延伸方向范围为一条LR可分派修补的长度范围50022，其中GR分派修补示例50026为图5B中GR方向虚线，LR分派修补示例50028为图5B中LR方向实线。
在步骤S506中，根据各个统一区域的范围将预设修补范围进行标准化处理，获得备用电路的标准化修补范围。将芯片或一个全域划分为各个统一区域的范围，将备用电路的修补范围对应到各个统一区域的范围。例 如可获得各个GR或LR对应的标准化修补范围。
在步骤S508中，根据标准化线宽对失效位元在芯片上的位置进行处理，获得失效位元的标准化位置为失效位元在对应的统一区域的位置。各个位元在芯片上的位置都可标准化为其在统一区域上的位置，可用位元值矩阵表示在芯片或区域上的位置的位元是否失效。在进行备用电路分配计算时，可用OR运算的方式进行标准化线宽，例如线宽为3位元(bit)，就是第一位元、第二位元及第三位元的值进行OR运算，即标准化位元值＝第一位元值or第二位元值or第三位元值。
在一些实施例中，例如，GR用于替换失效位元所在的字线，即GR＝RWL(Redundant Word Line，备用字线)，LR用于替换失效位元所在的位线，即LR＝RBL(Redundant Bit Line，备用位线)。例如RWL线宽为2(位元)，RBL线宽也为2，原始子域为
Figure PCTCN2021108195-appb-000001
则可标准化GR线宽为
Figure PCTCN2021108195-appb-000002
在另一些实施例中，可将芯片分区进行细化，例如，可将一个芯片(chip)划分为多个堆(banks)，GR与LR长度不会超过1bank范围，且GR长度>LR长度。每个bank划分为多个全域，每个全域划分多个区域(segments)，每个segment可划分多个子域的同时，也可划分为多个区(sections)，1子域或section＝多个数据区(或数据格，DQ)，1DQ＝多个位元。1个chip中，其bank与全域的大小会是一致的，segment、子域、DQ则可能会有不同大小。
根据本公开实施例提供的备用电路的规格转换方法，通过将各种产品的备用电路修补规格，转换为一个统一的标准规格，获得不同的备用电路修补规格的产品的标准化修补数据，其中不同的产品会有不同的处理过程， 可使最终输出的标准化修补数据符合共用单元的输入规格的要求，即可使任一电路分配算法在共用单元中对标准化修补规格的备用电路进行分配，提高修补演算法的通用性。
图6A是根据一示例性实施例示出的另一种备用电路的规格转换方法的流程图。如图6A所示的方法可为图6A中步骤S506的具体处理过程。如图6A所示的方法例如可以应用于上述系统的服务器端，也可以应用于上述系统的终端设备。
标准化修补范围包括标准化全域修补范围和标准化子域修补范围。
在步骤S602中，获得标准化全域修补范围为对应的统一区域的范围。
在步骤S604中，在子域备用电路用于同位修补时，对子域备用电路对应的子域修补范围进行标准化，获得标准化子域修补范围，标准化子域修补范围在全域备用电路的延伸方向的长度为一个数据格(DQ)。
在一些实施例中，例如，可标准化LR线宽为
Figure PCTCN2021108195-appb-000003
此即为标准化子域。纵轴以DQ为基本单位进行OR运算或加法运算，例如，若将每一个原始子域中纵向的DQ都视为一个矩阵，则
Figure PCTCN2021108195-appb-000004
其中d ijk表示原始子域中第i行第j列DQ中的第k个位元之值；
Figure PCTCN2021108195-appb-000005
表示标准化子域中第j列DQ中的第k个位元之值，如上所述，位元的值为0或1。
图6B是根据一示例性实施例示出的标准化子域划分示意图。如图6B所示，若LR拥有GR方向连续DQ中相同位置位修补的特征时，将原始子域6002进行标准化获得标准化子域6004，即在GR方向将原始子域6002的范围标准化为可接受的最小范围，通常为1DQ，可使统一规格数据在使用时无需考虑同位修补问题。
图6C是根据一示例性实施例示出的同位修补示意图。如图6C所示，在未进行统一规格数据的情况下，左图中为原始子域中有一点失效位元，右图则在LR方向分派的LR修补电路。一个LR就只是一条备用电路， 不是多条备用电路，看起来像多条(或行)是背后线路设计的原因，它们都算是同一条。在进行修补时，只是指定某一个LR位置，替换原本具有失效位元的那一条线路位置，以此达成修补失效位元的目的。
图7是根据一示例性实施例示出的统一规格数据示意图。如图7所示，一个芯片可包括多个全域6008，一个全域6008可划分为多个区域6006，一个区域6006可在GR方向划分为多个标准化子域6004。
图8是根据一示例性实施例示出的另一种失效位元修补方法的流程图。如图8所示的方法可为图5A中步骤S508之后进行的失效位元修补处理过程。如图8所示的方法例如可以应用于上述系统的服务器端，也可以应用于上述系统的终端设备。
在步骤S802中，在各个统一区域，采用备用电路分配算法根据失效位元在对应的统一区域的位置和标准化修补范围分配备用电路，获得标准化修补位置为备用电路在对应的统一区域的修补位置。可采用任何有效分派备用电路完全盖覆失效位元位置的备用电路分配算法，输出备用电路分派的位置与结果，该结果为该全域中的失效位元是否能成功的完全被有限的备用电路完全覆盖修补，若成功则为有效全域，否则为失效全域。
在步骤S804中，根据标准化线宽将备用电路在对应的统一区域的修补位置还原为备用电路在芯片上的修补位置以修补失效位元。在线宽按照位元进行标准化处理时获得了标准化线宽，例如标准化为1个、或2个、或3个位元，对应的GR方向则缩小为1/原GR线宽、或2/原GR线宽、或2/原GR线宽，LR方向缩小为1/原LR线宽、或2/原LR线宽、或2/原LR线宽，在最后输出修补位置数据时，需把缩小的位置给放大回来进行还原。
图9是根据图8示出的再一种备用电路分析系统的数据流转示意图。图9中实线连接箭头表示处理流程，虚线连接箭头表示输入/输出。
参考图9，其中与图3和图4A含义相同的模块的标号相同，此处不再赘述。如图9所示，共用单元308可包括输入控制模块3082，可用于输入众多已进行数据分割的统一规格数据3074，进而任一个区域的GR与LR分派处理过程不会影响其他区域，可以将每一个区域依序独自进入分派算法模块3084进行备用电路分派处理。在每一个区域进入分派算法 模块3084时，可给予额外的辅助参数，如当前全域中的GR与区域中的LR之可使用数量等等。分派算法模块3084中提供任何可有效分派备用电路完全盖覆失效位元位置的算法，输出备用电路分派的位置与结果即分派数据3088，该结果为该全域中的失效位元是否能成功的完全被有限的备用电路完全覆盖修补，若成功则为有效全域，否则为失效全域。失效全域所属的Bank也将被指定为失效Bank。位置还原模块3086借由统一规格数据3074中所提供的缩放比例参数，将分派数据3088中备用电路分派修补位置(为标准化后位置)还原成原始位置，输出所有分派修补原始位置至修补位置数据310。
图10是根据图8和图9示出的又一种备用电路分析系统的数据流转示意图。图10中实线连接箭头表示处理流程，虚线连接箭头表示输入/输出。
参考图10，其中与图3、图4A和图9含义相同的模块的标号相同，此处不再赘述。如图9所示，在共用单元308中，输入控制模块3082接收统一规格数据3074后，首先依序读取芯片中的全域(S3002)，再依序读取全域中的区域(S30010)后进入分派算法模块3084。分派算法模块3084进行备用电路分派时，判断分派结果是否为该区域中的失效位元能成功的完全被有限的备用电路完全覆盖修补(S3008)，若能，则进一步判断是否对应全域中是否存在未处理区域(S3004)，若存在未处理区域则返回步骤S30010进行读取，若不存在未处理区域则判断是否存在未处理全域(S3006)，若存在未处理全域则返回步骤S3002进行读取，若不存在未处理全域则进入位置还原模块3086，将分派数据3088中备用电路分派修补位置还原成原始位置，输出所有分派修补原始位置至修补位置数据310。
图11示出本公开实施例中一种电子设备的结构示意图。需要说明的是，图11示出的设备仅以计算机系统为示例，不应对本公开实施例的功能和使用范围带来任何限制。
如图11所示，设备1100包括中央处理单元(CPU)1101，其可以根据存储在只读存储器(ROM)1102中的程序或者从存储部分1108加载到随机访问存储器(RAM)1103中的程序而执行各种适当的动作和处理。 在RAM 1103中，还存储有设备1100操作所需的各种程序和数据。CPU1101、ROM 1102以及RAM 1103通过总线1104彼此相连。输入/输出(I/O)接口1105也连接至总线1104。
以下部件连接至I/O接口1105：包括键盘、鼠标等的输入部分1106；包括诸如阴极射线管(CRT)、液晶显示器(LCD)等以及扬声器等的输出部分1107；包括硬盘等的存储部分1108；以及包括诸如LAN卡、调制解调器等的网络接口卡的通信部分1109。通信部分1109经由诸如因特网的网络执行通信处理。驱动器1110也根据需要连接至I/O接口1105。可拆卸介质1111，诸如磁盘、光盘、磁光盘、半导体存储器等等，根据需要安装在驱动器1110上，以便于从其上读出的计算机程序根据需要被安装入存储部分1108。
特别地，根据本公开的实施例，上文参考流程图描述的过程可以被实现为计算机软件程序。例如，本公开的实施例包括一种计算机程序产品，其包括承载在计算机可读介质上的计算机程序，该计算机程序包含用于执行流程图所示的方法的程序代码。在这样的实施例中，该计算机程序可以通过通信部分1109从网络上被下载和安装，和/或从可拆卸介质1111被安装。在该计算机程序被中央处理单元(CPU)1101执行时，执行本公开的系统中限定的上述功能。
需要说明的是，本公开所示的计算机可读介质可以是计算机可读信号介质或者计算机可读存储介质或者是上述两者的任意组合。计算机可读存储介质例如可以是——但不限于——电、磁、光、电磁、红外线、或半导体的系统、装置或器件，或者任意以上的组合。计算机可读存储介质的更具体的例子可以包括但不限于：具有一个或多个导线的电连接、便携式计算机磁盘、硬盘、随机访问存储器(RAM)、只读存储器(ROM)、可擦式可编程只读存储器(EPROM或闪存)、光纤、便携式紧凑磁盘只读存储器(CD-ROM)、光存储器件、磁存储器件、或者上述的任意合适的组合。在本公开中，计算机可读存储介质可以是任何包含或存储程序的有形介质，该程序可以被指令执行系统、装置或者器件使用或者与其结合使用。而在本公开中，计算机可读的信号介质可以包括在基带中或者作为载波一部分传播的数据信号，其中承载了计算机可读的程序代码。这种传播 的数据信号可以采用多种形式，包括但不限于电磁信号、光信号或上述的任意合适的组合。计算机可读的信号介质还可以是计算机可读存储介质以外的任何计算机可读介质，该计算机可读介质可以发送、传播或者传输用于由指令执行系统、装置或者器件使用或者与其结合使用的程序。计算机可读介质上包含的程序代码可以用任何适当的介质传输，包括但不限于：无线、电线、光缆、RF等等，或者上述的任意合适的组合。
附图中的流程图和框图，图示了按照本公开各种实施例的系统、方法和计算机程序产品的可能实现的体系架构、功能和操作。在这点上，流程图或框图中的每个方框可以代表一个模块、程序段、或代码的一部分，上述模块、程序段、或代码的一部分包含一个或多个用于实现规定的逻辑功能的可执行指令。也应当注意，在有些作为替换的实现中，方框中所标注的功能也可以以不同于附图中所标注的顺序发生。例如，两个接连地表示的方框实际上可以基本并行地执行，它们有时也可以按相反的顺序执行，这依所涉及的功能而定。也要注意的是，框图或流程图中的每个方框、以及框图或流程图中的方框的组合，可以用执行规定的功能或操作的专用的基于硬件的系统来实现，或者可以用专用硬件与计算机指令的组合来实现。
描述于本公开实施例中所涉及到的模块可以通过软件的方式实现，也可以通过硬件的方式来实现。所描述的模块也可以设置在处理器中，例如，可以描述为：一种处理器包括参数获取模块、规格转换模块、电路分配模块和位置还原模块。其中，这些模块的名称在某种情况下并不构成对该模块本身的限定，例如，参数获取模块还可以被描述为“向所连接的终端获取芯片参数的模块”。
作为另一方面，本公开还提供了一种计算机可读介质，该计算机可读介质可以是上述实施例中描述的设备中所包含的；也可以是单独存在，而未装配入该设备中。上述计算机可读介质承载有一个或者多个程序，当上述一个或者多个程序被一个该设备执行时，使得该设备包括：获取失效位元所在芯片的备用电路的修补规格；将备用电路的修补规格进行标准化处理，获得标准化修补规格；获取失效位元在芯片上的位置；根据标准化修补规格对失效位元在芯片上的位置进行处理，获得失效位元的标准化位置；采用备用电路分配算法根据失效位元的标准化位置和标 准化修补规格分配备用电路，获得备用电路的标准化修补位置；根据标准化修补规格将备用电路的标准化修补位置还原为备用电路在芯片上的修补位置以修补失效位元。
以上具体地示出和描述了本公开的示例性实施例。应可理解的是，本公开不限于这里描述的详细结构、设置方式或实现方法；相反，本公开意图涵盖包含在所附权利要求的精神和范围内的各种修改和等效设置。

Claims (12)

  1. 一种失效位元修补方法，其中，包括：
    获取失效位元所在芯片的备用电路的修补规格；
    将所述备用电路的修补规格进行标准化处理，获得标准化修补规格；
    获取所述失效位元在所述芯片上的位置；
    根据所述标准化修补规格对所述失效位元在所述芯片上的位置进行处理，获得所述失效位元的标准化位置；
    采用备用电路分配算法根据所述失效位元的标准化位置和所述标准化修补规格分配所述备用电路，获得所述备用电路的标准化修补位置；
    根据所述标准化修补规格将所述备用电路的标准化修补位置还原为所述备用电路在芯片上的修补位置以修补所述失效位元。
  2. 根据权利要求1所述的方法，其中，所述备用电路的修补规格包括所述备用电路的线宽和所述备用电路的预设修补范围；
    所述标准化修补规格包括标准化线宽和标准化修补范围；
    所述将所述备用电路的修补规格进行标准化处理，获得标准化修补规格包括：
    将所述备用电路的线宽按照位元进行标准化处理，获得标准化线宽；
    根据所述预设修补范围将所述芯片划分为多个统一区域，获得各个统一区域的范围；
    根据所述各个统一区域的范围将所述预设修补范围进行标准化处理，获得所述备用电路的标准化修补范围。
  3. 根据权利要求2所述的方法，其中，所述根据所述标准化修补规格对所述失效位元在所述芯片上的位置进行处理，获得所述失效位元的标准化位置包括：
    根据所述标准化线宽对所述失效位元在所述芯片上的位置进行处理，获得所述失效位元的标准化位置为所述失效位元在对应的统一区域的位置；
    所述采用备用电路分配算法根据所述失效位元的标准化位置和所述 标准化修补规格分配所述备用电路包括：
    在所述各个统一区域，采用所述备用电路分配算法根据所述失效位元在对应的统一区域的位置和所述标准化修补范围分配所述备用电路，获得所述标准化修补位置为所述备用电路在对应的统一区域的修补位置。
  4. 根据权利要求3所述的方法，其中，所述根据所述标准化修补规格将所述备用电路的标准化修补位置还原为所述备用电路在芯片上的修补位置以修补所述失效位元包括：
    根据所述标准化线宽将所述备用电路在对应的统一区域的修补位置还原为所述备用电路在芯片上的修补位置以修补所述失效位元。
  5. 根据权利要求2-4任一项所述的方法，其中，所述根据所述预设修补范围将所述芯片划分为多个统一区域，获得各个统一区域的范围包括：
    获得各个统一区域的范围的长度为对应的预设修补范围在所述备用电路的延伸方向的长度，或
    获得各个统一区域的范围的宽度为对应的预设修补范围在所述备用电路的延伸方向的长度。
  6. 根据权利要求5所述的方法，其中，所述备用电路包括全域备用电路和子域备用电路；
    所述全域备用电路的延伸方向与所述子域备用电路的延伸方向正交；
    所述预设修补范围包括全域修补范围和子域修补范围，所述全域修补范围包括多个所述子域修补范围；
    所述全域备用电路用于修补所述芯片上的所述全域修补范围内的失效位元，所述子域备用电路用于修补所述芯片上的所述子域修补范围内的失效位元；
    所述各个统一区域的范围的长度与对应的全域修补范围在所述全域备用电路的延伸方向的长度相同，所述各个统一区域的范围的宽度与对应的子域修补范围在所述子域备用电路的延伸方向的长度相同。
  7. 根据权利要求6所述的方法，其中，所述标准化修补范围包括标 准化全域修补范围和标准化子域修补范围；
    所述根据所述各个统一区域的范围将所述预设修补范围进行标准化处理，获得所述备用电路的标准化修补范围包括：
    获得所述标准化全域修补范围为对应的统一区域的范围；
    在所述子域备用电路用于同位修补时，对所述子域备用电路对应的子域修补范围进行标准化，获得所述标准化子域修补范围，所述标准化子域修补范围在所述全域备用电路的延伸方向的长度为一个数据格。
  8. 根据权利要求2所述的方法，其中，所述根据所述标准化修补规格对所述失效位元在所述芯片上的位置进行处理，获得所述失效位元的标准化位置包括：
    根据所述备用电路的线宽和所述标准化线宽对所述失效位元在所述芯片上的位置进行缩放处理，获得所述失效位元的标准化位置。
  9. 根据权利要求8所述的方法，其中，所述根据所述标准化修补规格将所述备用电路的标准化修补位置还原为所述备用电路在芯片上的修补位置以修补所述失效位元包括：
    根据所述备用电路的线宽和所述标准化线宽将所述备用电路的标准化修补位置还原为所述备用电路在芯片上的修补位置以修补所述失效位元。
  10. 一种失效位元修补装置，其中，包括：
    参数获取模块，用于获取失效位元所在芯片的备用电路的修补规格；获取所述失效位元在所述芯片上的位置；
    规格转换模块，用于将所述备用电路的修补规格进行标准化处理，获得标准化修补规格；根据所述标准化修补规格对所述失效位元在所述芯片上的位置进行处理，获得所述失效位元的标准化位置；
    电路分配模块，用于采用备用电路分配算法根据所述失效位元的标准化位置和所述标准化修补规格分配所述备用电路，获得所述备用电路的标准化修补位置；
    位置还原模块，用于根据所述标准化修补规格将所述备用电路的标准化修补位置还原为所述备用电路在芯片上的修补位置以修补所述失效位元。
  11. 一种设备，包括：存储器、处理器及存储在所述存储器中并可在所述处理器中运行的可执行指令，其中，所述处理器执行所述可执行指令时实现如权利要求1-9任一项所述的方法。
  12. 一种计算机可读存储介质，其上存储有计算机可执行指令，其中，所述可执行指令被处理器执行时实现如权利要求1-9任一项所述的方法。
PCT/CN2021/108195 2020-11-05 2021-07-23 失效位元修补方法、装置、设备及存储介质 WO2022095512A1 (zh)

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