WO2022095474A1 - 一种像素单元和像素单元的信号处理方法 - Google Patents

一种像素单元和像素单元的信号处理方法 Download PDF

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WO2022095474A1
WO2022095474A1 PCT/CN2021/102394 CN2021102394W WO2022095474A1 WO 2022095474 A1 WO2022095474 A1 WO 2022095474A1 CN 2021102394 W CN2021102394 W CN 2021102394W WO 2022095474 A1 WO2022095474 A1 WO 2022095474A1
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pixel
type main
type
sub
main pixel
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French (fr)
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刘晓彦
刘力桥
杜刚
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Peking University
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Peking University
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/77—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N23/00—Cameras or camera modules comprising electronic image sensors; Control thereof
    • H04N23/70—Circuitry for compensating brightness variation in the scene
    • H04N23/73—Circuitry for compensating brightness variation in the scene by influencing the exposure time
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/50—Control of the SSIS exposure
    • H04N25/57—Control of the dynamic range
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/703—SSIS architectures incorporating pixels for producing signals other than image signals
    • H04N25/708—Pixels for edge detection
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/709—Circuitry for control of the power supply
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/79—Arrangements of circuitry being divided between different or multiple substrates, chips or circuit boards, e.g. stacked image sensors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/80—Constructional details of image sensors
    • H10F39/802—Geometry or disposition of elements in pixels, e.g. address-lines or gate electrodes

Definitions

  • the present application relates to the field of photodetectors, and in particular, to a pixel unit and a signal processing method for the pixel unit.
  • Image sensing and processing systems are widely used in production and life, especially in the fields of face recognition, security monitoring, and autonomous driving.
  • the imaging function is completed by an image sensor such as a CMOS-APS photoelectric device, and the complete image data is transmitted to an image signal processor for processing.
  • an image sensor such as a CMOS-APS photoelectric device
  • the amount of raw image data generated by the image sensor continues to increase.
  • applications such as intelligent visual recognition, there is a large amount of information redundancy in the original image data, which is difficult for data transmission and processing. It brings huge pressure and brings unnecessary delay and power consumption to the data transmission and processing of the system.
  • the demand for high-speed and low-power image processing in areas such as edge computing and the Internet of Things is getting higher and higher, and more efficient image sensing and processing systems are required.
  • the original image signal can be processed in real time, so as to perform feature extraction and information screening on the original image, and reduce the calculation amount of data transmission and image processing units.
  • some image preprocessing schemes mainly include adding various functional circuits in or around the pixels, such as comparators, convolution calculation circuits, etc., so that the pixel signals can be processed in real time, and the redundant data can be filtered out.
  • the data is input to the image processing unit for further processing, thereby reducing the time cost and energy consumption required for calculation and improving the operating efficiency of the entire system.
  • adding a preprocessing circuit at the pixel level will result in a complicated circuit, which will lead to an increase in the pixel area.
  • the present application proposes a pixel unit and a signal processing method for the pixel unit.
  • the present application provides a pixel unit, including at least one pixel; the pixel includes: an N-type main pixel, a P-type main pixel, and a sub-pixel;
  • Both the N-type main pixel and the P-type main pixel are used for outputting a current corresponding to the exposure intensity to the sub-pixels according to exposure;
  • the sub-pixel is between the N-type main pixel and the P-type main pixel, and is configured to generate and output a signal difference between the N-type main pixel and the P-type main pixel according to the current.
  • the present application provides a pixel unit including at least one adjacent first pixel and one second pixel; the first pixel includes an N-type main pixel, and the second pixel includes a P-type main pixel a pixel; the first pixel and the second pixel share one sub-pixel;
  • Both the N-type main pixel and the P-type main pixel are used for outputting a current corresponding to the exposure intensity to the sub-pixels according to exposure;
  • the sub-pixel generates and outputs a signal difference between the N-type main pixel and the P-type main pixel according to the current.
  • the N-type main pixel, the P-type main pixel and the sub-pixel all include an N-type MOS transistor structure, a buried oxide layer and a substrate.
  • the N-type MOS transistor structure includes: an N-type MOS transistor source region, an N-type MOS transistor channel region and an N-type MOS transistor drain region.
  • the thickness of the silicon film in the channel region of the N-type MOS transistor is 5 nanometers to 20 nanometers.
  • the length of the N-type MOS tube source region and the N-type MOS tube drain region is 20 nanometers to 90 nanometers.
  • the thickness of the buried oxide layer is 10 nanometers to 30 nanometers.
  • the substrate in the N-type main pixel is an N-type doped well
  • the substrate in the P-type main pixel is a P-type doped well.
  • shallow trench isolation is used for isolation between the N-type main pixel, the P-type main pixel and the sub-pixels.
  • the present application proposes a signal processing method for a pixel unit, using the above-mentioned pixel unit, including the following steps:
  • a positive voltage is applied to the N-type main pixel in the pixel unit, and a negative voltage is applied to the P-type main pixel;
  • the N-type main pixel and the P-type main pixel output a current corresponding to the exposure intensity to the sub-pixels according to exposure;
  • the sub-pixel generates and outputs a signal difference between the N-type main pixel and the P-type main pixel according to the current.
  • the advantage of the present application is that: by adding a sub-pixel between the two main pixels, the sub-pixel generates and outputs the signal difference between the N-type main pixel and the P-type main pixel according to the current sent by the two main pixels, which can directly communicate with the receiver.
  • the received signal is processed efficiently and the amount of output data is reduced. Since there is no need to increase the circuit, the pixel area will not be increased due to the complicated circuit.
  • FIG. 1 is a schematic diagram of a pixel unit provided by the present application.
  • FIG. 2 is a schematic diagram of another pixel unit provided by the present application.
  • FIG. 3 is a schematic structural diagram of a signal processing method for a pixel unit provided by the present application.
  • FIG. 4 is a schematic layout diagram of steps of a signal processing method for a pixel unit provided by the present application.
  • FIG. 5 is a graph of a threshold voltage variation of a sub-pixel of a pixel unit provided by the present application.
  • a pixel unit including at least one pixel 100; the pixel 100 includes: an N-type main pixel 101, a P-type main pixel 102 and a sub-pixel 103.
  • Both the N-type main pixel 101 and the P-type main pixel 102 are used for outputting a current corresponding to the exposure intensity to the sub-pixels 103 according to exposure.
  • the sub-pixel 103 is between the N-type main pixel 101 and the P-type main pixel 103, and is used for generating and outputting a signal difference between the N-type main pixel 101 and the P-type main pixel 102 according to the current.
  • the present application proposes a pixel unit, as shown in FIG. 2 , including at least one adjacent first pixel 201 and one second pixel 202; the first pixel 201 includes an N-type main pixel 101, and the second pixel 201
  • the pixel 202 includes a P-type main pixel 102 ; the first pixel 201 and the second pixel 202 share a sub-pixel 103 .
  • Both the N-type main pixel 101 and the P-type main pixel 102 are used for outputting a current corresponding to the exposure intensity to the sub-pixels 103 according to exposure.
  • the sub-pixel 103 generates and outputs the signal difference between the N-type main pixel 101 and the P-type main pixel 102 according to the current.
  • the N-type main pixel 101 , the P-type main pixel 102 and the sub-pixel 103 all include an N-type MOS transistor structure 310 , a buried oxide layer 320 and a substrate 330 .
  • the N-type MOS transistor structure 310 includes: an N-type MOS transistor source region 311 , an N-type MOS transistor channel region 312 and an N-type MOS transistor drain region 313 .
  • the thickness of the silicon film Tsi of the N-type MOS transistor channel region 312 is 5 nm to 20 nm.
  • the length of the N-type MOS transistor source region 311 (Ls) is 20 nanometers to 90 nanometers.
  • the length of the drain region 313 (Ld) of the N-type MOS transistor is 20 nanometers to 90 nanometers.
  • the thickness of the buried oxide layer 320 (Tbox) is 10 nm to 30 nm.
  • the length of the N-type MOS transistor channel region 313 (Lg) is 20 nanometers to 100 nanometers.
  • the substrate in the N-type main pixel 101 is the N-type doped well 330a
  • the substrate in the P-type main pixel 102 is the P-type doped well 330b.
  • Shallow trench isolation 340 is used for isolation between the N-type main pixel 101 , the P-type main pixel 102 and the sub-pixels 103 .
  • the main pixel is used to expose and convert the optical signal into an electrical signal, and save the original image signal, and the sub-pixel is used to generate and store the calculated result of the image signal.
  • the main pixel is divided into an N-type main pixel and a P-type main pixel.
  • the signal voltage of the N-type main pixel increases after exposure, and the signal voltage decreases after the P-type main pixel is exposed.
  • the signals generated by the two main pixels are coupled to the sub-pixels in the middle. , the difference between the two main pixel signals can be obtained in the sub-pixels. Through different pixel arrangement and exposure timing, this structure can realize the difference calculation of pixel signal in space and time.
  • two adjacent pixels include main pixels of different types, and after exposure, the signal difference between adjacent pixels can be obtained on the sub-pixels located between the two main pixels.
  • a pixel includes two main pixels and one sub-pixel. The two main pixels are exposed in two frames before and after respectively, and the signal difference between the two frames before and after the pixel can be obtained in the sub-pixel.
  • the spatial and temporal pixel signal differences are calculated in advance in many image processing algorithms. In this pixel structure, the results of the difference calculation can be obtained at the same time as the original signal is generated, which improves the computational efficiency.
  • the N-type main pixels, P-type main pixels and sub-pixels in the embodiments of the present application may be implemented by using traditional CMOS pixels or other new-type pixels.
  • the arrangement of the main pixels and sub-pixels and the exposure timing can be adjusted according to different needs.
  • Various structural parameters within the pixel can be adjusted separately.
  • the main pixel can be exposed in the form of backlight illumination.
  • the present application proposes a signal processing method for a pixel unit, as shown in FIG. 4 , including the following steps:
  • the N-type main pixel and the P-type main pixel output a current corresponding to the exposure intensity to the sub-pixels according to the exposure;
  • the sub-pixel generates and outputs the signal difference between the N-type main pixel and the P-type main pixel according to the current.
  • the photoelectric signal processing method of the embodiment of the present application is mainly divided into three processes: reset, collection and reading.
  • the corresponding electrode bias conditions are shown in Table 1.
  • reset collect read NMOS transistor gate voltage 0 0 +Vdd NMOS transistor drain voltage 0 0 +Vdd NMOS transistor source voltage 0 0 0 N-type doped region voltage -Vreset +Vdd +Vdd P-type doped region voltage +Vreset -Vdd -Vdd
  • a reset pulse signal Vreset (reset signal) is applied to the N terminal (N-type doped region) of the PN junction, the PN junction is forward biased, and the forward bias current injects charges into the floating P-type doped region and causes the P terminal (P
  • the voltage of the N-type MOS transistor source region 311, the N-type MOS transistor channel region 312 and the N-type MOS transistor drain region 313 are all zero, so that the N-type MOS transistor is in an off state .
  • the P-type doped well 330b and the N-type doped well 330a respectively apply reset pulse signals +Vreset and -Vreset to reset the voltage in the well to the initial voltage.
  • a negative voltage -Vdd is applied to the P-type doped well 330b, and a positive voltage +Vdd is applied to the N-type doped well 330a to generate a depletion region in the area of the doped well near the buried oxide layer 320.
  • the incident light generates photo-generated carriers in the doped well, and the photo-generated carriers are collected by the electric field in the depletion region.
  • the electric field of the depletion region of the P-type doped well 330b is directed downward, and photo-generated electrons are collected, and the potential of the P-type doped well 330b decreases after being illuminated.
  • the electric field of the depletion region of the N-type doped well 330a is directed upward, and the photo-generated holes are collected, and the potential of the N-type doped well 330a rises after being illuminated.
  • the sub-pixel 103 is located in the middle of the two main pixels, and the signals of the two adjacent main pixels will be coupled to the sub-pixel 103. Since the signal voltages of the two main pixels change in opposite directions after being illuminated, some of the signals after being coupled to the sub-pixel 103 cancel each other out. Thus, the difference between the signals of the two main pixels is obtained in the sub-pixel 103 .
  • the optical signal is read out through the current of the drain electrode on the drain end region 313 of the N-type MOS transistor above the buried oxide layer 320 .
  • the drain electrode on the N-type MOS transistor drain region 313 and the gate electrode on the N-type MOS transistor gate oxide dielectric layer 314 are both set to a positive voltage +Vdd.
  • the photogenerated carriers gathered under the buried oxide layer 320 will change the potential at the interface between the buried oxide layer 320 and the substrate 330, and act on the upper N-type MOS transistor channel region 312 through the buried oxide layer 320, so that the N-type MOS transistor can channel the threshold voltage changes.
  • the threshold voltage decreases after illumination, and the current of its drain (drain region 313) increases.
  • the threshold voltage increases after illumination, and the drain current (drain region 313) decreases.
  • the sub-pixel 103 when the illumination intensity of the N-type main pixel 101 is greater than that of the P-type main pixel 102, the threshold voltage decreases, and the drain terminal (drain terminal region 313) current increases; otherwise, the threshold voltage increases, the drain terminal (drain region 313) current decreases.
  • the illumination intensity can be estimated by measuring the current in the drain region of the main pixel, and the signal difference between the two main pixels can be obtained by measuring the current in the drain (drain region 313 ) in the sub-pixel 103 .
  • FIG. 5 it is the variation of the threshold voltage of the N-type MOS transistor structure 310 in the sub-pixel 103 under different exposure intensities of two adjacent main pixels.
  • the light intensity of main pixel 2 on different lines is different.
  • the light intensity of main pixel 2 on line 0 is 0, the light intensity of main pixel 2 on line 1 is 1, and the light intensity of main pixel 2 on line 2 is 2.
  • the light intensity of main pixel 2 on line 3 is 3, the light intensity of main pixel 2 on line 4 is 4, and the light intensity of main pixel 2 on line 5 is 5.
  • the change of the threshold voltage reflects the difference between the light intensity of the main pixel 1 and the main pixel 2, so when the light intensity of the main pixel 2 increases, the curve will shift downward.
  • the basic pixel structure of image sensing and computing that integrates image sensing and computing proposed by the embodiments of the present application, the pixel working mechanism that generates calculation results through the coupling of different types of main pixel signals, and the use of basic characteristics of pixels to achieve efficient image preview. deal with.
  • the sub-pixel by adding a sub-pixel between the two main pixels, the sub-pixel generates and outputs the signal difference between the N-type main pixel and the P-type main pixel according to the current sent by the two main pixels, which can directly
  • the received signal is processed efficiently to reduce the amount of output data. Since there is no need to increase the circuit, the pixel area will not be increased due to the complicated circuit.
  • the main pixel and the sub-pixel in the embodiments of the present application are both basic pixel structures, which retain a complete pixel structure while realizing computing functions, and avoid sacrificing imaging quality and pixel area.
  • the calculation results are generated simultaneously with the original signal, and there is no calculation delay compared to using the calculation circuit.
  • the original information of the image and the result after calculation are stored in the main pixel and the sub-pixel respectively, and the calculation result can be generated without losing the original information of the image.

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Abstract

一种像素单元和像素单元的信号处理方法，包括至少一个像素；所述像素包括：一个N型主像素、一个P型主像素和一个子像素；所述子像素在所述N型主像素与P型主像素之间。或包括相邻的至少一个第一像素和一个第二像素；所述第一像素包括一个N型主像素，所述第二像素包括一个P型主像素；所述第一像素和第二像素共用一个子像素。子像素根据电流，生成并输出N型主像素和P型主像素的信号差值。通过在两个主像素之间增加子像素，子像素根据两个主像素发送的电流，生成并输出N型主像素和P型主像素的信号差值，能够直接对接收到的信号进行高效处理，减小输出的数据量。由于不需要增加电路，因此不会因为复杂的电路导致像素面积增加。

Description

一种像素单元和像素单元的信号处理方法 技术领域
本申请涉及光电探测器领域，尤其涉及一种像素单元和像素单元的信号处理方法。
背景技术
图像传感与处理系统在生产生活中被广泛使用，尤其在人脸识别、安保监控、自动驾驶等领域。在目前主流图像传感与处理系统中，通过图像传感器如CMOS-APS光电器件完成成像功能，并将完整的图像数据传输给图像信号处理器进行处理。随着图像传感器的成像质量不断提高，图像传感器所产生的原始图像数据量不断增大，对于智能视觉识别等应用而言，原始的图像数据中存在着大量的信息冗余，给数据传输和处理带来了巨大压力，为系统的数据传输与处理带来了不必要的延迟与功耗。同时，边缘计算、物联网等领域对高速低功耗图像处理的需求越来越高，需要更高效的图像传感与处理系统。
通过在像素阵列层面设计相应的预处理电路能够对原始图像信号进行即时的处理，从而对原始图像进行特征提取和信息筛选，减少数据传输与图像处理单元的计算量。目前有的图像预处理方案主要包括在像素中或像素周围加入各种功能电路，例如比较器、卷积计算电路等，让像素信号得到即时的处理，将多余的数据过滤掉，只将有意义的数据输入到图像处理单元中进行进一步处理，从而降低计算所需的时间代价与能耗，提高整个系统的运行效率。然而在像素层面增加预处理电路，其电路复杂，会导致像素面积增大。
综上所述，需要提供一种能够在传感器中进行高效的图像处理，且不增大像素面积且电路复杂度低的像素单元和像素单元的信号处理方法。
发明内容
为解决以上问题，本申请提出了一种像素单元和像素单元的信号处理方法。
一方面，本申请提出了一种像素单元，包括至少一个像素；所述像素包括：一个N型主像素、一个P型主像素和一个子像素；
所述N型主像素和P型主像素均用于根据曝光，输出对应曝光强度的电流至所述子像素；
所述子像素在所述N型主像素与P型主像素之间，用于根据所述电流，生成并输出N型主像素和P型主像素的信号差值。
第二方面，本申请提出了一种像素单元，包括相邻的至少一个第一像素和一个第二像素；所述第一像素包括一个N型主像素，所述第二像素包括一个P型主像素；所述第一像素和第二像素共用一个子像素；
所述N型主像素和P型主像素均用于根据曝光，输出对应曝光强度的电流至所述子像素；
所述子像素根据所述电流，生成并输出N型主像素和P型主像素的信号差值。
优选地，所述N型主像素、P型主像素和子像素均包括N型MOS管结构、埋氧层和衬底。
优选地，所述N型MOS管结构包括：N型MOS管源端区域、N型MOS管沟道区域和N型MOS管漏端区域。
优选地，所述N型MOS管沟道区域的硅膜厚度为5纳米至20纳米。
优选地，所述N型MOS管源端区域和N型MOS管漏端区域的长度为20纳米至90纳米。
优选地，所述埋氧层的厚度为10纳米至30纳米。
优选地，所述N型主像素中的衬底为N型掺杂阱，所述P型主像素中的衬底为P型掺杂阱。
优选地，所述N型主像素、P型主像素和子像素之间使用浅沟槽隔离进行隔离。
第三方面，本申请提出了一种像素单元的信号处理方法，使用上述的像素单元，包括如下步骤：
对像素单元中的N型主像素施加正电压，对P型主像素施加负电压；
对所述像素单元进行曝光；
所述N型主像素和P型主像素根据曝光，输出对应曝光强度的电流至所述子像素；
所述子像素根据所述电流，生成并输出N型主像素和P型主像素的信号差值。
本申请的优点在于：通过在两个主像素之间增加子像素，子像素根据两个主像素发送的电流，生成并输出N型主像素和P型主像素的信号差值，能够直接对接收到的信号进行高效处理，减小输出的数据量。由于不需要增加电路，因此不会因为复杂的电路导致像素面积增加。
附图说明
通过阅读下文优选实施方式的详细描述，各种其他的优点和益处对于本领域普通技术人员将变得清楚明了。附图仅用于示出优选事实方案的目的，而并不认为是对本申请的限制。而且在整个附图中，用同样的参考符号表示相同的部件。在附图中：
图1是本申请提供的一种像素单元的示意图；
图2是本申请提供的另一种像素单元的示意图；
图3是本申请提供的一种像素单元的信号处理方法的结构示意图；
图4是本申请提供的一种像素单元的信号处理方法的步骤示意布图；
图5是本申请提供的一种像素单元的子像素的阈值电压变化量的曲线图。
具体实施方式
下面将参照附图更详细地描述本公开的示例性实施方式。虽然附图中显示了本公开的示例性实施方式，然而应当理解，可以以各种形式实现本公开而不应被这里阐述的实施方式所限制。相反，提供这些实施方式是为了能够更透彻地理解本公开，并且能够将本公开的范围完整的传达给本领域的技术人员。
根据本申请的实施方式，提出一种像素单元，如图1所示，包括至少一个 像素100；像素100包括：一个N型主像素101、一个P型主像素102和一个子像素103。
N型主像素101和P型主像素102均用于根据曝光，输出对应曝光强度的电流至子像素103。子像素103在N型主像素101与P型主像素103之间，用于根据电流，生成并输出N型主像素101和P型主像素102的信号差值。
第二方面，本申请提出了一种像素单元，如图2所示，包括相邻的至少一个第一像素201和一个第二像素202；第一像素201包括一个N型主像素101，第二像素202包括一个P型主像素102；第一像素201和第二像素202共用一个子像素103。
N型主像素101和P型主像素102均用于根据曝光，输出对应曝光强度的电流至子像素103。子像素103根据电流，生成并输出N型主像素101和P型主像素102的信号差值。
如图3所示，N型主像素101、P型主像素102和子像素103均包括N型MOS管结构310、埋氧层320和衬底330。
N型MOS管结构310包括：N型MOS管源端区域311、N型MOS管沟道区域312和N型MOS管漏端区域313。
N型MOS管沟道区域312的硅膜Tsi厚度为5纳米至20纳米。N型MOS管源端区域311(Ls)的长度为20纳米至90纳米。N型MOS管漏端区域313(Ld)的长度为20纳米至90纳米。埋氧层320(Tbox)的厚度为10纳米至30纳米。N型MOS管沟道区域313(Lg)的长度为20纳米至100纳米。
N型主像素101中的衬底为N型掺杂阱330a，P型主像素102中的衬底为P型掺杂阱330b。
N型主像素101、P型主像素102和子像素103之间使用浅沟槽隔离340进行隔离。
主像素用于曝光并将光信号转换为电信号，并保存图像原始信号，子像素用于产生并存储图像信号经过计算后的结果。主像素分为N型主像素和P型主像素，N型主像素曝光后信号电压增大，P型主像素曝光后信号电压减小，两种主像素产生的信号耦合至中间的子像素中，在子像素中即可得到两个主像素信号的差值。通过不同的像素排列方式与曝光时序，该结构能够实现像素信号在 空间上和时间上的求差计算。
如图2所示，两个相邻的像素中包含不同类型的主像素，在曝光之后，位于两个主像素之间的子像素上能够得到相邻像素的信号差值。如图1所示，一个像素中包含两种主像素和一个子像素，两个主像素在前后两帧分别曝光，在子像素中能够得到该像素前后两帧的信号差值。空间上和时间上的像素信号差值在许多图像处理算法中都是预先要完成的计算，在该像素结构中差值计算的结果在原始信号产生的同时即可得到，提高了运算效率。
本申请实施方式中的N型主像素、P型主像素和子像素可以采用传统cmos像素或其他新型像素实现。主像素和子像素的排列方式与曝光时序可以根据不同需求进行调整。像素内各项结构参数可以分别调整。能够采用背面光照射形式对主像素进行曝光。通过利用像素的基本结构与光电特性在像素内完成感光、信号存储和即时计算，可以有效地减少图像处理的延迟与资源消耗，提高图像处理效率。
第三方面，本申请提出了一种像素单元的信号处理方法，如图4所示，包括如下步骤：
S101，对像素单元中的N型主像素施加正电压，对P型主像素施加负电压；
S102，对像素单元进行曝光；
S103，N型主像素和P型主像素根据曝光，输出对应曝光强度的电流至子像素；
S104，子像素根据电流，生成并输出N型主像素和P型主像素的信号差值。
本申请实施例的光电信号处理方法主要分为复位、收集和读取三个过程。相应的电极偏置条件如表1所示。
表1
  复位 收集 读取
NMOS管栅极电压 0 0 +Vdd
NMOS管漏极电压 0 0 +Vdd
NMOS管源极电压 0 0 0
N型掺杂区电压 -Vreset +Vdd +Vdd
P型掺杂区电压 +Vreset -Vdd -Vdd
如表1和图3所示，在复位阶段，MOS管的源、漏和栅极电压为零，使MOS管处于关断状态。在PN结的N端(N型掺杂区)施加一个复位脉冲信号Vreset(复位信号)，将PN结正偏，正偏电流向浮置的P型掺杂区注入电荷并将P端(P型掺杂区)电压复位至初始电压N型MOS管源端区域311、N型MOS管沟道区域312和N型MOS管漏端区域313的电压均为零，使N型MOS处于关断状态。P型掺杂阱330b和N型掺杂阱330a分别施加复位脉冲信号+Vreset和-Vreset将阱中电压复位至初始电压。
在收集阶段，P型掺杂阱330b施加负电压-Vdd，N型掺杂阱330a施加正电压+Vdd，在掺杂阱中靠近埋氧层320的区域产生耗尽区。入射光在掺杂阱中产生光生载流子，光生载流子在耗尽区电场作用下被收集。P型掺杂阱330b的耗尽区电场方向向下，收集的是光生电子，光照后P型掺杂阱330b的电势下降。N型掺杂阱330a的耗尽区电场方向向上，收集的是光生空穴，光照后N型掺杂阱330a的电势上升。子像素103位于两种主像素中间，相邻两个主像素的信号会耦合至子像素103中，由于两种主像素光照后信号电压变化方向相反，耦合至子像素103后部分信号相互抵消，从而在子像素103中得到两主像素信号的差值。
在读取阶段，通过埋氧层320上方N型MOS管漏端区域313上的漏电极的电流来读出光信号。N型MOS管漏端区域313上的漏电极及N型MOS管栅氧介质层314上的栅电极均置正电压+Vdd。埋氧层320下方聚集的光生载流子将改变埋氧层320与衬底330界面处的电势，并通过埋氧层320作用于上方N型MOS管沟道区域312，使N型MOS管沟的阈值电压发生变化。对于N型主像素101，光照后阈值电压减小，其漏端(漏端区域313)电流增大。对于P型主像素102，光照后阈值电压增大，其漏端(漏端区域313)电流减小。对于子像素103，N型主像素101的光照强度大于P型主像素102的光照强度时阈值电压减小，其漏端(漏端区域313)电流增大；反之阈值电压增大，其漏端(漏端区域313)电流减小。通过测量主像素中的漏端区域电流可以评估光照强度，通过测量子像素103中的漏端(漏端区域313)电流可以得到两个主像素之间的信号差值。
如图5所示，为两个相邻主像素在不同曝光强度下，子像素103中N型MOS管结构310的阈值电压变化量。不同线上主像素2的光照强度不同，0号线上 主像素2的光照强度是0，1号线上主像素2的光照强度是1，2号线上主像素2的光照强度是2，3号线上主像素2的光照强度是3，4号线上主像素2的光照强度是4，5号线上主像素2的光照强度是5。阈值电压的变化体现的是主像素1与主像素2的光照强度的差值，所以当主像素2的光强增大时，曲线就会向下平移。
本申请实施方式提出的主像素与子像素相结合的图像传感与计算一体化的像素基本结构，通过不同类型主像素信号耦合产生计算结果的像素工作机理，利用像素基本特性实现图像的高效预处理。
本申请的实施方式中，通过在两个主像素之间增加子像素，子像素根据两个主像素发送的电流，生成并输出N型主像素和P型主像素的信号差值，能够直接对接收到的信号进行高效处理，减小输出的数据量。由于不需要增加电路，因此不会因为复杂的电路导致像素面积增加。本申请的实施方式中的主像素和子像素均为基本像素结构，在实现计算功能的同时保留了完整的像素结构，避免了牺牲成像质量与像素面积。利用像素的基本物理特性而非功能电路产生计算结果，计算结果与原始信号同时产生，与采用计算电路进行相比没有计算延迟。主像素与子像素中分别保存了图像的原始信息与计算之后的结果，能够在不丢失图像原始信息的前提下产生计算结果。
以上所述，仅为本申请较佳的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到的变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (10)

  1. 一种像素单元，其特征在于，包括至少一个像素；所述像素包括：一个N型主像素、一个P型主像素和一个子像素；
    所述N型主像素和P型主像素均用于根据曝光，输出对应曝光强度的电流至所述子像素；
    所述子像素在所述N型主像素与P型主像素之间，用于根据所述电流，生成并输出N型主像素和P型主像素的信号差值。
  2. 一种像素单元，其特征在于，包括相邻的至少一个第一像素和一个第二像素；所述第一像素包括一个N型主像素，所述第二像素包括一个P型主像素；所述第一像素和第二像素共用一个子像素；
    所述N型主像素和P型主像素均用于根据曝光，输出对应曝光强度的电流至所述子像素；
    所述子像素根据所述电流，生成并输出N型主像素和P型主像素的信号差值。
  3. 如权利要求1或2所述的像素单元，其特征在于，所述N型主像素、P型主像素和子像素均包括N型MOS管结构、埋氧层和衬底。
  4. 如权利要求3所述的像素单元，其特征在于，所述N型MOS管结构包括：N型MOS管源端区域、N型MOS管沟道区域和N型MOS管漏端区域。
  5. 如权利要求4所述的像素单元，其特征在于，所述N型MOS管沟道区域的硅膜厚度为5纳米至20纳米。
  6. 如权利要求4所述的像素单元，其特征在于，所述N型MOS管源端区域和N型MOS管漏端区域的长度为20纳米至90纳米。
  7. 如权利要求3所述的像素单元，其特征在于，所述埋氧层的厚度为10纳米至30纳米。
  8. 如权利要求3所述的像素单元，其特征在于，所述N型主像素中的衬底为N型掺杂阱，所述P型主像素中的衬底为P型掺杂阱。
  9. 如权利要求3所述的像素单元，其特征在于，所述N型主像素、P型主像素和子像素之间使用浅沟槽隔离进行隔离。
  10. 一种像素单元的信号处理方法，其特征在于，使用如权利要求1-9中任一项所述的像素单元，包括如下步骤：
    对像素单元中的N型主像素施加正电压，对P型主像素施加负电压；
    对所述像素单元进行曝光；
    所述N型主像素和P型主像素根据曝光，输出对应曝光强度的电流至所述子像素；
    所述子像素根据所述电流，生成并输出N型主像素和P型主像素的信号差值。
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