WO2022091755A1 - 撮像装置及び電子機器 - Google Patents
撮像装置及び電子機器 Download PDFInfo
- Publication number
- WO2022091755A1 WO2022091755A1 PCT/JP2021/037504 JP2021037504W WO2022091755A1 WO 2022091755 A1 WO2022091755 A1 WO 2022091755A1 JP 2021037504 W JP2021037504 W JP 2021037504W WO 2022091755 A1 WO2022091755 A1 WO 2022091755A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- pixel
- line
- power supply
- exposure
- shutter
- Prior art date
Links
- 238000003384 imaging method Methods 0.000 title claims abstract description 49
- 238000006243 chemical reaction Methods 0.000 claims abstract description 51
- 239000011159 matrix material Substances 0.000 claims abstract description 13
- 238000012546 transfer Methods 0.000 claims description 74
- 230000002194 synthesizing effect Effects 0.000 claims description 6
- 230000009471 action Effects 0.000 abstract description 3
- 238000000034 method Methods 0.000 description 35
- 239000004065 semiconductor Substances 0.000 description 33
- 230000006870 function Effects 0.000 description 26
- 238000001514 detection method Methods 0.000 description 22
- 238000010586 diagram Methods 0.000 description 22
- 238000012545 processing Methods 0.000 description 21
- 230000003321 amplification Effects 0.000 description 16
- 238000003199 nucleic acid amplification method Methods 0.000 description 16
- 238000009792 diffusion process Methods 0.000 description 13
- 238000007667 floating Methods 0.000 description 12
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 11
- 230000000875 corresponding effect Effects 0.000 description 9
- 230000008569 process Effects 0.000 description 9
- 230000003287 optical effect Effects 0.000 description 8
- 230000001276 controlling effect Effects 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 230000007246 mechanism Effects 0.000 description 4
- 230000002093 peripheral effect Effects 0.000 description 4
- 230000008878 coupling Effects 0.000 description 3
- 238000010168 coupling process Methods 0.000 description 3
- 238000005859 coupling reaction Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004044 response Effects 0.000 description 3
- 230000035945 sensitivity Effects 0.000 description 3
- 238000010408 sweeping Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000003705 background correction Methods 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000009434 installation Methods 0.000 description 2
- 238000005259 measurement Methods 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 230000003595 spectral effect Effects 0.000 description 2
- 238000012935 Averaging Methods 0.000 description 1
- 101100205847 Mus musculus Srst gene Proteins 0.000 description 1
- 241001282110 Pagrus major Species 0.000 description 1
- 240000004050 Pentaglottis sempervirens Species 0.000 description 1
- 235000004522 Pentaglottis sempervirens Nutrition 0.000 description 1
- 241000724291 Tobacco streak virus Species 0.000 description 1
- 230000001133 acceleration Effects 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 238000002583 angiography Methods 0.000 description 1
- 230000003796 beauty Effects 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000002485 combustion reaction Methods 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 230000006835 compression Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000012937 correction Methods 0.000 description 1
- 230000002596 correlated effect Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000005401 electroluminescence Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 238000012423 maintenance Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 230000000116 mitigating effect Effects 0.000 description 1
- 238000012544 monitoring process Methods 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000005070 sampling Methods 0.000 description 1
- 210000004761 scalp Anatomy 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 230000002123 temporal effect Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise
- H04N25/61—Noise processing, e.g. detecting, correcting, reducing or removing noise the noise originating only from the lens unit, e.g. flare, shading, vignetting or "cos4"
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/50—Control of the SSIS exposure
- H04N25/57—Control of the dynamic range
- H04N25/58—Control of the dynamic range involving two or more exposures
- H04N25/587—Control of the dynamic range involving two or more exposures acquired sequentially, e.g. using the combination of odd and even image fields
- H04N25/589—Control of the dynamic range involving two or more exposures acquired sequentially, e.g. using the combination of odd and even image fields with different integration times, e.g. short and long exposures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/1462—Coatings
- H01L27/14623—Optical shielding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14643—Photodiode arrays; MOS imagers
- H01L27/14645—Colour imagers
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/50—Control of the SSIS exposure
- H04N25/53—Control of the integration time
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise
- H04N25/617—Noise processing, e.g. detecting, correcting, reducing or removing noise for reducing electromagnetic interference, e.g. clocking noise
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/709—Circuitry for control of the power supply
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
- H04N25/7795—Circuitry for generating timing or clock signals
Definitions
- This disclosure relates to an image pickup device and an electronic device.
- a method of expanding the dynamic range of an image pickup device a method of continuously taking a plurality of images having different exposure times and synthesizing them is known. Specifically, for example, a long-exposure image and a short-exposure image are continuously and individually photographed, the long-exposure image is used for a dark image region, and the long-exposure image becomes overexposed. In such a bright image area, it is a method of generating one image by a composition process using a short exposure image. By synthesizing a plurality of different exposed images in this way, it is possible to obtain an image having a wide dynamic range (HighDynamicRange) without overexposure.
- HighDynamicRange Wide DynamicRange
- the image pickup apparatus having the fine shutter function with no limitation on the exposure time can suppress the occurrence of shading at any shutter timing and any input image.
- the present disclosure discloses an image pickup device capable of suppressing the occurrence of shading at any shutter timing and any input image in order to realize a fine shutter with no limitation on the exposure time, and an electronic device having the image pickup device.
- the purpose is to provide equipment.
- the imaging apparatus of the present disclosure for achieving the above object is 1 Equipped with a shutter function that enables shutter operation at the desired timing within the horizontal synchronization period.
- Pixels including a photoelectric conversion unit are arranged in a matrix, pixel control lines are wired for each pixel row to the matrix pixel arrangement, and a vertical signal is transmitted for each pixel row to a wiring layer different from the wiring layer of the pixel control lines.
- the vertical signal line is shielded by the power line of the low potential side power supply voltage for shielding.
- the electronic device of the present disclosure for achieving the above object has an image pickup device having the above configuration.
- FIG. 1 is a block diagram schematically showing an outline of a basic configuration of a CMOS image sensor, which is an example of an image pickup apparatus to which the technique according to the present disclosure is applied.
- FIG. 2 is a circuit diagram showing an example of a circuit configuration of pixels in which a part of a circuit element is shared among a plurality of pixels.
- FIG. 3 is a block diagram showing an example of the configuration of a column-parallel analog-to-digital converter mounted on a CMOS image sensor.
- FIG. 4 is an exploded perspective view schematically showing an outline of a laminated semiconductor chip structure of a CMOS image sensor.
- 5A and 5B are explanatory views of an example of pixel arrangement in the pixel array unit.
- FIG. 1 is a block diagram schematically showing an outline of a basic configuration of a CMOS image sensor, which is an example of an image pickup apparatus to which the technique according to the present disclosure is applied.
- FIG. 2 is a circuit diagram showing an example of a
- FIG. 6 is a timing chart for explaining the shutter timing and the read timing at the time of increasing the dynamic range.
- FIG. 7 is a timing chart showing the timing relationship of each signal that drives the pixel.
- FIG. 8 is a block diagram schematically showing a circuit configuration example for controlling the timing of the fine shutter.
- FIG. 9A is a timing chart (No. 1) for explaining the timing of the fine shutter, and
- FIG. 9B is a timing chart (No. 2) for explaining the timing of the fine shutter.
- FIG. 10 is a block diagram schematically showing an example of the internal configuration of the shutter address storage unit.
- FIG. 11 is a schematic diagram showing the current pixel layout configuration.
- FIG. 12 is a schematic diagram showing a pixel layout configuration according to the first embodiment.
- FIG. 13 is a schematic diagram showing a pixel layout configuration according to the second embodiment.
- FIG. 14 is a schematic diagram showing a pixel layout configuration according to the third embodiment.
- FIG. 15 is a schematic diagram showing a pixel layout configuration according to the fourth embodiment.
- FIG. 16 is a diagram showing an application example of the technique according to the present disclosure.
- FIG. 17 is a block diagram showing an outline of a configuration example of an imaging system which is an example of the electronic device of the present disclosure.
- FIG. 18 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile control system to which the technique according to the present disclosure can be applied.
- FIG. 19 is a diagram showing an example of an installation position of an image pickup unit in a mobile control system.
- a wide dynamic range image is generated by capturing a plurality of images having different exposure times and combining the plurality of images to generate one image. It can be configured to have a function.
- a long-exposure image having a relatively long exposure time and a short exposure time having a relatively short exposure time are used for a plurality of images having different exposure times. It can be configured as a time-exposure image. Further, the exposure time at the time of imaging the long-exposure image and the short-exposure image can be individually adjusted by using the shutter function capable of shutter operation at a desired timing within one horizontal synchronization period. can.
- the existing power supply line of the low potential side power supply voltage is parallel to the pixel control line in the wiring layer in which the pixel control line is wired.
- the power supply line of the low potential side power supply voltage for shielding is wired on the opposite side of the existing power supply line of the low potential side power supply voltage in a state of running in parallel with the pixel control line.
- the power supply line of the low potential side power supply voltage for shielding is wired in a wiring layer in which the vertical signal line is wired in a state of running parallel to the vertical signal line, more specifically, the vertical signal line. It can be configured to be wired between the power supply line of the high potential side power supply voltage and the power supply line.
- the vertical signal line is wired in a wiring layer different from the wiring layer in which the power supply line of the high potential side power supply voltage is wired.
- the power supply line of the low potential side power supply voltage for shielding may be configured to be wired in the wiring layer in which the power supply line of the high potential side power supply voltage is wired.
- the pixel control line when the pixel has a transfer transistor for transferring the charge photoelectrically converted by the photoelectric conversion unit to the charge voltage conversion unit, the pixel control line is used. , It can be configured as a transfer control line for transmitting a drive signal to the transfer transistor. Further, when the pixel has a reset transistor for resetting the charge-voltage conversion unit, the pixel control line may be configured to be a reset control line for transmitting a drive signal to the reset transistor.
- CMOS Complementary Metal Oxide Semiconductor
- a CMOS image sensor is an image sensor made by applying or partially using a CMOS process.
- FIG. 1 is a block diagram showing an outline of a basic configuration of a CMOS image sensor, which is an example of the image pickup apparatus of the present disclosure.
- the CMOS image sensor 1 has a configuration including a pixel array unit 11 and a peripheral circuit unit of the pixel array unit 11.
- the pixel array unit 11 is formed by two-dimensionally arranging pixels (pixel circuits) 20 including a photoelectric conversion unit (light receiving unit) in the row direction and the column direction, that is, in a matrix.
- the row direction means the arrangement direction (so-called horizontal direction) of the pixels 20 in the pixel row
- the column direction means the arrangement direction (so-called vertical direction) of the pixels 20 in the pixel row.
- the peripheral circuit unit of the pixel array unit 11 includes, for example, a row selection unit 12, a constant current source unit 13, an analog-to-digital conversion unit 14, a reference signal generation unit 15, a horizontal transfer scanning unit 16, a signal processing unit 17, and timing. It is composed of a control unit 18 and the like.
- pixel control lines 31 (31 1 to 31 m ) are wired along the row direction (horizontal direction) for each pixel row with respect to the matrix-shaped pixel array. Further, vertical signal lines 32 ( 321 to 32 n ) are wired along the column direction (vertical direction) for each pixel row.
- the pixel control line 31 transmits a drive signal for driving when reading a signal from the pixel 20.
- the pixel control line 31 is shown as one wiring, but the wiring is not limited to one, and the details thereof will be described later.
- One end of the pixel control line 31 is connected to the output end corresponding to each row of the row selection unit 12.
- the row selection unit 12 is composed of a shift register, an address decoder, and the like, and controls the scanning of the pixel row and the address of the pixel row when selecting each pixel 20 of the pixel array unit 11. Although the specific configuration of the row selection unit 12 is not shown, it generally has two scanning systems, a read scanning system and a sweep scanning system.
- the read scanning system selectively scans the pixels 20 of the pixel array unit 11 row by row in order to read the pixel signal from the pixels 20.
- the pixel signal read from the pixel 20 is an analog signal.
- the sweep scanning system performs sweep scanning in advance of the read scan performed by the read scan system by the time of the shutter speed.
- the photoelectric conversion unit is reset by sweeping out unnecessary charges from the photoelectric conversion unit of the pixel 20 in the read row. Then, by sweeping out (resetting) unnecessary charges by this sweeping scanning system, a so-called electronic shutter operation is performed.
- the electronic shutter operation refers to an operation of discarding the optical charge of the photoelectric conversion unit and starting a new exposure (starting the accumulation of the optical charge).
- the constant current source unit 13 includes a current source I composed of, for example, a MOS transistor connected to each of the vertical signal lines 32 1 to 32 n for each pixel row, and the pixel row selectively scanned by the row selection unit 12. A bias current is supplied to each pixel 20 of the above through each of the vertical signal lines 32 1 to 32 n .
- the analog-to-digital conversion unit 14 is composed of a set of a plurality of analog-to-digital converters provided corresponding to the pixel array of the pixel array unit 11 (for example, for each pixel array).
- the analog-to-digital conversion unit 14 is a column-parallel type analog-to-digital conversion unit that converts an analog pixel signal output through each of the vertical signal lines 32 1 to 32 n for each pixel string into a digital signal.
- analog-to-digital converter in the column-parallel analog-to-digital converter 14 for example, a single-slope analog-to-digital converter, which is an example of a reference signal comparison type analog-to-digital converter, can be used.
- analog-to-digital converter is not limited to the single slope type analog-to-digital converter, such as a serial comparison type analog-digital converter and a delta-sigma modulation type ( ⁇ modulation type) analog-digital converter. Can be used.
- the reference signal generation unit 15 is composed of a DA (digital-to-analog) converter, and generates a reference signal of a lamp (RAMP) wave whose level (voltage) monotonically decreases with the passage of time.
- the reference signal of the ramp wave generated by the reference signal generation unit 15 is supplied to the analog-to-digital conversion unit 14 and used as a reference signal at the time of analog-to-digital conversion.
- the horizontal transfer scanning unit 16 is composed of a shift register, an address decoder, and the like, and controls the scanning of the pixel train and the address of the pixel train when reading the signal of each pixel circuit (pixel) 2 of the pixel array unit 11. Under the control of the horizontal transfer scanning unit 16, the pixel signal converted into a digital signal by the analog-digital conversion unit 14 is read out to the horizontal transfer line 19 in units of pixel rows.
- the signal processing unit 17 performs predetermined signal processing on the digital pixel signal supplied through the horizontal transfer line 19 to generate two-dimensional image data. Specifically, the signal processing unit 17 corrects vertical line defects and point defects, clamps signals, performs parallel-serial conversion, compression, coding, addition, averaging, intermittent operation, and the like. Digital signal processing is performed. The signal processing unit 17 outputs the generated image data as an output signal of the CMOS image sensor 1 to a subsequent device.
- the timing control unit 18 generates various timing signals, clock signals, control signals, and the like, and based on these generated signals, the row selection unit 12, the constant current source unit 13, and the analog-digital conversion unit 14, refer to. Drive control of the signal generation unit 15, the horizontal transfer scanning unit 16, the signal processing unit 17, and the like is performed.
- FIG. 2 shows an example of a circuit configuration of a pixel 20 that shares a part of a circuit element between two pixels.
- the pixel 20 has, for example, two photodiodes 21-1 and 21-2 as a photoelectric conversion unit (photoelectric conversion element).
- the circuit configuration of the pixels is shown as the circuit configuration of one pixel 20, but the two photodiodes 21-1 and 21-2 are photoelectric conversions of the two pixels sharing a part of the circuit element. It is a part (photoelectric conversion element).
- Pixel 20 has two transfer transistors 22-1 and 22-2 corresponding to two photodiodes 21-1 and 21-2 .
- the two transfer transistors 22-1 and 22-2 together with the two photodiodes 21-1 and 21-2 constitute two pixels that share a part of the circuit element.
- the pixel 20 has a reset transistor 23, an amplification transistor 24, and a selection transistor 25 in addition to the two photodiodes 21 -1 and 21-2 and the two transfer transistors 22 -1 and 22-2 .
- the circuit configuration is such that the reset transistor 23, the amplification transistor 24, and the selection transistor 25, which are a part of the circuit element, are shared between two pixels including the photodiodes 21-1 and 21-2 , respectively. ..
- the five transistors of the transfer transistor 22-1 , 22-2 , the reset transistor 23, the amplification transistor 24, and the selection transistor 25 include, for example, an N-channel MOS field effect transistor; FET) is used.
- FET field effect transistor
- the combination of the five transistors 22 -1 , 22 ⁇ 2 to 25 exemplified here in the conductive type is only an example, and is not limited to these combinations.
- a plurality of pixel control lines specifically, a transfer control line 311, a transfer control line 312, a reset control line 313, and a selection control line. 314 is commonly wired to each pixel 20 in the same pixel row.
- These plurality of pixel control lines 311 to 314 are connected to the output end corresponding to each pixel row of the row selection unit 12 in pixel row units.
- the line selection unit 12 selects the transfer signal TRG -1 , the transfer signal TRG -2 , the reset signal RST, and the selection control line 311, the transfer control line 312, the reset control line 313, and the selection control line 314.
- the signal SEL is output as appropriate.
- the anode electrode is connected to the power supply line 33 of the low potential side power supply voltage (for example, ground level) VSS , and the received light is charged according to the amount of light. It is photoelectrically converted into a light charge (here, a photoelectron) and the light charge is accumulated.
- the cathode electrodes of the photodiodes 21-1 and 21-2 are electrically connected to the gate electrode of the amplification transistor 24 via the transfer transistors 22-1 and 22-2 .
- the region in which the gate electrode of the amplification transistor 24 is electrically connected is a floating diffusion (floating diffusion region / impurity diffusion region) FD.
- the floating diffusion FD is a charge-voltage conversion unit that converts electric charge into voltage.
- transfer signals TRG -1 and TRG -2 in which a high level (for example, high potential side power supply voltage V DD ) is active are transferred from the row selection unit 12.
- a high level for example, high potential side power supply voltage V DD
- the transfer transistors 22 -1 and 22 -2 are in a conductive state in response to the transfer signals TRG -1 and TRG -2 , and are photoelectrically converted by the photodiodes 21 -1 and 21 -2 , and the photodiode 21-
- the optical charge accumulated in 1 and 21-2 is transferred to the floating diffusion FD.
- the reset transistor 23 is connected between the power supply line 34 of the high potential side power supply voltage V DD and the floating diffusion FD.
- a reset signal RST in which a high level is activated is given to the gate electrode of the reset transistor 23 from the row selection unit 12 through the reset control line 313.
- the reset transistor 23 becomes conductive in response to the reset signal RST, and resets the floating diffusion FD by discarding the charge of the floating diffusion FD to the power supply node of the voltage V DD .
- the gate electrode is connected to the floating diffusion FD, and the drain electrode is connected to the power supply line 34 of the high potential side power supply voltage VDD .
- the amplification transistor 24 serves as an input unit for a source follower that reads out a signal obtained by photoelectric conversion with photodiodes 21-1 and 21-2 . That is, in the amplification transistor 24, the source electrode is connected to the vertical signal line 32 via the selection transistor 25.
- the amplification transistor 24 and the current source I connected to one end of the vertical signal line 32 form a source follower that converts the voltage of the floating diffusion FD into the potential of the vertical signal line 32.
- the drain electrode is connected to the source electrode of the amplification transistor 24, and the source electrode is connected to the vertical signal line 32.
- a selection signal SEL in which a high level is active is given to the gate electrode of the selection transistor 25 from the row selection unit 12 through the selection control line 314.
- the selection transistor 25 enters a conduction state in response to the selection signal SEL, so that the signal output from the amplification transistor 24 is transmitted to the vertical signal line 32 with the pixel 20 in the selection state.
- the circuit configuration of the pixel 20 is an example, and is not limited to the circuit configuration. Specifically, for example, the circuit configuration may be such that the selection transistor 25 is omitted and the amplification transistor 24 has the function of the selection transistor 25, or the number of transistors is increased as necessary. You can also do it.
- FIG. 3 shows an example of the configuration of the column-parallel analog-to-digital conversion unit 14.
- the analog-to-digital conversion unit 14 is composed of a set of a plurality of single-slope analog-digital converters provided corresponding to each of the pixels 20 of the pixel array unit 11, the single in the nth column.
- the slope type analog-to-digital converter 140 will be described as an example.
- the single slope type analog-to-digital converter 140 has a circuit configuration including a comparator 141, a counter circuit 142, and a latch circuit 143.
- the reference signal of the lamp wave generated by the reference signal generation unit 15 is used. Specifically, the reference signal of the lamp wave is given as a reference signal to the comparator 141 provided for each pixel sequence.
- the comparator 141 uses the analog pixel signal read from the pixel 20 as a comparison input and the reference signal of the lamp wave generated by the reference signal generation unit 15 as a reference input, and compares both signals. Then, for example, the comparator 141 has an output in the first state (for example, high level) when the reference signal is larger than the pixel signal, and the output is in the second state (for example) when the reference signal is equal to or less than the pixel signal. , Low level). As a result, the comparator 141 outputs a pulse signal having a pulse width corresponding to the signal level of the pixel signal, specifically, the magnitude of the signal level, as a comparison result.
- the first state for example, high level
- the comparator 141 outputs a pulse signal having a pulse width corresponding to the signal level of the pixel signal, specifically, the magnitude of the signal level, as a comparison result.
- a clock signal CLK is given to the counter circuit 142 from the timing control unit 18 at the same timing as the supply start timing of the reference signal to the comparator 141. Then, the counter circuit 142 measures the period of the pulse width of the output pulse of the comparator 141, that is, the period from the start of the comparison operation to the end of the comparison operation by performing the counting operation in synchronization with the clock signal CLK.
- the measurement result (count value) of the counter circuit 142 becomes a digital value obtained by digitizing an analog pixel signal.
- the latch circuit 143 holds (latch) the digital value which is the count result of the counter circuit 142. Further, the latch circuit 143 takes the difference between the D-phase count value corresponding to the signal level at the time of photoelectric conversion of the pixel 20 and the P-phase count value corresponding to the reset level at the time of resetting the pixel 20. CDS (Correlated Double Sampling) processing, which is an example of noise reduction processing, is performed. Then, under the drive of the horizontal transfer scanning unit 16, the latched digital value is output to the horizontal transfer line 19.
- CDS Correlated Double Sampling
- a digital value is obtained from the time information until the magnitude relationship with the analog pixel signal output from 20 changes.
- the analog-to-digital converter 140 is arranged as the column-parallel analog-to-digital converter 14 in a one-to-one relationship with respect to the pixel sequence. It is also possible to configure the analog-to-digital converter 140 as a unit.
- a flat semiconductor chip structure composed of a single semiconductor chip and a laminated semiconductor chip structure in which a plurality of semiconductor chips are laminated can be exemplified.
- the pixel structure when the substrate surface on the side where the wiring layer is formed is the front surface (front surface), a back surface irradiation type pixel structure that captures the light emitted from the back surface side on the opposite side can also be used.
- a surface-illuminated pixel structure that captures the light emitted from the surface side can also be used.
- FIG. 4 is an exploded perspective view schematically showing an outline of the laminated semiconductor chip structure of the CMOS image sensor 1.
- the laminated semiconductor chip structure according to this example has a structure in which at least two semiconductor chips of the first layer semiconductor chip 41 and the second layer semiconductor chip 42 are laminated.
- the first-layer semiconductor chip 41 is a pixel chip in which a pixel array portion 11 in which pixels 20 including a photodiode 21 are two-dimensionally arranged in a matrix is formed.
- Pads 43 for external connection and power supply are provided at, for example, both left and right ends of the semiconductor chip 41 of the first layer.
- the second layer semiconductor chip 42 includes a row selection unit 12, a constant current source unit 13, an analog-to-digital conversion unit 14, a reference signal generation unit 15, a horizontal transfer scanning unit 16, a signal processing unit 17, and a timing control unit 18. It is a circuit chip in which a circuit portion such as an analog is formed.
- a row selection unit 12, a constant current source unit 13, an analog-to-digital conversion unit 14, a reference signal generation unit 15, a horizontal transfer scanning unit 16, a signal processing unit 17, a timing control unit 18, and the like are shown. Although the arrangement is schematically shown, this arrangement example is an example and is not limited to this arrangement example.
- the pixel array portion 11 formed on the semiconductor chip 41 of the first layer and the peripheral circuit portion formed on the semiconductor chip 42 of the second layer form a Cu—Cu junction provided on both the semiconductor chips 41 and 42. It is electrically connected via junctions 44 and 45 including metal-metal junctions, through silicon vias (Through Silicon Vias: TSVs), microbumps and the like.
- a process suitable for manufacturing the pixel array portion 11 can be applied to the semiconductor chip 41 of the first layer, and the semiconductor chip 42 of the second layer is suitable for manufacturing the circuit portion.
- Process can be applied. This makes it possible to optimize the process in manufacturing the CMOS image sensor 1.
- an advanced process can be applied.
- a two-layer laminated semiconductor chip structure in which the first-layer semiconductor chip 41 and the second-layer semiconductor chip 42 are laminated is given as an example, but the structure is not limited to the two-layer laminated structure. It is also possible to have a laminated structure of three or more layers.
- a total of 4 pixels of 2 horizontal pixels ⁇ 2 vertical pixels is regarded as one unit, and the upper left pixel 20 -1 in the unit is an R pixel that photoelectrically converts light in the red (R) band.
- Pixel 20-2 in the lower left is a G pixel that mainly photoelectrically converts light in the green (G) band
- pixel 20-3 in the upper right is a G pixel that mainly photoelectrically converts light in the green (G) band.
- the lower right pixel 20-4 is mainly a B pixel that photoelectrically converts light in the blue (B) band.
- one unit of the bayer array can be configured.
- the R pixel, the G pixel, and the B pixel function as pixels having spectral sensitivity having characteristics in each color.
- FIG. 5B a total of 4 pixels of 2 horizontal pixels ⁇ 2 vertical pixels is regarded as one unit, and the upper left pixel 20 -1 in the unit is an R pixel, the lower left pixel 20-2, the upper right pixel 20 -3 , and so on. Pixels 20-4 in the lower right are C (colorless) pixels having total color matching spectral sensitivity.
- the C pixel is a pixel having higher sensitivity than the above R pixel, G pixel, and B pixel. Therefore, according to the pixel arrangement example of FIG. 5B provided with C pixels, it is easy to obtain a bright image even in a dark place, for example.
- the pixel arrangement examples shown in FIGS. 5A and 5B are examples, and are not limited to these pixel arrangement examples.
- the C pixel may be arranged on one of the two G pixels.
- a wide dynamic range image can be generated by capturing a plurality of images having different exposure times and combining the plurality of images to generate one image. ..
- the wide dynamic range will be described by taking as an example the case where three images having different exposure times are captured and the three images are combined to generate one image.
- a long exposure time is described as a long exposure
- an image captured by the long exposure is described as a long exposure image.
- a short exposure time is described as a short exposure
- an image captured by the short exposure is described as a short exposure image.
- An exposure time shorter than a long exposure but longer than a short exposure is described as a medium time exposure
- an image captured by the medium time exposure is described as a medium time exposure image.
- the wide dynamic range for example, the long-exposure image, the medium-time exposure image, and the short-time exposure image captured by the long-time exposure, the medium-time exposure, and the short-time exposure are combined.
- This will be described by taking as an example, but the process is not limited to the compositing process of three images. Specifically, for example, it is possible to achieve a wide dynamic range by combining two images captured with two exposure times (long exposure and short exposure) having different exposure times. ..
- imaging is performed by shifting the time. For example, after the long-exposure image is captured, the medium-time exposure image is captured, the medium-time exposure image is captured, and then the short-time exposure image is captured.
- the long-exposure image, the medium-time exposure image, and the short-time exposure image are captured in this order will be described as an example, but the short-time exposure image, the medium-time exposure image, and the long-time exposure image will be described. Imaging may be performed in the order of the exposed images.
- FIG. 5B the example of pixel arrangement shown in FIG. 5B, that is, the case of pixel arrangement in which R pixels and C pixels are arranged, and the pixels are arranged in the vertical direction (vertical direction / column direction).
- This will be described as a shared pixel (see FIG. 2) in which the R pixel and the C pixel are included in one unit pixel and share a part of the circuit.
- R pixel 20 -1 , C pixel 20 -2 , R pixel 20 -3 , C pixel 20 -4 , R pixel 20 -5 , and C pixel 20 -6 are arranged in the vertical direction (vertical direction / column direction). It is a pixel that has been. Further, the C pixel 20-2 and the R pixel 20 -3 are designated as shared pixels, and the C pixel 20 -4 and the R pixel 20 -5 are designated as shared pixels.
- “S” shown in the quadrangle indicates the timing at which the shutter is released, and “R” indicates the timing of reading.
- the shutter is released and the exposure is started for the R pixel 20 -1 and the C pixel 20 -2 .
- the shutter is released and the exposure is started for the R pixel 20 -3 and the C pixel 20 -4 .
- the shutter is released and the exposure is started for the R pixel 20 -5 and the C pixel 20 -6 .
- reading from R pixel 20 -1 and C pixel 20 -2 is started.
- the R pixel 20 -1 and the C pixel 20 -2 are exposed only for the time T 11 from the time t 1 to the time t 4 , and the exposure at this time T 11 is a long exposure.
- the exposure is started from the time t 2
- the reading from the R pixel 20 -3 and the C pixel 20 -4 is started at the time t 5 when the long exposure time T 11 has elapsed.
- the exposure is started from the time t 3
- the reading from the R pixel 20 -5 and the C pixel 20 -6 is started at the time t 6 when the long exposure time T 11 has elapsed.
- imaging in medium time exposure is started.
- the shutter is released and the exposure is started for the R pixel 20 -1 and the C pixel 20 -2 .
- the shutter is released and the exposure is started for the R pixel 20 -3 and the C pixel 20 -4 .
- the shutter is released and the exposure is started for the R pixel 20 -5 and the C pixel 20 -6 .
- reading from R pixel 20 -1 and C pixel 20 -2 is started.
- the R pixel 20 -1 and the C pixel 20 -2 are exposed only for the time T 12 from the time t 6 to the time t 8 , and the exposure at this time T 12 is the medium time exposure.
- the exposure is started from the time t 7
- the reading from the R pixel 20 -3 and the C pixel 20 -4 is started at the time t 10 when the time T 12 of the medium time exposure has elapsed.
- the exposure is started from the time t 3
- the reading from the R pixel 20 -5 and the C pixel 20 -6 is started at the time t 13 when the time T 12 of the medium time exposure has elapsed.
- the imaging in the short exposure is started.
- the shutter is released and the exposure is started for the R pixel 20-1 and the C pixel 20-2 .
- the shutter is released and the exposure is started for the R pixel 20 -3 and the C pixel 20 -4 .
- the shutter is released and the exposure is started for the R pixel 20 -5 and the C pixel 20 -6 .
- reading from R pixel 20 -1 and C pixel 20 -2 is started.
- the R pixel 20 -1 and the C pixel 20 -2 are exposed only for the time T 13 from the time t 9 to the time t 11 , and the exposure at this time T 13 is a short exposure.
- the exposure is started from the time t 13
- the reading from the R pixel 20 -3 and the C pixel 20 -4 is started at the time t 14 when the short exposure time T 13 has elapsed.
- the exposure is started from the time t 15
- the reading from the R pixel 20 -5 and the C pixel 20 -6 is started at the time t 16 when the short exposure time T 13 has elapsed.
- the long-time exposure time T 11 , the medium-time exposure time T 12 , and the short-time exposure time T 13 have the following relationship.
- the shutter of the R pixel 20 -1 is released at the time t 1 . That is, at time t 1 , the exposure is started by outputting the electronic shutter transfer signal CTRL and the electronic shutter reset signal SRST to the R pixel 20 -1 . Then, at time t 1 , when the reading is started, the reset signal RRST at the time of reading becomes the active state.
- the shutter is released within one horizontal synchronization period, and reading is performed within one horizontal synchronization period.
- the exposure time becomes equivalent to one horizontal synchronization period.
- the exposure time becomes equivalent to the two horizontal synchronization periods.
- the exposure time is an integral multiple of one horizontal synchronization period.
- the analog-to-digital conversion unit 14 performs analog-to-digital conversion (AD conversion) on a pixel signal output from each pixel 20 of the selected pixel row via the vertical signal line 32, and this analog-to-digital conversion is performed.
- the period for performing conversion is defined as the AD period.
- the 1AD period is defined as one horizontal synchronization period.
- the exposure time is an integral multiple of the 1AD period.
- the long exposure time T11, the medium time exposure time T12 , and the short time exposure time T13 are set and imaging is performed, these exposures are performed.
- Each time is an integral multiple of the 1AD period. This means that when the timing at which the shutter is released and the timing at which the reading is started are fixed within the 1AD period, the short exposure time T 13 is at least the 1AD period. ..
- a long-exposure image, a medium-time exposure image, and a short-exposure image are combined to generate an image having a wide dynamic range, for example, when an image is taken in a bright place, the composition ratio of the short-exposure image is high. Set high.
- the short-exposure image itself is not an appropriate exposure, for example, if the exposure time is longer than the appropriate exposure time, there is a possibility that the image will be overexposed. In such cases, as a result, it may not be possible to generate an image with an appropriate wide dynamic range.
- the short exposure time T 13 is at least the 1AD period. Even if the short-time exposure time T 13 is longer than the appropriate exposure time, the short-time exposure time T 13 is set to the same time as the 1AD period, and optimum imaging cannot be performed. there is a possibility.
- the short-exposure image has been described as an example, but similarly, in each of the long-exposure and medium-time exposure images, if the exposure time can be set only by an integral multiple of the 1AD period, it is short. As in the case of time-exposure images, there is a possibility that imaging will not be performed with an appropriate exposure time. Further, when the exposure time can be adjusted only in units of 1AD period, only rough settings can be made for the long exposure, medium time exposure, and short exposure settings, and the ratio of these exposure times is set to a desired ratio. It may not be possible. If the ratio of the exposure time of the long exposure, the medium exposure, and the short exposure does not become a desired ratio, the image quality of the combined image may deteriorate.
- the electronic shutter transfer signal CTRL and the electronic shutter reset signal RST can be output at a desired timing within one horizontal synchronization period.
- a plurality of clocks are illustrated to show that they can be output at any timing within one horizontal synchronization period.
- One of the plurality of clocks is the electronic shutter transfer pal signal CTRL and the electronic shutter reset signal RRST.
- the timing of releasing the shutter (that is, performing the shutter operation) can be adjusted at a desired timing in units of one clock within one horizontal synchronization period. Since the timing of releasing the shutter is the timing of the start of exposure, the exposure time can be adjusted in units of one clock within one horizontal synchronization period. In the following description, the description of "release the shutter” can be read as "start of exposure”.
- the 1AD period which is one horizontal synchronization period, is 8 microseconds
- one clock is set to 0.02 microseconds
- the timing at which the shutter is released that is, the timing at which exposure is started
- the exposure time is adjusted in units of 8 microseconds
- the timing at which the shutter is released is variable
- the exposure time is 0. It can be adjusted in units of 02 microseconds.
- the frequency of this clock may be set to a numerical value suitable for the accuracy required for the CMOS image sensor 1.
- circuit configuration example a circuit configuration for controlling the timing of the fine shutter.
- the circuit portion for controlling the timing of the fine shutter can be configured by the address decoder, for example, when the row selection unit 12 is composed of the address decoder.
- FIG. 8 schematically shows an example of a circuit configuration for controlling the timing of the fine shutter.
- the address decoder 120 constituting the row selection unit 12 is provided with a shutter address storage unit 121 and a read address storage unit 122 for each pixel row (line) of the pixel array unit 11.
- the shutter address storage unit 121 stores the addresses of the pixels that release the shutter.
- the read address storage unit 122 stores the addresses of the pixels to be read.
- the shutter address storage unit 121 has a first address storage unit 1211 and a second storage unit 1212.
- the address stored in the first address storage unit 1211 is transferred to and stored in the second storage unit 1212 at a predetermined timing.
- the address stored in the second storage unit 1212 is supplied to the pixel timing drive unit (not shown) in the subsequent stage of the address decoder 120, so that the shutter operation of the pixel 20 specified by the address is performed. ..
- the fine shutter address (hereinafter, may be appropriately referred to as "shutter address”) is managed by the two-stage address storage unit (1211, 1212).
- the shutter operation of the fine shutter is configured to be executed at a desired timing within the 1AD period, which is the 1 horizontal synchronization period.
- the timing chart of FIG. 9A illustrates the timing relationship between the horizontal synchronization signal and the electronic shutter transfer signal.
- the transfer pulse at the time of the electronic shutter is illustrated for the purpose of explaining the timing at which the shutter is released.
- this fine shutter it is possible to control to release the shutter at any timing of time t 21 , time t 22 or time t 23 within the AD period. In other words, it is possible to control the shutter to be released at any timing of the start of the AD period (horizontal synchronization period), the intermediate time, or the final stage.
- the shutter address is decoded at the AD period T 21 , and the shutter is released using the decoded shutter address at the AD period T 22 . Need to keep.
- the shutter address of the pixel 20 that releases the shutter is decoded in a period based on a pulse described later, and the first shutter address storage unit 121 is used. It is stored in the address storage unit 1211.
- the shutter address stored in the first address storage unit 1211 is obtained from the first address storage unit 1211 based on a pulse instructing the transfer of the shutter address from the first address storage unit 1211 to the second address storage unit 1212. It is transferred to the second address storage unit 1212.
- the shutter address decoded in the AD period T 21 is transferred from the first address storage unit 1211 to the second address storage unit 1212 at the time point t 31 before the AD period T 22 in the AD period T 21 . It is stored in the second address storage unit 1212. Then, within the AD period T 22 , the time point t 32 shutter is released based on the shutter address stored in the second address storage unit 1212.
- the AD period T 21 for decoding the shutter address and the AD period T 22 for releasing the shutter based on the shutter address are set to different AD periods, so that the shutter is released at a desired timing of the AD period. Is possible. The shutter can be released even if the desired timing is, for example, earlier in the AD period.
- the AD period T 21 for decoding the shutter address and the AD period T 22 for releasing the shutter based on the shutter address are set as different AD periods.
- the timing for releasing the shutter may be different.
- the AD period in which the decoded address is transferred to the second address storage unit 1212 and the AD period in which the shutter is released based on the shutter address are the same AD period. May be.
- the timing at which the shutter address is transferred from the first address storage unit 1211 to the second address storage unit 1212 is not always the same timing but different timing depending on when the shutter is released within the AD period. May be.
- the shutter address transfer is executed in the AD period before the shutter is released, and the shutter is released after the AD period.
- the transfer of the shutter address may be executed within the same AD period as the AD period when the shutter is released.
- the first address storage unit 1211 and the second address storage unit 1212 can be configured by, for example, a latch.
- the latch becomes a 3-bit latch as shown in FIG.
- the first address storage unit 1211 is composed of a latch 1213 _1 , a latch 1213 _2 , and a latch 1213 _3 .
- the second address storage unit 1212 is composed of a latch 1214 _1 , a latch 1214 _2 , and a latch 1214 _3 .
- latches 1213 _1 and latch 1214 _1 store shutter addresses for long exposures
- latches 1213 _2 and latch 1214 _2 store shutter addresses for medium time exposures
- latches 1213 _3 and latch 1214 _3 It can be configured to store the shutter address for short exposure.
- the internal configuration of the shutter address storage unit 121 is an example, and is not limited to the configuration.
- the first address storage unit 1211 and the second address storage unit 1212 may be configured.
- a 3-bit latch configuration for storing an address in each exposure has been described as an example.
- a 2-bit latch configuration can be used.
- the shutter can be released at a desired timing within the 1AD period (1 horizontal synchronization period), in other words, the exposure can be started, so that the exposure time is not limited. Can perform actions.
- the exposure can be started at a desired timing within the 1AD period, that is, the exposure time is not limited, so that the exposure time can be finely adjusted. Since the exposure time can be adjusted more finely, it is possible to take an image with an appropriate exposure time, so that the image quality of the captured image can be improved.
- a plurality of images having different exposure times for example, a long-exposure image having a relatively long exposure time and a short-exposure image having a relatively short exposure time are continuously and individually photographed to obtain a dark image area.
- a long-exposure image and using a short-exposure image in a bright image area where overexposure occurs in a long-exposure image a wide dynamic range image without overexposure can be obtained. ..
- the fine shutter function in which the exposure time is not limited the exposure time at the time of imaging the long-exposure image and the short-exposure image can be appropriately adjusted individually.
- VSS power line 33 is wired to the second wiring layer (shown by a solid line in the figure) in a parallel running state.
- the third wiring layer shown by a broken line in the figure with the vertical signal line 32 orthogonal to the transfer control line 311, the transfer control line 312, the reset control line 313, and the selection control line 314. Is wired to.
- the problem of shading peculiar to the fine shutter is solved in the CMOS image sensor 1 provided with the shutter function (that is, the fine shutter function) capable of shutter operation at a desired timing within one horizontal synchronization period. , It is possible to suppress the occurrence of shading at any shutter timing and any input image. Specifically, in the embodiment of the present disclosure, by adopting a pixel layout configuration in which the vertical signal line 32 is shielded by the VSS power supply line 33, shading correction is executed regardless of the input image, and shading peculiar to the fine shutter is generated. To suppress.
- the exposure time can be finely adjusted under the fine shutter function that does not limit the exposure time. ..
- the CMOS image sensor 1 having a function of capturing a plurality of images having different exposure times and synthesizing the plurality of images to generate an image having a wide dynamic range
- the plurality of images having different exposure times have different exposure times. Since the exposure time at the time of imaging can be appropriately adjusted, a high-quality captured image can be obtained.
- the first embodiment is an example in which the pixel control line 31 is shielded by a VSS power supply line additionally wired to the second wiring layer.
- FIG. 12 shows a schematic diagram of the pixel layout configuration according to the first embodiment.
- the VSS power supply line 33 runs parallel to the pixel control line 31, that is, the transfer control line 311, the transfer control line 312, the reset control line 313, and the selection control line 314. It is wired to the second wiring layer (shown by a solid line in the figure). Further, in a state where the vertical signal line 32 and the power supply line 34 of the high potential side power supply voltage V DD (hereinafter referred to as “V DD power supply line 34”) are orthogonal to the pixel control line 31 (311 to 314). It is wired to the third wiring layer (shown by a broken line in the figure).
- the two photodiodes 21-1 and 21-2 are described as “PD"
- the two transfer transistors 22-1 and 22-2 are described as “TGR Tr.”
- the reset transistor 23 is described as “TGR Tr.”
- the amplification transistor 24 is described as “AMP Tr.”
- the selection transistor 25 is described as "SEL Tr.”.
- the pixel control lines 31 (311 to 314) are wired to the second wiring layer (shown by a solid line in the figure), and the vertical signal line 32 and the VDD power supply line 34 are wired to the third wiring layer (in the figure). The same applies to the points of wiring (shown by a broken line) in each embodiment described later.
- a shield V is placed on the opposite side of the reset control line 313 running in parallel with the existing VSS power supply line 33 on the opposite side of the VSS power supply line 33.
- the SS power line 35 is additionally wired.
- the transfer control line 311 and the transfer control line 312 are shielded from the transfer control line 311 and the transfer control line 312 running in parallel across the existing VSS power supply line 33.
- the VS SS power line 36 for shielding and the VSS power line 37 for shielding are additionally wired.
- the transfer control line 311 is shielded by the existing VSS power supply line 33 and the VS SS power supply line 36 for shielding, and the transfer control is performed by the existing VSS power supply line 33 and the VS SS power supply line 37 for shielding.
- the wire 312 will be shielded.
- the reset control line 313 is shielded by the existing VSS power supply line 33 and the VS SS power supply line 35 for shielding, and the existing VSS power supply line 33 and the shield are used.
- the transfer control line 311 is shielded by the VSS power supply line 36 of the above, and the transfer control line 312 is shielded by the existing VSS power supply line 33 and the VS SS power supply line 37 for shielding.
- the influence of the transfer control line 311, the transfer control line 312, and the reset control line 313 on the vertical signal line 32 can be reduced, so that the occurrence of shading peculiar to the fine shutter can be suppressed.
- the second embodiment is an example in which a VSS power supply line is additionally wired to the third wiring layer and the vertical signal line 32 is shielded by the VSS power supply line.
- FIG. 13 shows a schematic diagram of the pixel layout configuration according to the second embodiment.
- the VERSS power line 38 for shielding is additionally wired in a state of running in parallel with the vertical signal line 32, and the shield is shielded.
- the vertical signal line 32 is shielded by the VSS power line 38 for use.
- the VS SS power line 38 for shielding is additionally wired between the vertical signal line 32 and the V DD power line 34.
- the VS SS power line 38 for shielding is additionally wired in the third wiring layer, and the vertical signal line 32 is provided by the VSS power line 38 for the shield. Is shielded.
- the influence of the pixel control lines 31 (311 to 314) and the VDD power supply line 34 on the vertical signal line 32 can be reduced, so that the occurrence of shading peculiar to the fine shutter can be suppressed.
- the third embodiment is an example in which the wiring layer of the vertical signal line 32 is raised by one layer from the third wiring layer to the fourth wiring layer.
- FIG. 14 shows a schematic diagram of the pixel layout configuration according to the third embodiment.
- the wiring layer of the vertical signal line 32 is raised by one layer from the wiring layer of the third layer and wired to the wiring layer of the fourth layer (shown by the alternate long and short dash line in the figure). It has become.
- the distance between the vertical signal line 32 and the pixel control lines 31 (311 to 314) can be set larger than when the vertical signal line 32 is wired to the third wiring layer.
- the distance between the vertical signal line 32 and the pixel control line 31 (311 to 314) is increased, so that the VSS due to the coupling at the time of the fine shutter is established. Since the influence of the potential fluctuation of the power supply line 33 on the vertical signal line 32 can be reduced, the occurrence of shading peculiar to the fine shutter can be suppressed.
- the fourth embodiment is a modification of the third embodiment, and is an example in which a VSS power supply line is additionally wired and shielded in the wiring layer of the third layer so as to be located below the vertical signal line 32 of the fourth layer.
- FIG. 15 shows a schematic diagram of the pixel layout configuration according to the fourth embodiment.
- the vertical signal line 32 is wired to the fourth wiring layer (shown by the alternate long and short dash line in the figure) as in the case of the third embodiment, and then the vertical signal line 32 is used.
- the VS SS power line 39 for shielding is additionally wired to the third wiring layer (shown by the broken line in the figure) so as to be located below.
- the vertical signal line 32 is shielded by the shielding VSS power supply line 39.
- the vertical signal line 32 of the wiring layer of the fourth layer is shielded by the VSS power line 39 of the wiring layer for shielding the third layer to be fine. Since the influence of the potential fluctuation of the VSS power line 33 on the vertical signal line 32 due to the coupling at the time of the shutter can be further reduced, the occurrence of shading peculiar to the fine shutter can be further suppressed.
- the technique according to the present disclosure has been described above based on the preferred embodiment, the technique according to the present disclosure is not limited to the embodiment.
- the configuration and structure of the image pickup apparatus described in the above embodiment are examples, and can be changed as appropriate.
- the circuit configuration of the pixel 20 a circuit configuration in which a part of the circuit element is shared between a plurality of pixels (for example, between two pixels) is exemplified, but a part of the circuit element is used. Even if the circuit configuration is not shared among a plurality of pixels, that is, each of the pixels 20 has a reset transistor 23, an amplification transistor 24, and a selection transistor 25 in addition to the photodiode 21 and the transfer transistor 22. good.
- the image pickup apparatus of the present disclosure described above can be used in various devices for sensing light such as visible light, infrared light, ultraviolet light, and X-ray. Specific examples of various devices are listed below.
- Devices that take images for viewing such as digital cameras and portable devices with camera functions.
- Devices used for traffic such as in-vehicle sensors that capture images of the rear, surroundings, and interior of vehicles, surveillance cameras that monitor traveling vehicles and roads, and distance measuring sensors that measure distance between vehicles.
- Equipment used in home appliances such as TVs, refrigerators, and air conditioners to take pictures and operate the equipment according to the gestures ⁇ Endoscopes and devices that perform angiography by receiving infrared light, etc.
- Equipment used for medical and healthcare purposes ⁇ Equipment used for security such as surveillance cameras for crime prevention and cameras for person authentication ⁇ Skin measuring instruments for taking pictures of the skin and taking pictures of the scalp Equipment used for beauty such as microscopes ⁇ Equipment used for sports such as action cameras and wearable cameras for sports applications ⁇ Camera for monitoring the condition of fields and crops, etc.
- Equipment used for agriculture ⁇ Equipment used for medical and healthcare purposes
- Equipment used for security such as surveillance cameras for crime prevention and cameras for person authentication
- Skin measuring instruments for taking pictures of the skin and taking pictures of the scalp Equipment used for beauty such as microscopes
- Equipment used for sports such as action cameras and wearable cameras for sports applications
- Camera for monitoring the condition of fields and crops, etc.
- Equipment used for agriculture ⁇ Equipment used for agriculture
- FIG. 17 is a block diagram showing a configuration example of an imaging system which is an example of the electronic device of the present disclosure.
- the image pickup system 100 includes an image pickup optical system 101 including a lens group and the like, an image pickup unit 102, a DSP (Digital Signal Processor) circuit 103, a frame memory 104, a display device 105, and a recording device 106. , Operation system 107, power supply system 108, and the like.
- the DSP circuit 103, the frame memory 104, the display device 105, the recording device 106, the operation system 107, and the power supply system 108 are connected to each other via the bus line 109.
- the image pickup optical system 101 captures incident light (image light) from the subject and forms an image on the image pickup surface of the image pickup unit 102.
- the image pickup unit 102 converts the amount of incident light imaged on the image pickup surface by the optical system 101 into an electric signal in pixel units and outputs it as a pixel signal.
- the DSP circuit 103 performs general camera signal processing, for example, white balance processing, demosaic processing, gamma correction processing, and the like.
- the frame memory 104 is appropriately used for storing data in the process of signal processing in the DSP circuit 103.
- the display device 105 comprises a panel-type display device such as a liquid crystal display device or an organic EL (electroluminescence) display device, and displays a moving image or a still image captured by the image pickup unit 102.
- the recording device 106 records the moving image or still image captured by the imaging unit 102 on a portable semiconductor memory, an optical disk, a recording medium such as an HDD (Hard Disk Drive), or the like.
- the operation system 107 issues operation commands for various functions of the image pickup apparatus 100 under the operation of the user.
- the power supply system 108 appropriately supplies various power sources that serve as operating power sources for the DSP circuit 103, the frame memory 104, the display device 105, the recording device 106, and the operation system 107 to these supply targets.
- the image pickup apparatus of the present disclosure can be used as the image pickup unit 102.
- the image pickup apparatus of the present disclosure in realizing a fine shutter with no limitation on the exposure time, it is possible to suppress the occurrence of shading at any shutter timing and any input image. Therefore, by using the image pickup apparatus of the present disclosure as the image pickup unit 102, a high-quality image can be obtained.
- the technique according to the present disclosure can be applied to various products.
- the technology according to the present disclosure is any kind of movement such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, a personal mobility, an airplane, a drone, a ship, a robot, a construction machine, and an agricultural machine (tractor). It may be realized as an image pickup device mounted on a body.
- FIG. 18 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile control system to which the technique according to the present disclosure can be applied.
- the vehicle control system 12000 includes a plurality of electronic control units connected via the communication network 12001.
- the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside information detection unit 12030, an in-vehicle information detection unit 12040, and an integrated control unit 12050.
- a microcomputer 12051, an audio image output unit 12052, and an in-vehicle network I / F (interface) 12053 are shown as a functional configuration of the integrated control unit 12050.
- the drive system control unit 12010 controls the operation of the device related to the drive system of the vehicle according to various programs.
- the drive system control unit 12010 has a driving force generator for generating a driving force of a vehicle such as an internal combustion engine or a driving motor, a driving force transmission mechanism for transmitting the driving force to the wheels, and a steering angle of the vehicle. It functions as a control device such as a steering mechanism for adjusting and a braking device for generating braking force of the vehicle.
- the body system control unit 12020 controls the operation of various devices mounted on the vehicle body according to various programs.
- the body system control unit 12020 functions as a keyless entry system, a smart key system, a power window device, or a control device for various lamps such as headlamps, back lamps, brake lamps, turn signals or fog lamps.
- the body system control unit 12020 may be input with radio waves transmitted from a portable device that substitutes for the key or signals of various switches.
- the body system control unit 12020 receives inputs of these radio waves or signals and controls a vehicle door lock device, a power window device, a lamp, and the like.
- the vehicle outside information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000.
- the image pickup unit 12031 is connected to the vehicle outside information detection unit 12030.
- the vehicle outside information detection unit 12030 causes the image pickup unit 12031 to capture an image of the outside of the vehicle and receives the captured image.
- the vehicle outside information detection unit 12030 may perform object detection processing or distance detection processing such as a person, a vehicle, an obstacle, a sign, or a character on the road surface based on the received image.
- the image pickup unit 12031 is an optical sensor that receives light and outputs an electric signal according to the amount of the light received.
- the image pickup unit 12031 can output an electric signal as an image or can output it as distance measurement information. Further, the light received by the image pickup unit 12031 may be visible light or invisible light such as infrared light.
- the in-vehicle information detection unit 12040 detects the in-vehicle information.
- a driver state detection unit 12041 that detects a driver's state is connected to the vehicle interior information detection unit 12040.
- the driver state detection unit 12041 includes, for example, a camera that images the driver, and the in-vehicle information detection unit 12040 determines the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041. It may be calculated, or it may be determined whether the driver has fallen asleep.
- the microcomputer 12051 calculates the control target value of the driving force generator, the steering mechanism, or the braking device based on the information inside and outside the vehicle acquired by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, and the drive system control unit.
- a control command can be output to 12010.
- the microcomputer 12051 realizes ADAS (Advanced Drive Assistance System) functions including vehicle collision avoidance or impact mitigation, follow-up driving based on inter-vehicle distance, vehicle speed maintenance driving, vehicle collision warning, vehicle lane deviation warning, and the like. It is possible to perform cooperative control for the purpose of.
- ADAS Advanced Drive Assistance System
- the microcomputer 12051 controls the driving force generating device, the steering mechanism, the braking device, and the like based on the information around the vehicle acquired by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040. It is possible to perform coordinated control for the purpose of automatic driving that runs autonomously without depending on the operation.
- the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information outside the vehicle acquired by the vehicle outside information detection unit 12030.
- the microcomputer 12051 controls the headlamps according to the position of the preceding vehicle or the oncoming vehicle detected by the outside information detection unit 12030, and performs cooperative control for the purpose of anti-glare such as switching the high beam to the low beam. It can be carried out.
- the audio image output unit 12052 transmits an output signal of at least one of audio and image to an output device capable of visually or audibly notifying information to the passenger or the outside of the vehicle.
- an audio speaker 12061, a display unit 12062, and an instrument panel 12063 are exemplified as output devices.
- the display unit 12062 may include, for example, at least one of an onboard display and a head-up display.
- FIG. 19 is a diagram showing an example of the installation position of the image pickup unit 12031.
- the vehicle 12100 has an imaging unit 12101, 12102, 12103, 12104, 12105 as an imaging unit 12031.
- the image pickup units 12101, 12102, 12103, 12104, 12105 are provided, for example, at positions such as the front nose, side mirrors, rear bumpers, back doors, and the upper part of the windshield in the vehicle interior of the vehicle 12100.
- the image pickup unit 12101 provided on the front nose and the image pickup section 12105 provided on the upper part of the windshield in the vehicle interior mainly acquire an image in front of the vehicle 12100.
- the image pickup units 12102 and 12103 provided in the side mirror mainly acquire images of the side of the vehicle 12100.
- the image pickup unit 12104 provided in the rear bumper or the back door mainly acquires an image of the rear of the vehicle 12100.
- the images in front acquired by the image pickup units 12101 and 12105 are mainly used for detecting a preceding vehicle, a pedestrian, an obstacle, a traffic light, a traffic sign, a lane, or the like.
- FIG. 19 shows an example of the shooting range of the imaging units 12101 to 12104.
- the imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose
- the imaging ranges 12112 and 12113 indicate the imaging range of the imaging units 12102 and 12103 provided on the side mirrors, respectively
- the imaging range 12114 indicates the imaging range.
- the imaging range of the imaging unit 12104 provided on the rear bumper or the back door is shown. For example, by superimposing the image data captured by the image pickup units 12101 to 12104, a bird's-eye view image of the vehicle 12100 can be obtained.
- At least one of the image pickup units 12101 to 12104 may have a function of acquiring distance information.
- at least one of the image pickup units 12101 to 12104 may be a stereo camera composed of a plurality of image pickup devices, or may be an image pickup device having pixels for phase difference detection.
- the microcomputer 12051 has a distance to each three-dimensional object within the image pickup range 12111 to 12114 based on the distance information obtained from the image pickup unit 12101 to 12104, and a temporal change of this distance (relative speed with respect to the vehicle 12100). By obtaining can. Further, the microcomputer 12051 can set an inter-vehicle distance to be secured in advance in front of the preceding vehicle, and can perform automatic brake control (including follow-up stop control), automatic acceleration control (including follow-up start control), and the like. In this way, it is possible to perform coordinated control for the purpose of automatic driving or the like that autonomously travels without relying on the driver's operation.
- automatic brake control including follow-up stop control
- automatic acceleration control including follow-up start control
- the microcomputer 12051 converts three-dimensional object data related to a three-dimensional object into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, electric poles, and other three-dimensional objects based on the distance information obtained from the image pickup units 12101 to 12104. It can be classified and extracted and used for automatic avoidance of obstacles. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. Then, the microcomputer 12051 determines the collision risk indicating the risk of collision with each obstacle, and when the collision risk is equal to or higher than the set value and there is a possibility of collision, the microcomputer 12051 via the audio speaker 12061 or the display unit 12062. By outputting an alarm to the driver and performing forced deceleration and avoidance steering via the drive system control unit 12010, driving support for collision avoidance can be provided.
- At least one of the image pickup units 12101 to 12104 may be an infrared camera that detects infrared rays.
- the microcomputer 12051 can recognize a pedestrian by determining whether or not a pedestrian is present in the captured image of the imaging unit 12101 to 12104.
- recognition of a pedestrian is, for example, a procedure for extracting feature points in an image captured by an image pickup unit 12101 to 12104 as an infrared camera, and pattern matching processing is performed on a series of feature points indicating the outline of an object to determine whether or not the pedestrian is a pedestrian. It is done by the procedure to determine.
- the audio image output unit 12052 determines the square contour line for emphasizing the recognized pedestrian.
- the display unit 12062 is controlled so as to superimpose and display. Further, the audio image output unit 12052 may control the display unit 12062 so as to display an icon or the like indicating a pedestrian at a desired position.
- the above is an example of a vehicle control system to which the technique according to the present disclosure can be applied.
- the technique according to the present disclosure can be applied to, for example, the image pickup unit 12031 among the configurations described above. Then, by applying the technique according to the present disclosure to the image pickup unit 12031 or the like, it is possible to suppress the occurrence of shading at any shutter timing and any input image, so that a high-quality image can be obtained.
- the present disclosure may also have the following configuration.
- Imaging device ⁇ [A-01] 1 It has a shutter function that enables shutter operation at a desired timing within the horizontal synchronization period. Pixels including a photoelectric conversion unit are arranged in a matrix, pixel control lines are wired for each pixel row to the matrix pixel arrangement, and a vertical signal is transmitted for each pixel row to a wiring layer different from the wiring layer of the pixel control lines. In a pixel layout configuration in which a line and a power line having a high potential side power supply voltage are wired, Shield the vertical signal line with a power line with a low potential side power supply voltage for shielding, Imaging device.
- [A-02] The above-mentioned [A-] having a function of generating a wide dynamic range image by capturing a plurality of images having different exposure times and synthesizing the plurality of images to generate one image. 01].
- the plurality of images having different exposure times are a long-exposure image having a relatively long exposure time and a short-time exposure image having a relatively short exposure time.
- [A-04] 1 Using the shutter function capable of shutter operation at a desired timing within the horizontal synchronization period, the exposure time at the time of capturing a long-exposure image and a short-exposure image is individually adjusted.
- the existing power line of the low potential side power supply voltage is wired in parallel with the pixel control line.
- the power line of the low potential side power supply voltage for shielding is wired on the opposite side of the existing power line of the low potential side power supply voltage in a state of running parallel to the pixel control line.
- the image pickup apparatus according to any one of the above [A-01] to the above [A-04].
- the power supply line of the low potential side power supply voltage for shielding is wired in a wiring layer in which the vertical signal line is wired in a state of running parallel to the vertical signal line.
- the image pickup apparatus according to any one of the above [A-01] to the above [A-04].
- the power supply line of the low potential side power supply voltage for shielding is wired between the vertical signal line and the power supply line of the high potential side power supply voltage.
- the vertical signal line is wired in a wiring layer different from the wiring layer in which the power supply line of the high potential side power supply voltage is wired.
- the power line of the low potential side power supply voltage for the shield is wired in the wiring layer to which the power supply line of the high potential side power supply voltage is wired.
- the image pickup apparatus according to any one of the above [A-01] to the above [A-04].
- the [A-09] pixel has a transfer transistor that transfers the charge photoelectrically converted by the photoelectric conversion unit to the charge-voltage conversion unit.
- the pixel control line is a transfer control line that transmits a drive signal to the transfer transistor.
- the imaging apparatus according to any one of the above [A-01] to the above [A-08].
- the [A-10] pixel has a reset transistor that resets the charge-voltage conversion unit.
- the pixel control line is a reset control line that transmits a drive signal to the reset transistor.
- the image pickup apparatus according to the above [A-09].
- ⁇ B. Electronic equipment ⁇ [B-01] 1 It has a shutter function that enables shutter operation at a desired timing within the horizontal synchronization period. Pixels including a photoelectric conversion unit are arranged in a matrix, pixel control lines are wired for each pixel row to the matrix pixel arrangement, and a vertical signal is transmitted for each pixel row to a wiring layer different from the wiring layer of the pixel control lines. In a pixel layout configuration in which a line and a power line having a high potential side power supply voltage are wired, Shield the vertical signal line with a power line with a low potential side power supply voltage for shielding, An electronic device having an image pickup device.
- [B-02] The above-mentioned [B-] having a function of generating a wide dynamic range image by capturing a plurality of images having different exposure times and synthesizing the plurality of images to generate one image.
- the electronic device according to. [B-03] The plurality of images having different exposure times are a long-exposure image having a relatively long exposure time and a short-time exposure image having a relatively short exposure time.
- [B-04] 1 Using the shutter function capable of shutter operation at a desired timing within the horizontal synchronization period, the exposure time at the time of capturing a long-exposure image and a short-exposure image is individually adjusted.
- the existing power line of the low potential side power supply voltage is wired in parallel with the pixel control line.
- the power line of the low potential side power supply voltage for shielding is wired on the opposite side of the existing power line of the low potential side power supply voltage in a state of running parallel to the pixel control line.
- the electronic device according to any one of the above [B-01] to the above [B-04].
- the power supply line of the low potential side power supply voltage for shielding is wired in a wiring layer in which the vertical signal line is wired in a state of running parallel to the vertical signal line.
- the power supply line of the low potential side power supply voltage for shielding is wired between the vertical signal line and the power supply line of the high potential side power supply voltage.
- the vertical signal line is wired in a wiring layer different from the wiring layer in which the power supply line of the high potential side power supply voltage is wired.
- the power line of the low potential side power supply voltage for the shield is wired in the wiring layer to which the power supply line of the high potential side power supply voltage is wired.
- the [B-09] pixel has a transfer transistor that transfers the charge photoelectrically converted by the photoelectric conversion unit to the charge-voltage conversion unit.
- the pixel control line is a transfer control line that transmits a drive signal to the transfer transistor.
- the [B-10] pixel has a reset transistor that resets the charge-voltage conversion unit.
- the pixel control line is a reset control line that transmits a drive signal to the reset transistor.
- CMOS image sensor 11 ... pixel array unit, 12 ... row selection unit, 13 ... constant current source unit, 14 ... analog-digital conversion unit, 15 ... reference signal generation Unit, 16 ... Horizontal transfer scanning unit, 17 ... Signal processing unit, 18 ... Timing control unit, 19 ... Horizontal transfer line, 20 ... Pixel, 21 (21 -1 , 21 -2 ) ) ... Photodiode (PD), 22 (22 -1 , 22 -2 ) ... Transfer transistor (TRG Tr.), 23 ... Reset transistor (RST Tr.), 24 ... Amplification transistor ( AMP Tr.), 25 ... Selective transistor (SEL Tr.), 31 (31 1 to 31 m ) ...
- Pixel control line, 32 ( 321 to 32 n ) ... Vertical signal line, 33 ... ⁇ Low potential side power supply voltage V SS power supply line, 34 ⁇ ⁇ ⁇ High potential side power supply voltage V DD power supply line, 35 to 39 ⁇ ⁇ ⁇ Low potential side power supply voltage V SS power supply line for shielding, 41 ⁇ ⁇ 1st layer semiconductor chip, 42 ... 2nd layer semiconductor chip, 311 ... transfer control line, 312 ... transfer control line, 313 ... reset control line, 314 ... selection control line
Landscapes
- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Electromagnetism (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Transforming Light Signals Into Electric Signals (AREA)
- Solid State Image Pick-Up Elements (AREA)
Abstract
Description
1水平同期期間内における所望のタイミングでシャッタ動作が可能なシャッタ機能を備えており、
光電変換部を含む画素が行列状に配列され、行列状の画素配列に対し、画素行毎に画素制御線が配線され、画素制御線の配線層と異なる配線層に、画素列毎に垂直信号線及び高電位側電源電圧の電源線が配線されて成る画素レイアウト構成において、
垂直信号線を、シールド用の低電位側電源電圧の電源線によってシールドする。
1.本開示の撮像装置及び電子機器、全般に関する説明
2.本開示に係る技術が適用される撮像装置
2-1.CMOSイメージセンサの構成例
2-2.画素の回路構成例
2-3.アナログ-デジタル変換部の構成例
2-4.半導体チップ構造
2-5.画素の配置例
2-6.広ダイナミックレンジ化について
2-7.ファインシャッタについて
2-8.ファインシャッタ特有のシェーディングの問題について
3.本開示の実施形態
3-1.実施例1
3-2.実施例2
3-3.実施例3
3-4.実施例4
4.変形例
5.応用例
6.本開示に係る技術の適用例
6-1.本開示の電子機器(撮像システムの例)
6-2.移動体への応用例
7.本開示がとることができる構成
本開示の撮像装置及び電子機器にあっては、露光時間が異なる複数の画像を撮像し、これら複数の画像を合成処理して1つの画像を生成することにより、広ダイナミックレンジの画像を生成する機能を備える構成とすることができる。
先ず、本開示に係る技術が適用される撮像装置(即ち、本開示の撮像装置)の基本的な構成について説明する。ここでは、撮像装置として、X-Yアドレス方式の撮像装置の一種であるCMOS(Complementary Metal Oxide Semiconductor)イメージセンサを例に挙げて説明する。CMOSイメージセンサは、CMOSプロセスを応用して、又は、部分的に使用して作製されたイメージセンサである。
図1は、本開示の撮像装置の一例であるCMOSイメージセンサの基本的な構成の概略を示すブロック図である。
ここでは、回路素子の一部を、複数の画素、例えば、2つの画素間で共有する画素20の回路構成を例示する。回路素子の一部を2つの画素間で共有する画素20の回路構成の一例を示す図2に示す。
次に、列並列アナログ-デジタル変換部14の構成例について説明する。列並列アナログ-デジタル変換部14の構成の一例を図3に示す。ここでは、アナログ-デジタル変換部14が、画素アレイ部11の各画素20のそれぞれに対応して設けられた複数のシングルスロープ型アナログ-デジタル変換器の集合から成る場合において、n列目のシングルスロープ型アナログ-デジタル変換器140を例に挙げて説明する。
上記の構成のCMOSイメージセンサ1の半導体チップ構造としては、単一の半導体チップから成る平置型の半導体チップ構造や、複数の半導体チップが積層されて成る積層型の半導体チップ構造を例示することができる。また、画素構造については、配線層が形成される側の基板面を表面(正面)とするとき、その反対側の裏面側から照射される光を取り込む裏面照射型の画素構造とすることもできるし、表面側から照射される光を取り込む表面照射型の画素構造とすることもできる。
画素アレイ部11における画素20の配置例について、図5A及び図5Bを参照して説明する。
上記の構成のCMOSイメージセンサ1において、露光時間が異なる複数の画像を撮像し、これら複数の画像を合成処理して1つの画像を生成することにより、広ダイナミックレンジの画像を生成することができる。
T11>T12>T13
長時間露光、中時間露光、及び、短時間露光の設定について粗い設定しか行えないと、という問題に対して、露光時間をより細かく調整できるようにし、適切とされる露光時間を設定できる電子シャッタとして、特許文献1に開示された、露光時間に制約がない、所謂、ファインシャッタの技術がある。以下に、ファインシャッタについて説明する。
続いて、ファインシャッタのタイミングを制御するための回路構成について説明する。ファインシャッタのタイミングを制御するための回路部分については、例えば、行選択部12がアドレスデコーダから成るとき、当該アドレスデコーダによって構成することができる。ファインシャッタのタイミングを制御するための回路構成の一例を図8に模式的に示す。
上述した露光時間に制約がないファインシャッタの場合、ファインシャッタ特有のシェーディングの問題が発生する場合がある。このファインシャッタ特有のシェーディングの問題について、図11に示す現状の画素レイアウト構成を用いて説明する。尚、図11には、2つのフォトダイオード21-1,21-2について「PD」と記し、2つの転送トランジスタ22-1,22-2について「TGR Tr.」と記し、リセットトランジスタ23について「RST Tr.」と記し、増幅トランジスタ24について「AMP Tr.」と記し、選択トランジスタ25について「SEL Tr.」と記している。
本開示の実施形態では、1水平同期期間内における所望のタイミングでシャッタ動作が可能なシャッタ機能(即ち、ファインシャッタ機能)を備えたCMOSイメージセンサ1において、ファインシャッタ特有のシェーディングの問題を解消し、どのようなシャッタタイミングでも、どのような入力画像でもシェーディングの発生を抑制できるようにする。具体的には、本開示の実施形態では、垂直信号線32をVSS電源線33でシールドする画素レイアウト構成とすることによって、入力画像によらないシェーディング補正実行し、ファインシャッタ特有のシェーディングの発生を抑制するようにする。
実施例1は、2層目の配線層に追加配線するVSS電源線で画素制御線31をシールドする例である。実施例1に係る画素レイアウト構成の模式図を図12に示す。
実施例2は、3層目の配線層にVSS電源線を追加配線し、当該VSS電源線で垂直信号線32をシールドする例である。実施例2に係る画素レイアウト構成の模式図を図13に示す。
実施例3は、垂直信号線32の配線層を、3層目の配線層から4層目の配線層へ1層上げる例である。実施例3に係る画素レイアウト構成の模式図を図14に示す。
実施例4は、実施例3の変形例であり、4層目の垂直信号線32の下に位置するように、3層目の配線層にVSS電源線を追加配線してシールドする例である。実施例4に係る画素レイアウト構成の模式図を図15に示す。
以上、本開示に係る技術について、好ましい実施形態に基づき説明したが、本開示に係る技術は当該実施形態に限定されるものではない。上記の実施形態において説明した撮像装置の構成、構造は例示であり、適宜、変更することができる。例えば、上記の実施形態では、画素20の回路構成として、回路素子の一部を、複数の画素間(例えば、2つの画素間)で共有する回路構成を例示したが、回路素子の一部を複数の画素間で共有しない回路構成、即ち、画素20の各々が、フォトダイオード21及び転送トランジスタ22の他に、リセットトランジスタ23、増幅トランジスタ24、及び、選択トランジスタ25を有する回路構成であってもよい。
以上説明した本開示の撮像装置は、例えば図16に示すように、可視光、赤外光、紫外光、X線等の光をセンシングする様々な装置に使用することができる。様々な装置の具体例について以下に列挙する。
・自動停止等の安全運転や、運転者の状態の認識等のために、自動車の前方や後方、周囲、車内等を撮影する車載用センサ、走行車両や道路を監視する監視カメラ、車両間等の測距を行う測距センサ等の、交通の用に供される装置
・ユーザのジェスチャを撮影して、そのジェスチャに従った機器操作を行うために、TVや、冷蔵庫、エアーコンディショナ等の家電に供される装置
・内視鏡や、赤外光の受光による血管撮影を行う装置等の、医療やヘルスケアの用に供される装置
・防犯用途の監視カメラや、人物認証用途のカメラ等の、セキュリティの用に供される装置
・肌を撮影する肌測定器や、頭皮を撮影するマイクロスコープ等の、美容の用に供され装置
・スポーツ用途等向けのアクションカメラやウェアラブルカメラ等の、スポーツの用に供される装置
・畑や作物の状態を監視するためのカメラ等の、農業の用に供される装置
本開示に係る技術は、様々な製品に適用することができる。以下に、より具体的な適用例について説明する。
ここでは、デジタルスチルカメラやビデオカメラ等の撮像システムや、携帯電話機などの撮像機能を有する携帯端末装置や、画像読取部に撮像装置を用いる複写機などの電子機器に適用する場合について説明する。
図17は、本開示の電子機器の一例である撮像システムの構成例を示すブロック図である。図17に示すように、本例に係る撮像システム100は、レンズ群等を含む撮像光学系101、撮像部102、DSP(Digital Signal Processor)回路103、フレームメモリ104、表示装置105、記録装置106、操作系107、及び、電源系108等を有している。そして、DSP回路103、フレームメモリ104、表示装置105、記録装置106、操作系107、及び、電源系108がバスライン109を介して相互に接続された構成となっている。
本開示に係る技術は、様々な製品へ応用することができる。例えば、本開示に係る技術は、自動車、電気自動車、ハイブリッド電気自動車、自動二輪車、自転車、パーソナルモビリティ、飛行機、ドローン、船舶、ロボット、建設機械、農業機械(トラクター)などのいずれかの種類の移動体に搭載される撮像装置として実現されてもよい。
尚、本開示は、以下のような構成をとることもできる。
[A-01]1水平同期期間内における所望のタイミングでシャッタ動作が可能なシャッタ機能を備えており、
光電変換部を含む画素が行列状に配列され、行列状の画素配列に対し、画素行毎に画素制御線が配線され、画素制御線の配線層と異なる配線層に、画素列毎に垂直信号線及び高電位側電源電圧の電源線が配線されて成る画素レイアウト構成において、
垂直信号線を、シールド用の低電位側電源電圧の電源線によってシールドする、
撮像装置。
[A-02]露光時間が異なる複数の画像を撮像し、これら複数の画像を合成処理して1つの画像を生成することにより、広ダイナミックレンジの画像を生成する機能を備える、上記[A-01]に記載の撮像装置。
[A-03]露光時間の異なる複数の画像は、露光時間が相対的に長い長時間露光画像、及び、露光時間が相対的に短い短時間露光画像である、
上記[A-02]に記載の撮像装置。
[A-04]1水平同期期間内における所望のタイミングでシャッタ動作が可能なシャッタ機能を用いて、長時間露光画像及び短時間露光画像の撮像時の露光時間を、それぞれ個別に調整する、
上記[A-03]に記載の撮像装置。
[A-05]画素制御線が配線された配線層には、既存の低電位側電源電圧の電源線が、画素制御線と並走した状態で配線されており、
シールド用の低電位側電源電圧の電源線は、既存の低電位側電源電圧の電源線と反対側に、画素制御線と並走した状態で配線されている、
上記[A-01]乃至上記[A-04]のいずれかに記載の撮像装置。
[A-06]シールド用の低電位側電源電圧の電源線は、垂直信号線が配線された配線層に、垂直信号線と並走した状態で配線されている、
上記[A-01]乃至上記[A-04]のいずれかに記載の撮像装置。
[A-07]シールド用の低電位側電源電圧の電源線は、垂直信号線及び高電位側電源電圧の電源線との間に配線されている、
上記[A-06]に記載の撮像装置。
[A-08]垂直信号線は、高電位側電源電圧の電源線が配線された配線層と異なる配線層に配線されており、
シールド用の低電位側電源電圧の電源線は、高電位側電源電圧の電源線が配線された配線層に配線されている、
上記[A-01]乃至上記[A-04]のいずれかに記載の撮像装置。
[A-09]画素は、光電変換部で光電変換された電荷を電荷電圧変換部に転送する転送トランジスタを有し、
画素制御線は、転送トランジスタに駆動信号を伝送する転送制御線である、
上記[A-01]乃至上記[A-08]のいずれかに記載の撮像装置。
[A-10]画素は、電荷電圧変換部をリセットするリセットトランジスタを有し、
画素制御線は、リセットトランジスタに駆動信号を伝送するリセット制御線である、
上記[A-09]に記載の撮像装置。
[B-01]1水平同期期間内における所望のタイミングでシャッタ動作が可能なシャッタ機能を備えており、
光電変換部を含む画素が行列状に配列され、行列状の画素配列に対し、画素行毎に画素制御線が配線され、画素制御線の配線層と異なる配線層に、画素列毎に垂直信号線及び高電位側電源電圧の電源線が配線されて成る画素レイアウト構成において、
垂直信号線を、シールド用の低電位側電源電圧の電源線によってシールドする、
撮像装置を有する電子機器。
[B-02]露光時間が異なる複数の画像を撮像し、これら複数の画像を合成処理して1つの画像を生成することにより、広ダイナミックレンジの画像を生成する機能を備える、上記[B-01]に記載の電子機器。
[B-03]露光時間の異なる複数の画像は、露光時間が相対的に長い長時間露光画像、及び、露光時間が相対的に短い短時間露光画像である、
上記[B-02]に記載の電子機器。
[B-04]1水平同期期間内における所望のタイミングでシャッタ動作が可能なシャッタ機能を用いて、長時間露光画像及び短時間露光画像の撮像時の露光時間を、それぞれ個別に調整する、
上記[B-03]に記載の電子機器。
[B-05]画素制御線が配線された配線層には、既存の低電位側電源電圧の電源線が、画素制御線と並走した状態で配線されており、
シールド用の低電位側電源電圧の電源線は、既存の低電位側電源電圧の電源線と反対側に、画素制御線と並走した状態で配線されている、
上記[B-01]乃至上記[B-04]のいずれかに記載の電子機器。
[B-06]シールド用の低電位側電源電圧の電源線は、垂直信号線が配線された配線層に、垂直信号線と並走した状態で配線されている、
上記[B-01]乃至上記[B-04]のいずれかに記載の電子機器。
[B-07]シールド用の低電位側電源電圧の電源線は、垂直信号線及び高電位側電源電圧の電源線との間に配線されている、
上記[B-06]に記載の電子機器。
[B-08]垂直信号線は、高電位側電源電圧の電源線が配線された配線層と異なる配線層に配線されており、
シールド用の低電位側電源電圧の電源線は、高電位側電源電圧の電源線が配線された配線層に配線されている、
上記[B-01]乃至上記[B-04]のいずれかに記載の電子機器。
[B-09]画素は、光電変換部で光電変換された電荷を電荷電圧変換部に転送する転送トランジスタを有し、
画素制御線は、転送トランジスタに駆動信号を伝送する転送制御線である、
上記[B-01]乃至上記[B-08]のいずれかに記載の電子機器。
[B-10]画素は、電荷電圧変換部をリセットするリセットトランジスタを有し、
画素制御線は、リセットトランジスタに駆動信号を伝送するリセット制御線である、
上記[B-09]に記載の電子機器。
Claims (11)
- 1水平同期期間内における所望のタイミングでシャッタ動作が可能なシャッタ機能を備えており、
光電変換部を含む画素が行列状に配列され、行列状の画素配列に対し、画素行毎に画素制御線が配線され、画素制御線の配線層と異なる配線層に、画素列毎に垂直信号線及び高電位側電源電圧の電源線が配線されて成る画素レイアウト構成において、
垂直信号線を、シールド用の低電位側電源電圧の電源線によってシールドする、
撮像装置。 - 露光時間が異なる複数の画像を撮像し、これら複数の画像を合成処理して1つの画像を生成することにより、広ダイナミックレンジの画像を生成する機能を備える、
請求項1に記載の撮像装置。 - 露光時間の異なる複数の画像は、露光時間が相対的に長い長時間露光画像、及び、露光時間が相対的に短い短時間露光画像である、
請求項2に記載の撮像装置。 - 1水平同期期間内における所望のタイミングでシャッタ動作が可能なシャッタ機能を用いて、長時間露光画像及び短時間露光画像の撮像時の露光時間を、それぞれ個別に調整する、
請求項3に記載の撮像装置。 - 画素制御線が配線された配線層には、既存の低電位側電源電圧の電源線が、画素制御線と並走した状態で配線されており、
シールド用の低電位側電源電圧の電源線は、既存の低電位側電源電圧の電源線と反対側に、画素制御線と並走した状態で配線されている、
請求項1に記載の撮像装置。 - シールド用の低電位側電源電圧の電源線は、垂直信号線が配線された配線層に、垂直信号線と並走した状態で配線されている、
請求項1に記載の撮像装置。 - シールド用の低電位側電源電圧の電源線は、垂直信号線及び高電位側電源電圧の電源線との間に配線されている、
請求項6に記載の撮像装置。 - 垂直信号線は、高電位側電源電圧の電源線が配線された配線層と異なる配線層に配線されており、
シールド用の低電位側電源電圧の電源線は、高電位側電源電圧の電源線が配線された配線層に配線されている、
請求項1に記載の撮像装置。 - 画素は、光電変換部で光電変換された電荷を電荷電圧変換部に転送する転送トランジスタを有し、
画素制御線は、転送トランジスタに駆動信号を伝送する転送制御線である、
請求項1に記載の撮像装置。 - 画素は、電荷電圧変換部をリセットするリセットトランジスタを有し、
画素制御線は、リセットトランジスタに駆動信号を伝送するリセット制御線である、
請求項9に記載の撮像装置。 - 1水平同期期間内における所望のタイミングでシャッタ動作が可能なシャッタ機能を備えており、
光電変換部を含む画素が行列状に配列され、行列状の画素配列に対し、画素行毎に画素制御線が配線され、画素制御線の配線層と異なる配線層に、画素列毎に垂直信号線及び高電位側電源電圧の電源線が配線されて成る画素レイアウト構成において、
垂直信号線を、シールド用の低電位側電源電圧の電源線によってシールドする、
撮像装置を有する電子機器。
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020237016187A KR20230097059A (ko) | 2020-10-27 | 2021-10-11 | 촬상 장치 및 전자기기 |
DE112021005698.0T DE112021005698T5 (de) | 2020-10-27 | 2021-10-11 | Bildgebungsvorrichtung und elektronische einrichtung |
CN202180071686.1A CN116458167A (zh) | 2020-10-27 | 2021-10-11 | 成像装置和电子设备 |
US18/029,181 US20230370736A1 (en) | 2020-10-27 | 2021-10-11 | Imaging device and electronic apparatus |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2020-179598 | 2020-10-27 | ||
JP2020179598A JP2022070502A (ja) | 2020-10-27 | 2020-10-27 | 撮像装置及び電子機器 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2022091755A1 true WO2022091755A1 (ja) | 2022-05-05 |
Family
ID=81383722
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2021/037504 WO2022091755A1 (ja) | 2020-10-27 | 2021-10-11 | 撮像装置及び電子機器 |
Country Status (6)
Country | Link |
---|---|
US (1) | US20230370736A1 (ja) |
JP (1) | JP2022070502A (ja) |
KR (1) | KR20230097059A (ja) |
CN (1) | CN116458167A (ja) |
DE (1) | DE112021005698T5 (ja) |
WO (1) | WO2022091755A1 (ja) |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2019004382A (ja) * | 2017-06-16 | 2019-01-10 | ソニーセミコンダクタソリューションズ株式会社 | 撮像装置 |
JP2019012752A (ja) * | 2017-06-29 | 2019-01-24 | キヤノン株式会社 | 撮像装置、撮像システム、移動体 |
JP2020107897A (ja) * | 2017-01-19 | 2020-07-09 | ソニーセミコンダクタソリューションズ株式会社 | 受光素子 |
-
2020
- 2020-10-27 JP JP2020179598A patent/JP2022070502A/ja active Pending
-
2021
- 2021-10-11 WO PCT/JP2021/037504 patent/WO2022091755A1/ja active Application Filing
- 2021-10-11 KR KR1020237016187A patent/KR20230097059A/ko unknown
- 2021-10-11 DE DE112021005698.0T patent/DE112021005698T5/de active Pending
- 2021-10-11 US US18/029,181 patent/US20230370736A1/en active Pending
- 2021-10-11 CN CN202180071686.1A patent/CN116458167A/zh active Pending
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2020107897A (ja) * | 2017-01-19 | 2020-07-09 | ソニーセミコンダクタソリューションズ株式会社 | 受光素子 |
JP2019004382A (ja) * | 2017-06-16 | 2019-01-10 | ソニーセミコンダクタソリューションズ株式会社 | 撮像装置 |
JP2019012752A (ja) * | 2017-06-29 | 2019-01-24 | キヤノン株式会社 | 撮像装置、撮像システム、移動体 |
Also Published As
Publication number | Publication date |
---|---|
US20230370736A1 (en) | 2023-11-16 |
KR20230097059A (ko) | 2023-06-30 |
CN116458167A (zh) | 2023-07-18 |
JP2022070502A (ja) | 2022-05-13 |
DE112021005698T5 (de) | 2023-08-24 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US11888004B2 (en) | Imaging apparatus having phase difference detection pixels receiving light transmitted through a same color filter | |
JP7029890B2 (ja) | 撮像素子、撮像素子の制御方法、及び、電子機器 | |
US11082649B2 (en) | Solid-state imaging device with pixels having an in-pixel capacitance | |
JP2019057873A (ja) | 固体撮像素子及び電子機器 | |
CN110383481B (zh) | 固态成像装置和电子设备 | |
WO2019171853A1 (ja) | 撮像装置及び撮像装置の信号処理方法、並びに、電子機器 | |
JP2020088676A (ja) | センサ及び制御方法 | |
JP2022103180A (ja) | 固体撮像装置、及び電子機器 | |
US20230402475A1 (en) | Imaging apparatus and electronic device | |
JP2022078127A (ja) | 撮像素子及び電子機器 | |
WO2018230367A1 (ja) | 撮像装置 | |
TW202103486A (zh) | 固態攝像裝置、電子機器及固態攝像裝置之控制方法 | |
WO2022014412A1 (ja) | 撮像装置及び電子機器 | |
WO2022091755A1 (ja) | 撮像装置及び電子機器 | |
WO2022030207A1 (ja) | 撮像装置及び電子機器 | |
WO2022009530A1 (ja) | 撮像装置及び電子機器 | |
JP2022087529A (ja) | 撮像装置及び電子機器 | |
WO2022118630A1 (ja) | 撮像装置及び電子機器 | |
WO2022201898A1 (ja) | 撮像素子および撮像装置 | |
WO2021157263A1 (ja) | 撮像装置及び電子機器 | |
WO2023132151A1 (ja) | 撮像素子および電子機器 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 21885874 Country of ref document: EP Kind code of ref document: A1 |
|
WWE | Wipo information: entry into national phase |
Ref document number: 202180071686.1 Country of ref document: CN |
|
ENP | Entry into the national phase |
Ref document number: 20237016187 Country of ref document: KR Kind code of ref document: A |
|
122 | Ep: pct application non-entry in european phase |
Ref document number: 21885874 Country of ref document: EP Kind code of ref document: A1 |