WO2022088446A1 - 多线圈耦合式单刀四掷开关及射频集成电路 - Google Patents

多线圈耦合式单刀四掷开关及射频集成电路 Download PDF

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Publication number
WO2022088446A1
WO2022088446A1 PCT/CN2020/138115 CN2020138115W WO2022088446A1 WO 2022088446 A1 WO2022088446 A1 WO 2022088446A1 CN 2020138115 W CN2020138115 W CN 2020138115W WO 2022088446 A1 WO2022088446 A1 WO 2022088446A1
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transistor
port
output port
control
coil
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PCT/CN2020/138115
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English (en)
French (fr)
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李苗
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西安科锐盛创新科技有限公司
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Publication of WO2022088446A1 publication Critical patent/WO2022088446A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H03K17/693—Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/002—Switching arrangements with several input- or output terminals
    • H03K17/007—Switching arrangements with several input- or output terminals with several outputs only

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  • the invention belongs to the field of radio frequency integrated circuits, and in particular relates to a multi-coil coupled single-pole four-throw switch and a radio frequency integrated circuit.
  • the present invention provides a multi-coil coupled single-pole four-throw switch and a radio frequency integrated circuit.
  • the technical problem to be solved by the present invention is realized by the following technical solutions:
  • a multi-coil coupled single-pole four-throw switch provided by an embodiment of the present invention includes:
  • a coupled inductance circuit the coupled inductance circuit includes an inductance coil connected to the input port and each output port respectively, and the coupled inductance circuit is used to isolate the first output port, the second output port, the first output port, and the first output port. three output ports and the fourth output port;
  • the transistor control circuit includes an nth control circuit respectively connected to the first output port, the second output port, the third output port, and the fourth output port, where n corresponds to is one to four; the transistor control circuit selects one output port to realize conduction with the input port based on the level signal of each control circuit, and utilizes the inductance coil connected to each output port, except for the output port The control circuit connected to the remaining output ports configures the load of the output port to realize the load matching of the output port.
  • the inductor coil of the coupled inductor circuit includes:
  • a first inductive coil, a second inductive coil and a third inductive coil the first inductive coil is connected to the input port, and the second inductive coil is connected between the first output port and the second output port and the third inductor coil is connected between the third output port and the fourth output port.
  • the multi-coil coupled single-pole four-throw switch further includes:
  • control port group includes a first control port, a second control port, a third control port and a fourth control port, the first control port is connected to the first control circuit, the second control port The port is connected to the second control circuit, the third control port is connected to the third control circuit, the fourth control port is connected to the fourth control circuit, and the control port group is used for the The transistor control circuit provides the level signal.
  • the nth control circuit includes: an nth transistor, an nth gate bias resistor, and an nth external resistor between the sources of the nth transistor, and the nth gate bias resistor is connected to the Between the gate of the nth transistor and the nth control port, the drain of the nth transistor is connected in parallel with the nth output port, the source of the nth transistor is grounded, and the nth external One end of the resistor is connected to the substrate of the nth transistor, and the other end of the nth external resistor is grounded.
  • the first control port provides a first level signal
  • the second control port, the third control port and the fourth control port provide a second level signal
  • the first transistor switch When turned off, the switches of the second transistor, the third transistor and the fourth transistor are turned on, and the input port and the first output port are turned on.
  • the second control port provides a first level signal
  • the first control port, the third control port and the fourth control port provide a second level signal
  • the second transistor switches When turned off, the first transistor, the third transistor, and the fourth transistor switch are turned on, and the input port and the second output port are turned on.
  • the third control port provides a first level signal
  • the first control port, the second control port and the fourth control port provide a second level signal
  • the third transistor switches When turned off, the first transistor, the second transistor, and the fourth transistor switch are turned on, and the input port and the third output port are turned on.
  • the fourth control port provides a first level signal
  • the first control port, the second control port and the third control port provide a second level signal
  • the first transistor, The second transistor and the third transistor switch are turned on, the fourth transistor switch is turned off, and the input port and the fourth output port are turned on.
  • the method further includes: a bypass capacitor, one end of the bypass capacitor is connected to the first inductor coil, and the other end of the bypass capacitor is grounded.
  • an embodiment of the present invention provides a radio frequency integrated circuit, comprising: the above-mentioned multi-coil coupled single-pole-four-throw switch.
  • the embodiment of the present invention provides a multi-coil coupled single-pole four-throw switch and a radio frequency integrated circuit, which utilizes a coupled inductance circuit to achieve high isolation between ports, and can select an output port based on the level signal of each control circuit , to realize the conduction between the input port and its connection, and to configure the load of the output port by using the inductance coil connected to each output port and the control circuit connected to the other output ports except the output port to realize the load matching of the output port.
  • the load of the output port By changing the load of the output port, the purpose of reducing the insertion loss is achieved, and a miniaturized switch that can be gated between different circuits and satisfies low insertion loss and high isolation is realized.
  • FIG. 1 is a schematic diagram of a circuit structure of a multi-coil coupled single-pole four-throw switch provided by an embodiment of the present invention
  • FIG. 2 is a schematic diagram of a specific structure of a multi-coil coupled single-pole four-throw switch provided by an embodiment of the present invention
  • 3 to 6 are equivalent circuit diagrams of a multi-coil coupled single-pole four-throw switch provided by an embodiment of the present invention under signals of different levels.
  • embodiments of the present invention provide a multi-coil coupled single-pole-four-throw switch and a radio frequency integrated circuit.
  • an embodiment of the present invention provides a multi-coil coupled single-pole, four-throw switch.
  • the multi-coil coupled single-pole four-throw switch is introduced.
  • FIG. 1 is a schematic diagram of a circuit structure of a multi-coil coupled single-pole four-throw switch provided by an embodiment of the present invention, including:
  • the coupled inductor circuit 100 includes an inductor coil connected to the input port P1 and each output port respectively, and the coupled inductor circuit 100 is used to isolate the first output port P2, the second output port P3, the third output port P4 and the first output port P2.
  • a transistor control circuit the transistor control circuit includes an nth control circuit respectively connected to the first output port P2, the second output port P3, the third output port P4, and the fourth output port P5, wherein n corresponds to one to four in turn; the transistor control The circuit selects an output port to realize conduction with the input port based on the level signal of each control circuit, and configures the control circuit using the inductance coil connected to each output port and the control circuits connected to the remaining output ports except the output port. The load of the output port to achieve the load matching of the output port.
  • the coupled inductor circuit 100 can use the inductor coil to isolate the input port P1, the first output port P2, the second output port P3, the third output port P4 and the fourth output port P5, so that the input port P1 can be separated from each other. Isolation between output ports.
  • the transistor control circuit includes a first control circuit 110, a second control circuit 120, a third control circuit 130 and a fourth control circuit 140.
  • the first control circuit 110 is connected to the first output port P2
  • the second control circuit 120 is connected to the second output
  • the port P3 is connected
  • the third control circuit 130 is connected to the third output port P4
  • the fourth control circuit 140 is connected to the fourth output port P5.
  • Each control circuit is configured with a corresponding level signal, and different working states can be realized under different level signals.
  • the embodiment of the present invention can control the working state of each control circuit by configuring the level signal of each control circuit, thereby realizing the conduction between the input port and a certain output port, and realizing the purpose of gating between different circuits. And, after gating a certain output port, use the inductance coil connected to each output port and the control circuit connected to the other output ports except the output port to configure the load of the output port correspondingly to realize the output.
  • the loads of the ports are matched. For different output ports, the configured loads of the output ports in the embodiments of the present invention are different, so that the purpose of reducing the insertion loss of each gating circuit can be achieved.
  • a ⁇ /4 transmission line is usually used for load matching, but it requires a large layout area, which is not conducive to on-chip integration.
  • the inductance coil and the control circuit are used to achieve load matching, so the area can be reduced, which is favorable for on-chip integration and realizes a miniaturized switch.
  • the multi-coil coupled single-pole four-throw switch provided by the embodiment of the present invention can use the coupled inductor circuit to achieve high isolation between ports, and can select an output port based on the level signal of each control circuit to realize the input port and its conduction. and use the inductance coil connected to each output port and the control circuit connected to the other output ports except the output port to configure the load of the output port to realize the load matching of the output port, by changing the output port load, to achieve the purpose of reducing insertion loss, and realize a miniaturized switch that can be gated between different circuits and satisfies low insertion loss and high isolation.
  • FIG. 2 is a multi-coil-coupled single-pole-four-throw switch provided by the embodiment of the present invention. Schematic diagram of the specific structure.
  • the inductor coil of the coupled inductor circuit 100 includes:
  • the multi-coil-coupled single-pole-four-throw switch provided by the embodiment of the present invention further includes: a control port group, where the control port group includes a first control port V1, a second control port V2, a third control port V3 and a fourth control port.
  • Control port V4 the first control port V1 is connected with the first control circuit 110
  • the second control port V2 is connected with the second control circuit 120
  • the third control port V3 is connected with the third control circuit 130
  • the fourth control port V4 is connected with the first control circuit 120.
  • the four control circuits 140 are connected, and the control port group is used to provide level signals for the transistor control circuit.
  • the nth control circuit includes: the nth transistor Mn, the nth gate bias resistor Rn, and the nth external resistor Rsubn between the sources of the nth transistor Mn, and the nth gate bias resistor Rn is connected to the nth gate bias resistor Rn.
  • the drain of the nth transistor Mn is connected in parallel with the nth output port, the source of the nth transistor Mn is grounded, and one end of the nth external resistor Rsub n is connected to the nth transistor
  • the substrate of Mn is connected, and the other end of the nth external resistor Rsub n is grounded.
  • the nth control circuit corresponds to the first control circuit 110 , the second control circuit 120 , the third control circuit 130 and the fourth control circuit 140 .
  • the first control port V1, the second control port V2, the third control port V3 and the fourth control port V4 provide power for the first control circuit 110, the second control circuit 120, the third control circuit 130 and the fourth control circuit 140, respectively. flat signal.
  • the first control circuit 110 includes a first transistor M1, a first gate bias resistor R1, and a first external resistor Rsub1 between the sources of the first transistor M1, and the first gate bias resistor R1 is connected to the first transistor M1. Between the gate and the first control port V1, the drain of the first transistor M1 is connected in parallel with the first output port P2, the source of the first transistor M1 is grounded, and one end of the first external resistor Rsub1 is connected to the substrate of the first transistor M1 connected, and the other end of the first external resistor Rsub1 is grounded.
  • the second control circuit 120 includes a second transistor M2, a second gate bias resistor R2, and a second external resistor Rsub2 between the sources of the second transistor M2, and the second gate bias resistor R2 is connected to the second transistor M2. Between the gate and the second control port V2, the drain of the second transistor M2 is connected in parallel with the second output port P3, the source of the second transistor M2 is grounded, and one end of the second external resistor Rsub2 is connected to the substrate of the second transistor M2 connected, and the other end of the second external resistor Rsub2 is grounded.
  • the third control circuit 130 includes a third transistor M3, a third gate bias resistor R3, and a third external resistor Rsub3 between the sources of the third transistor M3, and the third gate bias resistor R3 is connected to the third transistor M3
  • the drain of the third transistor M3 is connected in parallel with the third output port P4
  • the source of the third transistor M3 is grounded, and one end of the third external resistor Rsub3 is connected to the lining of the third transistor M3.
  • the bottom is connected, and the other end of the third external resistor Rsub3 is grounded.
  • the fourth control circuit 140 includes a fourth transistor M4, a fourth gate bias resistor R4, and a fourth external resistor Rsub4 between the sources of the fourth transistor M4, and the fourth gate bias resistor R4 is connected to the fourth transistor M4.
  • the drain of the fourth transistor M4 is connected in parallel with the fourth output port P5, the source of the fourth transistor M4 is grounded, and one end of the fourth external resistor Rsub4 is connected to the lining of the fourth transistor M4. The bottom is connected, and the other end of the fourth external resistor Rsub4 is grounded.
  • first gate bias resistor R1, the second gate bias resistor R2, the third gate bias resistor R3 and the fourth gate bias resistor R4 are used to improve the switching RF signal and level signal. of isolation.
  • the first external resistor Rsub1, the second external resistor Rsub2, the third external resistor Rsub3, and the fourth external resistor Rsub4 are used to reduce the resistance of the substrate of the transistor connected thereto, thereby reducing insertion loss.
  • the multi-coil coupled single-pole-four-throw switch provided by the embodiment of the present invention further includes: a bypass capacitor C1, one end of the bypass capacitor C1 is connected to the first inductor coil L1, and the other end of the bypass capacitor C1 is grounded.
  • bypass capacitor can bypass the high-frequency components in the AC signal mixed with high-frequency current and low-frequency current, and can filter the high-frequency noise in the signal of the input port P1 as a filter. Object, filter out the high-frequency clutter carried by the preamp.
  • 3 to 6 are equivalent circuit diagrams of a multi-coil coupled single-pole four-throw switch provided by an embodiment of the present invention under signals of different levels.
  • FIG. 3 is an equivalent circuit diagram when a first level signal is provided for the first control circuit.
  • the first control port V1 provides a first level signal
  • the second control port V2 the third control port V3 and the fourth control port V4 provide a second level signal
  • the switch of the first transistor M1 is turned off
  • the The switches of the second transistor M2, the third transistor M3 and the fourth transistor M4 are turned on, and the input port P1 and the first output port P2 are turned on.
  • the level signal is a signal represented by a level value, including a high level "1" and a low level "0".
  • the first level signal is a low level, such as 0; the second level signal is a high level, such as 1. It can be understood with reference to FIG. 3 that since the first control port V1 is provided with a low level, the level signal of the first control circuit 110 is also a low level, because the second control port V2, the third control port V3 and the fourth control The port V4 provides a high level, so the level signals of the second control circuit 120 , the third control point circuit 130 and the fourth control circuit 140 are also at a high level. Those skilled in the art can understand that, according to the working principle of the transistor, the switch of the first transistor M1 is turned off.
  • the first transistor M1 is equivalent to the transistor turn-off capacitor Coff1, the second transistor M2, the third transistor M3 and the fourth transistor M1.
  • the switch of the transistor M4 is turned on.
  • the second transistor M2 is equivalent to the transistor on-resistance Ron2
  • the third transistor M3 is equivalent to the transistor on-resistance Ron3
  • the fourth transistor M4 is equivalent to the transistor on-resistance Ron4. It includes the parasitic capacitance of the second transistor M2, the parasitic capacitance of the third transistor M3 and the parasitic capacitance of the fourth transistor M4.
  • the transistor turn-off capacitor Coff1 is equivalent to the bypass capacitor of the first output port P2, so that the level signal is transmitted from the input port P1 to the first output port P2;
  • the transistor on-resistance Ron2 is equivalent to the load of the second output port P3, and the transistor on-resistance Ron2 short-circuits the second output port P3 to ground, so the input port P1 is disconnected from the second output port P3;
  • the transistor on-resistance Ron3 is equivalent to the third
  • the transistor on-resistance Ron3 short-circuits the third output port P4 to ground, so the input port P1 is disconnected from the third output port P4;
  • the transistor on-resistance Ron4 is equivalent to the load of the fourth output port P5,
  • the transistor on-resistance Ron4 short-circuits the fourth output port P5 to ground, so the input port P1 is disconnected from the fourth output port P5.
  • the second inductance coil L2, the third inductance coil L3, the parasitic capacitance of the second transistor M2, the parasitic capacitance of the third transistor M3 and the parasitic capacitance of the fourth transistor M4 serve as loads of the first output port P2.
  • FIG. 4 is an equivalent circuit diagram when a first level signal is provided for the second control circuit.
  • the second control port V2 provides the first level signal
  • the first control port V1 the third control port V3 and the fourth control port V4 provide the second level signal
  • the switch of the second transistor M2 is turned off
  • the first control port V1, the third control port V3 and the fourth control port V4 provide the second level signal.
  • a transistor M1, a third transistor M3 and a fourth transistor M4 are switched on, and the input port P1 and the second output port P3 are turned on.
  • the first level signal is a low level, such as 0; the second level signal is a high level, such as 1. 4 , since the second control port V2 is provided with a low level, the level signal of the second control circuit 120 is also a low level, because the first control port V1 , the third control port V3 and the fourth control The port V4 provides a high level, so the level signals of the first control circuit 110 , the third control point circuit 130 and the fourth control circuit 140 are also at a high level.
  • the switch of the second transistor M2 is turned off.
  • the second transistor M2 is equivalent to the transistor turn-off capacitor Coff2, the first transistor M1, the third transistor M3 and the fourth transistor M2.
  • the switch of the transistor M4 is turned on.
  • the first transistor M1 is equivalent to the transistor on-resistance Ron1
  • the third transistor M3 is equivalent to the transistor on-resistance Ron3
  • the fourth transistor M4 is equivalent to the transistor on-resistance Ron4. It includes the parasitic capacitance of the first transistor M1, the parasitic capacitance of the third transistor M3 and the parasitic capacitance of the fourth transistor M4.
  • the transistor off capacitor Coff2 is equivalent to the bypass capacitor of the second output port P3, so that the level signal is transmitted from the input port P1 to the second output port P3;
  • the transistor on-resistance Ron1 is equivalent to the first output port P2 load, the transistor on-resistance Ron1 short-circuits the first output port P2 to ground, so the input port P1 is disconnected from the first output port P2;
  • the transistor on-resistance Ron3 is equivalent to the load of the third output port P4, and the transistor is on The resistor Ron3 short-circuits the third output port P4 to the ground, so the input port P1 is disconnected from the third output port P4;
  • the transistor on-resistance Ron4 is equivalent to the load of the fourth output port P5, and the transistor on-resistance Ron4 turns the fourth output The port P5 is shorted to ground, so the input port P1 is disconnected from the fourth output port P5.
  • the second inductance coil L2, the third inductance coil L3, the parasitic capacitance of the first transistor M1, the parasitic capacitance of the third transistor M3, and the parasitic capacitance of the fourth transistor M4 serve as loads of the second output port P3.
  • FIG. 5 is an equivalent circuit diagram when a first level signal is provided for the third control circuit.
  • the third control port V3 provides the first level signal
  • the first control port V1, the second control port V2 and the fourth control port V4 provide the second level signal
  • the switch of the third transistor M3 is turned off
  • the first control port V1, the second control port V2 and the fourth control port V4 provide the second level signal.
  • a transistor M1, a second transistor M2 and a fourth transistor M4 are switched on, and the input port P1 and the third output port P4 are turned on.
  • the first level signal is a low level, such as 0; the second level signal is a high level, such as 1. It can be understood with reference to FIG. 5 that since a low level is provided for the third control port V3, the level signal of the third control point circuit 130 is also a low level.
  • the control port V4 provides a high level, so the level signals of the first control circuit 110 , the second control circuit 120 and the fourth control circuit 140 are also at a high level.
  • the switch of the third transistor M3 is turned off. At this time, the third transistor M3 is equivalent to the transistor turn-off capacitor Coff3.
  • the first transistor M1, the second transistor M2 and the fourth transistor M3 The switch of the transistor M4 is turned on. At this time, the first transistor M1 is equivalent to the transistor on-resistance Ron1, the second transistor M2 is equivalent to the transistor on-resistance Ron2, and the fourth transistor M4 is equivalent to the transistor on-resistance Ron4. It includes the parasitic capacitance of the first transistor M1, the parasitic capacitance of the second transistor M2 and the parasitic capacitance of the fourth transistor M4.
  • the transistor turn-off capacitor Coff3 is equivalent to the bypass capacitor of the third output port P4, so that the level signal is transmitted from the input port P1 to the third output port P4;
  • the transistor on-resistance Ron1 is equivalent to the first output port P2 load, the transistor on-resistance Ron1 short-circuits the first output port P2 to ground, so the input port P1 is disconnected from the first output port P2;
  • the transistor on-resistance Ron2 is equivalent to the load of the second output port P3, and the transistor is on The resistor Ron2 short-circuits the second output port P3 to ground, so the input port P1 is disconnected from the second output port P3;
  • the transistor on-resistance Ron4 is equivalent to the load of the fourth output port P5, and the transistor on-resistance Ron4 turns the fourth output The port P5 is shorted to ground, so the input port P1 is disconnected from the fourth output port P5.
  • the second inductor coil L2, the third inductor coil L3, the parasitic capacitance of the first transistor M1, the parasitic capacitance of the second transistor M2, and the parasitic capacitance of the fourth transistor M4 serve as loads of the third output port P4.
  • FIG. 6 is an equivalent circuit diagram when a first level signal is provided for the fourth control circuit.
  • the fourth control port V4 provides the first level signal
  • the first control port V1 the second control port V2 and the third control port V3 provide the second level signal
  • the switch of the third transistor M3 is turned on
  • the switch of the fourth transistor M4 is turned off
  • the input port P1 and the fourth output port P5 are turned on.
  • the first level signal is a low level, such as 0; the second level signal is a high level, such as 1.
  • the level signal of the fourth control circuit 140 is also at a low level, because the first control port V1 , the second control port V2 and the third control The port V3 provides a high level, so the level signals of the first control circuit 110 , the second control circuit 120 and the third control point circuit 130 are also at a high level.
  • the switch of the fourth transistor M4 is turned off.
  • the fourth transistor M4 is equivalent to the transistor turn-off capacitor Coff4, the first transistor M1, the second transistor M2 and the third transistor M4.
  • the switch of the transistor M is turned on.
  • the first transistor M1 is equivalent to the transistor on-resistance Ron1
  • the second transistor M2 is equivalent to the transistor on-resistance Ron2
  • the third transistor M3 is equivalent to the transistor on-resistance Ron3. It includes the parasitic capacitance of the first transistor M1, the parasitic capacitance of the second transistor M2 and the parasitic capacitance of the third transistor M3.
  • the transistor off capacitor Coff4 is equivalent to the bypass capacitor of the fourth output port P5, so that the level signal is transmitted from the input port P1 to the fourth output port P5;
  • the transistor on-resistance Ron1 is equivalent to the first output port P2 load, the transistor on-resistance Ron1 short-circuits the first output port P2 to ground, so the input port P1 is disconnected from the first output port P2;
  • the transistor on-resistance Ron2 is equivalent to the load of the second output port P3, and the transistor is on The resistor Ron2 short-circuits the second output port P3 to ground, so the input port P1 is disconnected from the second output port P3;
  • the transistor on-resistance Ron3 is equivalent to the load of the third output port P4, and the transistor on-resistance Ron3 connects the third output The port P4 is shorted to ground, so the input port P1 is disconnected from the third output port P4.
  • the second inductance coil L2, the third inductance coil L3, the parasitic capacitance of the first transistor M1, the parasitic capacitance of the second transistor M2, and the parasitic capacitance of the third transistor M3 serve as loads of the fourth output port P5.
  • the third transistor M3 is composed of 6 groups of field effect transistors, and each group The field effect transistor includes 64 channels, and the channel width is 1 ⁇ m and the channel length is 40nm;
  • the fourth transistor M4 is composed of 6 groups of field effect transistors, and each group of field effect transistors includes 64 channels, and the channel length is 40nm.
  • the channel width is 1 ⁇ m and the channel length is 40 nm.
  • the resistance values of the first gate bias resistor R1 , the second gate bias resistor R2 , the third gate bias resistor R3 and the fourth gate bias resistor R4 are all 3K ⁇ .
  • the resistance values of the first external resistor Rsub1, the second external resistor Rsub2, the third external resistor Rsub3 and the fourth external resistor Rsub4 are all 6K ⁇ , and the capacitance of the bypass capacitor C1 is 40fF.
  • the coil-coupled single-pole-four-throw switch can realize: the application frequency band includes 40GHz to 55GHz. In the application frequency band, the mismatch of the insertion loss between the input port P1 and each output port is less than 0.24dB, the insertion loss between the input port P1 and each output port is less than 2.2dB, and the isolation between the input port P1 and each output port is greater than 23.2dB .
  • the structure parameters in the coil-coupled SP4-throw switch provided by the embodiment of the present invention are not limited to this, and those skilled in the art can think of using structures with different parameters to achieve the same effect according to different usage conditions.
  • the principle that transistors are turned on or off at different levels is used to control the level signals of the control port group, so that the level signal provided by the transistor of one control circuit and the level signal provided by the transistors of the other control circuits
  • the level signals are opposite, so the switching of the output ports can be realized.
  • by switching the load of the output port it can achieve lower insertion loss when the input port and different output ports are conducting.
  • the multi-coil-coupled single-pole-four-throw switch provided by the embodiment of the present invention can improve the switching RF signal and the switching frequency through the gate bias resistance of the transistor control circuit.
  • the isolation of the level signal can reduce the resistance of the substrate of the transistor through an external resistor to achieve the purpose of reducing the insertion loss, further ensuring that the single-pole four-throw switch has a small insertion loss and a high degree of The performance of isolation can achieve a good match between the input port of the millimeter-wave integrated circuit switch and the output of the four ports.
  • an embodiment of the present invention provides a radio frequency integrated circuit, including: the above-mentioned multi-coil coupled single-pole-four-throw switch.
  • the multi-coil coupled single-pole four-throw switch can be packaged as a radio frequency integrated circuit, and the radio frequency integrated circuit can be applied to radio frequency front-end equipment, such as: low noise amplifiers, filters, attenuators and phase shifters Wait.
  • the principle that transistors are turned on or off at different levels is used to control the level signals of the control port group, so that the level signal provided by the transistor of one control circuit and the level signal provided by the transistors of the other control circuits
  • the level signals are opposite, so the switching of the output ports can be realized.
  • the gate bias resistance of the transistor control circuit can improve the isolation of the switching RF signal and the level signal, and the resistance of the substrate of the transistor can be reduced by an external resistance, so as to reduce the insertion loss and further ensure the single pole.
  • the four-throw switch has lower insertion loss and higher isolation performance under different working conditions, and can achieve a good match between the input port of the millimeter-wave integrated circuit switch and the output of the four ports.

Abstract

一种多线圈耦合式单刀四掷开关，包括：输入端口(P1)、第一输出端口(P2)、第二输出端口(P3)、第三输出端口(P4)以及第四输出端口(P5)；耦合电感电路，包括与输入端口(P1)以及各个输出端口分别连接的电感线圈；晶体管控制电路，包括分别与第一输出端口(P2)、第二输出端口(P3)、第三输出端口(P4)、第四输出端口(P5)连接的第n控制电路，其中n依次对应为一至四；晶体管控制电路基于各个控制电路的电平信号，选择一个输出端口实现与输入端口(P1)导通，以及利用与各个输出端口连接的电感线圈、除该输出端口之外的其余输出端口所连接的控制电路，配置该输出端口的负载。上述多线圈耦合式单刀四掷开关能够满足在不同电路之间进行选通且低插入损耗、高隔离度以及小型化。

Description

多线圈耦合式单刀四掷开关及射频集成电路 技术领域
本发明属于射频集成电路领域，具体涉及一种多线圈耦合式单刀四掷开关及射频集成电路。
背景技术
随着毫米波集成电路的发展，在毫米波集成电路中，开关器件常应用于射频收发机中，用于控制接收和发射状态的切换。插入损耗、隔离度以及线性度是衡量射频集成开关的重要参数，通常需要设计出低插入损耗且高隔离度的开关。
然而，现如今对毫米波集成开关小型化要求越来越高，如何实现一种能够在不同电路之间进行选通且满足低插入损耗、高隔离度的开关，是本领域内亟待解决的问题。
发明内容
为了解决现有技术中存在的上述问题，本发明提供了一种多线圈耦合式单刀四掷开关及射频集成电路。本发明要解决的技术问题通过以下技术方案实现：
第一方面，本发明实施例提供的一种多线圈耦合式单刀四掷开关，包括：
输入端口、第一输出端口、第二输出端口、第三输出端口以及第四输出端口；
耦合电感电路，所述耦合电感电路包括与所述输入端口以及各个输出 端口分别连接的电感线圈，所述耦合电感电路用于隔离所述第一输出端口、所述第二输出端口、所述第三输出端口以及所述第四输出端口；
晶体管控制电路，所述晶体管控制电路包括分别与所述第一输出端口、所述第二输出端口、所述第三输出端口、所述第四输出端口连接的第n控制电路，其中n依次对应为一至四；所述晶体管控制电路基于各个控制电路的电平信号，选择一个输出端口实现与所述输入端口导通，以及利用与各个输出端口连接的所述电感线圈、除该输出端口之外的其余输出端口所连接的控制电路，配置该输出端口的负载，以实现该输出端口的负载匹配。
可选的，所述耦合电感电路的所述电感线圈，包括：
第一电感线圈、第二电感线圈以及第三电感线圈，所述第一电感线圈与所述输入端口连接，所述第二电感线圈连接在所述第一输出端口与所述第二输出端口之间，所述第三电感线圈连接在所述第三输出端口与所述第四输出端口之间。
可选的，所述多线圈耦合式单刀四掷开关还包括：
控制端口组，所述控制端口组包括第一控制端口，第二控制端口，第三控制端口以及第四控制端口，所述第一控制端口与所述第一控制电路连接，所述第二控制端口与所述第二控制电路连接，所述第三控制端口与所述第三控制电路连接，所述第四控制端口与所述第四控制电路连接，所述控制端口组用于为所述晶体管控制电路提供电平信号。
可选的，所述第n控制电路包括：第n晶体管、第n栅极偏置电阻以及所述第n晶体管的源极间的第n外接电阻，所述第n栅极偏置电阻连接在所述第n晶体管的栅极与所述第n控制端口之间，所述第n晶体管的漏极与所述第n输出端口并联，所述第n晶体管的源极接地，所述第n外接 电阻的一端与所述第n晶体管的衬底连接，所述第n外接电阻的另一端接地。
可选的，所述第一控制端口提供第一电平信号，所述第二控制端口、所述第三控制端口以及所述第四控制端口提供第二电平信号，所述第一晶体管开关断开，所述第二晶体管、所述第三晶体管以及所述第四晶体管开关导通，所述输入端口与所述第一输出端口导通。
可选的，所述第二控制端口提供第一电平信号，所述第一控制端口、所述第三控制端口以及所述第四控制端口提供第二电平信号，所述第二晶体管开关断开，所述第一晶体管、所述第三晶体管以及所述第四晶体管开关导通，所述输入端口与所述第二输出端口导通。
可选的，所述第三控制端口提供第一电平信号，所述第一控制端口、所述第二控制端口以及所述第四控制端口提供第二电平信号，所述第三晶体管开关断开，所述第一晶体管、所述第二晶体管以及所述第四晶体管开关导通，所述输入端口与所述第三输出端口导通。
可选的，所述第四控制端口提供第一电平信号，所述第一控制端口、所述第二控制端口以及所述第三控制端口提供第二电平信号，所述第一晶体管、所述第二晶体管以及所述第三晶体管开关导通，所述第四晶体管开关断开，所述输入端口与所述第四输出端口导通。
可选的，还包括：旁路电容，所述旁路电容一端与所述第一电感线圈相连，所述旁路电容的另一端接地。
第二方面，本发明实施利提供的一种射频集成电路，包括：上述的多线圈耦合式单刀四掷开关。
本发明实施例提供的一种多线圈耦合式单刀四掷开关及射频集成电路， 利用耦合电感电路实现各端口之间的高隔离度，并且能够基于各个控制电路的电平信号，选择一个输出端口，实现输入端口与其导通，以及利用与各个输出端口连接的电感线圈、除该输出端口之外的其余输出端口所连接的控制电路，配置该输出端口的负载，以实现该输出端口的负载匹配，通过改变输出端口的负载，达到减小插入损耗的目的，实现能够在不同电路之间进行选通且满足低插入损耗、高隔离度的小型化开关。
当然，实施本发明的任一产品或方法并不一定需要同时达到以上所述的所有优点。
以下将结合附图及实施例对本发明做进一步详细说明。
附图说明
图1是本发明实施例提供的一种多线圈耦合式单刀四掷开关的电路结构示意图；
图2是本发明实施例提供的一种多线圈耦合式单刀四掷开关的具体结构示意图；
图3～图6是本发明实施例提供的一种多线圈耦合式单刀四掷开关在不同电平信号下的等效电路图。
具体实施方式
下面结合具体实施例对本发明做进一步详细的描述，但本发明的实施方式不限于此。
为了实现一种能够在不同电路之间进行选通且满足低插入损耗、高隔离度的小型化开关，本发明实施例提供了一种多线圈耦合式单刀四掷开关及射频集成电路。
第一方面，本发明实施例提供了一种多线圈耦合式单刀四掷开关。下 面，对多线圈耦合式单刀四掷开关进行介绍。
参见图1，图1为本发明实施例提供的一种多线圈耦合式单刀四掷开关的电路结构示意图，包括：
输入端口P1、第一输出端口P2、第二输出端口P3、第三输出端口P4以及第四输出端口P5；
耦合电感电路100，耦合电感电路100包括与输入端口P1以及各个输出端口分别连接的电感线圈，耦合电感电路100用于隔离第一输出端口P2、第二输出端口P3、第三输出端口P4以及第四输出端口P5；
晶体管控制电路，晶体管控制电路包括分别与第一输出端口P2、第二输出端口P3、第三输出端口P4、第四输出端口P5连接的第n控制电路，其中n依次对应为一至四；晶体管控制电路基于各个控制电路的电平信号，选择一个输出端口实现与输入端口导通，以及利用与各个输出端口连接的电感线圈、除该输出端口之外的其余输出端口所连接的控制电路，配置该输出端口的负载，以实现该输出端口的负载匹配。
可以理解的是，耦合电感电路100能够利用电感线圈将输入端口P1、第一输出端口P2、第二输出端口P3、第三输出端口P4以及第四输出端口P5隔离起来，提高输入端口P1与各个输出端口之间的隔离度。
晶体管控制电路包括第一控制电路110、第二控制电路120、第三控制电路130以及第四控制电路140，第一控制电路110与第一输出端口P2连接，第二控制电路120与第二输出端口P3连接，第三控制电路130与第三输出端口P4连接，第四控制电路140与第四输出端口P5连接。
其中每个控制电路均配置有对应的电平信号，在不同电平信号下可以实现不同的工作状态。本发明实施例可以通过配置各个控制电路的电平信 号，进而控制各个控制电路的工作状态，从而实现输入端口与某个输出端口的导通，实现在不同电路之间进行选通的目的。并且，在选通某个输出端口后，利用与各个输出端口所连接的电感线圈、除该输出端口之外的其余输出端口所连接的控制电路，对应配置该输出端口的负载，以实现该输出端口的负载匹配，本发明实施例针对不同的输出端口，配置的输出端口的负载是不同的，从而可以实现减小每个选通电路的插入损耗的目的。
本领域内通常采用λ/4传输线进行负载匹配，但其需要较大的布板面积，不利于片上集成。但本发明实施例利用电感线圈和控制电路实现负载匹配，因此可以减小面积，有利于片上集成，实现小型化开关。
本发明实施例提供的多线圈耦合式单刀四掷开关能够利用耦合电感电路实现各端口之间的高隔离度，并且能够基于各个控制电路的电平信号，选择一个输出端口，实现输入端口与其导通，以及利用与各个输出端口连接的电感线圈、除该输出端口之外的其余输出端口所连接的控制电路，配置该输出端口的负载，以实现该输出端口的负载匹配，通过改变输出端口的负载，达到减小插入损耗的目的，实现能够在不同电路之间进行选通且满足低插入损耗、高隔离度的小型化开关。
以下对本发明实施例提供的多线圈耦合式单刀四掷开关的结构的可选实施方式进行说明，具体请参见图2，图2是本发明实施例提供的一种多线圈耦合式单刀四掷开关的具体结构示意图。
可选的，耦合电感电路100的电感线圈，包括：
第一电感线圈L1、第二电感线圈L2以及第三电感线圈L3，第一电感线圈L1与输入端口P1连接，第二电感线圈L2连接在第一输出端口P2与第二输出端口P3之间，第三电感线圈L3连接在第三输出端口P4与第四输 出端口P5之间。
可选的，本发明实施例提供的多线圈耦合式单刀四掷开关，还包括：控制端口组，控制端口组包括第一控制端口V1，第二控制端口V2，第三控制端口V3以及第四控制端口V4，第一控制端口V1与第一控制电路110连接，第二控制端口V2与第二控制电路120连接，第三控制端口V3与第三控制电路130连接，第四控制端口V4与第四控制电路140连接，控制端口组用于为晶体管控制电路提供电平信号。
可选的，第n控制电路包括：第n晶体管Mn、第n栅极偏置电阻Rn以及第n晶体管Mn的源极间的第n外接电阻Rsubn，第n栅极偏置电阻Rn连接在第n晶体管Mn的栅极与第n控制端口Vn之间，第n晶体管Mn的漏极与第n输出端口并联，第n晶体管Mn的源极接地，第n外接电阻Rsub n的一端与第n晶体管Mn的衬底连接，第n外接电阻Rsub n的另一端接地。
具体的，当n依次对应为一至四时，第n控制电路对应为第一控制电路110、第二控制电路120、第三控制电路130以及第四控制电路140。第一控制端口V1、第二控制端口V2，第三控制端口V3以及第四控制端口V4分别为第一控制电路110、第二控制电路120、第三控制电路130以及第四控制电路140提供电平信号。
那么，对应于前述的第n控制电路的具体结构如下：
第一控制电路110包括第一晶体管M1、第一栅极偏置电阻R1以及第一晶体管M1的源极间的第一外接电阻Rsub1，第一栅极偏置电阻R1连接在第一晶体管M1的栅极与第一控制端口V1之间，第一晶体管M1的漏极与第一输出端口P2并联，第一晶体管M1的源极接地，第一外接电阻Rsub1 的一端与第一晶体管M1的衬底连接，第一外接电阻Rsub1的另一端接地。
第二控制电路120包括第二晶体管M2、第二栅极偏置电阻R2以及第二晶体管M2的源极间的第二外接电阻Rsub2，第二栅极偏置电阻R2连接在第二晶体管M2的栅极与第二控制端口V2之间，第二晶体管M2的漏极与第二输出端口P3并联，第二晶体管M2的源极接地，第二外接电阻Rsub2的一端与第二晶体管M2的衬底连接，第二外接电阻Rsub2的另一端接地。
第三控制电路130包括第三晶体管M3、第三栅极偏置电阻R3以及第三晶体管M3的源极间的第三外接电阻Rsub3，第三栅极偏置电阻R3连接在第三晶体管M3的栅极与第三控制端口V3之间，第三晶体管M3的漏极与第三输出端口P4并连，第三晶体管M3的源极接地，第三外接电阻Rsub3的一端与第三晶体管M3的衬底连接，第三外接电阻Rsub3的另一端接地。
第四控制电路140包括第四晶体管M4、第四栅极偏置电阻R4以及第四晶体管M4的源极间的第四外接电阻Rsub4，第四栅极偏置电阻R4连接在第四晶体管M4的栅极与第四控制端口V4之间，第四晶体管M4的漏极与第四输出端口P5并连，第四晶体管M4的源极接地，第四外接电阻Rsub4的一端与第四晶体管M4的衬底连接，第四外接电阻Rsub4的另一端接地。
需要注意的是，第一栅极偏置电阻R1、第二栅极偏置电阻R2、第三栅极偏置电阻R3以及第四栅极偏置电阻R4用于提高开关射频信号与电平信号的隔离度。
第一外接电阻Rsub1、第二外接电阻Rsub2、第三外接电阻Rsub3以及第四外接电阻Rsub4用于减小与其连接的晶体管的衬底的电阻，能够减小插入损耗。
进一步的，本发明实施例提供的多线圈耦合式单刀四掷开关还包括： 旁路电容C1，旁路电容C1一端与第一电感线圈L1相连，旁路电容C1的另一端接地。
本领域技术人员可以理解的是，旁路电容可将混有高频电流和低频电流的交流信号中的高频成分旁路滤掉，能够把输入端口P1的信号中的高频噪声作为滤除对象，把前级携带的高频杂波滤除。
以下对多线圈耦合式单刀四掷开关的几种工作状态进行介绍，以便于理解本发明的多线圈耦合式单刀四掷开关的工作原理。
图3～图6是本发明实施例提供的一种多线圈耦合式单刀四掷开关在不同电平信号下的等效电路图。
参考图3，图3是为第一控制电路提供第一电平信号下的等效电路图。
本实施例中，第一控制端口V1提供第一电平信号，第二控制端口V2、第三控制端口V3以及第四控制端口V4提供第二电平信号，第一晶体管M1开关断开，第二晶体管M2、第三晶体管M3以及第四晶体管M4开关导通，输入端口P1与第一输出端口P2导通。
电平信号是电平值表示的信号，包括高电平“1”以及低电平“0”。
可选的实施方式为：第一电平信号为低电平，比如为0；第二电平信号为高电平，比如为1。结合图3理解，由于为第一控制端口V1提供低电平，所以第一控制电路110的电平信号也为低电平，由于为第二控制端口V2、第三控制端口V3以及第四控制端口V4提供高电平，所以第二控制电路120、第三控制点路130以及第四控制电路140的电平信号也为高电平。本领域技术人员可以理解的是，根据晶体管的工作原理，第一晶体管M1开关断开，此时第一晶体管M1等效为晶体管关断电容Coff1，第二晶体管M2、第三晶体管M3以及第四晶体管M4开关导通，此时第二晶体管M2等效为晶体 管导通电阻Ron2，第三晶体管M3等效为晶体管导通电阻Ron3，第四晶体管M4等效为晶体管导通电阻Ron4，同时，也包括第二晶体管M2的寄生电容、第三晶体管M3的寄生电容以及第四晶体管M4的寄生电容。本领域技术人员可以理解的是，这时，晶体管关断电容Coff1等效为第一输出端口P2的旁路电容，实现电平信号从输入端口P1传输到第一输出端口P2；晶体管导通电阻Ron2等效为第二输出端口P3的负载，晶体管导通电阻Ron2把第二输出端口P3短路到地，因此输入端口P1与第二输出端口P3断开；晶体管导通电阻Ron3等效为第三输出端口P4的负载，晶体管导通电阻Ron3把第三输出端口P4短路到地，因此输入端口P1与第三输出端口P4断开；晶体管导通电阻Ron4等效为第四输出端口P5的负载，晶体管导通电阻Ron4把第四输出端口P5短路到地，因此输入端口P1与第四输出端口P5断开。并且，第二电感线圈L2、第三电感线圈L3、第二晶体管M2的寄生电容、第三晶体管M3的寄生电容以及第四晶体管M4的寄生电容作为第一输出端口P2的负载。
参考图4，图4是为第二控制电路提供第一电平信号下的等效电路图。
本实施例中，第二控制端口V2提供第一电平信号，第一控制端口V1、第三控制端口V3以及第四控制端口V4提供第二电平信号，第二晶体管M2开关断开，第一晶体管M1、第三晶体管M3以及第四晶体管M4开关导通，输入端口P1与第二输出端口P3导通。
可选的实施方式为：第一电平信号为低电平，比如为0；第二电平信号为高电平，比如为1。结合图4理解，由于为第二控制端口V2提供低电平，所以第二控制电路120的电平信号也为低电平，由于为第一控制端口V1、第三控制端口V3以及第四控制端口V4提供高电平，所以第一控制电路110、 第三控制点路130以及第四控制电路140的电平信号也为高电平。本领域技术人员可以理解的是，根据晶体管的工作原理，第二晶体管M2开关断开，此时第二晶体管M2等效为晶体管关断电容Coff2，第一晶体管M1、第三晶体管M3以及第四晶体管M4开关导通，此时第一晶体管M1等效为晶体管导通电阻Ron1，第三晶体管M3等效为晶体管导通电阻Ron3，第四晶体管M4等效为晶体管导通电阻Ron4，同时，也包括第一晶体管M1的寄生电容、第三晶体管M3的寄生电容以及第四晶体管M4的寄生电容。这时，晶体管关断电容Coff2等效为第二输出端口P3的旁路电容，实现电平信号从输入端口P1传输到第二输出端口P3；晶体管导通电阻Ron1等效为第一输出端口P2的负载，晶体管导通电阻Ron1把第一输出端口P2短路到地，因此输入端口P1与第一输出端口P2断开；晶体管导通电阻Ron3等效为第三输出端口P4的负载，晶体管导通电阻Ron3把第三输出端口P4短路到地，因此输入端口P1与第三输出端口P4断开；晶体管导通电阻Ron4等效为第四输出端口P5的负载，晶体管导通电阻Ron4把第四输出端口P5短路到地，因此输入端口P1与第四输出端口P5断开。并且，第二电感线圈L2、第三电感线圈L3、第一晶体管M1的寄生电容、第三晶体管M3的寄生电容以及第四晶体管M4的寄生电容作为第二输出端口P3的负载。
参考图5，图5是为第三控制电路提供第一电平信号下的等效电路图。
本实施例中，第三控制端口V3提供第一电平信号，第一控制端口V1、第二控制端口V2以及第四控制端口V4提供第二电平信号，第三晶体管M3开关断开，第一晶体管M1、第二晶体管M2以及第四晶体管M4开关导通，输入端口P1与第三输出端口P4导通。
可选的实施方式为：第一电平信号为低电平，比如为0；第二电平信号 为高电平，比如为1。结合图5理解，由于为第三控制端口V3提供低电平，所以第三控制点路130的电平信号也为低电平，由于为第一控制端口V1、第二控制端口V2以及第四控制端口V4提供高电平，所以第一控制电路110、第二控制电路120以及第四控制电路140的电平信号也为高电平。本领域技术人员可以理解的是，根据晶体管的工作原理，第三晶体管M3开关断开，此时第三晶体管M3等效为晶体管关断电容Coff3，第一晶体管M1、第二晶体管M2以及第四晶体管M4开关导通，此时第一晶体管M1等效为晶体管导通电阻Ron1，第二晶体管M2等效为晶体管导通电阻Ron2，第四晶体管M4等效为晶体管导通电阻Ron4，同时，也包括第一晶体管M1的寄生电容、第二晶体管M2的寄生电容以及第四晶体管M4的寄生电容。这时，晶体管关断电容Coff3等效为第三输出端口P4的旁路电容，实现电平信号从输入端口P1传输到第三输出端口P4；晶体管导通电阻Ron1等效为第一输出端口P2的负载，晶体管导通电阻Ron1把第一输出端口P2短路到地，因此输入端口P1与第一输出端口P2断开；晶体管导通电阻Ron2等效为第二输出端口P3的负载，晶体管导通电阻Ron2把第二输出端口P3短路到地，因此输入端口P1与第二输出端口P3断开；晶体管导通电阻Ron4等效为第四输出端口P5的负载，晶体管导通电阻Ron4把第四输出端口P5短路到地，因此输入端口P1与第四输出端口P5断开。并且，第二电感线圈L2、第三电感线圈L3、第一晶体管M1的寄生电容、第二晶体管M2的寄生电容以及第四晶体管M4的寄生电容作为第三输出端口P4的负载。
参考图6，图6是为第四控制电路提供第一电平信号下的等效电路图。
本实施例中，第四控制端口V4提供第一电平信号，第一控制端口V1、第二控制端口V2以及第三控制端口V3提供第二电平信号，第一晶体管 M1、第二晶体管M2以及第三晶体管M3开关导通，第四晶体管M4开关断开，输入端口P1与第四输出端口P5导通。
可选的实施方式为：第一电平信号为低电平，比如为0；第二电平信号为高电平，比如为1。结合图3理解，由于为第四控制端口V4提供低电平，所以第四控制电路140的电平信号也为低电平，由于为第一控制端口V1、第二控制端口V2以及第三控制端口V3提供高电平，所以第一控制电路110、第二控制电路120以及第三控制点路130的电平信号也为高电平。本领域技术人员可以理解的是，根据晶体管的工作原理，第四晶体管M4开关断开，此时第四晶体管M4等效为晶体管关断电容Coff4，第一晶体管M1、第二晶体管M2以及第三晶体管M开关导通，此时第一晶体管M1等效为晶体管导通电阻Ron1，第二晶体管M2等效为晶体管导通电阻Ron2，第三晶体管M3等效为晶体管导通电阻Ron3，同时，也包括第一晶体管M1的寄生电容、第二晶体管M2的寄生电容以及第三晶体管M3的寄生电容。这时，晶体管关断电容Coff4等效为第四输出端口P5的旁路电容，实现电平信号从输入端口P1传输到第四输出端口P5；晶体管导通电阻Ron1等效为第一输出端口P2的负载，晶体管导通电阻Ron1把第一输出端口P2短路到地，因此输入端口P1与第一输出端口P2断开；晶体管导通电阻Ron2等效为第二输出端口P3的负载，晶体管导通电阻Ron2把第二输出端口P3短路到地，因此输入端口P1与第二输出端口P3断开；晶体管导通电阻Ron3等效为第三输出端口P4的负载，晶体管导通电阻Ron3把第三输出端口P4短路到地，因此输入端口P1与第三输出端口P4断开。并且，第二电感线圈L2、第三电感线圈L3、第一晶体管M1的寄生电容、第二晶体管M2的寄生电容以及第三晶体管M3的寄生电容作为第四输出端口P5的负载。
为了证实本发明实施例提供的线圈耦合式单刀四掷开关的工作效果，以下结合线圈耦合式单刀四掷开关的具体参数和仿真结果进行说明。
一种可选的实施方式中，第一晶体管M1由6组场效应晶体管组成，且每组场效应晶体管包括有64个沟道，且沟道宽度为1μm，沟道长度为40nm；第二晶体管M2由6组场效应晶体管组成，且每组场效应晶体管包括有64个沟道，且沟道宽度为1μm，沟道长度为40nm；第三晶体管M3由6组场效应晶体管组成，且每组场效应晶体管包括有64个沟道，且沟道宽度为1μm，沟道长度为40nm；第四晶体管M4由6组场效应晶体管组成，且每组场效应晶体管包括有64个沟道，且沟道宽度为1μm，沟道长度为40nm。
第一栅极偏置电阻R1、第二栅极偏置电阻R2、第三栅极偏置电阻R3以及第四栅极偏置电阻R4的阻值均为3KΩ。
第一外接电阻Rsub1、第二外接电阻Rsub2、第三外接电阻Rsub3以及第四外接电阻Rsub4的阻值均为6KΩ，旁路电容C1的电容为40fF。
针对上述结构参数的线圈耦合式单刀四掷开关，可以实现：应用频段包括40GHz～55GHz。在应用频段内，输入端口P1与各个输出端口的插入损耗的不匹配度小于0.24dB，输入端口P1与各个输出端口的插入损耗小于2.2dB，输入端口P1与各个输出端口的隔离度大于23.2dB。
需要注意的是，本发明实施例提供的线圈耦合式单刀四掷开关内的结构参数不局限于此，本领域技术人员能够想到根据使用条件不同使用不同参数的结构达到同样的效果。
本实施例中，利用晶体管在不同电平下导通或者关断的原理，通过控制控制端口组的电平信号，为其中一控制电路的晶体管提供的电平信号与其余控制电路的晶体管提供的电平信号相反，因此能够实现输出端口的切 换。同时，通过对输出端口的负载进行切换，实现在输入端口与不同输出端口导通时，均具有较低的插入损耗。
并且，相比于图1所示的多线圈耦合式单刀四掷开关，本发明实施例提供的多线圈耦合式单刀四掷开关，通过晶体管控制电路的栅极偏置电阻能够提高开关射频信号与电平信号的隔离度，通过外接电阻能够减小晶体管的衬底的电阻，达到减小插入损耗的目的，进一步保证了单刀四掷开关在不同工作状态下都具有较小的插入损耗以及较高隔离度的性能，能够实现毫米波集成电路开关输入端口到四个端口输出的良好匹配。
第二方面，本发明实施例提供了一种射频集成电路，包括：如上述的多线圈耦合式单刀四掷开关。
本发明实施例中，可以将多线圈耦合式单刀四掷开关封装为一种射频集成电路，该射频集成电路可以应用于射频前端设备，例如：低噪声放大器、滤波器、衰减器以及移相器等。
本实施例中，利用晶体管在不同电平下导通或者关断的原理，通过控制控制端口组的电平信号，为其中一控制电路的晶体管提供的电平信号与其余控制电路的晶体管提供的电平信号相反，因此能够实现输出端口的切换。同时，通过对输出端口的负载进行切换，实现在输入端口与不同输出端口导通时，均具有较低的插入损耗。并且，通过晶体管控制电路的栅极偏置电阻能够提高开关射频信号与电平信号的隔离度，通过外接电阻能够减小晶体管的衬底的电阻，达到减小插入损耗的目的，进一步保证了单刀四掷开关在不同工作状态下都具有较小的插入损耗以及较高隔离度的性能，能够实现毫米波集成电路开关输入端口到四个端口输出的良好匹配。
需要说明的是，在本文中，诸如第一和第二等之类的关系术语仅仅用 来将一个实体或者操作与另一个实体或操作区分开来，而不一定要求或者暗示这些实体或操作之间存在任何这种实际的关系或者顺序。而且，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者设备不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者设备所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括要素的过程、方法、物品或者设备中还存在另外的相同要素。
本说明书中的各个实施例均采用相关的方式描述，各个实施例之间相同相似的部分互相参见即可，每个实施例重点说明的都是与其他实施例的不同之处。尤其，对于系统实施例而言，由于其基本相似于方法实施例，所以描述的比较简单，相关之处参见方法实施例的部分说明即可。
以上内容是结合具体的优选实施方式对本发明所作的进一步详细说明，不能认定本发明的具体实施只局限于这些说明。对于本发明所属技术领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干简单推演或替换，都应当视为属于本发明的保护范围。

Claims (10)

  1. 一种多线圈耦合式单刀四掷开关，其特征在于，包括：
    输入端口(P1)、第一输出端口(P2)、第二输出端口(P3)、第三输出端口(P4)以及第四输出端口(P5)；
    耦合电感电路，所述耦合电感电路包括与所述输入端口(P1)以及各个输出端口分别连接的电感线圈，所述耦合电感电路用于隔离所述第一输出端口(P2)、所述第二输出端口(P3)、所述第三输出端口(P4)以及所述第四输出端口(P5)；
    晶体管控制电路，所述晶体管控制电路包括分别与所述第一输出端口(P2)、所述第二输出端口(P3)、所述第三输出端口(P4)、所述第四输出端口(P5)连接的第n控制电路，其中n依次对应为一至四；所述晶体管控制电路基于各个控制电路的电平信号，选择一个输出端口实现与所述输入端口导通，以及利用与各个输出端口连接的所述电感线圈、除该输出端口之外的其余输出端口所连接的控制电路，配置该输出端口的负载，以实现该输出端口的负载匹配。
  2. 根据权利要求1所述的多线圈耦合式单刀四掷开关，其特征在于，所述耦合电感电路的所述电感线圈，包括：
    第一电感线圈(L1)、第二电感线圈(L2)以及第三电感线圈(L3)，所述第一电感线圈(L1)与所述输入端口(P1)连接，所述第二电感线圈(L2)连接在所述第一输出端口(P2)与所述第二输出端口(P3)之间，所述第三电感线圈(L3)连接在所述第三输出端口(P4)与所述第四输出端口(P5)之间。
  3. 根据权利要求2所述的多线圈耦合式单刀四掷开关，其特征在于，所述多线圈耦合式单刀四掷开关还包括：
    控制端口组，所述控制端口组包括第一控制端口(V1)，第二控制端口(V2)，第三控制端口(V3)以及第四控制端口(V4)，所述第一控制端口(V1)与所述第一控制电路连接，所述第二控制端口(V2)与所述第二控制电路连接，所述第三控制端口(V3)与所述第三控制电路连接，所述第四控制端口(V4)与所述第四控制电路连接，所述控制端口组用于为所述晶体管控制电路提供电平信号。
  4. 根据权利要求3所述的多线圈耦合式单刀四掷开关，其特征在于，所述第n控制电路包括：第n晶体管(Mn)、第n栅极偏置电阻(Rn)以及所述第n晶体管(Mn)的源极间的第n外接电阻(Rsubn)，所述第n栅极偏置电阻(Rn)连接在所述第n晶体管(Mn)的栅极与所述第n控制端口(Vn)之间，所述第n晶体管(Mn)的漏极与所述第n输出端口并联，所述第n晶体管(Mn)的源极接地，所述第n外接电阻(Rsub n)的一端与所述第n晶体管(Mn)的衬底连接，所述第n外接电阻(Rsub n)的另一端接地。
  5. 根据权利要求4所述的多线圈耦合式单刀四掷开关，其特征在于，所述第一控制端口(V1)提供第一电平信号，所述第二控制端口(V2)、所述第三控制端口(V3)以及所述第四控制端口(V4)提供第二电平信号，所述第一晶体管(M1)开关断开，所述第二晶体管(M2)、所述第三晶体管(M3)以及所述第四晶体管(M4)开关导通，所述输入端口(P1)与所述第一输出端口(P2)导通。
  6. 根据权利要求4所述的多线圈耦合式单刀四掷开关，其特征在于，所述第二控制端口(V2)提供第一电平信号，所述第一控制端口(V1)、所述第三控制端口(V3)以及所述第四控制端口(V4)提供第二电平信号， 所述第二晶体管(M2)开关断开，所述第一晶体管(M1)、所述第三晶体管(M3)以及所述第四晶体管(M4)开关导通，所述输入端口(P1)与所述第二输出端口(P3)导通。
  7. 根据权利要求4所述的多线圈耦合式单刀四掷开关，其特征在于，所述第三控制端口(V3)提供第一电平信号，所述第一控制端口(V1)、所述第二控制端口(V2)以及所述第四控制端口(V4)提供第二电平信号，所述第三晶体管(M3)开关断开，所述第一晶体管(M1)、所述第二晶体管(M2)以及所述第四晶体管(M4)开关导通，所述输入端口(P1)与所述第三输出端口(P4)导通。
  8. 根据权利要求4所述的多线圈耦合式单刀四掷开关，其特征在于，所述第四控制端口(V4)提供第一电平信号，所述第一控制端口(V1)、所述第二控制端口(V2)以及所述第三控制端口(V3)提供第二电平信号，所述第一晶体管(M1)、所述第二晶体管(M2)以及所述第三晶体管(M3)开关导通，所述第四晶体管(M4)开关断开，所述输入端口(P1)与所述第四输出端口(P5)导通。
  9. 根据权利要求1所述的多线圈耦合式单刀四掷开关，其特征在于，还包括：旁路电容(C1)，所述旁路电容(C1)一端与所述第一电感线圈(L1)相连，所述旁路电容(C1)的另一端接地。
  10. 一种射频集成电路，其特征在于，包括如权利要求1-9任一项所述的多线圈耦合式单刀四掷开关。
PCT/CN2020/138115 2020-10-30 2020-12-21 多线圈耦合式单刀四掷开关及射频集成电路 WO2022088446A1 (zh)

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