WO2022088017A1 - 显示面板的驱动方法、存储介质、驱动设备及显示设备 - Google Patents

显示面板的驱动方法、存储介质、驱动设备及显示设备 Download PDF

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Publication number
WO2022088017A1
WO2022088017A1 PCT/CN2020/125158 CN2020125158W WO2022088017A1 WO 2022088017 A1 WO2022088017 A1 WO 2022088017A1 CN 2020125158 W CN2020125158 W CN 2020125158W WO 2022088017 A1 WO2022088017 A1 WO 2022088017A1
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WIPO (PCT)
Prior art keywords
voltage
light
frame
electrode
mapping relationship
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PCT/CN2020/125158
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English (en)
French (fr)
Inventor
李京勇
徐飞
王颜彬
洪俊
田文红
Original Assignee
京东方科技集团股份有限公司
合肥京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 合肥京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN202080002559.1A priority Critical patent/CN114766049B/zh
Priority to US17/423,468 priority patent/US12020639B2/en
Priority to PCT/CN2020/125158 priority patent/WO2022088017A1/zh
Publication of WO2022088017A1 publication Critical patent/WO2022088017A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0271—Adjustment of the gradation levels within the range of the gradation scale, e.g. by redistribution or clipping
    • G09G2320/0276—Adjustment of the gradation levels within the range of the gradation scale, e.g. by redistribution or clipping for the purpose of adaptation to the characteristics of a display device, i.e. gamma correction

Definitions

  • the embodiments of the present disclosure relate to, but are not limited to, the field of display technology, and more particularly, to a method for driving a display panel, a storage medium, a driving device, and a display device.
  • the Organic Light-Emitting Diode (OLED) display panel has the advantages of thin thickness, light weight, wide viewing angle, active light emission, continuously adjustable light emission color, low cost, fast response speed, low energy consumption, low driving voltage, and operating temperature. With the advantages of wide range, simple production process, high luminous efficiency and flexible display, it is more and more widely used in display fields such as mobile phones, tablet computers, and digital cameras.
  • the dynamic contrast displayed by the display panel is low.
  • the maximum brightness of the picture for example, 1/2 of the maximum brightness in the specification
  • the minimum brightness for example, 2 times the minimum brightness in the specification
  • an embodiment of the present disclosure provides a method for driving a display panel, wherein,
  • the display panel includes: a substrate substrate, a pixel driving circuit, and a light-emitting element that are stacked in sequence, the light-emitting element includes: a first electrode, an organic light-emitting layer, and a second electrode that are stacked in sequence, and the pixel driving circuit includes : a driving transistor coupled with the first electrode, a first power supply terminal coupled with the driving transistor, and a second power supply terminal coupled with the second electrode;
  • the driving method includes: in the Nth frame, based on the grayscale data of the Nth frame, applying a first voltage to the second electrode through the pixel driving circuit, and applying the same voltage to the first electrode to the first electrode. a voltage-matched first data signal; in the N+1th frame, based on the grayscale data of the N+1th frame, a second voltage is applied to the second electrode through the pixel driving circuit, and a second voltage is applied to the second electrode.
  • the first electrode applies a second data signal matched with a second voltage, wherein the first voltage and the second voltage are different; N is a positive integer.
  • an embodiment of the present disclosure further provides a computer-readable storage medium storing computer-executable instructions, where the computer-executable instructions are used to execute the steps of the above-mentioned method for driving a display panel.
  • an embodiment of the present disclosure further provides a driving device, including: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the program when the processor executes the program The steps of the above-mentioned driving method of the display panel.
  • an embodiment of the present disclosure further provides a display device, including: a display panel and the above-mentioned driving device.
  • FIG. 1 is a schematic structural diagram of a display panel in an embodiment of the disclosure
  • FIG. 2 is a schematic block diagram of a display panel in an embodiment of the present disclosure
  • 3A is a schematic structural diagram of a pixel driving circuit in an embodiment of the disclosure.
  • FIG. 3B is another schematic structural diagram of a pixel driving circuit in an embodiment of the disclosure.
  • FIG. 4 is a schematic flowchart of a method for driving a display panel according to an embodiment of the disclosure
  • FIG. 5 is a schematic diagram of a frame in an embodiment of the present disclosure.
  • FIG. 6 is a schematic diagram of a geometric position marker of a pixel in an embodiment of the present disclosure
  • FIG. 7 is a schematic diagram of a mapping relationship between gray scales and luminance in an embodiment of the present disclosure.
  • 8A is a signal timing diagram of a method for driving a display panel provided by an embodiment of the present disclosure.
  • FIG. 8B is another signal timing diagram of the driving method of the display panel provided by the embodiment of the present disclosure.
  • 9A is a display result diagram of the display panel when the driving voltage of the display panel is not adjusted.
  • 9B is a display result diagram of the display panel when only the voltage of the second electrode of the light-emitting element of the display panel is adjusted;
  • FIG. 9C is a display result diagram of the display panel obtained when the display panel driving method provided by the embodiment of the present disclosure is used to drive the display panel;
  • FIG. 10 is a schematic structural diagram of a driving device in an embodiment of the disclosure.
  • Coupled may be used in describing some embodiments to indicate that two or more components are in direct physical or electrical contact.
  • the terms “coupled” or “communicatively coupled” may also mean that two or more components are not in direct contact with each other, yet still co-operate or interact with each other.
  • the embodiments disclosed herein are not necessarily limited by the content herein.
  • a transistor refers to an element including at least three terminals of a gate electrode (or gate), a drain electrode, and a source electrode.
  • the transistor has a channel region between the drain electrode (or drain electrode terminal, drain region or drain) and the source electrode (or source electrode terminal, source region or source electrode), and current can flow through the drain electrode, channel region and source electrode.
  • the channel region refers to a region through which current mainly flows.
  • the first electrode may be the drain electrode and the second electrode may be the source electrode, or the first electrode may be the source electrode and the second electrode may be the drain electrode.
  • the functions of the "source electrode” and the “drain electrode” may be interchanged. Therefore, herein, “source electrode” and “drain electrode” may be interchanged with each other.
  • electrically connected includes the case where constituent elements are connected together by means of elements having some electrical function.
  • the "element having a certain electrical effect” is not particularly limited as long as it can transmit and receive electrical signals between the connected constituent elements.
  • the “element having a certain electrical effect” may be, for example, electrodes or wirings, or switching elements such as transistors, or other functional elements such as resistors, inductors, and capacitors.
  • Embodiments of the present disclosure provide a driving method of a display panel.
  • the driving method of the display panel can be applied to the display panel.
  • the display panel may include: a substrate substrate, a pixel driving circuit, and a light-emitting element stacked in sequence, wherein the light-emitting element may include: a first electrode, an organic light-emitting layer, and a second electrode stacked in sequence, and the pixel driving circuit may It includes: a driving transistor coupled with the first electrode, a first power supply terminal coupled with the driving transistor, and a second power supply terminal coupled with the second electrode.
  • the number of light-emitting elements may be multiple, and correspondingly, the number of pixel driving circuits may be multiple, wherein the multiple pixel driving circuits are respectively used to drive multiple light-emitting elements formed subsequently.
  • the circuit structure and layout of the pixel driving circuit can be designed according to the actual situation, which is not limited in this embodiment of the present disclosure.
  • the light-emitting element may include, but is not limited to, any one of an organic light-emitting diode (Organic Light-Emitting Diode, OLED), a quantum dot light-emitting diode (Quantum Dot Light Emitting Diodes, QLED), and an inorganic light-emitting diode kind.
  • OLED Organic Light-Emitting Diode
  • QLED Quantum Dot Light Emitting Diodes
  • the light-emitting element can be a micro-scale light-emitting element such as Micro-LED and Mini-LED.
  • the above-mentioned display panel may include, but is not limited to, an OLED display panel, a QLED display panel, and the like, which are not limited in this embodiment of the present disclosure.
  • the base substrate may be a flexible substrate, or may be a rigid substrate.
  • the flexible substrate may include a stacked first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer and a second inorganic material layer, and the materials of the first flexible material layer and the second flexible material layer may be poly materials such as imide (PI), polyethylene terephthalate (PET) or surface-treated soft polymer film, the materials of the first inorganic material layer and the second inorganic material layer can be silicon nitride (SiNx ) or silicon oxide (SiOx), etc., to improve the water and oxygen resistance of the substrate, and the material of the semiconductor layer can be amorphous silicon (a-si).
  • the base substrate may be a silicon-based base substrate.
  • the first electrode may act as an anode.
  • the first electrode may be electrically connected to the source electrode of the driving transistor in the corresponding pixel driving circuit (via the connection portion corresponding to the source electrode) through a tungsten metal-filled via hole (ie, a tungsten via hole, W-via), or,
  • the first electrode may also be electrically connected to the drain electrode.
  • the second electrode may act as a cathode.
  • the second electrode may be a transparent electrode.
  • the second electrode may be a common electrode, that is, a second electrode shared by a plurality of light-emitting elements on an entire surface.
  • the display panel is described below by taking the light-emitting element as an OLED and the display panel as a silicon-based OLED display panel as an example.
  • FIG. 1 is a schematic structural diagram of a display panel in an embodiment of the disclosure.
  • FIG. 1 only schematically shows three light-emitting elements and one driving transistor T1 in the three pixel driving circuits, where the driving transistor T1 is used for coupling with the light-emitting elements formed subsequently.
  • the display panel may further include various traces such as scan signal lines and data signal lines, which is not limited in the present disclosure.
  • the silicon-based OLED display panel may include: a silicon-based substrate 10 , a plurality of pixel driving circuits 11 and a plurality of light emitting elements 12 stacked in sequence.
  • each light-emitting element 12 may include a first electrode 121 (for example, as an anode), an organic light-emitting layer 122 and a second electrode 123 (for example, as a cathode) stacked in sequence;
  • each pixel driving circuit may include: A driving transistor T1 coupled to the electrode 121 , a first power terminal (not shown in FIG. 1 ) coupled to the driving transistor T1 , and a second power terminal (not shown in FIG. 1 ) coupled to the second electrode 123 .
  • the second electrode 123 may be a transparent electrode.
  • the second electrode 123 may be a common electrode, that is, a plurality of light emitting elements 12 may share a whole surface of the second electrode 123 .
  • the driving transistor T1 may include: a gate electrode G, a source electrode S and a drain electrode D.
  • the three electrodes are respectively electrically connected to the three electrode connecting parts, for example, through a tungsten metal-filled via hole (ie, a tungsten via hole, W-via) for electrical connection; further, the three electrodes can be respectively connected through corresponding electrodes
  • the connection portion is electrically connected to other electrical structures (eg, transistors, traces, light-emitting elements, etc.).
  • the organic light-emitting layer of the OLED light-emitting element may include an emission layer (Emitting Layer, EML), and a hole injection layer (Hole Injection Layer, HIL), a hole transport layer (Hole Transport Layer, One of HTL), Hole Block Layer (HBL), Electron Block Layer (EBL), Electron Injection Layer (EIL), Electron Transport Layer (ETL) or multiple layers.
  • EML emission layer
  • HIL hole injection layer
  • HTL hole transport layer
  • HBL Hole Block Layer
  • EBL Electron Block Layer
  • EIL Electron Transport Layer
  • ETL Electron Transport Layer
  • the organic light-emitting layer may be formed by using a fine metal mask (Fine Metal Mask, FMM) evaporation, or using an open mask (Open Mask) evaporation, or using a spray Ink process preparation and formation.
  • FMM Fine Metal Mask
  • Open Mask Open Mask
  • the silicon-based substrate and the pixel driving circuit can be fabricated by processing a single crystal silicon wafer (wafer) by a front-end fab.
  • the silicon-based OLED display device may further include: a first encapsulation layer 13 , a color filter layer 14 , a second encapsulation layer 14 , a color filter layer 14 , and a second layer arranged on the plurality of light-emitting elements 12 in sequence.
  • the encapsulation layer 15 and the cover plate 16 may be polymer or/and ceramic thin film encapsulation layers, but not limited thereto.
  • the color filter layer 14 may include a red filter unit R, a green filter unit G, and a blue filter unit R, but is not limited thereto.
  • a filter unit and the corresponding light-emitting element and pixel driving circuit can be divided into a sub-pixel; for example, the red filter unit R, the green filter unit G and the blue filter unit R correspond to the red sub-pixel, pixel and blue subpixel.
  • the cover plate 16 may be a glass cover plate, but is not limited thereto.
  • the light-emitting element including the first electrode, the organic light-emitting layer and the second electrode, the first encapsulation layer, the color filter layer, the second encapsulation layer and the cover plate can all be fabricated in a back-end panel factory Finish.
  • FIG. 1 only exemplarily shows the structure of a display area (also called an active area, Active Aera, AA) of a silicon-based OLED display panel.
  • the silicon-based OLED display panel may also include a non-display area (an area other than the display area).
  • the non-display area may be further divided into dummy areas ( Dummy Area, DA), binding area (Bonding Area, BA), integrated circuit functional area (IC function block), etc.
  • the structure of the dummy area is basically the same as that of the display area, and can be used to ensure the uniformity of the display area; for example, the bonding area may include pads for electrical connection with external circuits and signal transmission; for example, integrated circuit functions
  • the region can be used to set gate electrode driver circuits (eg, gate driver circuits formed by GOA (Gate Driver On Array) technology) and circuits with other functions, and the like.
  • FIG. 2 is a schematic block diagram of a display panel according to an embodiment of the present disclosure.
  • the display panel may include: a pixel driving circuit and a light-emitting element
  • the pixel driving circuit may include: a driving transistor M0, a first power supply terminal 111 and a second power supply terminal 112
  • the driving transistor M0 may include: a gate 113, the second pole 115, and the first pole 114 coupled to the first power supply terminal 111
  • the light-emitting element may include: a first electrode 121 coupled to the second pole 115 of the driving transistor M0
  • a second power supply terminal 112 is coupled to the second electrode 123 .
  • the pixel driving circuit may include, in addition to driving transistors, switching transistors, storage capacitors, and other elements.
  • the pixel driving circuit may have a circuit structure such as a 3T1C circuit, a 4T1C circuit, a 5T1C circuit, a 5T2C circuit, a 6T1C circuit, or a 7T1C circuit, which is not limited in this embodiment of the present disclosure.
  • FIG. 3A is a schematic structural diagram of a pixel driving circuit in an embodiment of the disclosure.
  • the pixel driving circuit may include 6 transistors (ie, a driving transistor M0, a first switching transistor M1, a second switching transistor M2, a third switching transistor M3, a fourth switching transistor M4, and a fifth switching transistor M5) , 1 storage capacitor Cst, and 8 signal lines (ie reset control signal terminal, reset voltage terminal, first power supply terminal, second power supply terminal, lighting control signal terminal, transmission control signal terminal, scan signal terminal and data signal terminal) ).
  • an OLED light-emitting element is also shown in FIG. 3A.
  • the first electrode (eg, anode) of the OLED light-emitting element is coupled to the second electrode of the driving transistor M0, and the second electrode (eg, the cathode) of the OLED light-emitting element is coupled It is coupled to the second power terminal to receive the second power voltage VSS (ie, the common voltage Vcom).
  • the second power supply voltage VSS ie the common voltage Vcom
  • the second power supply voltage VSS ie the common voltage Vcom
  • the second power supply voltage VSS ie the common voltage Vcom
  • the second power supply voltage VSS ie the common voltage Vcom
  • the gate of the driving transistor M0 is connected to the fourth node N4, the first pole of the driving transistor M0 is connected to the second node N2, and the second pole of the driving transistor M0 is connected to the fourth node N4.
  • the third node N3 is connected.
  • the driving transistor M0 may be an N-type transistor, and embodiments of the present disclosure include but are not limited to this.
  • the gate of the first switch transistor M1 is connected to the reset control signal terminal to receive the reset control signal RS, and the first pole of the first switch transistor M1 is connected to the reset voltage terminal To receive the reset voltage Vinit, the second pole of the first switching transistor M1 is connected to the first node N1.
  • the first switching transistor M1 may be an N-type transistor, and embodiments of the present disclosure include but are not limited to this.
  • the reset voltage Vinit may be a zero voltage or a ground voltage, or may be other fixed levels, such as a low voltage, etc., which is not limited in this embodiment of the present disclosure.
  • the reset control signal RS is at a high level
  • the N-type first switch transistor M1 is turned on; when the reset control signal RS is at a low level, the N-type first switch transistor M1 is turned off.
  • the gate of the second switch transistor M2 is connected to the light-emitting control signal terminal to receive the light-emitting control signal EM, and the first electrode of the second switch transistor M2 is connected to the first power terminal Connected to receive the first power supply voltage VDD, the second pole of the second switching transistor M2 is connected to the first node N1.
  • the second switching transistor M2 may be a P-type transistor, and embodiments of the present disclosure include but are not limited to this.
  • the first power supply voltage VDD may be a corresponding driving voltage (analog signal) determined by the grayscale data actually displayed.
  • the first power supply voltage VDD may be determined by the grayscale data of the Nth frame.
  • the corresponding driving voltage determined by the data, or, in the N+1 th frame, the first power supply voltage VDD may be the corresponding driving voltage determined by the processed grayscale data of the N+1 th frame.
  • the gate of the third switching transistor M3 is connected to the transmission control signal terminal to receive the transmission control signal VT, and the first pole of the third switching transistor M3 is connected to the first node N1 connected, and the second pole of the third switching transistor M3 is connected to the second node N2.
  • the third switching transistor M2 may be an N-type transistor, and embodiments of the present disclosure include but are not limited to this. For example, when the transmission control signal VT is at a high level, the N-type third switch transistor M3 is turned on; when the transmission control signal VT is at a low level, the N-type third switch transistor M3 is turned off.
  • the gate of the fourth switch transistor M4 is connected to the scan signal terminal to receive the scan signal SN, and the first pole of the fourth switch transistor M4 is connected to the data signal terminal to receive
  • the data signal DATA ie, the gamma voltage Gamma
  • the second pole of the fourth switching transistor M4 is connected to the fourth node N4
  • the first end of the storage capacitor Cst is connected to the fourth node N4 (ie, coupled to the gate of the driving transistor M0).
  • the second terminal of the storage capacitor Cst is connected to the first voltage terminal to receive the first control voltage V_1.
  • the first control voltage V_1 may be a fixed voltage, such as a zero voltage or a ground voltage.
  • the storage capacitor Cst may store the data signal DATA (ie, the gamma voltage Gamma) written into the fourth node N4 (ie, the gate of the driving transistor M0 ).
  • the fourth switch transistor M4 may be an N-type transistor, and embodiments of the present disclosure include but are not limited to this. For example, when the scan signal SN is at a high level, the N-type fourth switch transistor M4 is turned on; when the scan signal SN is at a low level, the N-type fourth switch transistor M4 is turned off.
  • the data signal DATA (i.e., the gamma voltage Gamma) may be the first data signal, or in the N+1th frame, the data signal DATA (i.e., the gamma voltage Gamma) may be the second data signal.
  • the gate of the fifth switching transistor M5 is used to receive the inverted signal SN′ of the scan signal SN (for example, the scan signal SN can be input to the input terminal of the inverting circuit , so that the output terminal of the inverting circuit outputs the inverting signal SN'), the first pole of the fifth switching transistor M5 is connected to the data signal terminal to receive the data signal DATA (ie the gamma voltage Gamma), and the fifth switching transistor M5 The second pole is connected to the fourth node N4.
  • the fifth switching transistor M5 and the fourth switching transistor M4 are of different types; for example, as shown in FIG.
  • the fifth switching transistor M4 when the fourth switching transistor is an N-type transistor, the fifth switching transistor M4 is a P-type transistor.
  • the scan signal SN when the scan signal SN is at a high level, the inverted signal SN' is at a low level, and the P-type fifth switch transistor M5 is turned on; when the scan signal SN is at a low level, the inverted signal SN' is at a high level level, the P-type fifth switching transistor M5 is turned off. That is to say, the fifth switch transistor M5 and the fourth switch transistor M4 can be turned on and turned off at the same time.
  • the fifth switching transistor M5 and the fourth switching transistor M4 may be transistor devices with symmetrical structures; for example, the fifth switching transistor M5 and the fourth switching transistor M4 may form a transmission gate (Transmission Gate, also called an analog switch).
  • the data signal DATA ie, the gamma voltage Gamma
  • the data signal DATA ie, the gamma voltage Gamma
  • the second data signal in the Nth frame, the data signal DATA (ie, the gamma voltage Gamma) may be the second data signal.
  • FIG. 3B is another schematic structural diagram of a pixel driving circuit in an embodiment of the disclosure.
  • the pixel driving circuit shown in FIG. 3B may further include a sixth switch transistor M6 .
  • other circuit structures eg, the driving transistor M0, the first to fifth switching transistors M1 to M5, the storage capacitor Cst, etc.
  • the gate of the sixth switching transistor M6 is connected to the second voltage terminal to receive the second control voltage V_2, and the first pole of the sixth switching transistor M6 is connected to the third node N3 is connected, the second pole of the sixth switching transistor M6 is coupled with the first electrode (eg, anode) of the OLED light-emitting element, and the second electrode (eg, cathode) of the OLED light-emitting element is connected with the second power terminal to receive the second The power supply voltage VSS (ie the common voltage Vcom).
  • the sixth switching transistor M6 may be a P-type transistor, and embodiments of the present disclosure include but are not limited thereto.
  • the second control voltage V_2 may be zero voltage or ground voltage, or may be other fixed levels, such as a low voltage.
  • the sixth switching transistor M6 is basically kept in an on state under the control of the second control voltage V_2.
  • the storage capacitor Cst may be a capacitor device fabricated through a process, for example, a capacitor device may be realized by fabricating a special capacitor electrode, and each electrode of the capacitor may be fabricated through a metal layer, a semiconductor layer (eg, a doped electrode). Polysilicon), etc., and the capacitance can also be a parasitic capacitance between various devices, which can be realized by the transistor itself and other devices and lines.
  • the connection method of the capacitor is not limited to the method described above, and can also be other suitable connection methods, as long as the level of the corresponding node can be stored
  • the first node N1 , the second node N2 , the third node N3 and the fourth node N4 do not represent components that must actually exist, but rather represent the confluence of relevant electrical connections in the circuit diagram.
  • FIG. 4 is a schematic flowchart of a driving method of a display panel according to an embodiment of the disclosure. As shown in FIG. 4 , the driving method may include the following steps 401 to 402:
  • Step 401 In the Nth frame, based on the gray-scale data of the Nth frame, a first voltage is applied to the second electrode through the pixel driving circuit, and a first data signal matching the first voltage is applied to the first electrode; N is positive integer;
  • Step 402 In the N+1th frame, based on the grayscale data of the N+1th frame, apply a second voltage to the second electrode through the pixel driving circuit, and apply a second data signal matching the second voltage to the first electrode , wherein the first voltage and the second voltage are different.
  • the pixel driving circuit performs voltage adjustment on the display panel (including adjusting the voltage applied to the second electrode of the display panel and adjusting the voltage of the display panel).
  • the data signal applied to the first electrode of the display panel is adjusted) to implement different driving modes for the display panel according to different pictures, so that the dynamic contrast of the display panel can be increased.
  • the voltage applied to the second electrode may be a low voltage.
  • the first voltage or the second voltage may be a low voltage.
  • the absolute value of the first voltage when the highest grayscale of the Nth frame is greater than the highest grayscale of the N+1th frame, the absolute value of the first voltage may be greater than the absolute value of the second voltage (that is, when the N+1th frame When the highest gray level of the frame is smaller than the highest gray level of the Nth frame, the absolute value of the second voltage may be smaller than the absolute value of the first voltage).
  • the light-emitting element when displaying a lower gray scale, by reducing the voltage applied to the second electrode, the light-emitting element can have a lower luminous brightness. In this way, the brightness of the low gray scale can not only be greatly reduced, but also the dynamic contrast ratio of the display panel can be improved. Moreover, the power consumption of the display panel can also be reduced.
  • the absolute value of the first voltage when the lowest grayscale of the Nth frame is greater than the lowest grayscale of the N+1th frame, the absolute value of the first voltage may be greater than the absolute value of the second voltage (that is, when the N+1th frame When the lowest gray level of the frame is smaller than the lowest gray level of the Nth frame, the absolute value of the second voltage may be smaller than the absolute value of the first voltage).
  • the light-emitting element when displaying a lower gray scale, by reducing the voltage applied to the second electrode, the light-emitting element can have a lower luminous brightness. In this way, the brightness of the low gray scale can not only be greatly reduced, but also the dynamic contrast ratio of the display panel can be improved. Moreover, the power consumption of the display panel can also be reduced.
  • the data signal provided to the pixel in the first data signal and the data signal provided to the pixel in the second data signal may be Not the same. In this way, when the voltage applied to the second electrode is adjusted, the data signal applied to the first electrode can be adjusted at the same time, so that the gray scale brightness can be rematched, thereby forming a high dynamic contrast display effect.
  • the first data signal when the highest grayscale of the Nth frame is greater than the highest grayscale of the N+1th frame, the first data signal
  • the voltage of the data signal provided to the pixel in the second data signal may be smaller than the voltage of the data signal provided to the pixel in the second data signal.
  • the light-emitting element when displaying a lower grayscale, the light-emitting element can have a lower luminous brightness by reducing the voltage of the data signal applied to the first electrode. In this way, the brightness of the low grayscale can be greatly reduced and the brightness of the display panel can be improved. Dynamic contrast.
  • the first data signal when the lowest grayscale of the Nth frame is greater than the lowest grayscale of the N+1th frame, the first data signal
  • the voltage of the data signal provided to the pixel in the second data signal may be smaller than the voltage of the data signal provided to the pixel in the second data signal.
  • the light-emitting element when displaying a lower grayscale, the light-emitting element can have a lower luminance by reducing the voltage of the data signal applied to the first electrode. In this way, the brightness of the low grayscale can be greatly reduced and the display panel can be improved. Dynamic contrast.
  • the absolute value of the first voltage is not higher than the absolute value of the standard common voltage
  • the absolute value of the second voltage is not higher than the absolute value of the standard common voltage
  • the standard common voltage is for displaying a white picture voltage of the second electrode.
  • the voltage of the first data signal is not less than the standard gamma voltage
  • the voltage of the second data signal is not less than the standard gamma voltage
  • the standard gamma voltage is the voltage of the first electrode when a white picture is displayed Voltage.
  • the driving process of one frame period may include a reset phase S1 , a data writing phase S2 and a light-emitting phase S3 .
  • the timing waveforms of the respective control signals (including the reset control signal RS, the scan signal SN, the transmission control signal VT and the light emission control signal EM) in each stage are shown in FIG. 5 . in:
  • the reset control signal RS and the transfer control signal VT are input, the reset voltage Vinit is applied to the first electrode of the light-emitting element, and then the first electrode (eg, the anode) of the OLED light-emitting element is connected through the pixel driving circuit.
  • the second electrode (eg, the cathode) of the OLED light-emitting element is connected to the second power supply voltage VSS (ie, the common voltage Vcom), so that the light-emitting element is reset.
  • the reset control signal RS and the transmission control signal VT are input, the N-type first switch transistor M1 is turned on by the high level of the reset control signal RS, and the N-type third switch transistor M3 is transmitted The high level of the control signal VT is turned on; at the same time, the P-type second switch transistor M2 is turned off by the high level of the lighting control signal EM, and the N-type fourth switch transistor M4 is turned off by the low level of the scan signal SN, corresponding to Ground, the P-type fifth switch transistor M5 is turned off by the high level of the inverted signal SN' of the scan signal SN; in addition, the driving transistor M0 is driven by the level of the fourth node N4 (that is, in the process of displaying the previous frame of the picture) , the data signal DATA) stored in the storage capacitor Cst is turned on.
  • the scanning signal SN is input, the data signal DATA (i.e. the gamma voltage Gamma) is written into the gate of the driving transistor, and the written data signal DATA is stored by the storage capacitor Cst.
  • the data signal DATA i.e. the gamma voltage Gamma
  • the data signal DATA may be the first data signal
  • the data signal DATA ie, the gamma voltage Gamma
  • the data signal DATA ie, the gamma voltage Gamma
  • the second data signal ie, the gamma voltage Gamma
  • the N-type fourth switch transistor M4 is turned on by the high level of the scan signal SN, and correspondingly, the P-type fifth switch transistor M5 is turned on by the inverted signal SN' of the scan signal SN
  • the N-type first switch transistor M1 is turned off by the low level of the reset control signal RS
  • the P-type second switch transistor M2 is turned off by the high level of the light-emitting control signal EM
  • the N-type first switch transistor M2 is turned off by the high level of the light-emitting control signal EM
  • the three-switch transistor M3 is turned off by the low level of the transfer control signal VT.
  • the data signal DATA charges the first end of the storage capacitor Cst (that is, the fourth node N4, that is, the gate of the driving transistor M0), so that the potential of the first end of the storage capacitor Cst becomes the data signal DATA, and the driving transistor M0 is kept in a conducting state under the control of the data signal DATA.
  • the potential of the first end of the storage capacitor Cst (that is, the fourth node N4, that is, the gate of the driving transistor M0) is the data signal DATA, that is, the voltage information of the data signal DATA. It is stored in the storage capacitor Cst and used to control the driving transistor M0 to generate a driving current in the subsequent light-emitting stage S3.
  • the first power supply voltage VDD is applied to the first pole of the driving transistor, so that the driving transistor is based on the data signal DATA (ie the gamma voltage Gamma) of the gate of the driving transistor and the first pole of the driving transistor.
  • the power supply voltage VDD controls the voltage Vs of the second electrode of the driving transistor, and generates a driving current based on the voltage Vs of the second electrode of the driving transistor to drive the OLED light-emitting element to emit light.
  • the first electrode of the OLED light-emitting element is connected to the data signal DATA (ie, the gamma voltage Gamma), and the second electrode of the OLED light-emitting element is connected to the second power supply voltage VSS (ie the common voltage Vcom), so that the OLED The light-emitting element can emit light under the action of the driving current flowing through the driving transistor M0.
  • DATA data signal
  • VSS second power supply voltage VSS
  • the second power supply voltage VSS (ie the common voltage Vcom) may be the first voltage
  • the data signal DATA (ie the gamma voltage Gamma) may be the first data signal
  • the second power supply voltage VSS may be the second voltage
  • the data signal DATA may be the second data signal.
  • the first power supply voltage VDD may be a corresponding driving voltage determined by the grayscale data of the Nth frame, or, in the N+1th frame, the first power supply voltage VDD may be processed by The corresponding driving voltage is determined by the grayscale data of the N+1th frame.
  • the lighting control signal EM and the transmission control signal VT are input, the P-type second switching transistor M2 is turned on by the low level of the lighting control signal EM, and the N-type third switching transistor M3 is transmitted The high level of the control signal VT is turned on; at the same time, the N-type first switch transistor M1 is turned off by the low level of the reset control signal RS, and the N-type fourth switch transistor M4 is turned off by the low level of the scan signal SN.
  • the P-type fifth switch transistor M5 is turned off by the high level of the inverted signal SN' of the scan signal SN; in addition, the drive transistor M0 is turned off by the level of the fourth node N4 (that is, in the data writing phase S2, the storage capacitor The voltage of the data signal DATA stored in Cst) is turned on.
  • the first electrode of the OLED light-emitting element is connected to the data signal DATA (ie, the gamma voltage Gamma), and the second electrode of the OLED light-emitting element is connected to the second power supply voltage VSS (ie the common voltage Vcom), so that the OLED The light-emitting element can emit light under the action of the driving current flowing through the driving transistor M0.
  • DATA data signal
  • VSS second power supply voltage VSS
  • the reset phase may be the last several timings of one frame period or the first several timings of one frame period.
  • one frame period may include 9 timings from 0 to 8
  • the reset phase S1 may be a time period represented by timings 0 to 1
  • the reset phase may be a time period represented by timings 7 to 8.
  • the reset stage may also be other, and may be set by those skilled in the art according to actual conditions, which is not limited in this embodiment of the present disclosure.
  • the signal timing diagram shown in FIG. 5 is schematic.
  • the signal timing during operation may be determined according to actual needs, which is not limited by the embodiment of the present disclosure.
  • the driving method may further include the following steps 403 and 404 At least one of:
  • Step 403 In the reset phase of the Nth frame, a reset voltage is applied to the first electrode through the pixel driving circuit.
  • Step 404 in the reset phase of the N+1th frame, apply a reset voltage to the first electrode through the pixel driving circuit.
  • the reset voltage may be a low voltage, such as a ground voltage or a zero voltage, or the like. This embodiment of the present disclosure does not limit this.
  • the pixel driving circuit applies the reset voltage Vinit to the first electrode, so that the light-emitting element is reset (for example, for an exemplary implementation, please refer to the aforementioned reset phase S1 related descriptions, which will not be repeated here). Therefore, undesirable display phenomena such as afterimages caused by the accumulation of residual charges in the previous frame can be avoided, and further, the dynamic contrast and display effect of the display panel can be improved.
  • the driving method may further include the following step 405:
  • Step 405 Insert a blank frame between the Nth frame and the N+1th frame.
  • the pixel driving circuit switches the voltage signal applied to the second electrode from the first voltage to the third voltage.
  • the absolute value of the third voltage is smaller than the absolute value of the first voltage
  • the absolute value of the third voltage is smaller than the absolute value of the second voltage.
  • the third voltage may be zero voltage.
  • the first voltage may be a level less than 0, and the second voltage may be a level less than 0.
  • the driving method may further include the following step 406:
  • Step 406 In the blank frame, cut off the electrical connection between the first power supply terminal and the driving transistor. In this way, the power supply voltage output by the first power supply terminal cannot be applied to the driving transistor, so that the light-emitting element stops emitting light in the blank frame. In this way, undesirable display phenomena such as afterimages caused by the accumulation of residual charges in the previous frame (eg, the Nth frame) of the blank frame can be avoided, thereby further improving the dynamic contrast and further improving the display effect. In addition, the power consumption of the display panel can also be reduced.
  • the input of the transmission control signal VT may be stopped (other control signals still maintain the state in the light-emitting phase S3),
  • the transmission control signal VT changes from a high level to a low level, so that the third switching transistor M3 is turned off, so that the electrical connection between the first power supply terminal and the driving transistor is disconnected, so that the first power supply voltage VDD cannot be applied to the driving transistor.
  • the driving transistor M0 cannot generate a driving current, and the OLED light-emitting element stops emitting light.
  • cutting off the electrical connection between the first power supply terminal and the driving transistor can also be implemented in other manners, and is not limited to the above manner.
  • it can be realized by controlling whether the light emission control signal EM is input, or by controlling whether the light emission control signal EM and the transmission control signal VT are input.
  • this embodiment of the present disclosure does not limit this.
  • the following takes the N+1th frame as an example to describe how to determine the second data signal applied to the first electrode and the second voltage applied to the second electrode through the pixel driving circuit based on the grayscale data of the N+1th frame .
  • step 402 may include the following steps 4021 to 4025:
  • Step 4021 Determine a first gray level based on the gray level data of the N+1th frame.
  • step 4021 may include, but is not limited to, the following three ways:
  • Mode 1 From the grayscale data of the N+1th frame, determine the highest grayscale; determine the highest grayscale as the first grayscale.
  • Gmax can be determined as the first grayscale.
  • the process of reading the highest gray level GL in the gray level data of the N+1th frame through an image algorithm may be as follows:
  • FIG. 6 is a schematic diagram of the geometric position markers of pixels when n is 25 as an example.
  • the process of finding the highest gray level may include the following steps 1) to 4):
  • Step 1) Record the gray scale of (x1, y1) to A;
  • Step 2) Record the gray scale of (x2, y2) to B;
  • Step 3) Compare A and B to get the larger value of the two and record it to A;
  • Step 4) Repeat the above steps 1) to 3) until the maximum gray level point (xm, ym) is compared, and the gray level of the point (xm, ym) is recorded as the highest gray level GL.
  • Method 2 Determine the highest top X gray levels from the gray level data of the N+1th frame; determine the average value of the highest top X gray levels as the first gray level; where X is greater than 1 positive integer.
  • the mean value Gmean of Gmax1, Gmax2, and Gmax3 can be determined. for the first grayscale.
  • Gmean (Gmax1+Gmax2+Gmax3)/3.
  • Mode 3 From the grayscale data of the N+1th frame, determine the grayscale located in the preset area; determine the highest grayscale among the grayscales located in the preset area as the first grayscale.
  • the preset area may refer to the person P In the area where the character P is located, it is assumed that the gray-scale data of the area where the character P is located in the gray-scale data of the N+1th frame is between G0 and Gp, and Gp is the highest gray-scale in the area where the character P is located. Then, Gp can be determined as first grayscale.
  • the preset area may be an area where a target object is located, such as a target person, a target object, and the like.
  • the preset area may be a center area of the picture with a preset size in the N+1th frame.
  • the preset area may also be other, which can be determined by those skilled in the art according to the actual situation, which is not limited in the embodiments of the present disclosure.
  • the number of preset regions may be one or more. It can be determined by those skilled in the art according to the actual situation, which is not limited by the embodiments of the present disclosure.
  • Step 4022 Determine the first light emission brightness corresponding to the first grayscale according to the pre-established first mapping relationship.
  • the first mapping relationship is used to describe the relationship between the gray scale and the luminous brightness when the display panel is driven by applying a standard common voltage to the second electrode and applying a standard gamma voltage to the first electrode.
  • the standard common voltage is the voltage of the second electrode when the white screen is displayed by adjusting the optical parameters in the debugging stage of the display module of the display panel;
  • the standard gamma voltage is the adjustment stage of the display module of the display panel, adjusting the optical parameters The voltage of the first electrode when displaying a white picture under the obtained standard gamma value.
  • the standard common voltage (standard Vcom) and the standard gamma voltage (standard Gamma) are obtained by debugging optical parameters, and the standard Vcom and standard Gamma are recorded at the same time.
  • Different luminous brightness corresponding to different gray scales under Gamma ie, the brightness of the display module in the display panel
  • the data table A1 shown in FIG. 7 ie, the above-mentioned first mapping relationship
  • the first luminous brightness corresponding to the first gray level can be obtained by searching the first mapping relationship.
  • Step 4023 Determine whether there is a mapping relationship matching the first luminous intensity in the at least one pre-established second mapping relationship.
  • the second mapping relationship is used to describe the mapping relationship between the candidate common voltage and the light emission brightness and the candidate gamma voltage.
  • step 4024 may be executed to drive the light-emitting element by using the adjusted driving voltage.
  • step 4025 may be executed to drive the light-emitting element by using a standard driving voltage.
  • Step 4024 Apply the candidate common voltage in the matched mapping relationship as the second voltage to the second electrode, and apply the matched candidate gamma voltage in the mapping relationship as the second data signal to the first electrode.
  • Step 4025 Apply the standard common voltage as the second voltage to the second electrodes, and apply the standard gamma voltage as the second data signal to the first electrodes.
  • step 4023 may include the following steps 4023a to 4023d:
  • Step 4023a Compare the first luminous intensity with the luminous intensity in at least one second mapping relationship.
  • the second mapping relationship is used to describe the mapping relationship between the candidate common voltage and the light emission brightness and the candidate gamma voltage.
  • Step 4023b According to the comparison result, determine whether there is a second light-emitting luminance matching the first light-emitting luminance among the light-emitting luminances in the at least one second mapping relationship.
  • step 4023c If there is a second light-emitting luminance matching the first light-emitting luminance among the light-emitting luminances in at least one second mapping relationship, step 4023c may be performed. If there is no second light emission luminance matching the first light emission luminance among the light emission luminances in the at least one second mapping relationship, step 4023d may be executed.
  • Step 4023c Determine that there is a mapping relationship matching the first luminous brightness value in at least one second mapping relationship.
  • Step 4023d Determine that there is no mapping relationship matching the first luminous intensity value in the at least one second mapping relationship.
  • step 4023b may include but is not limited to the following three situations:
  • Case 1 if the first luminous intensity is less than the minimum luminous intensity among the luminous luminosity in the at least one second mapping relationship, it is determined that there is a second luminous intensity matching the first luminous intensity in the luminous intensity in the at least one second mapping relationship, Wherein, the second light-emitting brightness is the minimum light-emitting brightness.
  • Case 2 If the first luminous brightness is less than the maximum luminous brightness among the luminous luminances in the at least one second mapping relationship, and not less than the other luminous luminances except the maximum luminous brightness among the luminous luminances in the at least one second mapping relationship, It is determined that there is a second light-emitting luminance matching the first light-emitting luminance value in the light-emitting luminance in at least one second mapping relationship, wherein the second light-emitting luminance is the maximum light-emitting luminance.
  • Case 3 If the first luminous intensity is in the luminous intensity interval formed by two adjacent luminous intensities in the at least one second mapping relationship, it is determined that there is a difference between the luminous intensity in the at least one second mapping relationship and the first luminous intensity.
  • the second light-emitting luminance is matched with the light-emitting luminance, wherein the second light-emitting luminance is the light-emitting luminance corresponding to the larger end point of the light-emitting luminance interval.
  • Vcom common voltages
  • VSS the second power supply voltage
  • VSS the second power supply voltage
  • different matching gammas are obtained.
  • the voltage Gamma ie, the data signal DATA applied to the first electrode of the light-emitting element
  • the matching table A2 shown in Table 1 below ie, the above-mentioned second mapping relationship
  • Vcom1, Vcom2 and Vcom3 are smaller than the standard Vcom; L1 is smaller than L2, and L2 is smaller than L3.
  • the driving method will be described. Whether the first luminous brightness is less than L1; if the first luminous brightness is less than L1, it indicates that there is a second luminous brightness matching the first luminous brightness in the luminous brightness in the second mapping relationship (at this time, the second luminous brightness is L1), Then, Vcom1 can be applied to the second electrode through the pixel driving circuit, and Gamma1 corresponding to Vcom1 can be applied to the first electrode; if the first light-emitting brightness is not less than L1, it can be judged whether the first light-emitting brightness is less than L2; Next, If the first light-emitting brightness is less than L2, it indicates that there is a second light-emitting brightness matching the first light-emitting brightness in the light-emitting brightness in the second mapping relationship (at this time, the second light-emitting brightness is L2), then Vcom2 can be set by the pixel driving circuit Apply to the second electrode, and apply
  • the corresponding Gamma3 is applied to the first electrode; if the first light-emitting luminance is not less than L3, it indicates that there is no second light-emitting luminance matching the first light-emitting luminance in the light-emitting luminance in the second mapping relationship, then the pixel driving circuit can pass the standard Vcom is applied to the second electrode and standard Gamma is applied to the first electrode.
  • step 402 may further include the following steps 4026 to 4028:
  • Step 4026 According to the pre-established third mapping relationship, determine a second grayscale corresponding to the luminous brightness in the matched mapping relationship.
  • the third mapping relationship is used to describe the relationship between the gray scale and the luminous brightness when the display panel is driven by the candidate common voltage and the candidate gamma voltage in the matched mapping relationship.
  • a candidate common voltage (different from the standard Vcom) and a candidate gamma voltage (different from the standard Gamma) are obtained, and these values are recorded at the same time.
  • the candidate common voltage (candidate Vcom) and the candidate gamma voltage (candidate Gamma) the different luminous brightnesses corresponding to different gray scales (that is, the brightness of the display module in the display panel), in this way, the third mapping relationship (with the table below) can be obtained. 1 is similar, only the driving voltage is different, so I won't go into details here).
  • mapping relationship a mapping relationship matching the first luminous brightness in the at least one pre-established second mapping relationship, according to the luminous brightness in the matched mapping relationship (that is, the above-mentioned second luminous brightness) According to the mapping relationship, a second gray scale corresponding to the luminous intensity in the matched mapping relationship (ie, the above-mentioned second luminous intensity) can be obtained.
  • Step 4027 Multiply the grayscale data of the N+1th frame by the ratio between the first grayscale and the second grayscale to obtain the processed grayscale data of the N+1th frame.
  • Step 4028 Apply the driving voltage corresponding to the processed grayscale data of the N+1th frame to the driving transistor.
  • the corresponding driving voltage (ie, the first power supply voltage VDD) determined by the processed gray-scale data of the N+1 th frame is applied to the driving transistor the first pole, so that the driving transistor controls the voltage Vs of the second pole of the driving transistor according to the data signal DATA (ie the gamma voltage Gamma) of the gate of the driving transistor and the first power supply voltage VDD of the first pole of the driving transistor, and A driving current is generated based on the voltage Vs of the second electrode of the driving transistor to drive the OLED light-emitting element to emit light.
  • the data signal DATA ie the gamma voltage Gamma
  • the first data signal applied to the first electrode and the first voltage applied to the second electrode through the pixel driving circuit determines the first data signal applied to the first electrode and the first voltage applied to the second electrode through the pixel driving circuit, and the above grayscale data based on the N+1th frame is determined.
  • the descriptions of the second data signal applied to the first electrode and the second voltage applied to the second electrode by the pixel driving circuit are similar, please refer to the relevant description in the embodiments of the present disclosure to understand, do not do it here More to say.
  • the pixel driving circuit can apply the first voltage to the second electrode, and apply the same voltage to the first electrode to the first electrode.
  • the voltage-matched first data signal; N is a positive integer; in the N+1th frame, a second voltage can be applied to the second electrode through the pixel driving circuit based on the grayscale data of the N+1th frame, and the first electrode A second data signal matching the second voltage is applied, wherein the first voltage and the second voltage are different.
  • FIG. 8A is a signal timing diagram of the driving method of the display panel provided by the embodiment of the present disclosure
  • FIG. 8B is another signal timing diagram of the driving method of the display panel provided by the embodiment of the present disclosure.
  • the voltage levels of the signal timing diagrams shown in FIG. 8A and FIG. 8B are only schematic, and do not represent actual voltage values or relative proportions.
  • the following describes a method for driving a display panel provided by an embodiment of the present disclosure with reference to the signal timing diagrams shown in FIG. 8A and FIG. 8B .
  • Step 1 Read the highest gray level GL (ie, the first gray level above) in the gray level data of the N+1th frame through an image algorithm.
  • the process of reading the highest grayscale GL can be as follows:
  • a1) Mark the geometric position of each pixel in the whole picture of the N+1th frame, such as (x1, y1), (x2, y2), , (xn, yn).
  • the process of finding the global maximum value may include the following steps 11) to 14):
  • Step 11 record the gray scale of (x1, y1) to A;
  • Step 12 record the gray scale of (x2, y2) to B;
  • Step 13 compare A and B to obtain the larger value in both and record to A;
  • Step 14 repeating the process from step 1 to step 3, until the maximum gray level point (xm, ym) is compared, and the gray level of the point (xm, ym) is recorded as the highest gray level GL.
  • Step 2 using the highest gray level GL to search inversely the highest brightness L output by the product (ie, the above-mentioned first luminous brightness corresponding to the first gray level).
  • the process of finding the highest brightness L can be as follows:
  • the standard common voltage (standard Vcom) and the standard gamma voltage (standard Gamma) are obtained by debugging the optical parameters of the display module.
  • the display panel is driven by standard Vcom and standard Gamma, the brightness of each grayscale and its corresponding module (that is, the above-mentioned luminous brightness) is recorded, so that the different grayscales and their corresponding The luminous brightness can be obtained from the data table A1 shown in FIG. 7 (ie, the above-mentioned first mapping relationship).
  • step b2) according to the highest gray level GL obtained in step 1, inversely check the data table A1, the highest brightness L that the product needs to output can be obtained.
  • Step 3 Search through the highest luminance L to obtain the best Vcom (ie, the above-mentioned second voltage) and the best Gamma (ie, the above-mentioned first data signal) adapted to the best Vcom.
  • the process of finding the best Vcom and the best Gamma adapted to the best Vcom can be as follows:
  • Step 31 judge whether L is less than L1;
  • Step 32 if L is less than L1, then use Vcom1 and the Gamma1 that matches this Vcom1 as the best Vcom and the best Gamma of its adaptation; if L is not less than L1, then judge whether L is less than L2;
  • Step 33 if L is less than L2, then use Vcom2 and the Gamma2 matched with this Vcom2 as the best Vcom and the best Gamma of its adaptation; if L is not less than L2, judge whether L is less than L3;
  • Step 34 if L is less than L3, use Vcom3 and the Gamma3 that matches the Vcom23; if L is not less than L3, use the standard Vcom and the standard Gamma that matches the standard Vcom as the best Vcom and the best fit for it. Gamma.
  • Step 4 Process the grayscale data of the N+1th frame according to the ratio between the first grayscale and the actual grayscale (ie, the second grayscale) of the brightest luminance L under the optimal Vcom and the best Gamma. , to obtain the processed grayscale data of the N+1th frame.
  • the grayscale data of the N+1th frame is multiplied by the ratio between the first grayscale and the second grayscale to obtain the processed grayscale data of the N+1th frame.
  • the second power supply voltage VSS (ie, the common voltage Vcom) connected to the second electrode of the light-emitting element in the Nth frame is the first voltage V1, and in the Nth frame and the N+1th frame In the blank frame between, the second power supply voltage VSS (ie the common voltage Vcom) connected to the second electrode of the light-emitting element is switched from the first voltage V1 to the third voltage V3, and the second power supply voltage VSS of the light-emitting element is connected in the N+1th frame.
  • VSS the common voltage Vcom
  • the second power supply voltage VSS (that is, the common voltage Vcom) of the electrode is switched from the third voltage V3 to the second voltage V2 (that is, the above-mentioned optimum Vcom); the data of the first electrode of the second electrode of the light-emitting element is connected in the Nth frame
  • the signal DATA (ie the gamma voltage Gamma) is the first data signal G1, and the blank frame between the Nth frame and the N+1th frame will be connected to the data signal DATA (ie the gamma voltage Gamma) of the first electrode of the light-emitting element ) switch from the first data signal G1 to the second data signal G2 (that is, the above-mentioned optimal Gamma adapted to the optimal Vcom), and the second data signal is connected to the second electrode of the light-emitting element in the N+1th frame G2 (that is, the above-mentioned best Gamma adapted to the best Vcom); the blank frame between the Nth frame and the N+1th frame
  • the third voltage V3 may be equal to zero voltage, wherein the absolute value of the third voltage V3 is less than the absolute value of the first voltage V1 , and the absolute value of the third voltage V3 is less than The absolute value of the second voltage V2.
  • the absolute value of the optimal Vcom is not higher than the absolute value of the standard Vcom, and the optimal Gamma is not smaller than the standard Gamma. In this way, not only the brightness of low gray scales can be greatly reduced, the dynamic contrast ratio of the display panel can be increased, but also the power consumption of the display panel can be reduced.
  • the second electrode of the second electrode of the light-emitting element can be connected to the second
  • the power supply voltage VSS (ie the common voltage Vcom) is switched from the second voltage V2 to the third voltage V3, and the blank frame between the N+2th frame and the N+3th frame can be connected to the second electrode of the light-emitting element.
  • the two power supply voltages VSS (ie the common voltage Vcom) are switched from the fourth voltage V4 to the third voltage V3, wherein the absolute value of the third voltage V3 is smaller than the absolute value of the fourth voltage V4.
  • the voltage can be adjusted according to different pictures, so the waveform of the second power supply voltage VSS (ie the common voltage Vcom) connected to the second electrode of the light-emitting element can be adjusted according to the picture
  • VSS the common voltage Vcom
  • the update frequency is floating.
  • FIG. 9A shows the display result of the display panel obtained when the driving voltage of the display panel is not adjusted (that is, the voltage of the second electrode and the voltage of the first electrode of the light-emitting element are not adjusted)
  • FIG. 9B shows The display result of the display panel obtained when only the voltage of the second electrode of the light-emitting element of the display panel is adjusted is shown
  • FIG. 9C shows the display panel when the display panel is driven by the driving method of the display panel provided by the embodiment of the present disclosure. The resulting display panel display results. Comparing the display results in FIG. 9B and FIG. 9A , it can be seen that although the display brightness of the two display panels is different, the contrast ratio is the same. Comparing the display results in FIG. 9C and FIG.
  • the pixel driving circuit performs voltage adjustment on the display panel (including: dynamically adjusting the voltage applied to the second electrode of the display panel) and dynamically adjusting the data signal applied to the first electrode of the display panel) to implement different driving modes for the display panel according to different pictures, so that the dynamic contrast of the display panel can be increased and the display effect can be improved.
  • the present disclosure also provides a driving device.
  • the driving device may include a processor, a memory, and a computer program stored in the memory and running on the processor, wherein, when the processor executes the computer program, the steps of the method for driving a display panel in any of the foregoing embodiments of the present disclosure are implemented .
  • FIG. 10 is a schematic structural diagram of a driving device in an embodiment of the disclosure.
  • the driving device 100 includes: at least one processor 1001 ; A memory 1002 and a bus 1003; wherein, the processor 1001 and the memory 1002 communicate with each other through the bus 1003; the processor 1001 is used to call program instructions in the memory 1002 to execute the drive of the display panel in any of the above embodiments steps of the method.
  • the processor can be a central processing unit (Central Processing Unit, CPU), a microprocessor (Micro Processor Unit, MPU), a digital signal processor (Digital Signal Processor, DSP), an application specific integrated circuit (ASIC), an off-the-shelf programmable gate array (Field Programmable Gate Array, FPGA), transistor logic devices, etc., which are not limited in this disclosure.
  • CPU Central Processing Unit
  • MPU Micro Processor Unit
  • DSP Digital Signal Processor
  • ASIC application specific integrated circuit
  • FPGA Field Programmable Gate Array
  • transistor logic devices etc., which are not limited in this disclosure.
  • the memory may include Read Only Memory (ROM) and Random Access Memory (RAM), and provide instructions and data to the processor.
  • a portion of the memory may also include non-volatile random access memory.
  • the memory may also store device type information.
  • the bus may also include a power bus, a control bus, a status signal bus, and the like.
  • the various buses are labeled as buses in FIG. 9 .
  • the processing performed by the processing device may be completed by hardware integrated logic circuits in the processor or instructions in the form of software. That is, the method steps in the embodiments of the present disclosure may be embodied as executed by a hardware processor, or executed by a combination of hardware and software modules in the processor.
  • the software modules may be located in random access memory, flash memory, read-only memory, programmable read-only memory or electrically erasable programmable memory, registers and other storage media.
  • the storage medium is located in the memory, and the processor reads the information in the memory, and completes the steps of the above method in combination with its hardware. To avoid repetition, detailed description is omitted here.
  • the present disclosure also provides a display device.
  • the display setting may include: the display panel provided by any of the above-mentioned embodiments of the present disclosure and the driving device provided by any of the above-mentioned embodiments of the present disclosure.
  • the display device may be any product with a display function, such as a mobile phone, a tablet computer, a television, a notebook computer, a navigator, an electronic paper display device, a digital photo frame, a virtual reality device, an augmented reality device, etc. part.
  • the display device may also include other conventional components or structures.
  • those skilled in the art may set other conventional components or structures according to actual application scenarios. Do limit.
  • the present disclosure also provides a computer-readable storage medium, where the computer-readable storage medium stores executable instructions, which, when executed by a processor, can implement any of the above-mentioned aspects of the present disclosure
  • Embodiments provide a driving method of a display panel.
  • the driving method of the display panel can be used to drive the display panel provided by the above-mentioned embodiments of the present disclosure to display, thereby improving the contrast of the display screen and improving the display effect.
  • the above-mentioned computer-readable storage medium may be, for example, a ROM/RAM, a magnetic disk, an optical disk, and the like. This disclosure does not limit this.
  • Computer storage media includes both volatile and nonvolatile implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data flexible, removable and non-removable media.
  • Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disk (DVD) or other optical disk storage, magnetic cartridges, magnetic tape, magnetic disk storage or other magnetic storage devices, or may Any other medium used to store desired information and which can be accessed by a computer.
  • communication media typically embodies computer readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and can include any information delivery media, as is well known to those of ordinary skill in the art .

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Abstract

一种显示面板的驱动方法、存储介质、驱动设备及显示设备，所述驱动方法包括：在第N帧，基于所述第N帧的灰阶数据，通过所述像素驱动电路向所述第二电极施加第一电压，并向所述第一电极施加与第一电压匹配的第一数据信号；N为正整数；在第N+1帧，基于所述第N+1帧的灰阶数据，通过所述像素驱动电路向所述第二电极施加第二电压，并向所述第一电极施加与第二电压匹配的第二数据信号，其中，所述第一电压和所述第二电压不相同。

Description

显示面板的驱动方法、存储介质、驱动设备及显示设备 技术领域
本公开实施例涉及但不限于显示技术领域，尤指一种显示面板的驱动方法、存储介质、驱动设备及显示设备。
背景技术
有机发光二极管(Organic Light-Emitting Diode，OLED)显示面板具有厚度薄、质量轻、宽视角、主动发光、发光颜色连续可调、成本低、响应速度快、能耗小、驱动电压低、工作温度范围宽、生产工艺简单、发光效率高及可柔性显示等优点，在手机、平板电脑、数码相机等显示领域的应用越来越广泛。
目前，在驱动OLED显示面板显示画面的过程中，当低灰阶下亮度偏高时，会导致显示面板所表现出来的动态对比度较低。例如，当画面的最亮亮度较低(例如为规格书里的最高亮度的1/2)，而最低亮度较高(例如为规格书里的最低亮度的2倍)时，那么，在此画面下显示面板所表现出来的动态对比度就只有规格书里的1/4。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
一方面，本公开实施例提供了一种显示面板的驱动方法，其中，
所述显示面板，包括：依次叠设的衬底基板、像素驱动电路和发光元件，所述发光元件包括：依次叠设的第一电极、有机发光层和第二电极，所述像素驱动电路包括：与所述第一电极耦接的驱动晶体管、与所述驱动晶体管耦接的第一电源端和与所述第二电极耦接的第二电源端；
所述驱动方法，包括：在第N帧，基于所述第N帧的灰阶数据，通过所述像素驱动电路向所述第二电极施加第一电压，并向所述第一电极施加与第一电压匹配的第一数据信号；在第N+1帧，基于所述第N+1帧的灰阶数据， 通过所述像素驱动电路向所述第二电极施加第二电压，并向所述第一电极施加与第二电压匹配的第二数据信号，其中，所述第一电压和所述第二电压不相同；N为正整数。
另一方面，本公开实施例还提供了一种计算机可读存储介质，存储有计算机可执行指令，所述计算机可执行指令用于执行上述的显示面板的驱动方法的步骤。
另一方面，本公开实施例还提供了一种驱动设备，包括：存储器、处理器及存储在存储器上并可在处理器上运行的计算机程序，其中，所述处理器执行所述程序时实现如上述的显示面板的驱动方法的步骤。
另一方面，本公开实施例还提供了一种显示设备，包括：显示面板和如上述的驱动设备。
当然，实施本公开的任一产品或方法并不一定要同时达到以上所述的所有优点。本公开的其它特征和优点将在随后的说明书实施例中阐述，或者通过实施本公开而了解。本公开实施例的目的和其他优点可通过在说明书、权利要求书以及附图中所特别指出的结构来实现和获得。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
附图用来提供对本公开技术方案的进一步理解，并且构成说明书的一部分，与本公开实施例一起用于解释本公开的技术方案，并不构成对本公开技术方案的限制。附图中各部件的形状和大小不反映真实比例，目的只是示意说明本公开内容。
图1为本公开实施例中的显示面板的结构示意图；
图2为本公开实施例中的显示面板的示意框图；
图3A为本公开实施例中的像素驱动电路的一种结构示意图；
图3B为本公开实施例中的像素驱动电路的另一种结构示意图；
图4为本公开实施例中的显示面板的驱动方法的流程示意图；
图5为本公开实施例中一帧的示意图；
图6为本公开实施例中的像素的几何位置标记的示意图；
图7为本公开实施例中的灰阶与亮度之间的映射关系的示意图；
图8A为本公开实施例提供的显示面板的驱动方法的一种信号时序图；
图8B为本公开实施例提供的显示面板的驱动方法的另一种信号时序图；
图9A为未对显示面板的驱动电压进行调整时的显示面板的显示结果图；
图9B为仅对显示面板的发光元件的第二电极的电压进行调整时的显示面板的显示结果图；
图9C为采用本公开实施例所提供的显示面板的驱动方法来驱动显示面板时所得到的显示面板的显示结果图；
图10为本公开实施例中的驱动设备的结构示意图。
具体实施方式
本文描述了多个实施例，但是该描述是示例性的，而不是限制性的，在本文所描述的实施例包含的范围内可以有更多的实施例和实现方案。尽管在附图中示出了许多可能的特征组合，并在具体实施方式中进行了讨论，但是所公开的特征的许多其它组合方式也是可能的。除非特意加以限制的情况以外，任何实施例的任何特征或元件可以与任何其它实施例中的任何其他特征或元件结合使用，或可以替代任何其它实施例中的任何其他特征或元件。
在描述具有代表性的实施例时，说明书可能已经将方法和/或过程呈现为特定的步骤序列。然而，在该方法或过程不依赖于本文所述步骤的特定顺序的程度上，该方法或过程不应限于所述的特定顺序的步骤。如本领域普通技术人员将理解的，其它的步骤顺序也是可能的。因此，说明书中阐述的步骤的特定顺序不应被解释为对权利要求的限制。此外，针对该方法和/或过程的权利要求不应限于按照所写顺序执行它们的步骤，本领域技术人员可以容易地理解，这些顺序可以变化，并且仍然保持在本公开实施例的精神和范围内。
除非另外定义，本公开实施例使用的技术术语或者科学术语应当为本发明所属领域内具有一般技能的人士所理解的通常意义。本公开实施例中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性， 而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”、“耦接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。例如，描述一些实施例时可能使用了术语“耦接”以表明两个或两个以上部件有直接物理接触或电接触。然而，术语“耦接”或“通信耦合(communicatively coupled)”也可能指两个或两个以上部件彼此间并无直接接触，但仍彼此协作或相互作用。这里所公开的实施例并不必然限制于本文内容。
在本文中，晶体管是指至少包括栅电极(或称栅极)、漏电极以及源电极这三个端子的元件。晶体管在漏电极(或称漏电极端子、漏区域或漏极)与源电极(或称源电极端子、源区域或源极)之间具有沟道区域，并且电流能够流过漏电极、沟道区域以及源电极。在本文中，沟道区域是指电流主要流过的区域。
在本文中，第一极可以为漏电极、第二极可以为源电极，或者第一极可以为源电极、第二极可以为漏电极。在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况下，“源电极”及“漏电极”的功能有时可以互相调换。因此，在本文中，“源电极”和“漏电极”可以互相调换。
在本文中，“电连接”包括构成要素通过具有某种电作用的元件连接在一起的情况。“具有某种电作用的元件”只要可以进行连接的构成要素间的电信号的授受，就对其没有特别的限制。“具有某种电作用的元件”例如可以是电极或布线，或者是晶体管等开关元件，或者是电阻器、电感器或电容器等其它功能元件等。
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述。
本公开实施例提供一种显示面板的驱动方法。在实际应用中，该显示面板的驱动方法可以应用于显示面板中。
该显示面板可以包括：依次叠设的衬底基板、像素驱动电路和发光元件，其中，该发光元件可以包括：依次叠设的第一电极、有机发光层和第二电极， 该像素驱动电路可以包括：与第一电极耦接的驱动晶体管、与驱动晶体管耦接的第一电源端和与第二电极耦接的第二电源端。
在一种示例性实施例中，发光元件的数量可以为多个，对应地，像素驱动电路的数量可以为多个，其中，多个像素驱动电路分别用于驱动后续形成的多个发光元件。这里，像素驱动电路的电路结构及布局可以根据实际情况进行设计，本公开实施例对此不做限定。
在一种示例性实施例中，发光元件可以包括但不限于有机发光二极管(Organic Light-Emitting Diode，OLED)、量子点发光二极管(Quantum Dot Light Emitting Diodes，QLED)和无机发光二极管中的任意一种。例如，发光元件可以采用如Micro-LED、Mini-LED等微米级发光元件。
在一种示例性实施例中，上述显示面板可以包括但不限于OLED显示面板、QLED显示面板等，本公开实施例对此不做限定。
在一种示例性实施例中，衬底基板可以是柔性基板，或者可以是刚性基板。柔性基板可以包括叠设的第一柔性材料层、第一无机材料层、半导体层、第二柔性材料层和第二无机材料层，第一柔性材料层和第二柔性材料层的材料可以采用聚酰亚胺(PI)、聚对苯二甲酸乙二酯(PET)或经表面处理的聚合物软膜等材料，第一无机材料层和第二无机材料层的材料可以采用氮化硅(SiNx)或氧化硅(SiOx)等，用于提高基板的抗水氧能力，半导体层的材料可以采用非晶硅(a-si)。例如，衬底基板可以为硅基衬底基板。
在一种示例性实施例中，第一电极，可以作为阳极。例如，第一电极可以通过钨金属填充的过孔(即钨过孔，W-via)与对应的像素驱动电路中的驱动晶体管的源电极电连接(经由源电极对应的连接部)，或者，第一电极也可以与漏电极电连接。
在一种示例性实施例中，第二电极，可以作为阴极。例如，第二电极可以为透明电极。例如，第二电极可以为公共电极，即多个发光元件共用一整面的第二电极。
下面以发光元件为OLED、以显示面板为硅基OLED显示面板为例，对显示面板进行说明。
图1为本公开实施例中的显示面板的结构示意图。为了清晰和简洁，图1仅示意性地示出了三个发光元件和三个像素驱动电路中的一个驱动晶体管T1，该驱动晶体管T1用于与后续形成的发光元件耦接。例如，显示面板还可以包括扫描信号线和数据信号线等各种走线，本公开对此不作限制。
在一种示例性实施例中，如图1所示，该硅基OLED显示面板可以包括：依次叠设的硅基衬底基板10、多个像素驱动电路11和多个发光元件12。其中，每个发光元件12可以包括依次叠设的第一电极121(例如，作为阳极)、有机发光层122和第二电极123(例如，作为阴极)；每个像素驱动电路可以包括：与第一电极121耦接的驱动晶体管T1、与驱动晶体管T1耦接的第一电源端(图1中未示出)和与第二电极123耦接的第二电源端(图1中未示出)。
在一种示例性实施例中，第二电极123可以为透明电极。例如，第二电极123可以为公共电极，即多个发光元件12可以共用一整面的第二电极123。
在一种示例性实施例中，如图1所示，驱动晶体管T1可以包括：栅电极G、源电极S和漏电极D。例如，该三个电极分别与三个电极连接部电连接，例如通过钨金属填充的过孔(即钨过孔，W-via)进行电连接；进而，该三个电极可以分别通过对应的电极连接部与其它电学结构(例如，晶体管、走线、发光元件等)进行电连接。
在一种示例性实施例中，OLED发光元件的有机发光层可以包括发光层(Emitting Layer，EML)，以及包括空穴注入层(Hole Injection Layer，HIL)、空穴传输层(Hole Transport Layer，HTL)、空穴阻挡层(Hole Block Layer，HBL)、电子阻挡层(Electron Block Layer，EBL)、电子注入层(Electron Injection Layer，EIL)、电子传输层(Electron Transport Layer，ETL)中的一个或多个膜层。在阳极和阴极的电压驱动下，利用有机材料的发光特性根据需要的灰度发光。
在一种示例性实施例中，有机发光层可以通过采用精细金属掩模版(Fine Metal Mask，FMM)蒸镀制备形成，或者采用开放式掩膜版(Open Mask)蒸镀制备形成，或者采用喷墨工艺制备形成。
在一种示例性实施例中，硅基衬底基板和像素驱动电路可以由前端的晶 圆厂对单晶硅晶圆(wafer)进行工艺处理而制作完成。
在一种示例性实施例中，如图1所示，该硅基OLED显示器件还可以包括：依次设置在多个发光元件12之上的第一封装层13、彩色滤光层14、第二封装层15和盖板16。例如，第一封装层13和第二封装层15可以为聚合物或/和陶瓷薄膜封装层，但不限于此。例如，彩色滤光层14可以包括红色滤光单元R、绿色滤光单元G和蓝色滤光单元R，但不限于此。例如，一个滤光单元与对应的发光元件及像素驱动电路可以划分为一个子像素；例如，红色滤光单元R、绿色滤光单元G和蓝色滤光单元R分别对应红色子像素、绿色子像素和蓝色子像素。例如，盖板16可以为玻璃盖板，但不限于此。
在一种示例性实施例中，包括第一电极、有机发光层和第二电极的发光元件、第一封装层、彩色滤光层、第二封装层和盖板均可以在后端的面板厂制作完成。
此外，图1仅示例性地示出了硅基OLED显示面板的显示区(也称为有源区，Active Aera，AA)的结构。该硅基OLED显示面板还可以包括非显示区(除显示区之外的区域)，例如，根据非显示区中的各个区域的结构和功能的不同，非显示区域还可以进一步划分为虚设区(Dummy Area，DA)、绑定区(Bonding Area，BA)、集成电路功能区(IC function block)等。例如，虚设区的结构与显示区基本相同，可以用于保证显示区的均一性；例如，绑定区可以包括焊盘，用于与外界电路的电连接以及信号的传输；例如，集成电路功能区可以用于设置栅电极驱动电路(例如，采用GOA(Gate driver On Array)技术形成栅电极驱动电路)和具有其他功能的电路等。
图2为本公开实施例中显示面板的示意框图。如图2所示，该显示面板可以包括：像素驱动电路和发光元件，该像素驱动电路可以包括：驱动晶体管M0、第一电源端111和第二电源端112，驱动晶体管M0可以包括：栅极113、第二极115、以及与第一电源端111耦接的第一极114，发光元件可以包括：与驱动晶体管M0的第二极115耦接的第一电极121、以及与第二电源端112耦接的第二电极123。
在一种示例性实施方式中，像素驱动电路除了可以包括驱动晶体管，还可以包括开关晶体管、存储电容等元件。例如，像素驱动电路可以为3T1C 电路、4T1C电路、5T1C电路、5T2C电路、6T1C电路或7T1C电路等电路结构，本公开实施例对此不做限定。
图3A为本公开实施例中的像素驱动电路的一种结构示意图。如图3A所示，像素驱动电路可以包括6个晶体管(即驱动晶体管M0、第一开关晶体管M1、第二开关晶体管M2、第三开关晶体管M3、第四开关晶体管M4和第五开关晶体管M5)、1个存储电容Cst、以及8个信号线(即复位控制信号端、复位电压端、第一电源端、第二电源端、发光控制信号端、传输控制信号端、扫描信号端和数据信号端)。此外，图3A中还示出了OLED发光元件。
在一种示例性实施例中，如图3A所示，OLED发光元件的第一电极(例如，阳极)与驱动晶体管M0的第二极耦接，OLED发光元件的第二电极(例如，阴极)与第二电源端耦接以接收第二电源电压VSS(即公共电压Vcom)。例如，在第N帧，第二电源电压VSS(即公共电压Vcom)可以为第一电压，或者，在第N+1帧，第二电源电压VSS(即公共电压Vcom)可以为第二电压。
在一种示例性实施例中，如图3A所示，驱动晶体管M0的栅极与第四节点N4连接，驱动晶体管M0的第一极与第二节点N2连接，驱动晶体管M0的第二极与第三节点N3连接。例如，如图3A所示，驱动晶体管M0可以为N型晶体管，本公开的实施例包括但不限于此。
在一种示例性实施例中，如图3A所示，第一开关晶体管M1的栅极与复位控制信号端连接以接收复位控制信号RS，第一开关晶体管M1的第一极与复位电压端连接以接收复位电压Vinit，第一开关晶体管M1的第二极与第一节点N1连接。例如，如图3A所示，第一开关晶体管M1可以为N型晶体管，本公开的实施例包括但不限于此。例如，复位电压Vinit可以为零电压或接地电压，也可以为其他固定的电平，例如低电压等，本公开的实施例对此不作限制。例如，在复位控制信号RS为高电平时，N型的第一开关晶体管M1导通；在复位控制信号RS为低电平时，N型的第一开关晶体管M1截止。
在一种示例性实施例中，如图3A所示，第二开关晶体管M2的栅极与 发光控制信号端连接以接收发光控制信号EM，第二开关晶体管M2的第一极与第一电源端连接以接收第一电源电压VDD，第二开关晶体管M2的第二极与第一节点N1连接。例如，如图3A所示，第二开关晶体管M2可以为P型晶体管，本公开的实施例包括但不限于此。例如，在发光控制信号EM为低电平时，P型的第二开关晶体管M2导通；在发光控制信号EM为高电平时，P型的第二开关晶体管M2截止。例如，第一电源电压VDD可以是由实际显示的灰阶数据决定的与之对应的驱动电压(模拟信号)，例如，在第N帧，第一电源电压VDD可以是由第N帧的灰阶数据决定的与之对应的驱动电压，或者，在第N+1帧，第一电源电压VDD可以是由处理后的第N+1帧的灰阶数据决定的与之对应的驱动电压。
在一种示例性实施例中，如图3A所示，第三开关晶体管M3的栅极与传输控制信号端连接以接收传输控制信号VT，第三开关晶体管M3的第一极与第一节点N1连接，第三开关晶体管M3的第二极与第二节点N2连接。例如，如图3A所示，第三开关晶体管M2可以为N型晶体管，本公开的实施例包括但不限于此。例如，在传输控制信号VT为高电平时，N型的第三开关晶体管M3导通；在传输控制信号VT为低电平时，N型的第三开关晶体管M3截止。
在一种示例性实施例中，如图3A所示，第四开关晶体管M4的栅极与扫描信号端连接以接收扫描信号SN，第四开关晶体管M4的第一极与数据信号端连接以接收数据信号DATA(即伽马电压Gamma)，第四开关晶体管M4的第二极与第四节点N4连接，存储电容Cst的第一端与第四节点N4连接(即与驱动晶体管M0的栅极耦接)，存储电容Cst的第二端与第一电压端连接以接收第一控制电压V_1。例如，第一控制电压V_1可以为固定电压，例如零电压或接地电压。例如，存储电容Cst可以存储写入第四节点N4(即驱动晶体管M0的栅极)的数据信号DATA(即伽马电压Gamma)。例如，如图3A所示，第四开关晶体管M4可以为N型晶体管，本公开的实施例包括但不限于此。例如，在扫描信号SN为高电平时，N型的第四开关晶体管M4导通；在扫描信号SN为低电平时，N型的第四开关晶体管M4截止。例如，在第N帧，数据信号DATA(即伽马电压Gamma)可以为第一数据信 号，或者，在第N+1帧，数据信号DATA(即伽马电压Gamma)可以为第二数据信号。
在一种示例性实施例中，如图3A所示，第五开关晶体管M5的栅极用于接收扫描信号SN的反相信号SN’(例如，可以将扫描信号SN输入反相电路的输入端，从而在反相电路的输出端输出反相信号SN’)，第五开关晶体管M5的第一极与数据信号端连接以接收数据信号DATA(即伽马电压Gamma)，第五开关晶体管M5的第二极与第四节点N4连接。例如，第五开关晶体管M5和第四开关晶体管M4的类型不同；例如，如图3A所示，在第四开关晶体管为N型晶体管的情况下，第五开关晶体管M4为P型晶体管。例如，在扫描信号SN为高电平时，其反相信号SN’为低电平，P型的第五开关晶体管M5导通；在扫描信号SN为低电平时，其反相信号SN’为高电平，P型的第五开关晶体管M5截止。也就是说，第五开关晶体管M5和第四开关晶体管M4可以同时导通，同时截止。例如，第五开关晶体管M5和第四开关晶体管M4可以为结构对称的晶体管器件；例如，第五开关晶体管M5和第四开关晶体管M4可以形成传输门(Transmission Gate，也称为模拟开关)。例如，在第N帧，数据信号DATA(即伽马电压Gamma)可以为第一数据信号，或者，在第N+1帧，数据信号DATA(即伽马电压Gamma)可以为第二数据信号。
图3B为本公开实施例中的像素驱动电路的另一种结构示意图。如图3B所示，在图3A所示的像素驱动电路的基础上，图3B所示的像素驱动电路还可以包括第六开关晶体管M6。这里，图3B所示的像素电路中的其他电路结构(例如，驱动晶体管M0、第一至第五开关晶体管M1～M5、存储电容Cst等)与图3A所示的像素电路基本相同，在此重复之处不再赘述。
在一种示例性实施例中，如图3B所示，第六开关晶体管M6的栅极与第二电压端连接以接收第二控制电压V_2，第六开关晶体管M6的第一极与第三节点N3连接，第六开关晶体管M6的第二极与OLED发光元件的第一电极(例如，阳极)耦接，OLED发光元件的第二电极(例如，阴极)与第二电源端连接以接收第二电源电压VSS(即公共电压Vcom)。例如，如图3B所示，第六开关晶体管M6可以为P型晶体管，本公开的实施例包括但不 限于此。例如，在第六开关晶体管M6为P型晶体管的情况下，第二控制电压V_2可以为零电压或接地电压，也可以为其他固定的电平，例如低电压等。例如，第六开关晶体管M6在第二控制电压V_2的控制下基本保持导通状态。
在本公开的示例性实施例中，存储电容Cst可以是通过工艺制程制作的电容器件，例如通过制作专门的电容电极来实现电容器件，电容的各个电极可以通过金属层、半导体层(例如掺杂多晶硅)等实现，并且，电容也可以是各个器件之间的寄生电容，可以通过晶体管本身与其他器件、线路来实现。电容的连接方式不局限于上面描述的方式，也可以为其他适用的连接方式，只要能存储相应节点的电平即可
在本公开的示例性实施例中，第一节点N1、第二节点N2、第三节点N3和第四节点N4并非表示必须实际存在的部件，而是表示电路图中相关电连接的汇合点。
下面结合图2所示的显示面板，对本公开的实施例所提供的显示面板的驱动方法进行详细说明。
图4为本公开实施例中的显示面板的驱动方法的流程示意图，如图4所示，该驱动方法可以包括如下步骤401至步骤402：
步骤401：在第N帧，基于第N帧的灰阶数据，通过像素驱动电路向第二电极施加第一电压，并向第一电极施加与第一电压匹配的第一数据信号；N为正整数；
步骤402：在第N+1帧，基于第N+1帧的灰阶数据，通过像素驱动电路向第二电极施加第二电压，并向第一电极施加与第二电压匹配的第二数据信号，其中，第一电压和第二电压不相同。
这样，本公开实施例所提供的显示面板的驱动方法，基于不同画面的灰阶数据，通过像素驱动电路对显示面板进行电压调整(包括对施加给显示面板的第二电极的电压进行调整和对施加给显示面板的第一电极的数据信号进行调整)，来实现根据不同的画面对显示面板采用不同的驱动方式，如此，能够增加显示面板的动态对比度。
在一种示例性实施例中，当第二电极作为公共阴极时，向第二电极施加 的电压可以为低电压。例如，第一电压或第二电压可以为低电压。
在一种示例性实施例中，当第N帧的最高灰阶大于第N+1帧的最高灰阶时，第一电压的绝对值可以大于第二电压的绝对值(即当第N+1帧的最高灰阶小于第N帧的最高灰阶时，第二电压的绝对值可以小于第一电压的绝对值)。这样，在显示较低灰阶时，通过减小施加给第二电极的电压，使得发光元件可以具有较低的发光亮度，如此，不但能够大大降低低灰阶的亮度，提高显示面板的动态对比度，而且，还能够降低显示面板的功耗。
在一种示例性实施例中，当第N帧的最低灰阶大于第N+1帧的最低灰阶时，第一电压的绝对值可以大于第二电压的绝对值(即当第N+1帧的最低灰阶小于第N帧的最低灰阶时，第二电压的绝对值可以小于第一电压的绝对值)。这样，在显示较低灰阶时，通过减小施加给第二电极的电压，使得发光元件可以具有较低的发光亮度，如此，不但能够大大降低低灰阶的亮度，提高显示面板的动态对比度，而且，还能够降低显示面板的功耗。
在一种示例性实施例中，针对第N帧与第N+1帧中灰阶相同的像素，第一数据信号中提供给像素的数据信号和第二数据信号中提供给像素的数据信号可以不相同。如此，在调整施加给第二电极的电压的情况下，同时调整施加给第一电极的数据信号，可以使得灰阶亮度重新匹配，从而形成高动态对比度显示效果。
在一种示例性实施例中，针对第N帧与第N+1帧中灰阶相同的像素，当第N帧的最高灰阶大于第N+1帧的最高灰阶时，第一数据信号中提供给像素的数据信号的电压可以小于第二数据信号中提供给像素的数据信号的电压。这样，在显示较低灰阶时，通过减小施加给第一电极的数据信号的电压，使得发光元件可以具有较低的发光亮度，如此，能够大大降低低灰阶的亮度，提高显示面板的动态对比度。
在一种示例性实施例中，针对第N帧与第N+1帧中灰阶相同的像素，当第N帧的最低灰阶大于第N+1帧的最低灰阶时，第一数据信号中提供给像素的数据信号的电压可以小于第二数据信号中提供给像素的数据信号的电压。这样，在显示较低灰阶时，通过减小施加给第一电极的数据信号的电压，使得发光元件可以具有较低的发光亮度，如此，能够大大降低低灰阶的亮度， 提高显示面板的动态对比度。
在一种示例性实施例中，第一电压的绝对值不高于标准公共电压的绝对值，第二电压的绝对值不高于标准公共电压的绝对值，其中，标准公共电压为显示白画面时第二电极的电压。如此，由于第一电压、第二电压的绝对值不高于标准公共电压的绝对值，因此，可以降低显示面板的功耗。
在一种示例性实施例中，第一数据信号的电压不小于标准伽马电压，第二数据信号的电压不小于标准伽马电压，其中，标准伽马电压为显示白画面时第一电极的电压。如此，能够提高动态对比度。
以下，以图2所示的显示面板为例，并以图3A所示的像素驱动电路的电路结构作参考，对本公开的实施例提供的显示面板的驱动方法进行详细说明。
在一种示例性实施例中，如图5所示，一个帧周期的驱动过程可以包括复位阶段S1、数据写入阶段S2和发光阶段S3。图5中示出了每个阶段中各个控制信号(包括复位控制信号RS、扫描信号SN、传输控制信号VT和发光控制信号EM)的时序波形。其中：
在复位阶段S1，输入复位控制信号RS和传输控制信号VT，将复位电压Vinit施加至发光元件的第一电极，进而，通过像素驱动电路，OLED发光元件的第一电极(例如，阳极)接入复位电压Vinit，OLED发光元件的第二电极(例如，阴极)接入第二电源电压VSS(即公共电压Vcom)，从而，发光元件被复位。
在一种示例性实施例中，输入复位控制信号RS和传输控制信号VT，N型的第一开关晶体管M1被复位控制信号RS的高电平导通，N型的第三开关晶体管M3被传输控制信号VT的高电平导通；同时，P型的第二开关晶体管M2被发光控制信号EM的高电平截止，N型的第四开关晶体管M4被扫描信号SN的低电平截止，相应地，P型的第五开关晶体管M5被扫描信号SN的反相信号SN’的高电平截止；另外，驱动晶体管M0被第四节点N4的电平(即在显示上一帧画面的过程中，存储电容Cst存储的数据信号DATA)导通。
在数据写入阶段S2，输入扫描信号SN，将数据信号DATA(即伽马电 压Gamma)写入驱动晶体管的栅极，并由存储电容Cst存储写入的数据信号DATA。例如，在第N帧，数据信号DATA(即伽马电压Gamma)可以为第一数据信号，或者，在第N+1帧，数据信号DATA(即伽马电压Gamma)可以为第二数据信号。
在一种示例性实施例中，N型的第四开关晶体管M4被扫描信号SN的高电平导通，相应地，P型的第五开关晶体管M5被扫描信号SN的反相信号SN’的低电平导通；同时，N型的第一开关晶体管M1被复位控制信号RS的低电平截止，P型的第二开关晶体管M2被发光控制信号EM的高电平截止，N型的第三开关晶体管M3被传输控制信号VT的低电平截止。如此，数据信号DATA对存储电容Cst的第一端(即第四节点N4，也即驱动晶体管M0的栅极)进行充电，使存储电容Cst的第一端的电位变为数据信号DATA，驱动晶体管M0在该数据信号DATA的控制下保持为导通状态。如此，经过数据写入阶段S2后，存储电容Cst的第一端(即第四节点N4，也即驱动晶体管M0的栅极)的电位为数据信号DATA，也就是说，数据信号DATA的电压信息存储在了存储电容Cst中，以用于后续在发光阶段S3时，控制驱动晶体管M0产生驱动电流。
在发光阶段S3，将第一电源电压VDD施加至驱动晶体管的第一极，使驱动晶体管根据驱动晶体管的栅极的数据信号DATA(即伽马电压Gamma)和驱动晶体管的第一极的第一电源电压VDD控制驱动晶体管的第二极的电压Vs，并基于驱动晶体管的第二极的电压Vs产生驱动电流，以驱动OLED发光元件发光。如此，通过像素驱动电路，OLED发光元件的第一电极接入数据信号DATA(即伽马电压Gamma)，OLED发光元件的第二电极接入第二电源电压VSS(即公共电压Vcom)，从而OLED发光元件可以在流经驱动晶体管M0的驱动电流的作用下发光。例如，在第N帧，第二电源电压VSS(即公共电压Vcom)可以为第一电压，数据信号DATA(即伽马电压Gamma)可以为第一数据信号，或者，在第N+1帧，第二电源电压VSS可以为第二电压，数据信号DATA可以为第二数据信号。例如，在第N帧，第一电源电压VDD可以是由第N帧的灰阶数据决定的与之对应的驱动电压，或者，在第N+1帧，第一电源电压VDD可以是由处理后的第N+1帧的灰阶 数据决定的与之对应的驱动电压。
在一种示例性实施例中，输入发光控制信号EM和传输控制信号VT，P型的第二开关晶体管M2被发光控制信号EM的低电平导通，N型的第三开关晶体管M3被传输控制信号VT的高电平导通；同时，N型的第一开关晶体管M1被复位控制信号RS的低电平截止，N型的第四开关晶体管M4被扫描信号SN的低电平截止，相应地，P型的第五开关晶体管M5被扫描信号SN的反相信号SN’的高电平截止；另外，驱动晶体管M0被第四节点N4的电平(即在数据写入阶段S2，存储电容Cst存储的数据信号DATA的电压)导通。如此，通过像素驱动电路，OLED发光元件的第一电极接入数据信号DATA(即伽马电压Gamma)，OLED发光元件的第二电极接入第二电源电压VSS(即公共电压Vcom)，从而OLED发光元件可以在流经驱动晶体管M0的驱动电流的作用下发光。
在一种示例性实施例中，复位阶段可以为一个帧周期的后几个时序或者一个帧周期的前几个时序。例如，一个帧周期可以包括：0至8这9个时序，复位阶段S1可以为0至1时序所表示的时间段，或者，复位阶段可以为7至8时序所表示的时间段。当然，复位阶段还可以为其它，可以由本领域技术人员根据实际情况进行设定，这里，本公开实施例对此不做限定。
其中，图5所示的信号时序图是示意性的，对于本公开实施例提供的显示基板，其工作时的信号时序可以根据实际需要而定，本公开实施例对此不作限制。
在一种示例性实施例中，以第N帧和第N+1帧中的至少一个可以包括复位阶段数据写入阶段和发光阶段为例，则该驱动方法还可以包括如下步骤403和步骤404中的至少一个：
步骤403：在第N帧的复位阶段，通过像素驱动电路向第一电极施加复位电压。
步骤404：在第N+1帧的复位阶段，通过像素驱动电路向第一电极施加复位电压。
在一种示例性实施例中，复位电压可以为低电压，如接地电压或零电压等。本公开实施例对此不做限定。
如此，在一个帧周期中的复位阶段(如结束时刻或开始时刻)，通过像素驱动电路向第一电极施加复位电压Vinit，使得发光元件复位(例如，示例性实现方式可以参考前述关于复位阶段S1的相关描述，在此不再赘述)。从而，可以避免前一帧残余的电荷累积而导致的残像等不良显示现象，进而，能够提高显示面板的动态对比度和显示效果。
在一种示例性实施例中，该驱动方法还可以包括如下步骤405：
步骤405：在第N帧和第N+1帧之间插入空白帧，在空白帧，通过像素驱动电路，将向第二电极施加的电压信号从第一电压切换成第三电压。其中，第三电压的绝对值小于第一电压的绝对值，且第三电压的绝对值小于第二电压的绝对值。如此，可以避免相邻两帧中的前一帧(如第N帧)残余的电荷累积而导致的残像等不良显示现象对后一帧(如N+1帧)的显示效果造成影响，从而，能够进一步提高动态对比度和显示效果。
在一种示例性实施例中，第三电压可以为零电压。如此，第一电压可以为小于0的电平，第二电压可以为小于0的电平。
在一种示例性实施例中，该驱动方法还可以包括如下步骤406：
步骤406：在空白帧，切断第一电源端与驱动晶体管的电连接。这样，使得第一电源端输出的电源电压不能被施加至驱动晶体管，从而，使得发光元件在空白帧停止发光。如此，可以避免空白帧的前一帧(如第N帧)残余的电荷累积而导致的残像等不良显示现象，从而，能够进一步提高动态对比度，进而提高显示效果。此外，还可以降低显示面板的功耗。
在一种示例性实施例中，如图5所示，在第N帧的发光阶段S3持续一段时间后，可以停止输入传输控制信号VT(其他控制信号仍然保持为发光阶段S3中的状态)，例如传输控制信号VT从高电平变为低电平，使第三开关晶体管M3截止，从而，第一电源端与驱动晶体管的电连接被断开，使第一电源电压VDD不能被施加至驱动晶体管M0的第一极，驱动晶体管M0不能产生驱动电流，OLED发光元件停止发光。
当然，切断第一电源端与驱动晶体管的电连接还可以通过其他方式实现， 而不限于上述方式。例如，可以通过控制是否输入发光控制信号EM来实现，或者，通过控制是否输入发光控制信号EM和传输控制信号VT来实现。这里，本公开实施例对此不做限定。
下面以第N+1帧为例，对如何基于第N+1帧的灰阶数据，确定通过像素驱动电路向第一电极施加的第二数据信号和向第二电极施加的第二电压进行说明。
在一种示例性实施例中，步骤402可以包括以下步骤4021至步骤4025：
步骤4021：基于第N+1帧的灰阶数据，确定出第一灰阶。
在一种示例性实施例中，步骤4021可以包括但不限于以下三种方式：
方式1：从第N+1帧的灰阶数据中，确定出最高的一个灰阶；将最高的一个灰阶，确定为第一灰阶。
举例来说，假设第N+1帧的灰阶数据在G0至Gmax之间，Gmax为最高灰阶，则可以将Gmax确定为第一灰阶。
在一种示例性实施例中，可以通过图像算法读取第N+1帧的灰阶数据中最高灰阶GL的过程可以如下所示：
a)、对第N+1帧的整副画面中的每个像素进行几何位置标记，如(x1,y1)，(x2,y2)，……，(xn,yn)。其中，图6为以n为25为例时的像素的几何位置标记的示意图。
b)、依次移动标记(x1,y1)->(xn,yn)，在第N+1帧上去寻找全局最大值(最高灰阶)。寻找最高灰阶的过程可以包括以下步骤1)至步骤4)：
步骤1)：记录(x1,y1)的灰阶到A；
步骤2)：记录(x2,y2)的灰阶到B；
步骤3)：比较A和B得到两者中的较大值并记录到A；
步骤4)：重复上述步骤1)至步骤3)的过程，直到比较出灰阶最大点(xm,ym)，并将点(xm,ym)的灰阶记录为最高灰阶GL。
方式2：从第N+1帧的灰阶数据中，确定出最高的前X个灰阶；将最高的前X个灰阶的均值，确定为第一灰阶；其中，X为大于1的正整数。
举例来说，以X＝3为例，假设第N+1帧的灰阶数据中最高的前3个灰阶依次分别为Gmax1、Gmax2和Gmax3，则可以将Gmax1、Gmax2和Gmax3的均值Gmean确定为第一灰阶。其中，Gmean＝(Gmax1+Gmax2+Gmax3)/3。
方式3：从第N+1帧的灰阶数据中，确定出位于预设区域内的灰阶；将位于预设区域内的灰阶中的最高的一个灰阶，确定为第一灰阶。
举例来说，假设第N+1帧的灰阶数据在G0至Gmax之间，Gmax为最高灰阶，而第N+1帧画面中包含一个人物P，则预设区域可以是指该人物P所在区域，假设第N+1帧的灰阶数据中该人物P所在区域的灰阶数据在G0至Gp之间，Gp为该人物P所在区域中的最高灰阶，那么，可以将Gp确定为第一灰阶。
在一种示例性实施例中，预设区域可以为目标对象所在区域，例如目标人、目标物等。或者，预设区域可以为第N+1帧中的预设尺寸的画面中心区域。当然，预设区域还可以为其它，可由本领域技术人员根据实际情况进行确定，本公开的实施例对此不做限定。
在一种示例性实施例中，预设区域的数量可以为一个或多个。可由本领域技术人员根据实际情况进行确定，本公开的实施例对此不做限定。
步骤4022：根据预先建立的第一映射关系，确定出与第一灰阶对应的第一发光亮度。
其中，第一映射关系用于描述以向第二电极施加标准公共电压并向第一电极施加标准伽马电压的方式驱动显示面板时，灰阶与发光亮度之间的关系。这里，标准公共电压为在显示面板的显示模组调试阶段，调节光学参数测量到的显示白画面时第二电极的电压；标准伽马电压为在显示面板的显示模组调试阶段，调节光学参数得到的标准伽马值下的显示白画面时第一电极的电压。
在一种示例性实施例中，在显示面板的显示模组调试阶段，通过调试光学参数，得到标准公共电压(标准Vcom)以及标准伽马电压(标准Gamma)，同时记录下此标准Vcom以及标准Gamma下不同灰阶对应的不同发光亮度(即显示面板中显示模组的亮度)，如此，就可以得到如图7所示的数据表 格A1(即上述第一映射关系)。那么，在根据一帧的灰阶数据得到对应的第一灰阶时，就可以通过查找第一映射关系，得到与该第一灰阶对应的第一发光亮度。
步骤4023：确定预先建立的至少一个第二映射关系中是否存在与第一发光亮度匹配的映射关系。
其中，第二映射关系用于描述候选公共电压与发光亮度和候选伽马电压之间的映射关系。
若预先建立的至少一个第二映射关系中存在与第一发光亮度匹配的映射关系，则可以执行步骤4024，采用调整后的驱动电压来驱动发光元件。或者，若预先建立的至少一个第二映射关系中并不存在与第一发光亮度匹配的映射关系，则可以执行步骤4025，采用标准驱动电压来驱动发光元件。
步骤4024：将匹配到的映射关系中的候选公共电压作为第二电压施加给第二电极，并将匹配到的映射关系中的候选伽马电压作为第二数据信号施加给第一电极。
步骤4025：将标准公共电压作为第二电压施加给第二电极，将标准伽马电压作为第二数据信号施加给第一电极。
在一种示例性实施例中，步骤4023可以包括以下步骤4023a至步骤4023d：
步骤4023a：将第一发光亮度与至少一个第二映射关系中的发光亮度进行比较。
其中，第二映射关系用于描述候选公共电压与发光亮度和候选伽马电压之间的映射关系。
步骤4023b：根据比较结果，确定至少一个第二映射关系中的发光亮度中是否存在与第一发光亮度匹配的第二发光亮度。
若至少一个第二映射关系中的发光亮度中存在与第一发光亮度匹配的第二发光亮度，则可以执行步骤4023c。若至少一个第二映射关系中的发光亮度中并不存在与第一发光亮度匹配的第二发光亮度，则可以执行步骤4023d。
步骤4023c：确定至少一个第二映射关系中存在与第一发光亮度值匹配 的映射关系。
步骤4023d：确定至少一个第二映射关系中不存在与第一发光亮度值匹配的映射关系。
在一种示例性实施例中，步骤4023b可以包括但不限于以下三种情况：
情况1：若第一发光亮度小于至少一个第二映射关系中的发光亮度中的最小发光亮度，确定至少一个第二映射关系中的发光亮度中存在与第一发光亮度匹配的第二发光亮度，其中，第二发光亮度为最小发光亮度。
情况2：若第一发光亮度小于至少一个第二映射关系中的发光亮度中的最大发光亮度，且不小于至少一个第二映射关系中的发光亮度中除最大发光亮度之外的其它发光亮度，确定至少一个第二映射关系中的发光亮度中存在与第一发光亮度值匹配的第二发光亮度，其中，第二发光亮度为最大发光亮度。
情况3：若第一发光亮度处于至少一个第二映射关系中的发光亮度中两两相邻发光亮度所形成的发光亮度间隔中，确定至少一个第二映射关系中的发光亮度中存在与第一发光亮度匹配的第二发光亮度，其中，第二发光亮度为发光亮度间隔的较大端点对应的发光亮度。
在一种示例性实施例中，在显示面板的显示模组调试阶段，通过调节不同公共电压Vcom(即施加给发光元件的第二电极的第二电源电压VSS)，得到匹配的不同的伽马电压Gamma(即施加给发光元件的第一电极的数据信号DATA)以及对应的不同最高亮度，如此，就可以得到如下表1所示的匹配表格A2(即上述第二映射关系)。其中，Vcom1、Vcom2和Vcom3小于标准Vcom；L1小于L2，L2小于L3。
公共电压 伽马电压 最高亮度
Vcom1 Gamma1 L1
Vcom2 Gamma2 L2
Vcom3 Gamma3 L3
表1
举例来说，以上述表1所示的第二映射关系为例，对驱动方法进行说明，在根据预先建立的第一映射关系，确定出与第一灰阶对应的第一发光亮度之后，判断第一发光亮度是否小于L1；如果第一发光亮度小于L1，表明第二映射关系中的发光亮度中存在与第一发光亮度匹配的第二发光亮度(此时，第二发光亮度为L1)，则可以通过像素驱动电路将Vcom1施加给第二电极，并将与Vcom1对应的Gamma1施加给第一电极；如果第一发光亮度不小于L1，则可以判断第一发光亮度是否小于L2；接下来，如果第一发光亮度小于L2，表明第二映射关系中的发光亮度中存在与第一发光亮度匹配的第二发光亮度(此时，第二发光亮度为L2)，则可以通过像素驱动电路将Vcom2施加给第二电极，并将与Vcom2对应的Gamma2施加给第一电极；如果第一发光亮度不小于L2，则判断第一发光亮度是否小于L3；然后，如果第一发光亮度小于L3，表明第二映射关系中的发光亮度中存在与第一发光亮度匹配的第二发光亮度(此时，第二发光亮度为L3)，则可以通过像素驱动电路将Vcom3施加给第二电极，并将与Vcom3对应的Gamma3施加给第一电极；如果第一发光亮度不小于L3，表明第二映射关系中的发光亮度中不存在与第一发光亮度匹配的第二发光亮度，则可以通过像素驱动电路将标准Vcom施加给第二电极，并将标准Gamma施加给第一电极。
在一种示例性实施例中，步骤402还可以包括以下步骤4026至步骤4028：
步骤4026：根据预先建立的第三映射关系，确定出与匹配到的映射关系中的发光亮度对应的第二灰阶。
其中，第三映射关系用于描述以匹配到的映射关系中的候选公共电压和候选伽马电压驱动显示面板时，灰阶与发光亮度之间的关系。
在一种示例性实施例中，在显示面板的显示模组调试阶段，通过调试光学参数，得到候选公共电压(与标准Vcom不同)和候选伽马电压(与标准Gamma不同)，同时记录下此候选公共电压(候选Vcom)以及候选伽马电压(候选Gamma)下，不同灰阶对应的不同发光亮度(即显示面板中显示模组的亮度)，如此，就可以得到第三映射关系(与表1类似，仅驱动电压不同，此处不做过多赘述)。那么，在确定预先建立的至少一个第二映射关系中存在与第一发光亮度匹配的映射关系之后，可以根据匹配到的映射关系中 的发光亮度(即上述第二发光亮度)，通过查找第三映射关系，就可以得到与该匹配到的映射关系中的发光亮度(即上述第二发光亮度)对应的第二灰阶。
步骤4027：给第N+1帧的灰阶数据乘以第一灰阶和第二灰阶之间的比值，得到处理后的第N+1帧的灰阶数据。
步骤4028：将与处理后的第N+1帧的灰阶数据对应的驱动电压施加给驱动晶体管。
在一种示例性实施例中，如图3A所示，将由处理后的第N+1帧的灰阶数据决定的与之对应的驱动电压(即第一电源电压VDD)，施加至驱动晶体管的第一极，以使驱动晶体管根据驱动晶体管的栅极的数据信号DATA(即伽马电压Gamma)和驱动晶体管的第一极的第一电源电压VDD控制驱动晶体管的第二极的电压Vs，并基于驱动晶体管的第二极的电压Vs产生驱动电流，以驱动OLED发光元件发光。
例如，基于第N帧的灰阶数据，确定通过像素驱动电路向第一电极施加的第一数据信号和向第二电极施加的第一电压，与以上关于基于第N+1帧的灰阶数据，确定通过像素驱动电路向第一电极施加的第二数据信号和向第二电极施加的第二电压的描述是类似的，请参照本公开实施例中的相关描述而理解，在此不做过多赘述。
采用本公开实施例中的显示面板的驱动方法，在第N帧，可以基于第N帧的灰阶数据，通过像素驱动电路向第二电极施加第一电压，并向第一电极施加与第一电压匹配的第一数据信号；N为正整数；在第N+1帧，可以基于第N+1帧的灰阶数据，通过像素驱动电路向第二电极施加第二电压，并向第一电极施加与第二电压匹配的第二数据信号，其中，第一电压和第二电压不相同。这样，通过在不同帧给发光元件的第二电极(例如，作为阴极)施加不同的电压，并给发光元件的第一电极(例如，作为阳极)施加与第二电极的电压匹配的数据信号，实现了根据不同帧对显示面板采用不同的驱动方式，如此，能够降低低灰阶的亮度，提高显示面板的动态对比度。
图8A为本公开实施例提供的显示面板的驱动方法的一种信号时序图，图8B为本公开实施例提供的显示面板的驱动方法的另一种信号时序图。这 里，图8A和图8B中所示的信号时序图的电压的高低仅是示意性的，不代表真实电压值或相对比例。
下面以第N+1帧为例，结合图8A和图8B所示的信号时序图，对本公开的实施例提供的一种显示面板的驱动方法进行说明。
步骤1、通过图像算法读取第N+1帧的灰阶数据中的最高灰阶GL(即上述第一灰阶)。
举例来说，读取最高灰阶GL的过程可以如下所示：
a1)、对第N+1帧的整副画面中的每个像素进行几何位置标记，如(x1,y1),(x2,y2)，……，(xn,yn)。
b1)、依次移动标记(x1,y1)->(xn,yn)，在第N+1帧上去找全局最大值。找全局最大值的过程可以包括以下步骤11)至步骤14)：
步骤11)、记录(x1,y1)的灰阶到A；
步骤12)、记录(x2,y2)的灰阶到B；
步骤13)、比较A和B得到两者中的较大值并记录到A；
步骤14)、重复上述步骤1至步骤3的过程，直到比较出灰阶最大点(xm,ym)，并将点(xm,ym)的灰阶记录为最高灰阶GL。
步骤2、利用最高灰阶GL反向查找产品输出的最高亮度L(即上述与第一灰阶对应的第一发光亮度)。
其中，查找最高亮度L的过程可以如下所示：
a2)、在显示面板的显示模组调试阶段，根据调试需求，通过调试显示模组的光学参数，调试得到标准公共电压(标准Vcom)以及标准伽马电压(标准Gamma)。同时，记录下以标准Vcom以及标准Gamma驱动显示面板时，每个灰阶及其对应的模组亮度(即上述发光亮度)，从而，以标准Vcom以及标准Gamma下的不同灰阶及其对应的发光亮度可以得到如图7所示的数据表格A1(即上述第一映射关系)。
b2)、根据步骤1得到的最高灰阶GL反查数据表格A1，就可以得到产品需要输出的最高亮度L。
步骤3、通过最高亮度L查找得到最佳Vcom(即上述第二电压)以及与该最佳Vcom适配的最佳Gamma(即上述第一数据信号)。
其中，查找最佳Vcom以及与该最佳Vcom适配的最佳Gamma的过程可以如下所示：
a3)、在显示面板的显示模组调试阶段，通过调节不同公共电压Vcom(施加给发光元件的第二电极的电压)，得到匹配的不同的伽马电压Gamma(施加给发光元件的第一电极的电压)以及对应的不同最高亮度，如此，就可以得到如下表1所示的匹配表格A2(即上述第二映射关系)。
b3)、根据步骤2得到的最高亮度L反查匹配表格A2，就可以得到最佳Vcom以及与该最佳Vcom适配的最佳Gamma。
举例来说，下面以三组第二映射关系(如上表1所示)为例进行说明。查找最佳Vcom以及与该最佳Vcom适配的最佳Gamma的过程可以如下所示：
步骤31)、判断L是否小于L1；
步骤32)、如果L小于L1，则使用Vcom1以及与该Vcom1匹配的Gamma1作为最佳Vcom及其适配的最佳Gamma；如果L不小于L1，则判断L是否小于L2；
步骤33)、如果L小于L2，则使用Vcom2以及与该Vcom2匹配的Gamma2，作为最佳Vcom及其适配的最佳Gamma；如果L不小于L2，判断L是否小于L3；
步骤34)、如果L小于L3，则使用Vcom3以及与该Vcom23匹配的Gamma3；如果L不小于L3，则使用标准Vcom以及与该标准Vcom匹配的标准Gamma作为最佳Vcom及其适配的最佳Gamma。
步骤4、根据第一灰阶与最亮亮度L在最佳Vcom和最佳Gamma下的实际灰阶(即第二灰阶)之间的比值，对第N+1帧的灰阶数据进行处理，得到处理后的第N+1帧的灰阶数据。例如，给第N+1帧的灰阶数据乘以第一灰阶和第二灰阶之间的比值，计算得到处理后的第N+1帧的灰阶数据。
步骤5、如图8A所示，在第N帧接入发光元件的第二电极的第二电源 电压VSS(即公共电压Vcom)为第一电压V1，在第N帧与第N+1帧之间的空白帧将接入发光元件的第二电极的第二电源电压VSS(即公共电压Vcom)从第一电压V1切换为第三电压V3，在第N+1帧接入发光元件的第二电极的第二电源电压VSS(即公共电压Vcom)从第三电压V3切换为第二电压V2(即上述最佳Vcom)；在第N帧接入发光元件的第二电极的第一电极的数据信号DATA(即伽马电压Gamma)为第一数据信号G1，在第N帧与第N+1帧之间的空白帧将接入发光元件的第一电极的数据信号DATA(即伽马电压Gamma)从第一数据信号G1切换为第二数据信号G2(即上述与该最佳Vcom适配的最佳Gamma)，在第N+1帧接入发光元件的第二电极的为第二数据信号G2(即上述与该最佳Vcom适配的最佳Gamma)；在第N帧与第N+1帧之间的空白帧将与处理后的第N+1帧的灰阶数据对应的驱动电压施加给驱动晶体管的第一极。
在一种示例性实施例中，如图8A所示，第三电压V3可以等于零电压，其中，第三电压V3的绝对值小于第一电压V1的绝对值，且第三电压V3的绝对值小于第二电压V2的绝对值。
在一种示例性实施例中，最佳Vcom的绝对值不高于标准Vcom的绝对值，最佳Gamma不小于标准Gamma。如此，不但能够大大降低低灰阶的亮度，增加显示面板的动态对比度，而且可以降低显示面板的功耗。
此外，如图8B所示，仍然以第三电压V3为零电压为例，在第N+1帧与第N+2帧之间的空白帧可以将接入发光元件的第二电极的第二电源电压VSS(即公共电压Vcom)从第二电压V2切换为第三电压V3，在第N+2帧与第N+3帧之间的空白帧可以将接入发光元件的第二电极的第二电源电压VSS(即公共电压Vcom)从第四电压V4切换为第三电压V3，其中，第三电压V3的绝对值小于第四电压V4的绝对值。
另，如图8B所示，本公开实施例中，可以根据不同的画面进行电压的调整，因此接入发光元件的第二电极的第二电源电压VSS(即公共电压Vcom)的波形可以根据画面更新的频率进行浮动。
下面以图9A至图9C以显示面板对标准测试图进行显示所得到的显示结果对上述显示面板的驱动方法的性能进行说明。
其中，图9A示出了未对显示面板的驱动电压进行调整(即未对发光元件的第二电极的电压和第一电极的电压进行调整)时所得到的显示面板的显示结果，图9B示出了仅对显示面板的发光元件的第二电极的电压进行调整时所得到的显示面板的显示结果，图9C示出了采用本公开实施例所提供的显示面板的驱动方法来驱动显示面板时所得到的显示面板的显示结果。图9B与图9A中的显示结果相比，可见：两个显示面板虽然显示亮度是不同的，但是对比度是相同的。图9C与图9A中的显示结果相比，可见：两个显示面板的显示亮度和对比度都是不相同的，而且图9C所示的对比度要高于图9A所示的对比度。因此，本公开实施例所提供的显示面板的驱动方法，基于不同帧的灰阶数据，通过像素驱动电路对显示面板进行电压调整(包括：对施加给显示面板的第二电极的电压进行动态调整和对施加给显示面板的第一电极的数据信号进行动态调整)，来实现根据不同画面对显示面板采用不同的驱动方式，如此，能够增加显示面板的动态对比度，提高显示效果。
在一种示例性实施例中，本公开还提供了一种驱动设备。该驱动设备可以包括处理器、存储器及存储在存储器上并可在处理器上运行的计算机程序，其中，处理器执行计算机程序时实现本公开上述任一实施例中的显示面板的驱动方法的步骤。
在一种示例性实施例中，图10为本公开实施例中的驱动设备的结构示意图，如图10所示，该驱动设备100包括：至少一个处理器1001；以及与处理器1001连接的至少一个存储器1002、总线1003；其中，处理器1001、存储器1002通过总线1003完成相互间的通信；处理器1001用于调用存储器1002中的程序指令，以执行上述任一实施例中的显示面板的驱动方法的步骤。
处理器可以是中央处理单元(Central Processing Unit，CPU)、微处理器(Micro Processor Unit，MPU)、数字信号处理器(Digital Signal Processor，DSP)、专用集成电路(ASIC)、现成可编程门阵列(Field Programmable Gate Array，FPGA)、晶体管逻辑器件等，本公开对此不做限定。
存储器可以包括只读存储器(Read Only Memory，ROM)和随机存取存储器(Random Access Memory，RAM)，并向处理器提供指令和数据。存储 器的一部分还可以包括非易失性随机存取存储器。例如，存储器还可以存储设备类型的信息。
总线除包括数据总线之外，还可以包括电源总线、控制总线和状态信号总线等。但是为了清楚说明起见，在图9中将各种总线都标为总线。
在实现过程中，处理设备所执行的处理可以通过处理器中的硬件的集成逻辑电路或者软件形式的指令完成。即本公开实施例的方法步骤可以体现为硬件处理器执行完成，或者用处理器中的硬件及软件模块组合执行完成。软件模块可以位于随机存储器，闪存、只读存储器，可编程只读存储器或者电可擦写可编程存储器、寄存器等存储介质中。该存储介质位于存储器，处理器读取存储器中的信息，结合其硬件完成上述方法的步骤。为避免重复，这里不再详细描述。
在一种示例性实施例中，本公开还提供了一种显示设备。该显示设置可以包括：本公开上述任一实施例提供的显示面板和本公开上述任一实施例提供的驱动设备。
在一种示例性实施例中，显示设备可以为手机、平板电脑、电视机、笔记本电脑、导航仪、电子纸显示装置、数码相框、虚拟现实设备、增强现实设备等任何具有显示功能的产品或部件。这里，该显示设备还可以包括其他常规部件或结构，例如，为实现显示装置的必要功能，本领域技术人员可以根据实际应用场景设置其他的常规部件或结构，这里，本公开实施例对此不做限定。
在一种示例性实施例中，本公开还提供了一种计算机可读存储介质，该计算机可读存储介质存储有可执行指令，该可执行指令被处理器执行时可以实现本公开上述任一实施例提供的显示面板的驱动方法。该显示面板的驱动方法可以用于驱动本公开上述实施例提供的显示面板进行显示，从而提高显示画面的对比度，提高显示效果。
在一种示例性实施例中，上述计算机可读存储介质可以如：ROM/RAM、磁碟、光盘等。本公开对此不做限定。
以上驱动设备、显示设备、计算机可读存储介质实施例的描述，与上述显示面板的驱动方法实施例的描述是类似的，具有方法实施例相似的有益效 果。对于本公开驱动设备、显示设备、计算机可读存储介质实施例中未披露的技术细节，请参照本公开方法实施例的描述而理解，在此不做赘述。
在本公开实施例的描述中，需要理解的是，术语“中部”、“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本公开和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。
本领域普通技术人员可以理解，上文中所公开方法中的全部或某些步骤、系统、装置中的功能模块/单元可以被实施为软件、固件、硬件及其适当的组合。在硬件实施方式中，在以上描述中提及的功能模块/单元之间的划分不一定对应于物理组件的划分；例如，一个物理组件可以具有多个功能，或者一个功能或步骤可以由若干物理组件合作执行。某些组件或所有组件可以被实施为由处理器，如数字信号处理器或微处理器执行的软件，或者被实施为硬件，或者被实施为集成电路，如专用集成电路。这样的软件可以分布在计算机可读介质上，计算机可读介质可以包括计算机存储介质(或非暂时性介质)和通信介质(或暂时性介质)。如本领域普通技术人员公知的，术语计算机存储介质包括在用于存储信息(诸如计算机可读指令、数据结构、程序模块或其他数据)的任何方法或技术中实施的易失性和非易失性、可移除和不可移除介质。计算机存储介质包括但不限于RAM、ROM、EEPROM、闪存或其他存储器技术、CD-ROM、数字多功能盘(DVD)或其他光盘存储、磁盒、磁带、磁盘存储或其他磁存储装置、或者可以用于存储期望的信息并且可以被计算机访问的任何其他的介质。此外，本领域普通技术人员公知的是，通信介质通常包含计算机可读指令、数据结构、程序模块或者诸如载波或其他传输机制之类的调制数据信号中的其他数据，并且可包括任何信息递送介质。
虽然本公开所揭露的实施方式如上，但所述的内容仅为便于理解本公开而采用的实施方式，并非用以限定本公开。任何本公开所属领域内的技术人员，在不脱离本公开所揭露的精神和范围的前提下，可以在实施的形式及细节上进行任何的修改与变化，但本公开的保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (20)

  1. 一种显示面板的驱动方法，其中，
    所述显示面板，包括：依次叠设的衬底基板、像素驱动电路和发光元件，所述发光元件包括：依次叠设的第一电极、有机发光层和第二电极，所述像素驱动电路包括：与所述第一电极耦接的驱动晶体管、与所述驱动晶体管耦接的第一电源端和与所述第二电极耦接的第二电源端；
    所述驱动方法，包括：
    在第N帧，基于所述第N帧的灰阶数据，通过所述像素驱动电路向所述第二电极施加第一电压，并向所述第一电极施加与第一电压匹配的第一数据信号；N为正整数；
    在第N+1帧，基于所述第N+1帧的灰阶数据，通过所述像素驱动电路向所述第二电极施加第二电压，并向所述第一电极施加与第二电压匹配的第二数据信号，其中，所述第一电压和所述第二电压不相同。
  2. 根据权利要求1所述的驱动方法，还包括：
    在所述第N帧和所述第N+1帧之间插入空白帧，在所述空白帧，通过所述像素驱动电路，将向所述第二电极施加的电压信号从所述第一电压切换成第三电压，其中，所述第三电压的绝对值小于所述第一电压的绝对值，且所述第三电压小于所述第二电压的绝对值。
  3. 根据权利要求2所述的驱动方法，所述第三电压为零电压。
  4. 根据权利要求1至3任一项所述的驱动方法，其中，当所述第N帧的最高灰阶大于所述第N+1帧的最高灰阶时，所述第一电压的绝对值大于所述第二电压的绝对值。
  5. 根据权利要求1至3任一项所述的驱动方法，其中，当所述第N帧的最低灰阶大于所述第N+1帧的最低灰阶时，所述第一电压的绝对值大于所述第二电压的绝对值。
  6. 根据权利要求2所述的驱动方法，还包括：在所述空白帧，切断所述第一电源端与所述驱动晶体管的电连接。
  7. 根据权利要求1所述的驱动方法，还包括：在所述第N帧的复位阶段，通过所述像素驱动电路向所述第一电极施加复位电压，或者，在所述第N+1帧的复位阶段，通过所述像素驱动电路向所述第一电极施加复位电压。
  8. 根据权利要求1所述的驱动方法，其中，针对所述第N帧与所述第N+1帧中灰阶相同的像素，所述第一数据信号中提供给所述像素的数据信号和第二数据信号中提供给所述像素的数据信号不相同。
  9. 根据权利要求1或8所述的驱动方法，其中，针对所述第N帧与所述第N+1帧中灰阶相同的像素，当所述第N帧的最高灰阶大于所述第N+1帧的最高灰阶时，所述第一数据信号中提供给所述像素的数据信号的电压小于所述第二数据信号中提供给所述像素的数据信号的电压。
  10. 根据权利要求1或8所述的驱动方法，其中，针对所述第N帧与所述第N+1帧中灰阶相同的像素，当所述第N帧的最低灰阶大于第N+1帧的最低灰阶时，所述第一数据信号中提供给所述像素的数据信号的电压小于所述第二数据信号中提供给所述像素的数据信号的电压。
  11. 根据权利要求1所述的驱动方法，其中，所述第一电压的绝对值不高于标准公共电压的绝对值，所述第二电压的绝对值不高于标准公共电压的绝对值，所述标准公共电压为显示白画面时的第二电极的电压。
  12. 根据权利要求1或11所述的驱动方法，其中，所述第一数据信号的电压不小于标准伽马电压，所述第二数据信号的电压不小于标准伽马电压，所述标准伽马电压为显示白画面时的第一电极的电压。
  13. 根据权利要求1所述的驱动方法，其中，所述基于所述第N+1帧的灰阶数据，通过所述像素驱动电路向所述第二电极施加第二电压，并向所述第一电极施加第二数据信号，包括：
    基于所述第N+1帧的灰阶数据，确定出第一灰阶；
    根据预先建立的第一映射关系，确定出与所述第一灰阶对应的第一发光亮度；其中，第一映射关系用于描述以向第二电极施加标准公共电压并向第一电极施加标准伽马电压的方式驱动显示面板时，灰阶与发光亮度之间的关系；
    确定预先建立的至少一个第二映射关系中是否存在与所述第一发光亮度匹配的映射关系；其中，第二映射关系用于描述候选公共电压与发光亮度和候选伽马电压之间的映射关系；
    若存在，将匹配到的映射关系中的候选公共电压作为第二电压施加给第二电极，并将匹配到的映射关系中的候选伽马电压作为第二数据信号施加给第一电极；或者，若不存在，将标准公共电压作为第二电压施加给第二电极，将标准伽马电压作为第二数据信号施加给第一电极。
  14. 根据权利要求13所述的驱动方法，还包括：
    根据预先建立的第三映射关系，确定出与所述匹配到的映射关系中的发光亮度对应的第二灰阶；其中，第三映射关系用于描述以匹配到的映射关系中的候选公共电压和候选伽马电压驱动显示面板时，灰阶与发光亮度之间的关系；
    给所述第N+1帧的灰阶数据乘以所述第一灰阶和所述第二灰阶之间的比值，得到处理后的第N+1帧的灰阶数据；
    将与所述处理后的第N+1帧的灰阶数据对应的驱动电压施加给所述驱动晶体管。
  15. 根据权利要求13所述的驱动方法，其中，所述确定预先建立的至少一个第二映射关系中是否存在与所述第一发光亮度匹配的映射关系，包括：
    将所述第一发光亮度与所述至少一个第二映射关系中的发光亮度进行比较；
    根据比较结果，确定所述至少一个第二映射关系中的发光亮度中是否存在与所述第一发光亮度匹配的第二发光亮度；
    若所述至少一个第二映射关系中的发光亮度中存在与所述第一发光亮度匹配的第二发光亮度，则所述至少一个第二映射关系中存在与所述第一发光亮度值匹配的映射关系；否则，所述至少一个第二映射关系中不存在与所述第一发光亮度值匹配的映射关系。
  16. 根据权利要求15所述的驱动方法，其中，所述根据比较结果，确定所述至少一个第二映射关系中的发光亮度中是否存在与所述第一发光亮度匹 配的第二发光亮度，包括：
    若所述第一发光亮度小于所述至少一个第二映射关系中的发光亮度中的最小发光亮度，确定所述至少一个第二映射关系中的发光亮度中存在与所述第一发光亮度匹配的第二发光亮度，其中，所述第二发光亮度为所述最小发光亮度；
    或者，若所述第一发光亮度小于所述至少一个第二映射关系中的发光亮度中的最大发光亮度，且不小于所述至少一个第二映射关系中的发光亮度中除所述最大发光亮度之外的其它发光亮度，确定所述至少一个第二映射关系中的发光亮度中存在与所述第一发光亮度值匹配的第二发光亮度，其中，所述第二发光亮度为所述最大发光亮度；
    或者，若所述第一发光亮度处于所述至少一个第二映射关系中的发光亮度中两两相邻发光亮度所形成的发光亮度间隔中，确定所述至少一个第二映射关系中的发光亮度中存在与所述第一发光亮度匹配的第二发光亮度，其中，所述第二发光亮度为所述发光亮度间隔的较大端点对应的发光亮度。
  17. 根据权利要求13所述的驱动方法，其中，所述基于所述第N+1帧的灰阶数据，确定出第一灰阶，包括：
    从所述第N+1帧的灰阶数据中，确定出最高的一个灰阶；将所述最高的一个灰阶，确定为所述第一灰阶；
    或者，从所述第N+1帧的灰阶数据中，确定出最高的前X个灰阶；将所述最高的前X个灰阶的均值，确定为所述第一灰阶；其中，X为大于1的正整数；
    或者，从所述第N+1帧的灰阶数据中，确定出位于预设区域内的灰阶；将所述位于预设区域内的灰阶中的最高的一个灰阶，确定为所述第一灰阶。
  18. 一种计算机可读存储介质，存储有计算机可执行指令，所述计算机可执行指令用于执行权利要求1至17中任一项所述的显示面板的驱动方法的步骤。
  19. 一种驱动设备，包括：存储器、处理器及存储在存储器上并可在处理器上运行的计算机程序，其中，所述处理器执行所述程序时实现如权利要 求1至17中任一项所述的显示面板的驱动方法的步骤。
  20. 一种显示设备，包括：显示面板和如权利要求19所述的驱动设备。
PCT/CN2020/125158 2020-10-30 2020-10-30 显示面板的驱动方法、存储介质、驱动设备及显示设备 WO2022088017A1 (zh)

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