WO2022087776A1 - 飞行时间传感器、测距系统及电子装置 - Google Patents

飞行时间传感器、测距系统及电子装置 Download PDF

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Publication number
WO2022087776A1
WO2022087776A1 PCT/CN2020/123617 CN2020123617W WO2022087776A1 WO 2022087776 A1 WO2022087776 A1 WO 2022087776A1 CN 2020123617 W CN2020123617 W CN 2020123617W WO 2022087776 A1 WO2022087776 A1 WO 2022087776A1
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Prior art keywords
clock signal
clock
phase difference
time
delay line
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PCT/CN2020/123617
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English (en)
French (fr)
Inventor
梁佑安
杨孟达
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深圳市汇顶科技股份有限公司
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Priority to PCT/CN2020/123617 priority Critical patent/WO2022087776A1/zh
Priority to EP20923710.6A priority patent/EP4043926A1/en
Priority to US17/473,844 priority patent/US20220128669A1/en
Publication of WO2022087776A1 publication Critical patent/WO2022087776A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/135—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
    • G01S17/00—Systems using the reflection or reradiation of electromagnetic waves other than radio waves, e.g. lidar systems
    • G01S17/88—Lidar systems specially adapted for specific applications
    • G01S17/89—Lidar systems specially adapted for specific applications for mapping or imaging
    • G01S17/894—3D imaging with simultaneous measurement of time-of-flight at a 2D array of receiver pixels, e.g. time-of-flight cameras or flash lidar
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
    • G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
    • G01S7/48—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S17/00
    • G01S7/483—Details of pulse systems
    • G01S7/484—Transmitters
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
    • G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
    • G01S7/48—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S17/00
    • G01S7/483—Details of pulse systems
    • G01S7/486—Receivers
    • G01S7/4861—Circuits for detection, sampling, integration or read-out
    • G01S7/4863—Detector arrays, e.g. charge-transfer gates
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
    • G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
    • G01S7/48—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S17/00
    • G01S7/483—Details of pulse systems
    • G01S7/486—Receivers
    • G01S7/4865—Time delay measurement, e.g. time-of-flight measurement, time of arrival measurement or determining the exact position of a peak
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
    • G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
    • G01S7/48—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S17/00
    • G01S7/491—Details of non-pulse systems
    • G01S7/4911—Transmitters
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
    • G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
    • G01S7/48—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S17/00
    • G01S7/491—Details of non-pulse systems
    • G01S7/4912—Receivers
    • G01S7/4913—Circuits for detection, sampling, integration or read-out
    • G01S7/4914—Circuits for detection, sampling, integration or read-out of detector arrays, e.g. charge-transfer gates
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
    • G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
    • G01S7/48—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S17/00
    • G01S7/491—Details of non-pulse systems
    • G01S7/4912—Receivers
    • G01S7/4915—Time delay measurement, e.g. operational details for pixel components; Phase measurement

Definitions

  • the present application relates to a sensor, and in particular, to a time-of-flight sensor, a ranging system and an electronic device.
  • CMOS image sensors have been mass-produced and applied.
  • Traditional image sensors can generate two-dimensional (2D) images and videos.
  • image sensors and systems that can generate three-dimensional (3D) images have received extensive attention.
  • These three-dimensional image sensors can be applied to face recognition, augmented reality (AR) )/virtual reality (VR), drones, etc.
  • AR augmented reality
  • VR virtual reality
  • One of the existing implementations of the 3D image sensor is the distance measurement technology based on time of flight (TOF).
  • TOF time of flight
  • the phase relationship between the sampling time points is synchronized or fixed at a preset value, otherwise the accuracy will be reduced. Therefore, how to achieve the above purpose has become an important work item in the field.
  • One of the purposes of this application is to disclose a time-of-flight sensor, a ranging system and an electronic device that can ensure that the phase relationship between the emission time point of the light pulse and the sampling time point of the reflected light pulse is fixed at a preset value, so as to solve the problem. above problem.
  • An embodiment of the present application discloses a time-of-flight sensor that controls a light-emitting module to emit light pulses intermittently, and the light pulses are reflected by a target to generate reflected light pulses.
  • the time-of-flight sensor includes: a clock signal generating a circuit for generating a first clock signal and a second clock signal, wherein the frequencies of the first clock signal and the second clock signal are the same, and there is a difference between the first clock signal and the second clock signal a predetermined phase difference; a transmission circuit for generating a third clock signal according to the first clock signal, the third clock signal is output to the light-emitting module, so that the light-emitting module emits the light intermittently Pulse; replica transmission circuit, used to simulate the transmission circuit, and generate a fourth clock signal according to the second clock signal, so that the phase difference between the fourth clock signal and the third clock signal and the The predetermined phase difference can remain the same under temperature, bias or process variation; a delay locked loop is coupled to the replica
  • An embodiment of the present application discloses a time-of-flight ranging system, the time-of-flight ranging system includes: the above-mentioned time-of-flight sensor; and the light-emitting module includes: a light source control path for Three clock signals generate a light source control signal; and a light source for intermittently emitting the light pulses according to the light source control signal.
  • An embodiment of the present application discloses a time-of-flight ranging system
  • the time-of-flight ranging system includes: the above-mentioned time-of-flight sensor; and the light-emitting module includes: a light source control path for Three clock signals generate a light source control signal to replicate the light source control path, which is coupled between the replicated transmission circuit and the delay-locked loop.
  • Four clock signals generate a seventh clock signal to the delay locked loop of the time-of-flight sensor so that the phase difference and the predetermined phase difference between the light source control signal and the seventh clock signal vary with temperature, bias, or remain the same for process variation; and a light source for intermittently emitting the light pulses in accordance with the light source control signal.
  • An embodiment of the present application discloses an electronic device, including the above-mentioned ranging system: and a processor, which is coupled to the ranging system.
  • the time-of-flight sensor, ranging system and electronic device of the present application can ensure that the phase relationship between the emission time point of the light pulse and the sampling time point of the reflected light pulse is fixed at a preset value, so as to maintain the accuracy of the obtained depth information .
  • FIG. 1 is a schematic diagram of a first embodiment of a time-of-flight ranging system of the present application.
  • FIG. 2 is a schematic diagram of a first embodiment of the delay locked loop in FIG. 1 .
  • FIG. 3 is a schematic diagram of a second embodiment of the delay locked loop in FIG. 1 .
  • FIG. 4 is a schematic diagram of an embodiment of the light emitting module in FIG. 1 .
  • FIG. 5 is a schematic diagram of a second embodiment of the time-of-flight ranging system of the present application.
  • FIG. 6 is a schematic diagram of an embodiment of the light emitting module in FIG. 5 .
  • first and second features are in direct contact with each other; and may also include Certain embodiments may have additional components formed between the first and second features described above, such that the first and second features may not be in direct contact.
  • present disclosure may reuse reference numerals and/or reference numerals in various embodiments. Such reuse is for brevity and clarity, and does not in itself represent a relationship between the different embodiments and/or configurations discussed.
  • spatially relative terms such as “below”, “below”, “below”, “above”, “above” and the like, may be used to facilitate the description of the drawings. relationship between one component or feature shown with respect to another component or feature.
  • These spatially relative terms are intended to encompass many different orientations of the device in use or operation in addition to the orientation depicted in the figures.
  • the device may be positioned in other orientations (eg, rotated 90 degrees or at other orientations) and these spatially relative descriptors should be interpreted accordingly.
  • 3D image sensors stereo binocular, structured light and time of flight (ToF).
  • ToF time of flight
  • light pulses are emitted first, and then the reflected light pulses are sampled by the time-of-flight sensor to calculate the flight time of photons between the target and the time-of-flight sensor, thereby obtaining the target object. depth information.
  • the time-of-flight obtained by a time-of-flight sensor is often affected by the physical properties of the electronic components in the time-of-flight sensor.
  • the physical characteristics of the electronic components of the time-of-flight sensor may change, resulting in the emission time point of the light pulse and the sampling time of the reflected light pulse.
  • the phase relationship between the points cannot be fixed at a preset value, which reduces the accuracy of the obtained depth information.
  • the phase relationship between the emission time point of the light pulse and the sampling time point of the reflected light pulse is not affected by temperature, voltage or manufacturing process, the accuracy of the time-of-flight sensor can be improved, the details of which are described below.
  • FIG. 1 is a schematic diagram of a first embodiment of a time-of-flight ranging system 100 of the present application.
  • the time-of-flight ranging system 100 includes a time-of-flight sensor 102 and a light-emitting module 120, which can be used to detect the distance between the target 124 and the ranging system 100. It should be noted that the distance between the target 124 and the ranging system 100 It should be less than or equal to the maximum measurement distance of the ranging system 100 .
  • the time-of-flight sensor 102 is disposed on the first chip, for example, the first chip may be a sensor chip, or the time-of-flight sensor 102 is a part of the first chip; the light-emitting module 120 is disposed on the second chip , and the first chip and the second chip can be disposed in an electronic device, for example, the electronic device can be any electronic device such as a smart phone, a personal digital assistant, a handheld computer system or a tablet computer.
  • the time-of-flight sensor 102 controls the light-emitting module 120 to emit light pulses 122 according to a preset frequency and intensity. In this embodiment, the time-of-flight sensor 102 controls the light-emitting module 120 to emit light pulses 122 intermittently. Light pulse 122 is reflected by target 124 to generate reflected light pulse 126 . The time-of-flight sensor 102 senses and samples the reflected light pulses 126 to generate a sampling result pout, which can be used to calculate the distance between the target 124 and the ranging system 100 by measuring the different parts of the target 124. The depth information of the target 124 can be obtained by the calculation of the distance.
  • Time-of-flight sensor 102 includes clock signal generation circuit 104 , transfer circuit 106 , replica transfer circuit 108 , delay locked loop 110 , clock tree 112 , and pixel array 114 .
  • the clock signal generating circuit 104 is used for generating the first clock signal clk1 and the second clock signal clk2, wherein the frequencies of the first clock signal clk1 and the second clock signal clk2 are the same, and the difference between the first clock signal clk1 and the second clock signal clk2 with a predetermined phase difference between
  • the clock signal generating circuit 104 can generate the first clock signal clk1 and the second clock signal clk2 according to a reference clock (not shown in the figure), wherein the source of the reference clock can be from a place where the time-of-flight sensor is located.
  • the predetermined phase difference can be set according to the time-of-flight algorithm, and its decision method is not within the scope of this application, so this application does not limit the predetermined phase difference
  • the value of that is, the predetermined phase difference Can be greater than zero, less than zero, or equal to zero.
  • the first clock signal clk1 passes through a path to control the light-emitting module 120 to emit light pulses 122; the second clock signal clk2 passes through another path to control the timing of sampling the reflected light pulses 126 by the pixel array 114.
  • the present application The purpose is to keep the difference between the time point when the light emitting module 120 emits the light pulse 122 and the time point when the pixel array 114 samples the reflected light pulse 126 as much as possible at the predetermined phase difference ⁇ 1, and is not affected by temperature, voltage or Manufacturing process impact.
  • the transmission circuit 106 is used for generating a third clock signal clk3 according to the first clock signal clk1, and the third clock signal clk3 is output to the light emitting module 120, so that the light emitting module 120 emits light pulses 122 intermittently.
  • the second chip where the light-emitting module 120 is located and the second chip where the time-of-flight sensor 102 is located are different chips, and the frequency of the first clock signal clk1 may be several hundred MHz.
  • the first clock signal clk1 needs to be processed.
  • the transmission circuit 106 is a low-voltage differential signal (Low-Voltage Differential Signaling, LVDS) circuit.
  • the first clock signal clk1 is converted into a small amplitude differential signal to reduce noise and save power consumption.
  • the present application is not limited to this, and the transmission circuit 106 may also use other methods, for example, the third clock signal clk3 may be a non-differential signal.
  • the solution of the present application is to additionally add a copy transmission circuit 108 in the path from the second clock signal clk2 to the pixel array 114 to simulate the transmission circuit 106, and the copy transmission circuit 108 generates the fourth clock signal clk4 according to the second clock signal clk2.
  • the designs of the replica transfer circuit 108 and the transfer circuit 106 are substantially the same, so the respective delays caused to the first clock signal clk1 and the third clock signal clk3 are also approximately the same. Furthermore, since the replica transfer circuit 108 and the transfer circuit 106 are located in the same chip, the effects of temperature, voltage or manufacturing process on the replica transfer circuit 108 and the transfer circuit 106 are approximately the same, in other words, temperature, voltage or manufacturing process changes will The replica transfer circuit 108 and the transfer circuit 106 are changed synchronously so that the phase difference between the fourth clock signal clk4 and the third clock signal clk3 can be maintained at a predetermined phase difference under temperature, bias or process changes. In some embodiments, the layout of the transfer circuit 106 is directly adjacent to the layout of the replica transfer circuit 108 , so that the effects of temperature, voltage or manufacturing process on the transfer circuit 106 and the replica transfer circuit 108 are more closely aligned.
  • the layout of the replica transfer circuit 108 is exactly the same as that of the transfer circuit 106 .
  • the present application is not limited to this.
  • the layout of the replica transfer circuit 108 and the layout of the transfer circuit 106 are not exactly the same. Or through other special designs, as long as the delay caused by the transmission circuit 106 to the first clock signal clk1 and the delay caused by the replica transmission circuit 108 to the third clock signal clk3 can be approximately the same, it falls within the scope of the present application.
  • the fourth clock signal clk4 needs to be distributed to multiple pixel columns of the pixel array 114, generally the number of pixel columns of the pixel array 114 is huge, so in order to provide a sufficient driving force, the clock tree 12 is required to generate a sufficient driving force.
  • the plurality of sixth clock signals clk6 are supplied to the plurality of pixel columns of the pixel array 114, and the phase relationship of the plurality of sixth clock signals clk6 with each other is kept constant.
  • the delay locked loop 110 is to ensure that the phase difference between the plurality of sixth clock signals clk6 and the fourth clock signals clk4 output by the clock tree 12 can be kept zero when the temperature, bias voltage or process changes.
  • phase difference between the plurality of sixth clock signals clk6 and the third clock signal clk3 output by the clock tree 12 is kept within the predetermined phase difference Specifically, the phases of the plurality of sixth clock signals clk6 output by the clock tree 12 are all the same, and the delay locked loop 110 generates the fifth clock signal clk5 according to one of the plurality of sixth clock signals clk6 and the fourth clock signal clk4 .
  • the clock tree 112 includes a plurality of paths, the plurality of paths respectively include a start end and an end end, the plurality of start ends share the same point and are used for receiving the fifth clock signal clk5, and the plurality of end ends are respectively coupled to the pixels
  • the fifth clock signal clk5 starts from the source and passes through the plurality of paths to become a plurality of sixth clock signals clk6 to the plurality of pixel columns, and the plurality of paths are respectively
  • each transmission line between the clock signal generation circuit 104, the transmission circuit 106, the replica transmission circuit 108, the delay locked loop 110, the clock tree 112, and the pixel array 114 in FIG. 1 is compared with that of the replica transmission circuit. 108, the delay-locked loop 110, and the compensation brought by the clock tree 112 are relatively small, so the simple delay of each transmission line is ignored and not discussed here.
  • FIG. 2 is a schematic diagram of a first embodiment of the delay locked loop 110 in FIG. 1 .
  • Delay locked loop 110 includes phase detector 202 , charge pump 204 , filter 206 and voltage controlled delay line 208 .
  • the phase detector 202 receives the sixth clock signal clk6 and the fourth clock signal clk4 of any one channel, and is used to generate the phase difference information se1 between the sixth clock signal and the fourth clock signal clk4.
  • the identification Phaser 202 is implemented using analog circuits.
  • the charge pump 204 is used for charging or discharging the filter 206 in response to the phase difference information se1 to generate the voltage information sc1, and the filter 206 performs filtering processing on the voltage information sc1 to generate the voltage-controlled delay line control signal sf1.
  • filter 206 is implemented using analog circuitry.
  • the voltage controlled delay line 208 is used to pass the fourth clock signal clk4 through the voltage controlled delay line 208 to generate the fifth clock signal clk5, and the voltage controlled delay line 208 causes a variable phase between the fifth clock signal clk5 and the fourth clock signal clk4. and the variable phase difference is controlled by the voltage-controlled delay line control signal sf1.
  • the voltage controlled delay line 208 is implemented using analog circuitry. That is, the voltage-controlled delay line is controlled by the control signal sf1 so that the fourth clock signal clk4 input to the voltage-controlled delay line generates a corresponding phase difference to output the fifth clock signal clk5.
  • FIG. 3 is a schematic diagram of a second embodiment of the delay locked loop 110 in FIG. 1 .
  • Delay locked loop 110 includes phase detector 302 , accumulator 304 , filter 306 , and digital delay line 308 . Similar to the delay locked loop 110 of FIG. 3 and the delay locked loop 110 of FIG. 2 , the difference is that the delay locked loop 110 of FIG. 3 is implemented using digital circuits.
  • the phase detector 302 is used to generate the phase difference information se2 between one of the plurality of sixth clock signals clk6 and the fourth clock signal clk4. In the embodiment shown in FIG. 3, the phase detector 202 is implemented using an analog circuit.
  • the accumulator 304 is used for generating the accumulated phase information sc2 to the filter 306 according to the accumulated phase difference information se2, so that the filter 306 performs filtering processing on the voltage information sc2 to generate the digital delay line control signal sf2.
  • filter 306 is implemented using digital circuitry.
  • the digital delay line 308 is used to pass the fourth clock signal clk4 through the digital delay line 308 to generate the fifth clock signal clk5, and the digital delay line 208 causes a variable phase difference between the fifth clock signal clk5 and the fourth clock signal clk4, And the variable phase difference is controlled by the digital delay line control signal sf2.
  • the pixel array 114 has a plurality of pixel columns, which respectively sample the reflected light pulses 126 according to a plurality of sixth clock signals clk6 to generate a sampling result pout.
  • the time-of-flight sensor 102 may include a depth determination unit 116, and the depth determination unit 116 is configured to obtain depth information of the target object 124 according to the sampling result pout.
  • the depth determination unit 116 may be unnecessary, for example, the sampling result pout generated by the pixel array 114 is sent to a processor outside the chip where the time-of-flight sensor 102 is located to calculate the depth information of the target 124 .
  • FIG. 4 in order to ensure that the time between the time when the third clock signal clk3 reaches the light emitting module 120 and the time when the light pulse 122 is actually emitted changes accordingly due to changes in temperature, bias voltage or process, FIG. 4 can be used.
  • FIG. 4 is a schematic diagram of an embodiment of the light emitting module 120 in FIG. 1 .
  • the light source control signal s1 is generated through the light source control path 402, and the light source 404 intermittently emits light pulses 122 according to the light source control signal s1.
  • the light source 404 may be, but is not limited to, a laser diode (LD), light emitting diode (LED), or other light source that can generate the light pulses 122.
  • the light source control path 402 is specially designed so that the phase difference between the light source control signal s1 and the third clock signal clk3 is not affected by temperature, bias voltage or process.
  • the embodiment of FIG. 1 is not limited to use the light emitting module 120 of FIG. 4 .
  • using a general light emitting module may contribute a slight error, so that the difference between the time point when the light emitting module 120 emits the light pulse 122 and the time point when the pixel array 114 samples the reflected light pulse 126 is not exactly equal to the predetermined phase Difference Therefore, the present application also proposes the embodiment of FIG. 5 to provide another method other than using the light emitting module 120 of FIG. 4 .
  • FIG. 5 is a schematic diagram of a second embodiment of a time-of-flight ranging system 500 of the present application.
  • the difference between the time-of-flight ranging system 500 in FIG. 5 and the time-of-flight ranging system 100 in FIG. 1 is that the fourth clock signal clk4 in FIG. 1 is directly sent to the delay locked loop 110, but the fourth clock signal clk4 in FIG.
  • the four clock signals clk4 are fed back to the delay-locked loop 110 only after the four-clock signal clk4 is sent to the light-emitting module 520 outside the chip where the time-of-flight sensor 502 is located.
  • the purpose is to additionally simulate the light source control path 602 of the light emitting module 520 in the path of the second clock signal clk2 to match the path of the first clock signal clk1 .
  • FIG. 6 is a schematic diagram of an embodiment of the light emitting module 520 in FIG. 5 .
  • a duplicate light source control path 604 is additionally added to the light emitting module 520 to simulate the light source control path 602 , and the duplicate light source control path 604 generates a seventh light source control path according to the fourth clock signal clk4
  • the clock signal clk7 since the design of the replica light source control path 604 and the light source control path 602 are substantially the same, the delays caused to the third clock signal clk3 and the fourth clock signal clk4 are also substantially the same.
  • the replicated light source control path 604 and the light source control path 602 are located in the same chip, the effects of temperature, voltage or manufacturing process on the replicated light source control path 604 and the light source control path 602 are approximately the same, in other words, the temperature, voltage or Manufacturing process changes will cause the replica light source control path 604 and the light source control path 602 to change synchronously, so that the phase difference between the light source control signal s1 and the seventh clock signal clk7 can be maintained at a predetermined phase difference when temperature, bias or process changes The seventh clock signal clk7 is fed back to the delay locked loop 110 of the delay locked loop 110 .
  • the layout of the duplicate light source control path 604 is exactly the same as the layout of the light source control path 602 .
  • the present application is not limited to this.
  • the layout of the light source control path 604 and the layout of the light source control path 602 are copied, for example, the layout of the copied light source control path 604 and the layout of the light source control path 602 are set against each other. , or through other special designs, as long as the delay caused by the light source control path 602 to the third clock signal clk3 and the delay caused by the duplicate light source control path 604 to the fourth clock signal clk4 can be approximately the same, it is within the scope of the present application.

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Abstract

一种飞行时间传感器（102）及相关芯片、电子装置及测距系统（100），飞行时间传感器（102）包括：时钟信号产生电路（104），用来产生第一时钟信号（clk1）与第二时钟信号（clk2）；传送电路（106），用来依据第一时钟信号（clk1）产生第三时钟信号（clk3），第三时钟信号（clk3）被输出至发光模组（120）；复制传送电路（108），用来仿真传送电路（106），并依据第二时钟信号（clk2）产生第四时钟信号（clk4）；延迟锁定环路（110），用来依据多个第六时钟信号（clk6）的其中之一和第四时钟信号（clk4）产生第五时钟信号（clk5）；时钟树（112），用来依据第五时钟信号（clk5）产生多个第六时钟信号（clk6）；像素阵列（114），其中多列像素列分别依据多个第六时钟信号（clk6）对反射光脉冲（126）进行采样以产生采样结果；以及深度判断单元（116），用来依据采样结果得到深度信息。

Description

飞行时间传感器、测距系统及电子装置 技术领域
本申请涉及一种传感器，尤其涉及一种飞行时间传感器、测距系统及电子装置。
背景技术
CMOS图像传感器已经得到大规模生产和应用。传统的图像传感器可以生成二维(2D)图像和视频，近来可以产生三维(3D)图像的图像传感器和系统受到广泛关注，这些三维图像传感器可以应用于脸部识别，增强现实(augmented reality，AR)/虚拟现实(virtual reality，VR)，无人机等。
现有的三维图像传感器的实现方式之一为基于飞行时间(time of flight，TOF)的距离测量技术，在此技术中，为了增加准确度，需要确保光脉冲的发射时间点与反射光脉冲的采样时间点之间的相位关系同步或固定在预设值，否则准确度会降低，因此，如何达到上述目的，已成为本领域一个重要的工作项目。
发明内容
本申请的目的之一在于公开一种能够确保光脉冲的发射时间点与反射光脉冲的采样时间点之间的相位关固定在预设值的飞行时间传感器、测距系统及电子装置，来解决上述问题。
本申请的一实施例公开了一种所述飞行时间传感器控制发光模组间歇性地发出光脉冲，所述光脉冲被目标物反射而产生反射光脉冲，所述飞行时间传感器包括：时钟信号产生电路，用来产生第一时钟信 号与第二时钟信号，其中所述第一时钟信号和所述第二时钟信号的频率相同，且所述第一时钟信号和所述第二时钟信号之间具有预定相位差；传送电路，用来依据所述第一时钟信号产生第三时钟信号，所述第三时钟信号被输出至所述发光模组，使所述发光模组间歇性地发出所述光脉冲；复制传送电路，用来仿真所述传送电路，并依据所述第二时钟信号产生第四时钟信号，使所述第四时钟信号和所述第三时钟信号之间的相位差和所述预定相位差在温度、偏压或工艺变化时能保持相同；延迟锁定环路，耦接至所述复制传送电路以及多个第六时钟信号的其中之一以产生第五时钟信号，使所述多个第六时钟信号的其中之一和所述第四时钟信号之间的相位差保持为零；时钟树，用来依据所述第五时钟信号产生所述多个第六时钟信号，其中所述多个第六时钟信号的多个相位彼此皆相同；以及像素阵列，具有多列像素列，所述多列像素列分别依据所述多个第六时钟信号对所述反射光脉冲进行采样以产生采样结果。
本申请的一实施例公开了一种飞行时间测距系统，所述飞行时间测距系统包括：上述的飞行时间传感器；以及所述发光模组，包括：光源控制路径，用来依据所述第三时钟信号产生光源控制信号；以及光源，用来依据所述光源控制信号间歇性地发出所述光脉冲。
本申请的一实施例公开了一种飞行时间测距系统，所述飞行时间测距系统包括：上述的飞行时间传感器；以及所述发光模组，包括：光源控制路径，用来依据所述第三时钟信号产生光源控制信号复制光源控制路径，耦接于所述复制传送电路和所述延迟锁定环路之间，所述复制光源控制路径用来仿真所述光源控制路径，并依据所述第四时钟信号产生第七时钟信号至所述飞行时间传感器的所述延迟锁定环路，使所述光源控制信号和所述第七时钟信号之间的相位差和预定相位差在温度、偏压或工艺变化时能保持相同；以及光源，用来依据所述光源控制信号间歇性地发出所述光脉冲。
本申请的一实施例公开了一种电子装置，包括上述的测距系统：以及处理器，耦接至所述测距系统。
本申请的飞行时间传感器、测距系统及电子装置能够确保光脉冲的发射时间点与反射光脉冲的采样时间点之间的相位关系固定在预设值，以维持所得到的深度信息的准确度。
附图说明
图1为本申请的飞行时间测距系统的第一实施例的示意图。
图2为图1中的延迟锁定环路的第一实施例的示意图。
图3为图1中的延迟锁定环路的第二实施例的示意图。
图4为图1中的发光模组的实施例的示意图。
图5为本申请的飞行时间测距系统的第二实施例的示意图。
图6为图5中的发光模组的实施例的示意图。
具体实施方式
以下揭示内容提供了多种实施方式或例示，其能用以实现本揭示内容的不同特征。下文所述之组件与配置的具体例子系用以简化本揭示内容。当可想见，这些叙述仅为例示，其本意并非用于限制本揭示内容。举例来说，在下文的描述中，将一第一特征形成于一第二特征上或之上，可能包括某些实施例其中所述的第一与第二特征彼此直接接触；且也可能包括某些实施例其中还有额外的组件形成于上述第一与第二特征之间，而使得第一与第二特征可能没有直接接触。此外，本揭示内容可能会在多个实施例中重复使用组件符号和/或标号。此种重复使用乃是基于简洁与清楚的目的，且其本身不代表所讨论的不同实施例和/或组态之间的关系。
再者，在此处使用空间上相对的词汇，譬如「之下」、「下方」、「低于」、「之上」、「上方」及与其相似者，可能是为了方便说明图中所绘示的一组件或特征相对于另一或多个组件或特征之间的关系。这 些空间上相对的词汇其本意除了图中所绘示的方位之外，还涵盖了装置在使用或操作中所处的多种不同方位。可能将所述设备放置于其他方位(如，旋转90度或处于其他方位)，而这些空间上相对的描述词汇就应该做相应的解释。
虽然用以界定本申请较广范围的数值范围与参数皆是约略的数值，此处已尽可能精确地呈现具体实施例中的相关数值。然而，任何数值本质上不可避免地含有因个别测试方法所致的标准偏差。在此处，「约」通常系指实际数值在一特定数值或范围的正负10％、5％、1％或0.5％之内。或者是，「约」一词代表实际数值落在平均值的可接受标准误差之内，视本申请所属技术领域中具有通常知识者的考虑而定。当可理解，除了实验例之外，或除非另有明确的说明，此处所用的所有范围、数量、数值与百分比(例如用以描述材料用量、时间长短、温度、操作条件、数量比例及其他相似者)均经过「约」的修饰。因此，除非另有相反的说明，本说明书与附随申请专利范围所揭示的数值参数皆为约略的数值，且可视需求而更动。至少应将这些数值参数理解为所指出的有效位数与套用一般进位法所得到的数值。在此处，将数值范围表示成由一端点至另一端点或介于二端点之间；除非另有说明，此处所述的数值范围皆包括端点。
现有的三维图像传感器主要有三种实现方式：立体双目，结构光和飞行时间(time of flight，ToF)。通常，在飞行时间的实现方式当中，会先发射光脉冲，再利用飞行时间传感器来对反射光脉冲进行采样以计算出光子在目标物和飞行时间传感器之间飞行的时间，藉此得到目标物的深度信息。
然而，通过飞行时间传感器所得到的飞行时间往往会受到飞行时间传感器中的电子元件的物理特性的影响。举例来说，当飞行时间传感器所处的操作环境的温度、电压或制造工艺改变时，可能会改变飞行时间传感器的电子元件的物理特性，造成光脉冲的发射时间点与反射光脉冲的采样时间点之间的相位关系无法固定在预设值，使得到的深度信息的准确度下降。反之，若能使光脉冲的发射时间点与反射光 脉冲的采样时间点之间的相位关系不受温度、电压或制造工艺影响，便可提升飞行时间传感器的准确度，其细节说明如下。
图1为本申请的飞行时间测距系统100的第一实施例的示意图。飞行时间测距系统100包含飞行时间传感器102以及发光模组120，可用于探测目标物124与测距系统100之间的距离，需注意的是，目标物124与测距系统100之间的距离应小于或等于测距系统100的最大测量距离。在本实施例中，飞行时间传感器102设置于第一芯片，例如所述第一芯片可以是传感器芯片，或者飞行时间传感器102属于所述第一芯片的一部分；发光模组120设置于第二芯片，且所述第一芯片及所述第二芯片可以设置于电子装置中，例如所述电子装置可为例如智能型手机、个人数字助理、手持式计算机系统或平板计算机等任何电子装置。
具体来说，飞行时间传感器102控制发光模组120按照预设的频率、强度等发出光脉冲122，在本实施例中，飞行时间传感器102控制发光模组120间歇性地发出光脉冲122。光脉冲122被目标物124反射而产生反射光脉冲126。飞行时间传感器102对反射光脉冲126进行传感以及采样以产生采样结果pout，采样结果pout可以用来计算出目标物124与测距系统100之间的距离，而通过对目标物124上不同部分的距离的计算，可以得到目标物124的深度信息。
飞行时间传感器102包含时钟信号产生电路104、传送电路106、复制传送电路108、延迟锁定环路110、时钟树112以及像素阵列114。其中时钟信号产生电路104用来产生第一时钟信号clk1与第二时钟信号clk2，其中第一时钟信号clk1和第二时钟信号clk2的频率相同，且第一时钟信号clk1和第二时钟信号clk2之间具有预定相位差
Figure PCTCN2020123617-appb-000001
举例来说，时钟信号产生电路104可以依据参考时脉(未绘示于图中)来产生第一时钟信号clk1与第二时钟信号clk2，其中所述参考时脉源头可以来自飞行时间传感器所在的芯片外部的晶体振荡器。另外，应注意的是，预定相位差
Figure PCTCN2020123617-appb-000002
的值可以依据飞行时间算法来设定，其决定方式不在本申请的讨论范围，因此本申请中不限定预定相位差
Figure PCTCN2020123617-appb-000003
的值，即预定相位差
Figure PCTCN2020123617-appb-000004
可大于零、小于零或等于零。
由图1可以看出，第一时钟信号clk1经过一路径控制发光模组120发射光脉冲122；第二时钟信号clk2经过另一路径控制像素阵列114对反射光脉冲126进行采样的时序，本申请的目的在于使发光模组120发射光脉冲122的时间点和像素阵列114对反射光脉冲126进行采样的时间点之间的差距尽可能地保持在预定相位差φ1，且不受温度、电压或制造工艺影响。
传送电路106用来依据第一时钟信号clk1产生第三时钟信号clk3，第三时钟信号clk3被输出至发光模组120，使发光模组120间歇性地发出光脉冲122。一般来说，发光模组120所在的所述第二芯片和飞行时间传感器102所在的第二芯片为不同的芯片，且第一时钟信号clk1的频率可能为几百MHz等级，因此传送电路106为了将第一时钟信号clk1传送出飞行时间传感器102所在的芯片，需要对第一时钟信号clk1做处理，举例来说，传送电路106为低电压差分信号(Low-Voltage Differential Signaling,LVDS)电路，将第一时钟信号clk1转换为小振幅差分信号，以降低噪声并节省功耗。但本申请不以此为限，传送电路106亦可使用其他作法，例如第三时钟信号clk3可以是非差分信号。
总而言之，无论传送电路106使用任何的作法，都不可能不对第一时钟信号clk1造成延迟，也就是很难保证第一时钟信号clk1经过传送电路106后，和第二时钟信号clk2之间的相位不会改变，进而使控制发光模组120发射光脉冲122的时间点变得无法掌握。本申请的解决方式在于在第二时钟信号clk2到像素阵列114的路径中，额外增加复制传送电路108来仿真传送电路106，复制传送电路108依据第二时钟信号clk2产生第四时钟信号clk4，由于复制传送电路108和传送电路106的设计大致相同，因此对第一时钟信号clk1和第三时钟信号clk3所分别造成的延迟也大致相同。此外，由于复制传送电路108和传送电路106位于同一芯片中，温度、电压或制造工艺对复制传送电路108和传送电路106所造成的影响大致相同，换句话说， 温度、电压或制造工艺改变会使复制传送电路108和传送电路106同步改变，使第四时钟信号clk4和第三时钟信号clk3之间的相位差在温度、偏压或工艺变化时能保持在预定相位差
Figure PCTCN2020123617-appb-000005
在某些实施例中，传送电路106的布局直接相邻复制传送电路108的布局，使温度、电压或制造工艺对传送电路106和复制传送电路108造成的影响更接近一致。
在本实施例中，复制传送电路108的布局和传送电路106的布局完全相同。但本申请不以此为限，在某些实施例中，复制传送电路108的布局和传送电路106的布局不完全相同，例如将复制传送电路108的布局和传送电路106的布局对衬设置，或通过其他特殊的设计，只要可以使传送电路106对第一时钟信号clk1造成的延迟和复制传送电路108对第三时钟信号clk3造成的延迟大致相同，即属本申请的范围。
由于第四时钟信号clk4需要分配给像素阵列114的多列像素列，一般来说像素阵列114的像素列数目庞大，因此为了提供足够的驱动力，需要时钟树12来产生出具有足够驱动力的多个第六时钟信号clk6给像素阵列114的多列像素列，且维持多个第六时钟信号clk6彼此的相位关系保持固定。而延迟锁定环路110则是为了确保时钟树12输出的多个第六时钟信号clk6和第四时钟信号clk4之间的相位差在温度、偏压或工艺变化时能保持为零，如此一来即可确保时钟树12输出的多个第六时钟信号clk6和第三时钟信号clk3之间的相位差保持在预定相位差
Figure PCTCN2020123617-appb-000006
具体来说，时钟树12输出的多个第六时钟信号clk6的相位皆一致，延迟锁定环路110依据多个第六时钟信号clk6的其中之一和第四时钟信号clk4产生第五时钟信号clk5。
时钟树112包含多个路径，所述多个路径分别包含起始端与结束端，所述多个起始端共点且用来接收第五时钟信号clk5，所述多个结束端分别耦接至像素阵列114的多列像素列，使第五时钟信号clk5从所述源头开始，经由所述多个路径后成为多个第六时钟信号clk6至所述多列像素列，所述多个路径上分别具有多个缓冲器以增加驱动 力，且所述多个路径各自从所述起始端到所述结束端的信号传递距离及缓冲器的设置皆经过设计，例如所述多个路径的长度相同，且具有相同数目的缓冲器，使多个第六时钟信号clk6之间的相位差在温度、偏压或工艺变化时能保持为零。
应注意的是，图1中的时钟信号产生电路104、传送电路106、复制传送电路108、延迟锁定环路110、时钟树112以及像素阵列114之间的各传输线的延迟相较于复制传送电路108及延迟锁定环路110、时钟树112带来的补偿来说相对微小，因此单纯各传输线的延迟在此忽略而不加以讨论。
图2为图1中的延迟锁定环路110的第一实施例的示意图。延迟锁定环路110包括鉴相器202、电荷泵204、滤波器206以及压控延迟线208。鉴相器202接收任意一路的第六时钟信号clk6和第四时钟信号clk4，并用来产生第六时钟信号和第四时钟信号clk4之间的相位差信息se1，在图2中的实施例，鉴相器202使用模拟电路实现。电荷泵204用来响应于相位差信息se1以产生电压信息sc1来对滤波器206进行充电或放电，滤波器206对电压信息sc1进行滤波处理以产生压控延迟线控制信号sf1。在图2中的实施例，滤波器206使用模拟电路实现。
压控延迟线208用来使第四时钟信号clk4经过压控延迟线208以产生第五时钟信号clk5，且压控延迟线208造成第五时钟信号clk5和第四时钟信号clk4之间具有可变相位差，且所述可变相位差受到压控延迟线控制信号sf1的控制。在图2中的实施例，压控延迟线208使用模拟电路实现。即，压控延迟线受控于控制信号sf1而使得输入到压控延迟线第四时钟信号clk4产生对应的相位差以输出第五时钟信号clk5。
图3为图1中的延迟锁定环路110的第二实施例的示意图。延迟锁定环路110包括鉴相器302、累加器304、滤波器306以及数字延迟线308。和图3的延迟锁定环路110和图2的延迟锁定环路110类似，差异在于图3的延迟锁定环路110使用数字电路实现。鉴相器 302用来产生多个第六时钟信号clk6的其中之一和第四时钟信号clk4之间的相位差信息se2，在图3中的实施例，鉴相器202为使用模拟电路实现。累加器304用来依据累加相位差信息se2以产生累加相位信息sc2至滤波器306，使滤波器306对电压信息sc2进行滤波处理以产生数字延迟线控制信号sf2。在图3中的实施例，滤波器306使用数字电路实现。
数字延迟线308用来使第四时钟信号clk4经过数字延迟线308以产生第五时钟信号clk5，且数字延迟线208造成第五时钟信号clk5和第四时钟信号clk4之间具有可变相位差，且所述可变相位差受到数字延迟线控制信号sf2的控制。
像素阵列114具有多列像素列，所述多列像素列分别依据多个第六时钟信号clk6对反射光脉冲126进行采样以产生采样结果pout。在某些实施例中，飞行时间传感器102可包含深度判断单元116，深度判断单元116用来依据采样结果pout得到目标物124的深度信息。在某些其他实施例中，深度判断单元116可以是非必要的，例如像素阵列114产生的采样结果pout被送至飞行时间传感器102所在的芯片之外的处理器来计算目标物124的深度信息。
在某些实施例中，为了确保第三时钟信号clk3到达发光模组120的时间点和真正发出光脉冲122的时间点的间隔时间因温度、偏压或工艺的变化跟著改变，可以使用图4中的发光模组120。图4为图1中的发光模组120的实施例的示意图。其中第三时钟信号clk3到达发光模组120后，通过光源控制路径402产生光源控制信号sl，光源404依据光源控制信号sl间歇性地发出光脉冲122。光源404可以是(但不限于)激光二极管(laser diode，LD)、发光二极管(light emitting diode，LED)或其他可以产生光脉冲122的光源。其中光源控制路径402经过特殊设计，能够使光源控制信号sl与第三时钟信号clk3之间的相位差不受温度、偏压或工艺的影响。
然图1的实施例并不限制要使用图4的发光模组120。然而，使用一般的发光模组可能会贡献些微的误差，使发光模组120发射光脉 冲122的时间点和像素阵列114对反射光脉冲126进行采样的时间点之间的差距不完全等于预定相位差
Figure PCTCN2020123617-appb-000007
因此，本申请还提出图5的实施例来提供除使用图4的发光模组120之外的另一种作法。
图5为本申请的飞行时间测距系统500的第二实施例的示意图。图5中的飞行时间测距系统500和图1中的飞行时间测距系统100的差异在于，图1中的第四时钟信号clk4直接被送至延迟锁定环路110，但图5中的第四时钟信号clk4被送至飞行时间传感器502所在的芯片之外的发光模组520后，才反馈回延迟锁定环路110。其目的是为了要在第二时钟信号clk2的路径中额外仿真出发光模组520的光源控制路径602，以匹配第一时钟信号clk1的路径。
图6为图5中的发光模组520的实施例的示意图。本申请在第二时钟信号clk2到像素阵列114的路径中，额外在发光模组520中增加复制光源控制路径604来仿真光源控制路径602，复制光源控制路径604依据第四时钟信号clk4产生第七时钟信号clk7，由于复制光源控制路径604和光源控制路径602的设计大致相同，因此对第三时钟信号clk3和第四时钟信号clk4所分别造成的延迟也大致相同。此外，由于复制光源控制路径604和光源控制路径602位于同一芯片中，温度、电压或制造工艺对复制光源控制路径604和光源控制路径602所造成的影响大致相同，换句话说，温度、电压或制造工艺改变会使复制光源控制路径604和光源控制路径602同步改变，使光源控制信号sl和第七时钟信号clk7之间的相位差在温度、偏压或工艺变化时能保持在预定相位差
Figure PCTCN2020123617-appb-000008
第七时钟信号clk7并反馈回延迟锁定环路110的延迟锁定环路110。
在本实施例中，复制光源控制路径604的布局和光源控制路径602的布局完全相同。但本申请不以此为限，在某些实施例中，复制光源控制路径604的布局和光源控制路径602的布局，例如将复制光源控制路径604的布局和光源控制路径602的布局对衬设置，或通过其他特殊的设计，只要可以使光源控制路径602对第三时钟信号clk3造成的延迟和复制光源控制路径604对第四时钟信号clk4造成的延 迟大致相同，即属本申请的范围。
上文的叙述简要地提出了本申请某些实施例之特征，而使得本申请所属技术领域具有通常知识者能够更全面地理解本揭示内容的多种态样。本申请所属技术领域具有通常知识者当可明了，其可轻易地利用本揭示内容作为基础，来设计或更动其他工艺与结构，以实现与此处所述之实施方式相同的目的和/或达到相同的优点。本申请所属技术领域具有通常知识者应当明白，这些均等的实施方式仍属于本揭示内容之精神与范围，且其可进行各种变更、替代与更动，而不会悖离本揭示内容之精神与范围。

Claims (14)

  1. 一种飞行时间传感器，所述飞行时间传感器控制发光模组间歇性地发出光脉冲，所述光脉冲被目标物反射而产生反射光脉冲，其特征在于，所述飞行时间传感器包括：
    时钟信号产生电路，用来产生第一时钟信号与第二时钟信号，其中所述第一时钟信号和所述第二时钟信号的频率相同，且所述第一时钟信号和所述第二时钟信号之间具有预定相位差；
    传送电路，用来依据所述第一时钟信号产生第三时钟信号，所述第三时钟信号被输出至所述发光模组，使所述发光模组间歇性地发出所述光脉冲；
    复制传送电路，用来仿真所述传送电路，并依据所述第二时钟信号产生第四时钟信号，使所述第四时钟信号和所述第三时钟信号之间的相位差和所述预定相位差保持相同；
    延迟锁定环路，耦接至所述复制传送电路以及多个第六时钟信号的其中之一以产生第五时钟信号，使所述多个第六时钟信号的其中之一和所述第四时钟信号之间的相位差保持为零；
    时钟树，用来依据所述第五时钟信号产生所述多个第六时钟信号，其中所述多个第六时钟信号的多个相位彼此皆相同；以及
    像素阵列，具有多列像素列，所述多列像素列分别依据所述多个第六时钟信号对所述反射光脉冲进行采样以产生采样结果。
  2. 如权利要求1所述的飞行时间传感器，其特征在于，所述时钟树包含多个路径，所述多个路径分别包含起始端与结束端，所述多个起始端共点且用来接收所述第五时钟信号，所述多个结束端分别耦接至所述多列像素列，使所述第五时钟信号从所述源头开始，经由所述多个路径后成为多个第六时钟信号至所述多列像素列，且所述多个路径各自从所述起始端到所述结束端的信号传递距离皆彼此匹配，使所述多个第六时钟信号之间的相位差在温度、偏压或工艺变化时能保持为零。
  3. 如权利要求1所述的飞行时间传感器，其特征在于，所述飞行时间传感器设置于第一芯片，且所述传送电路的布局相邻所述复制 传送电路的布局。
  4. 如权利要求1所述的飞行时间传感器，其特征在于，所述延迟锁定环路依据所述第四时钟信号及所述多个第六时钟信号的其中之一以产生所述第五时钟信号。
  5. 如权利要求4所述的飞行时间传感器，其特征在于，所述延迟锁定环路包括：
    鉴相器，用来产生所述多个第六时钟信号的其中之一和所述第四时钟信号之间的相位差信息；
    电荷泵，用来依据所述相位差信息产生电压信息至滤波器；
    所述滤波器，用来对所述电压信息进行滤波处理以产生压控延迟线控制信号；以及
    压控延迟线，用来使所述第四时钟信号经过所述压控延迟线以产生所述第五时钟信号，且所述压控延迟线造成所述第五时钟信号和所述第四时钟信号之间具有可变相位差，且所述可变相位差受到所述压控延迟线控制信号的控制。
  6. 如权利要求4所述的飞行时间传感器，其特征在于，所述延迟锁定环路包括：
    鉴相器，用来产生所述多个第六时钟信号的其中之一和所述第四时钟信号之间的相位差信息；
    累加器，用来依据累加所述相位差信息以产生累加相位信息至滤波器；
    所述滤波器，用来对所述累加相位信息进行滤波处理以产生数字延迟线控制信号；以及
    数字延迟线，用来使所述第四时钟信号经过所述数字延迟线以产生所述第五时钟信号，且所述数字延迟线造成所述第五时钟信号和所述第四时钟信号之间具有可变相位差，且所述可变相位差受到所述数字延迟线控制信号的控制。
  7. 如权利要求1所述的飞行时间传感器，其特征在于，所述飞行时 间传感器还包括：
    深度判断单元，用来依据所述采样结果得到深度信息。
  8. 一种飞行时间测距系统，其特征在于，所述飞行时间测距系统包括：
    如权利要求1至7中任一项所述的飞行时间传感器；以及
    所述发光模组，包括：
    光源控制路径，用来依据所述第三时钟信号产生光源控制信号；以及
    光源，用来依据所述光源控制信号间歇性地发出所述光脉冲。
  9. 如权利要求8所述的测距系统，其特征在于，所述第三时钟信号和所述光源控制信号之间的相位差为零。
  10. 一种飞行时间测距系统，其特征在于，所述飞行时间测距系统包括：
    如权利要求1至3及6中任一项所述的飞行时间传感器；以及
    所述发光模组，包括：
    光源控制路径，用来依据所述第三时钟信号产生光源控制信号；
    复制光源控制路径，耦接于所述复制传送电路和所述延迟锁定环路之间，所述复制光源控制路径用来仿真所述光源控制路径，并依据所述第四时钟信号产生第七时钟信号至所述飞行时间传感器的所述延迟锁定环路，使所述光源控制信号和所述第七时钟信号之间的相位差和预定相位差在温度、偏压或工艺变化时能保持相同；以及
    光源，用来依据所述光源控制信号间歇性地发出所述光脉冲。
  11. 如权利要求10所述的测距系统，其特征在于，所述发光模组设置于第二芯片，且所述光源控制路径的布局相邻所述复制光源控制路径的布局。
  12. 如权利要求10所述的测距系统，其特征在于，所述延迟锁定环路包括：
    鉴相器，用来产生所述多个第六时钟信号的其中之一和所述第七时钟信号之间的相位差信息；
    电荷泵，用来依据所述相位差信息产生电压信息至滤波器；
    所述滤波器，用来对所述电压信息进行滤波处理以产生压控延迟线控制信号；以及
    压控延迟线，用来使所述第七时钟信号经过所述压控延迟线以产生所述第五时钟信号，且所述压控延迟线造成所述第五时钟信号和所述第七时钟信号之间具有可变相位差，且所述可变相位差受到所述压控延迟线控制信号的控制。
  13. 如权利要求10所述的测距系统，其特征在于，所述延迟锁定环路包括：
    鉴相器，用来产生所述多个第六时钟信号的其中之一和所述第七时钟信号之间的相位差信息；
    累加器，用来依据累加所述相位差信息以产生累加相位信息至滤波器；
    所述滤波器，用来对所述累加相位信息进行滤波处理以产生数字延迟线控制信号；以及
    数字延迟线，用来使所述第四时钟信号经过所述数字延迟线以产生所述第五时钟信号，且所述数字延迟线造成所述第五时钟信号和所述第七时钟信号之间具有可变相位差，且所述可变相位差受到所述数字延迟线控制信号的控制。
  14. 一种电子装置，其特征在于，包括：
    如权利要求8至13中任一项所述的测距系统；以及
    处理器，耦接至所述测距系统。
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