WO2022083059A1 - 一种基于ltcc工艺的超宽通带五阶带通滤波器 - Google Patents

一种基于ltcc工艺的超宽通带五阶带通滤波器 Download PDF

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Publication number
WO2022083059A1
WO2022083059A1 PCT/CN2021/082523 CN2021082523W WO2022083059A1 WO 2022083059 A1 WO2022083059 A1 WO 2022083059A1 CN 2021082523 W CN2021082523 W CN 2021082523W WO 2022083059 A1 WO2022083059 A1 WO 2022083059A1
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layer
capacitor
parallel resonance
ceramic substrate
parallel
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PCT/CN2021/082523
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English (en)
French (fr)
Inventor
罗昌桅
卢冠宇
华嘉源
潘枫
刘楠
王利利
徐鑫
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嘉兴佳利电子有限公司
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Priority to US17/778,015 priority Critical patent/US20220399868A1/en
Priority to EP21881485.3A priority patent/EP4236068A1/en
Priority to KR1020227015938A priority patent/KR20220100874A/ko
Priority to JP2022536659A priority patent/JP7425202B2/ja
Publication of WO2022083059A1 publication Critical patent/WO2022083059A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H7/00—Multiple-port networks comprising only passive electrical elements as network components
    • H03H7/46—Networks for connecting several sources or loads, working on different frequencies or frequency bands, to a common load or source
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H7/00—Multiple-port networks comprising only passive electrical elements as network components
    • H03H7/01—Frequency selective two-port networks
    • H03H7/0115—Frequency selective two-port networks comprising only inductors and capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F27/00—Details of transformers or inductances, in general
    • H01F27/28—Coils; Windings; Conductive connections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F27/00—Details of transformers or inductances, in general
    • H01F27/40—Structural association with built-in electric component, e.g. fuse
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H3/00—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators
    • H03H3/007—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H7/00—Multiple-port networks comprising only passive electrical elements as network components
    • H03H7/01—Frequency selective two-port networks
    • H03H7/0153—Electrical filters; Controlling thereof
    • H03H7/0161—Bandpass filters
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H7/00—Multiple-port networks comprising only passive electrical elements as network components
    • H03H7/01—Frequency selective two-port networks
    • H03H7/17—Structural details of sub-circuits of frequency selective networks
    • H03H7/1708—Comprising bridging elements, i.e. elements in a series path without own reference to ground and spanning branching nodes of another series path
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H7/00—Multiple-port networks comprising only passive electrical elements as network components
    • H03H7/01—Frequency selective two-port networks
    • H03H7/17—Structural details of sub-circuits of frequency selective networks
    • H03H7/1741—Comprising typical LC combinations, irrespective of presence and location of additional resistors
    • H03H7/1775—Parallel LC in shunt or branch path
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F17/00—Fixed inductances of the signal type 
    • H01F17/0006—Printed inductances
    • H01F17/0013—Printed inductances with stacked layers
    • H01F2017/0026—Multilayer LC-filter
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/40—Structural combinations of fixed capacitors with other electric elements, the structure mainly consisting of a capacitor, e.g. RC combinations
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H1/00—Constructional details of impedance networks whose electrical mode of operation is not specified or applicable to more than one type of network
    • H03H2001/0021—Constructional details
    • H03H2001/0085—Multilayer, e.g. LTCC, HTCC, green sheets
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00—Reducing energy consumption in communication networks
    • Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks

Definitions

  • the invention relates to the technical field of filters, in particular to an ultra-wide passband fifth-order bandpass filter based on an LTCC process.
  • LTCC low temperature co-sintering ceramics, which can realize the packaging of three major passive devices (resistors, capacitors, inductors) and various passive devices (such as filters, transformers, etc.) Such as power MOS, transistor, IC module, etc.) are integrated into a complete circuit system. It has been widely used in various types of mobile phones, Bluetooth, GPS modules, WLAN modules, WIFI modules, etc.; in addition, due to the high reliability of its products, it is widely used in automotive electronics, communications, aerospace and military, MEMS, sensor technology Applications in other fields are also on the rise.
  • LTCC plays an important role, because LTCC can adapt to high current and high temperature resistance. From mobile phones, wearable devices to automobiles and other fields, RF components need to be used. LTCC is a key component. In terms of mobile phone applications, 5G The number of mobile phones used has grown by 40% compared with 4G, which has pushed up the demand for LTCC to grow significantly.
  • the LTCC band-pass filter There are usually three ways to realize the LTCC band-pass filter: the first is the traditional parallel resonant band-pass filter, which is realized by the parallel resonance unit formed by the inductor and the capacitor in parallel; the second is the use of distributed capacitor plates, The effect of the band-pass filter is achieved through the coupling between the pole plates; the third is achieved through the series connection of a high-pass filter and a low-pass filter.
  • the band-pass filters realized by the three structures have their own advantages and difficulties in fabrication and design.
  • the near-band suppression of the traditional parallel resonant structure band-pass filter is deeper than the other two, but with the increase of parallel resonant units, its pass-band insertion loss continues to increase, and the loss of the signal is difficult to control; using distributed
  • the structure of the band-pass filter has simple design, convenient debugging and balanced electrical properties, but because the structure is mainly realized by the coupling between the plates and the plates, the requirements for the production process are higher, and the LTCC diaphragm lamination and cutting and sintering process are It is easy to cause problems in the medium and the batch consistency is poor; the band-pass filter using the series structure of the high-pass filter and the low-pass filter has a wider passband, better insertion loss, and high signal fidelity, but the out-of-band suppression is poor, and the structure Complex and difficult to debug.
  • the purpose of the present invention is to provide an ultra-wide passband fifth-order bandpass filter based on the LTCC process, which is small in size and solves the problem of traditional filters with narrow passbands and large insertion loss.
  • an ultra-wide passband fifth-order bandpass filter based on LTCC technology comprising a ceramic substrate, a bottom input electrode, a bottom output electrode and a bottom ground electrode; the ceramic substrate
  • the interior includes five parallel resonances, one ground plate SD, two series-connected capacitors, two series-connected inductors, one cross-coupling capacitor C15 and one parallel-connected inductor L24; the two series-connected capacitors include the first series capacitor C12, The second series capacitor C45; the two series connection inductors include a first series inductor L23 and a second series inductor L34; the five parallel resonant units are distributed in mirror symmetry, including the first inductor L1 and the first parallel resonant capacitor.
  • the capacitor C45 is connected; the lower end of the first parallel resonant capacitor CC1 is connected to the bottom input electrode through the hole pillar Hin; the lower end of the fifth parallel resonant capacitor CC5 is connected to the bottom output electrode through the hole pillar Hout; the ground plate SD is located in
  • the interior of the ceramic base is divided into ten layers, wherein the ground electrode plate SD is located on the tenth layer of the ceramic base, and the first inductor L1 includes a hole column H11, a double-layer electrode plate J1 and a hole column H12;
  • the layer electrode plate J1 is located on the first layer and the second layer of the ceramic substrate;
  • the hole post H11 is located between the first layer and the tenth layer of the ceramic substrate, the upper end is connected to the double-layer electrode plate J1, and the lower end is connected to the ground electrode plate SD;
  • the hole column H12 is located between the first layer and the eighth layer of the ceramic base, the upper end is connected to the double-layer pole plate J1, and the lower end is connected to the first parallel resonance capacitor CC1;
  • the first parallel resonance capacitor CC1 is located on the sixth layer of the ceramic base.
  • the left end is connected to the hole column H12 of the first inductor L1
  • the first series capacitor C12 is located on the sixth and eighth layers of the ceramic substrate, and the left ends of the two layers are connected to the right end of the first parallel resonant capacitor CC1.
  • the second inductor L2 includes a hole column H21, a double-layer pole plate J2, and a hole column H22;
  • the double-layer pole plate J2 is located on the first layer and the second layer of the ceramic substrate;
  • the hole column H21 is located at Between the first layer and the tenth layer of the ceramic substrate, the upper end is connected to the double-layer electrode plate J2, and the lower end is connected to the ground electrode plate SD;
  • the hole post H22 is located between the first layer and the ninth layer of the ceramic substrate, and the upper end is connected to the double-layer electrode plate SD.
  • Plate J2 the second parallel resonant capacitor CC2 is located on the seventh layer and the ninth layer of the ceramic substrate, and is connected to the lower end of the hole column H22 of the second inductor L2.
  • the third inductor L3 includes a hole column H31, a double-layer pole plate J3, and a hole column H32;
  • the double-layer pole plate J3 is located on the first layer and the second layer of the ceramic substrate;
  • the hole column H31 is located at Between the first layer and the tenth layer of the ceramic substrate, the upper end is connected to the double-layer electrode plate J2, and the lower end is connected to the ground electrode plate SD;
  • the hole post H32 is located between the first layer and the ninth layer of the ceramic substrate, and the upper end is connected to the double-layer electrode plate SD.
  • the third parallel resonant capacitor CC3 is located on the seventh and ninth layers of the ceramic substrate, and is connected to the lower end of the hole post H32 of the third inductor L3; the first series inductor L23 is located on the third layer of the ceramic substrate, The left end is connected to the second inductance hole post H21, and the right end is connected to the third inductance hole column H31.
  • the fourth inductor L4 includes a hole column H41, a double-layer pole plate J4, and a hole column H42;
  • the double-layer pole plate J4 is located on the first layer and the second layer of the ceramic substrate;
  • the hole column H41 is located at Between the first layer and the tenth layer of the ceramic substrate, the upper end is connected to the double-layer electrode plate J4, and the lower end is connected to the ground electrode plate SD;
  • the hole post H42 is located between the first layer and the ninth layer of the ceramic substrate, and the upper end is connected to the double-layer electrode plate SD.
  • the fourth parallel resonant capacitor CC4 is located on the seventh and ninth layers of the ceramic substrate, and is connected to the lower end of the hole post H42 of the fourth inductor L4; the second series inductor L34 is located on the third layer of the ceramic substrate, The left end is connected to the third inductance hole post H31, and the right end is connected to the fourth inductance hole column H41.
  • the fifth inductor L5 includes a hole column H51, a double-layer pole plate J5, and a hole column H52;
  • the double-layer pole plate J5 is located on the first layer and the second layer of the ceramic substrate;
  • the hole column H51 is located at Between the first layer and the tenth layer of the ceramic substrate, the upper end is connected to the double-layer electrode plate J5, and the lower end is connected to the ground electrode plate SD;
  • the hole post H52 is located between the first layer and the eighth layer of the ceramic substrate, and the upper end is connected to the double-layer electrode plate SD.
  • the fifth parallel resonant capacitor CC5 is located on the sixth and eighth layers of the ceramic substrate, the left end is connected to the lower end of the hole post H52 of the fifth inductor L5, and the right end is connected to the second series capacitor C45.
  • the cross-coupling capacitor C15 is located on the fifth layer of the ceramic substrate, and adopts an in-line structure to form coupling with the sixth-layer polar plate of the first parallel resonant capacitor CC1 and the sixth-layer polar plate of the fifth parallel resonant capacitor CC5;
  • the parallel inductance L24 is located on the third layer of the ceramic substrate, adopts a C-type structure, and is connected to the second inductance hole post H21 and the fourth inductance hole column H41 respectively.
  • the holes of the first inductor L1, the second inductor L2, the third inductor L3, the fourth inductor L4, and the fifth inductor L5 all adopt the column-type metal hole-pillar structure;
  • the two parallel resonant capacitors CC2, the third parallel resonant capacitor CC3, the fourth parallel resonant capacitor CC4, the fifth parallel resonant capacitor CC5 and the cross-coupling capacitor C15 all adopt the structure of a pair of flat capacitor plates;
  • the first series capacitor C12, the first The series capacitor C45 adopts a vertical in-line capacitor plate structure.
  • the first parallel resonance and the fifth parallel resonance, the second parallel resonance and the fourth parallel resonance, the first series capacitor C12 and the second series capacitor C45, the first series inductance L23 and the second series inductance L34 The structure is mirror-symmetrical, and the third parallel resonance, the cross-coupling capacitor C15, and the parallel inductance L24 are centrally symmetrical.
  • the dielectric constant of the ceramic substrate is 9.8, the loss tangent is 0.003, and the bottom ground electrode, bottom input electrode, and bottom output electrode are all printed with silver material, and the passband range of the filter is It is 3.64-7.04GHz, the maximum insertion loss in the passband is 1.75dB, and the suppression in the low-end stopband 0-3GHz is more than 30dB; the suppression in the high-end stopband 7.8GHz-12.5GHz is more than 30dB; the triple frequency 12.5-17GHz suppression is more than 15dB.
  • the present invention proposes an ultra-wide pass-band fifth-order band-pass filter based on the LTCC process, which aims to solve the problem of the pass-band passing of the parallel resonant structure of the existing LTCC band-pass filter.
  • Narrow, high-pass filter and low-pass filter series structure suppresses the problem of not deep.
  • the filter adopts a fifth-order parallel resonance structure, five parallel resonance units deepen the out-of-band suppression, and innovatively introduces a cross-coupling capacitor, a parallel inductor and two series-connected inductors, which greatly broadens the band-pass filter. Passband, deepening the out-of-band rejection of three times, changing the traditional fifth-order bandpass filter narrow passband and large insertion loss problem.
  • FIG. 1 is a schematic diagram of an equivalent circuit of the LTCC bandpass filter of the present invention.
  • FIG. 2 is a schematic diagram of the external structure of the LTCC bandpass filter of the present invention.
  • FIG. 3 is a schematic diagram of the internal overall structure of the LTCC bandpass filter of the present invention.
  • FIG. 4 is an exploded schematic diagram of the internal overall structure of the LTCC bandpass filter of the present invention.
  • FIG. 5 is a schematic diagram of the internal frontal structure of the LTCC bandpass filter of the present invention.
  • FIG. 6 is a schematic diagram of the internal side view structure of the LTCC bandpass filter of the present invention.
  • FIG. 7 is a plan view of the first layer of the LTCC bandpass filter of the present invention.
  • FIG. 8 is a plan view of the second layer of the LTCC bandpass filter of the present invention.
  • FIG. 9 is a plan view of the third layer of the LTCC bandpass filter of the present invention.
  • FIG. 10 is a plan view of the fourth layer of the LTCC bandpass filter of the present invention.
  • FIG. 11 is a plan view of the fifth layer of the LTCC bandpass filter of the present invention.
  • FIG. 12 is a plan view of the sixth layer of the LTCC bandpass filter of the present invention.
  • FIG. 13 is a plan view of the seventh layer of the LTCC bandpass filter of the present invention.
  • FIG. 14 is a plan view of the eighth layer of the LTCC bandpass filter of the present invention.
  • FIG. 15 is a plan view of the ninth layer of the LTCC bandpass filter of the present invention.
  • FIG. 16 is a plan view of the tenth layer of the LTCC bandpass filter of the present invention.
  • FIG. 17 is a diagram showing the S11 simulation result of the LTCC bandpass filter of the present invention.
  • FIG. 18 is a diagram showing the S21 simulation result of the LTCC bandpass filter of the present invention.
  • FIG. 19 is a diagram showing the S22 simulation result of the LTCC bandpass filter of the present invention.
  • FIG. 1 is a schematic diagram of an equivalent circuit of the LTCC bandpass filter of the present invention.
  • the main body of the present invention adopts a traditional fifth-order band-pass filter, including a first parallel resonance composed of a first inductor L1 and a first parallel resonance capacitor CC1, and a second parallel resonance capacitor CC2 composed of a second inductor L2 and a second parallel resonance capacitor CC2.
  • the second parallel resonance formed is the third parallel resonance formed by the third inductor L3 and the third parallel resonance capacitor CC3, the fourth parallel resonance formed by the fourth inductor L4 and the fourth parallel resonance capacitor CC4, and the fifth inductor L5.
  • the present invention is based on the structure of the traditional fifth-order band-pass filter by introducing two series inductances L23 connecting the second parallel resonance and the third parallel resonance, and a series inductance L34 connecting the third parallel resonance and the fourth parallel resonance and connecting the second parallel resonance L34.
  • the parallel inductance L24 and the cross-coupling capacitor C15 of the parallel resonance and the fourth parallel resonance greatly widen the passband, and increase the suppression of the near end of the passband and the triple frequency.
  • FIG. 2 is a schematic diagram of the external structure of the LTCC bandpass filter of the present invention, including a ceramic substrate, a bottom input electrode, a bottom output electrode, and a bottom ground electrode.
  • the overall external size of the present invention is 2.0mm ⁇ 1.25mm ⁇ 0.8mm, and the ceramic material is used with a dielectric constant of 9.8 and a loss tangent of 0.003.
  • the bottom input electrode and the bottom output electrode are printed on the left and right sides of the bottom of the ceramic base in a mirror image distribution; the bottom ground electrode is printed on the center of the bottom of the ceramic base.
  • the internal structure of the present invention is divided into ten layers, wherein the ground electrode plate SD is located on the tenth layer of the ceramic substrate, and is connected to the bottom ground electrode through the hole post Hsd.
  • the five internal parallel resonance units are distributed in mirror symmetry, including a first parallel resonance composed of a first inductance L1 and a first parallel resonance capacitor CC1, and a second parallel resonance composed of a second inductance L2 and a second parallel resonance capacitor CC2,
  • the third parallel resonance composed of the third inductance L3 and the third parallel resonance capacitor CC3, the fourth parallel resonance composed of the fourth inductance L4 and the fourth parallel resonance capacitor CC4, the fifth inductance L5 and the fifth parallel resonance capacitor CC5
  • the fifth parallel resonance is formed; the first parallel resonance and the second parallel resonance are connected through the first series capacitor C12, the second parallel resonance and the third parallel resonance are connected through the first series inductance L23, and the third parallel resonance is connected with the fourth parallel resonance.
  • the parallel resonance is connected through the second series inductor L34, and the fourth parallel resonance and the fifth parallel resonance are connected through the second series capacitor C45.
  • the first parallel resonance and the fifth parallel resonance, the second parallel resonance and the fourth parallel resonance, the first series capacitor C12 and the second series capacitor C45, and the first series inductance L23 and the second series inductance L34 have the same mirror-symmetric structure.
  • the first inductor L1 adopts a hole-pillar-plate-hole-pillar structure, and includes a hole-pillar H11 connected to the ground plate, a double-layered pole plate J1, and a hole-pillar H12 connected to the first parallel resonant capacitor CC1.
  • the double-layer plate J1 is located on the first layer and the second layer of the ceramic base, the hole column H11 connected with the ground plate is located between the first layer and the tenth layer of the ceramic base, and the hole column connected with the first parallel resonant capacitor CC1 H12 is located between the first layer and the eighth layer of the ceramic matrix.
  • the upper end of the hole column H11 connected with the grounding plate is connected to the double-layered plate J1, and the lower end is connected to the grounding plate SD; the upper end of the hole column H12 connected with the first parallel resonance capacitor CC1 is connected to the double-layered plate J1, and the lower end is connected with the first parallel resonance.
  • the capacitor CC1 is connected; the first parallel resonant capacitor CC1 is located on the sixth and eighth layers of the ceramic substrate, the left end is connected to the hole column H12 of the first inductor L1, the right end is connected to the first series capacitor C12, and the lower end is connected to the bottom input electrode through the hole column Hin. connect.
  • the first series capacitor C12 is located on the sixth layer and the eighth layer of the ceramic substrate, and the left ends of the two layers are both connected to the first parallel resonance capacitor CC1.
  • the second inductor L2 adopts a hole-pillar-plate-hole-pillar structure, including a hole-pillar H21 connected to the ground plate, a double-layered pole plate J2, and a hole-pillar H22 connected to the second parallel resonant capacitor CC2.
  • the double-layer plate J2 is located on the first layer and the second layer of the ceramic substrate, the hole column H21 connected to the ground plate is located between the first layer and the tenth layer of the ceramic substrate, and the hole column connected with the second parallel resonant capacitor CC2 H22 is located between the first layer and the ninth layer of the ceramic matrix.
  • the upper end of the hole post H21 connected with the grounding pole plate is connected with the double-layer pole plate J2, and the lower end is connected with the grounding pole plate SD;
  • the upper end of the hole column H22 connected with the second parallel resonance capacitor CC2 is connected with the double-layer pole plate J2, and the lower end is connected in parallel with the second The resonant capacitor CC2 is connected;
  • the second parallel resonant capacitor CC2 is located on the seventh layer and the ninth layer of the ceramic substrate, and is connected to the hole post H22 of the second inductor L2.
  • the third inductor L3 adopts a hole-pillar-plate-hole-pillar structure, including a hole-pillar H31 connected to the ground plate, a double-layered pole plate J3, and a hole-pillar H32 connected to the third parallel resonant capacitor CC3.
  • the double-layer plate J3 is located on the first layer and the second layer of the ceramic base, the hole column H31 connected to the ground plate is located between the first layer and the tenth layer of the ceramic base, and the hole column connected with the third parallel resonant capacitor CC3 H32 is located between the first layer and the ninth layer of the ceramic matrix.
  • the upper end of the hole column H31 connected with the grounding plate is connected to the double-layer plate J2, and the lower end is connected to the grounding plate SD; the upper end of the hole column H32 connected with the third parallel resonance capacitor CC3 is connected to the double-layer plate J3, and the lower end is connected in parallel with the third The resonant capacitor CC3 is connected; the third parallel resonant capacitor CC3 is located on the seventh layer and the ninth layer of the ceramic substrate, and is connected to the hole post H32 of the third inductor L3.
  • the first series inductance L23 is located on the third layer of the ceramic substrate, the left end is connected to the second inductance hole post H21, and the right end is connected to the third inductance hole column H31.
  • the fourth inductor L4 adopts a hole-pillar-plate-hole-pillar structure, including a hole-pillar H41 connected to the ground plate, a double-layered pole plate J4, and a hole-pillar H42 connected to the fourth parallel resonant capacitor CC4.
  • the double-layer pole plate J4 is located on the first and second layers of the ceramic base, the hole column H41 connected to the ground plate is located between the first and tenth layers of the ceramic base, and the hole column connected with the fourth parallel resonant capacitor CC4 H42 is located between the first layer and the ninth layer of the ceramic matrix.
  • the upper end of the hole column H41 connected with the grounding plate is connected with the double-layered pole plate J4, and the lower end is connected with the grounding plate SD;
  • the upper end of the hole column H42 connected with the fourth parallel resonance capacitor CC4 is connected with the double-layered pole plate J4, and the lower end is connected in parallel with the fourth
  • the resonant capacitor CC4 is connected;
  • the fourth parallel resonant capacitor CC4 is located on the seventh and ninth layers of the ceramic substrate, and is connected to the hole post H42 of the fourth inductor L4.
  • the second series inductance L34 is located on the third layer of the ceramic substrate, the left end is connected to the third inductance hole post H31, and the right end is connected to the fourth inductance hole column H41.
  • the fifth inductor L5 adopts a hole-pillar-plate-hole-pillar structure, including a hole-pillar H51 connected to the ground plate, a double-layered pole plate J5, and a hole-pillar H52 connected to the fifth parallel resonant capacitor CC5.
  • the double-layer pole plate J5 is located on the first and second layers of the ceramic base, the hole column H51 connected to the ground plate is located between the first layer and the tenth layer of the ceramic base, and the hole column connected with the fifth parallel resonant capacitor CC5 H52 is located between the first layer and the eighth layer of the ceramic matrix.
  • the upper end of the hole column H51 connected with the grounding plate is connected with the double-layered pole plate J5, and the lower end is connected with the grounding plate SD; the upper end of the hole column H52 connected with the fifth parallel resonant capacitor CC5 is connected with the double-layered pole plate J5, and the lower end is connected with the first.
  • Five parallel resonant capacitors CC5 are connected; the fifth parallel resonant capacitor CC5 is located on the sixth and eighth layers of the ceramic substrate, the left end is connected to the fifth inductor L5 hole column H52, the left end is connected to the second series capacitor C45, and the lower end is connected to the hole column Hout through the hole column H52. Bottom output electrode connection.
  • the cross-coupling capacitor C15 is located on the fifth layer of the ceramic base, and is coupled with the sixth-layer plate of the first parallel resonant capacitor CC1 and the sixth-layer plate of the fifth parallel resonant capacitor CC5 using an in-line structure; the parallel inductor L24 is located on the ceramic base.
  • the third layer adopts a C-type structure and is connected to the second inductance hole H21 and the fourth inductance hole H41 respectively.
  • each layer of the above-mentioned bandpass filter is shown in Figures 7-16.
  • the capacitor of the band-pass filter mentioned above is used in combination with the vertical in-line type (VIC type) and the plane type (MIM type), aiming to achieve the required capacitance value in the smallest space and reduce the occupation of the capacitor plate.
  • volume of. In the internal structure layout, the five parallel resonant units adopt a mirror-symmetrical design method, which reasonably optimizes the internal space structure, reduces the difficulty of design and debugging and avoids errors in the production process.
  • the volume of the filter is only 2.0mm ⁇ 1.25 mm ⁇ 0.8mm.
  • 17-19 are simulation diagrams of the S-parameter results of the bandpass filter of the present invention.
  • the passband range of the band-pass filter is 3.64-7.04GHz
  • the maximum insertion loss of the passband is 1.75dB
  • the suppression is greater than 30dB in the low-end stopband 0-3GHz; in the high-end stopband 7.8GHz-12.5GHz
  • the suppression is greater than 30dB; the triple frequency 12.5-17GHz suppression is greater than 15dB.
  • the beneficial effects of the present invention are as follows: (1) The hole-pillar-plate-hole-pillar structure inductor is adopted, which avoids the problems of large space occupation, difficult debugging and high manufacturing process requirements of traditional LTCC multi-layer spiral fold-line inductors. . At the same time, using the structure inductance can increase the coupling capacitance between the inductance and the inductance, reduce the volume of the series capacitance between the two parallel resonance units, and make the device miniaturized.

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Abstract

一种基于LTCC工艺的超宽通带五阶带通滤波器，包括陶瓷基体(1)、底部输入电极(2)、底部输出电极(4)和底部接地电极(3)；陶瓷基体(1)内部包括五个并联谐振、一个接地极板(SD)、两个串联连接电容、两个串联连接电感、一个交叉耦合电容(C15)及一个并联电感(L24)；两个串联连接电容包括第一串联电容(C12)、第二串联电容(C45)；所述两个串联连接电感包括第一串联电感(L23)、第二串联电感(L34)；该滤波器采用五阶并联谐振结构，五个并联谐振单元加深了带外抑制，并且引入了一个交叉耦合电容(C15)、一个并联电感(L24)及两个串联连接电感，极大地拓宽了带通滤波器的通带，加深了三倍频带外抑制，改变了传统五阶带通滤波器通带窄插损大的问题。

Description

一种基于LTCC工艺的超宽通带五阶带通滤波器 技术领域
本发明涉及的是滤波器技术领域，具体涉及一种基于LTCC工艺的超宽通带五阶带通滤波器。
 背景技术
随着通信技术的飞速发展，全球通讯行业正逐步迈入5G时代。LTCC 即低温共烧结陶瓷，可以实现三大无源器件（电阻、电容、电感） 及其各种无源器件（如滤波器、变压器等）封装于多层布线基板中，并与 有源器件（如功率 MOS、晶体管、IC 模块等）共同集成为完整的电路系 统。现已广泛应用于各种制式的手机、蓝牙、GPS 模块、WLAN 模块、 WIFI 模块等；此外，由于其产品的高可靠性，在汽车电子、通讯、航空航 天与军事、微机电系统、传感器技术等领域的应用也日益上升。
5G时代来临，LTCC扮演重要角色，因为LTCC能适应大电流和耐高温，从手机、穿戴装置到车用等领域，都需要运用到RF零组件，LTCC作为关键组件，以手机应用而言，5G手机的使用数量就比4G大幅成长40％，推升LTCC需求量大幅成长。
LTCC带通滤波器的实现方式通常有一下三种：第一种是传统并联谐振式带通滤波器，通过电感与电容并联构成的并联谐振单元实现；第二种是采用分布式电容极板，通过极板与极板间的耦合实现带通滤波器的效果；第三种是通过高通滤波器与低通滤波器串联实现。三种结构实现的带通滤波器在制作和设计上分别存在着各自的优点与困难。传统并联谐振式结构带通滤波器的近带抑制相较另外两种更深，但其随着并联谐振单元的增加，其通带插损不断变大，对信号的损失难以把控；采用分布式结构的带通滤波器，其设计简单，调试方便，电性能均衡，但由于结构上主要由极板与极板间耦合实现，对制作工艺要求更高，在LTCC膜片叠层及切割烧结过程中容易产生问题，批量一致性差；采用高通滤波器与低通滤波器串联结构的带通滤波器其通带较宽，插损较好，信号保真率高，但带外抑制较差，结构复杂，调试困难。
 技术问题
为了解决上述技术问题，本发明的目的是提供一种基于LTCC工艺的超宽通带五阶带通滤波器，该滤波器体积小，且解决了传统滤波器通带窄插损大的问题。
 技术解决方案
为了实现上述发明目的，本发明采用以下技术方案：一种基于LTCC工艺的超宽通带五阶带通滤波器，包括陶瓷基体、底部输入电极、底部输出电极和底部接地电极；所述陶瓷基体内部包括五个并联谐振、一个接地极板SD、两个串联连接电容、两个串联连接电感、一个交叉耦合电容C15及一个并联电感L24；所述两个串联连接电容包括第一串联电容C12、第二串联电容C45；所述两个串联连接电感包括第一串联电感L23、第二串联电感L34；所述五个并联谐振单元呈镜像对称分布，包括由第一电感L1与第一并联谐振电容CC1构成的第一并联谐振，由第二电感L2与第二并联谐振电容CC2构成的第二并联谐振，由第三电感L3与第三并联谐振电容CC3构成的第三并联谐振，由第四电感L4与第四并联谐振电容CC4构成的第四并联谐振，由第五电感L5与第五并联谐振电容CC5构成的第五并联谐振；所述第一并联谐振与第二并联谐振通过第一串联电容C12连接，第二并联谐振与第三并联谐振通过第一串联电感L23连接，第三并联谐振与第四并联谐振通过第二串联电感L34连接，第四并联谐振与第五并联谐振通过第二串联电容C45连接；所述第一并联谐振电容CC1下端通过孔柱Hin与底部输入电极连接；所述第五并联谐振电容CC5下端通过孔柱Hout与底部输出电极连接；所述接地极板SD位于陶瓷基体内部最下层，且通过孔柱Hsd与底部接地电极连接。
作为优选方案：所述陶瓷基体内部共分十层，其中接地极板SD位于陶瓷基体第十层，所述第一电感L1包括孔柱H11、双层极板J1和孔柱H12；所述双层极板J1位于陶瓷基体的第一层与第二层；所述孔柱H11位于陶瓷基体的第一层与第十层间，上端连接双层极板J1，下端与接地极板SD连接；所述孔柱H12位于陶瓷基体的第一层与第八层间，上端连接双层极板J1，下端与第一并联谐振电容CC1连接；所述第一并联谐振电容CC1位于陶瓷基体第六层与第八层，左端与第一电感L1孔柱H12连接，所述第一串联电容C12位于陶瓷基体第六层与第八层，两层左端均与第一并联谐振电容CC1的右端连接。
作为优选方案：所述第二电感L2包括孔柱H21，双层极板J2，孔柱H22；所述双层极板J2位于陶瓷基体的第一层与第二层；所述孔柱H21位于陶瓷基体的第一层与第十层间，上端连接双层极板J2，下端与接地极板SD连接；所述孔柱H22位于陶瓷基体的第一层与第九层间，上端连接双层极板J2，所述第二并联谐振电容CC2位于陶瓷基体第七层与第九层，且与第二电感L2孔柱H22的下端连接。
作为优选方案：所述第三电感L3包括孔柱H31，双层极板J3，孔柱H32；所述双层极板J3位于陶瓷基体的第一层与第二层；所述孔柱H31位于陶瓷基体的第一层与第十层间，上端连接双层极板J2，下端与接地极板SD连接；所述孔柱H32位于陶瓷基体的第一层与第九层间，上端连接双层极板J3，所述第三并联谐振电容CC3位于陶瓷基体第七层与第九层，且与第三电感L3的孔柱H32下端连接；所述第一串联电感L23位于陶瓷基体第三层，左端与第二电感孔柱H21相连，右端与第三电感孔柱H31相连。
作为优选方案：所述第四电感L4包括孔柱H41，双层极板J4，孔柱H42；所述双层极板J4位于陶瓷基体的第一层与第二层；所述孔柱H41位于陶瓷基体的第一层与第十层间，上端连接双层极板J4，下端与接地极板SD连接；所述孔柱H42位于陶瓷基体的第一层与第九层间，上端连接双层极板J4，所述第四并联谐振电容CC4位于陶瓷基体第七层与第九层，且与第四电感L4的孔柱H42的下端连接；述第二串联电感L34位于陶瓷基体第三层，左端与第三电感孔柱H31相连，右端与第四电感孔柱H41相连。
作为优选方案：所述第五电感L5包括孔柱H51，双层极板J5，孔柱H52；所述双层极板J5位于陶瓷基体的第一层与第二层；所述孔柱H51位于陶瓷基体的第一层与第十层间，上端连接双层极板J5，下端与接地极板SD连接；所述孔柱H52位于陶瓷基体的第一层与第八层间，上端连接双层极板J5，所述第五并联谐振电容CC5位于陶瓷基体第六层与第八层，左端与第五电感L5的孔柱H52下端连接，右端与第二串联电容C45连接。
作为优选方案：所述交叉耦合电容C15位于陶瓷基体第五层，采用一字型结构分别与第一并联谐振电容CC1第六层极板和第五并联谐振电容CC5第六层极板形成耦合；所述并联电感L24位于陶瓷基体第三层，采用C型结构，分别与第二电感孔柱H21和第四电感孔柱H41连接。
作为优选方案：所述第一电感L1、第二电感L2、第三电感L3、第四电感L4、第五电感L5的孔柱均采用柱型金属孔柱结构；第一并联谐振电容CC1、第二并联谐振电容CC2、第三并联谐振电容CC3、第四并联谐振电容CC4、第五并联谐振电容CC5及交叉耦合电容C15均采用对平板式电容极板的结构；第一串联电容C12、第一串联电容C45采用垂直直插式电容极板结构。
作为优选方案：所述第一并联谐振与第五并联谐振、第二并联谐振与第四并联谐振、第一串联电容C12与第二串联电容C45、第一串联电感L23与第二串联电感L34的结构呈镜像对称，第三并联谐振、交叉耦合电容C15、并联电感L24结构呈中心对称。
作为优选方案：所述陶瓷基体的材料的介电常数为9.8，损耗角正切0.003的陶瓷材料，底部接地电极、底部输入电极、底部输出电极均采用银材料印刷，所述滤波器的通带范围为3.64-7.04GHz，通带最大插入损耗为1.75dB，在低端阻带0-3GHz抑制大于30dB；在高端阻带7.8GHz-12.5GHz抑制大于30dB；三倍频12.5-17GHz抑制大于15dB。
 有益效果
与现有技术相比，本发明的有益效果为：本发明提出一种基于LTCC工艺的超宽通带五阶带通滤波器，旨在解决现有LTCC带通滤波器并联谐振结构通带过窄，高通滤波器与低通滤波器串联结构抑制不深的问题。该滤波器采用五阶并联谐振结构，五个并联谐振单元加深了带外抑制，并且创新的引入了一个交叉耦合电容、一个并联电感及两个串联连接电感，极大地拓宽了带通滤波器的通带，加深了三倍频带外抑制，改变了传统五阶带通滤波器通带窄插损大的问题。
 附图说明
构成本申请的一部分的说明书附图用来提供对本申请的进一步理解，本申请的示意性实施例及其说明用于解释本申请，并不构成对本申请的限定。
图1为本发明的LTCC带通滤波器的等效电路原理图。
图2为本发明的LTCC带通滤波器的外部结构示意图。
图3为本发明的LTCC带通滤波器的内部整体结构示意图。
图4为本发明的LTCC带通滤波器的内部整体结构分解示意图。
图5为本发明的LTCC带通滤波器的内部正视结构示意图。
图6为本发明的LTCC带通滤波器的内部侧视结构示意图。
图7为本发明的LTCC带通滤波器的第1层平面结构图。
图8为本发明的LTCC带通滤波器的第2层平面结构图。
图9为本发明的LTCC带通滤波器的第3层平面结构图。
图10为本发明的LTCC带通滤波器的第4层平面结构图。
图11为本发明的LTCC带通滤波器的第5层平面结构图。
图12为本发明的LTCC带通滤波器的第6层平面结构图。
图13为本发明的LTCC带通滤波器的第7层平面结构图。
图14为本发明的LTCC带通滤波器的第8层平面结构图。
图15为本发明的LTCC带通滤波器的第9层平面结构图。
图16为本发明的LTCC带通滤波器的第10层平面结构图。
图17为本发明的LTCC带通滤波器的S11仿真结果图。
图18为本发明的LTCC带通滤波器的S21仿真结果图。
图19为本发明的LTCC带通滤波器的S22仿真结果图。
 本发明的最佳实施方式
下面结合附图与实施例对本发明作进一步说明。
为了更清楚详细的阐述本发明的技术实施方案，以下结合附图对本发明进行进一步详细说明。
图1为本发明的LTCC带通滤波器的等效电路原理图。如图1所示，本发明主体采用传统五阶带通滤波器，包括由第一电感L1与第一并联谐振电容CC1构成的第一并联谐振，由第二电感L2与第二并联谐振电容CC2构成的第二并联谐振，由第三电感L3与第三并联谐振电容CC3构成的第三并联谐振，由第四电感L4与第四并联谐振电容CC4构成的第四并联谐振，由第五电感L5与第五并联谐振电容CC5构成的第五并联谐振，第一并联谐振与第二并联谐振通过第一串联电容C12连接，第四并联谐振与第五并联谐振通过第二串联电容C45连接。本发明在传统五阶带通滤波器的架构上通过引入两个连接第二并联谐振与第三并联谐振的串联电感L23与连接第三并联谐振与第四并联谐振的串联电感L34和连接第二并联谐振与第四并联谐振的并联电感L24、交叉耦合电容C15极大地拓宽通带，增加了通带近端与三倍频的抑制。
图2为本发明的LTCC带通滤波器的外部结构示意图，包括陶瓷基体、底部输入电极、底部输出电极、底部接地电极。本发明外部整体尺寸为2.0mm×1.25mm×0.8mm，采用介电常数9.8，损耗角正切0.003的陶瓷材料。外部输入电极、外部输出电极。底部输入电极、底部输出电极呈镜像分布印刷在陶瓷基体底部左右两侧；所述底部接地电极印刷在陶瓷基体底部中心。
如图3至图6所示，本发明内部结构共分十层，其中接地极板SD位于陶瓷基体第十层，通过孔柱Hsd与底部接地电极连接。内部五个并联谐振单元呈镜像对称分布，包括由第一电感L1与第一并联谐振电容CC1构成的第一并联谐振，由第二电感L2与第二并联谐振电容CC2构成的第二并联谐振，由第三电感L3与第三并联谐振电容CC3构成的第三并联谐振，由第四电感L4与第四并联谐振电容CC4构成的第四并联谐振，由第五电感L5与第五并联谐振电容CC5构成的第五并联谐振；所述第一并联谐振与第二并联谐振通过第一串联电容C12连接，第二并联谐振与第三并联谐振通过第一串联电感L23连接，第三并联谐振与第四并联谐振通过第二串联电感L34连接，第四并联谐振与第五并联谐振通过第二串联电容C45连接。第一并联谐振与第五并联谐振、第二并联谐振与第四并联谐振、第一串联电容C12与第二串联电容C45、第一串联电感L23与第二串联电感L34呈镜像对称结构相同。
第一电感L1采用孔柱-极板-孔柱结构，包括与接地极板连接的孔柱H11，双层极板J1，与第一并联谐振电容CC1连接的孔柱H12。双层极板J1位于陶瓷基体的第一层与第二层，与接地极板连接的孔柱H11位于陶瓷基体的第一层与第十层间，与第一并联谐振电容CC1连接的孔柱H12位于陶瓷基体的第一层与第八层间。与接地极板连接的孔柱H11上端连接双层极板J1，下端与接地极板SD连接；第一并联谐振电容CC1连接的孔柱H12上端连接双层极板J1，下端与第一并联谐振电容CC1连接；第一并联谐振电容CC1位于陶瓷基体第六层与第八层，左端与第一电感L1孔柱H12连接，右端与第一串联电容C12连接，下端通过孔柱Hin与底部输入电极连接。
第一串联电容C12位于陶瓷基体第六层与第八层，两层左端均与第一并联谐振电容CC1连接。
第二电感L2采用孔柱-极板-孔柱结构，包括与接地极板连接的孔柱H21，双层极板J2，与第二并联谐振电容CC2连接的孔柱H22。双层极板J2位于陶瓷基体的第一层与第二层，与接地极板连接的孔柱H21位于陶瓷基体的第一层与第十层间，与第二并联谐振电容CC2连接的孔柱H22位于陶瓷基体的第一层与第九层间。与接地极板连接的孔柱H21上端连接双层极板J2，下端与接地极板SD连接；与第二并联谐振电容CC2连接的孔柱H22上端连接双层极板J2，下端与第二并联谐振电容CC2连接；第二并联谐振电容CC2位于陶瓷基体第七层与第九层，与第二电感L2孔柱H22连接。
第三电感L3采用孔柱-极板-孔柱结构，包括与接地极板连接的孔柱H31，双层极板J3，与第三并联谐振电容CC3连接的孔柱H32。双层极板J3位于陶瓷基体的第一层与第二层，与接地极板连接的孔柱H31位于陶瓷基体的第一层与第十层间，与第三并联谐振电容CC3连接的孔柱H32位于陶瓷基体的第一层与第九层间。与接地极板连接的孔柱H31上端连接双层极板J2，下端与接地极板SD连接；与第三并联谐振电容CC3连接的孔柱H32上端连接双层极板J3，下端与第三并联谐振电容CC3连接；第三并联谐振电容CC3位于陶瓷基体第七层与第九层，与第三电感L3孔柱H32连接。
第一串联电感L23位于陶瓷基体第三层，左端与第二电感孔柱H21相连，右端与第三电感孔柱H31相连。
第四电感L4采用孔柱-极板-孔柱结构，包括与接地极板连接的孔柱H41，双层极板J4，与第四并联谐振电容CC4连接的孔柱H42。双层极板J4位于陶瓷基体的第一层与第二层，与接地极板连接的孔柱H41位于陶瓷基体的第一层与第十层间，与第四并联谐振电容CC4连接的孔柱H42位于陶瓷基体的第一层与第九层间。与接地极板连接的孔柱H41上端连接双层极板J4，下端与接地极板SD连接；与第四并联谐振电容CC4连接的孔柱H42上端连接双层极板J4，下端与第四并联谐振电容CC4连接；第四并联谐振电容CC4位于陶瓷基体第七层与第九层，与第四电感L4孔柱H42连接。
第二串联电感L34位于陶瓷基体第三层，左端与第三电感孔柱H31相连，右端与第四电感孔柱H41相连。
第五电感L5采用孔柱-极板-孔柱结构，包括与接地极板连接的孔柱H51，双层极板J5，与第五并联谐振电容CC5连接的孔柱H52。双层极板J5位于陶瓷基体的第一层与第二层，与接地极板连接的孔柱H51位于陶瓷基体的第一层与第十层间，与第五并联谐振电容CC5连接的孔柱H52位于陶瓷基体的第一层与第八层间。与接地极板连接的孔柱H51上端连接双层极板J5，下端与接地极板SD连接；所述与第五并联谐振电容CC5连接的孔柱H52上端连接双层极板J5，下端与第五并联谐振电容CC5连接；第五并联谐振电容CC5位于陶瓷基体第六层与第八层，左端与第五电感L5孔柱H52连接，左端与第二串联电容C45连接，下端通过孔柱Hout与底部输出电极连接。
交叉耦合电容C15位于陶瓷基体第五层，采用一字型结构分别与第一并联谐振电容CC1第六层极板和第五并联谐振电容CC5第六层极板形成耦合；并联电感L24位于陶瓷基体第三层，采用C型结构，分别与第二电感孔柱H21和第四电感孔柱H41连接。
如上所述的带通滤波器各层具体结构如图7-图16所示。如上所述的带通滤波器的电容采用垂直直插式（VIC型）和对平面式（MIM型）结合使用，旨在最小的空间中达到满足要求的电容值，减少了电容极板所占用的体积。在内部结构布局上五个并联谐振单元采用了镜像对称的设计方式，合理优化了内部空间结构，降低了设计调试难度及规避了生产过程中出现的误差，该滤波器体积仅为2.0mm×1.25mm×0.8mm。
图17-图19为本发明带通滤波器S参数结果仿真图。如图所示，该带通滤波器的通带范围为3.64-7.04GHz，通带最大插入损耗为1.75dB，在低端阻带0-3GHz抑制大于30dB；在高端阻带7.8GHz-12.5GHz抑制大于30dB；三倍频12.5-17GHz抑制大于15dB。
综上所述，本发明的有益效果如下，（1）采用孔柱-极板-孔柱结构电感，避免了LTCC传统多层螺旋式折线电感空间占用大，调试困难，制作工艺要求高的问题。同时采用该结构电感能够增加电感与电感间的耦合电容，减小两个并联谐振单元间的串联电容体积，使得器件小型化。
（2）创新的在传统五阶带通滤波器的基础上引入了一个连接第二并联谐振单元与第四并联谐振单元的并联电感，两个连接第二并联谐振单元与第三并联谐振单元、第三并联谐振单元与第四并联谐振单元的串联连接电感，极大地拓宽通带，所设计的带通滤波器通带宽度为3.4GHz，插损控制在1.75dB以内，改善了传统五阶带通滤波器通带窄插损大的问题。
（3）通过引入一个连接第二并联谐振单元与第四并联谐振单元的并联电感与一个交叉耦合电容，增加了通带近端与三倍频的抑制，所设计的带通滤波器在低端阻带0-3GHz抑制大于30dB；在高端阻带7.8GHz-12.5GHz抑制大于30dB；三倍频12.5-17GHz抑制大于15dB。
以上所描述是实施例是本发明中的一个较好的实施例，并不以上述实施方式限制本发明。基于本发明的实施例，本领域普通技术人员在没有做出创造性劳动的前提下，基于本发明所作的任何修改、等同替换、改进所获得的其他实施例，皆应纳入权利要求书中记载的保护范围内。

Claims (10)

  1. 一种基于LTCC工艺的超宽通带五阶带通滤波器，包括陶瓷基体（1）、底部输入电极（2）、底部输出电极（4）和底部接地电极（3）；其特征在于：所述陶瓷基体（1）内部包括五个并联谐振、一个接地极板SD、两个串联连接电容、两个串联连接电感、一个交叉耦合电容C15及一个并联电感L24；所述两个串联连接电容包括第一串联电容C12、第二串联电容C45；所述两个串联连接电感包括第一串联电感L23、第二串联电感L34；所述五个并联谐振单元呈镜像对称分布，包括由第一电感L1与第一并联谐振电容CC1构成的第一并联谐振，由第二电感L2与第二并联谐振电容CC2构成的第二并联谐振，由第三电感L3与第三并联谐振电容CC3构成的第三并联谐振，由第四电感L4与第四并联谐振电容CC4构成的第四并联谐振，由第五电感L5与第五并联谐振电容CC5构成的第五并联谐振；所述第一并联谐振与第二并联谐振通过第一串联电容C12连接，第二并联谐振与第三并联谐振通过第一串联电感L23连接，第三并联谐振与第四并联谐振通过第二串联电感L34连接，第四并联谐振与第五并联谐振通过第二串联电容C45连接；所述第一并联谐振电容CC1下端通过孔柱Hin与底部输入电极（2）连接；所述第五并联谐振电容CC5下端通过孔柱Hout与底部输出电极（4）连接；所述接地极板SD位于陶瓷基体（1）内部最下层，且通过孔柱Hsd与底部接地电极（3）连接。
  2. 根据权利要求1所述的一种基于LTCC工艺的超宽通带五阶带通滤波器，其特征在于：所述陶瓷基体（1）内部共分十层，其中接地极板SD位于陶瓷基体（1）第十层，所述第一电感L1包括孔柱H11、双层极板J1和孔柱H12；所述双层极板J1位于陶瓷基体（1）的第一层与第二层；所述孔柱H11位于陶瓷基体（1）的第一层与第十层间，上端连接双层极板J1，下端与接地极板SD连接；所述孔柱H12位于陶瓷基体（1）的第一层与第八层间，上端连接双层极板J1，下端与第一并联谐振电容CC1连接；所述第一并联谐振电容CC1位于陶瓷基体（1）第六层与第八层，左端与第一电感L1孔柱H12连接，所述第一串联电容C12位于陶瓷基体（1）第六层与第八层，两层左端均与第一并联谐振电容CC1的右端连接。
  3. 根据权利要求2所述的一种基于LTCC工艺的超宽通带五阶带通滤波器，其特征在于：所述第二电感L2包括孔柱H21，双层极板J2，孔柱H22；所述双层极板J2位于陶瓷基体（1）的第一层与第二层；所述孔柱H21位于陶瓷基体（1）的第一层与第十层间，上端连接双层极板J2，下端与接地极板SD连接；所述孔柱H22位于陶瓷基体（1）的第一层与第九层间，上端连接双层极板J2，所述第二并联谐振电容CC2位于陶瓷基体第七层与第九层，且与第二电感L2孔柱H22的下端连接。
  4. 根据权利要求3所述的一种基于LTCC工艺的超宽通带五阶带通滤波器，其特征在于：所述第三电感L3包括孔柱H31，双层极板J3，孔柱H32；所述双层极板J3位于陶瓷基体（1）的第一层与第二层；所述孔柱H31位于陶瓷基体（1）的第一层与第十层间，上端连接双层极板J2，下端与接地极板SD连接；所述孔柱H32位于陶瓷基体（1）的第一层与第九层间，上端连接双层极板J3，所述第三并联谐振电容CC3位于陶瓷基体第七层与第九层，且与第三电感L3的孔柱H32下端连接；所述第一串联电感L23位于陶瓷基体第三层，左端与第二电感孔柱H21相连，右端与第三电感孔柱H31相连。
  5. 根据权利要求4所述的一种基于LTCC工艺的超宽通带五阶带通滤波器，其特征在于：所述第四电感L4包括孔柱H41，双层极板J4，孔柱H42；所述双层极板J4位于陶瓷基体（1）的第一层与第二层；所述孔柱H41位于陶瓷基体（1）的第一层与第十层间，上端连接双层极板J4，下端与接地极板SD连接；所述孔柱H42位于陶瓷基体（1）的第一层与第九层间，上端连接双层极板J4，所述第四并联谐振电容CC4位于陶瓷基体第七层与第九层，且与第四电感L4的孔柱H42的下端连接；述第二串联电感L34位于陶瓷基体第三层，左端与第三电感孔柱H31相连，右端与第四电感孔柱H41相连。
  6. 根据权利要求5所述的一种基于LTCC工艺的超宽通带五阶带通滤波器，其特征在于：所述第五电感L5包括孔柱H51，双层极板J5，孔柱H52；所述双层极板J5位于陶瓷基体（1）的第一层与第二层；所述孔柱H51位于陶瓷基体（1）的第一层与第十层间，上端连接双层极板J5，下端与接地极板SD连接；所述孔柱H52位于陶瓷基体（1）的第一层与第八层间，上端连接双层极板J5，所述第五并联谐振电容CC5位于陶瓷基体（1）第六层与第八层，左端与第五电感L5的孔柱H52下端连接，右端与第二串联电容C45连接。
  7. 根据权利要求6所述的一种基于LTCC工艺的超宽通带五阶带通滤波器，其特征在于：所述交叉耦合电容C15位于陶瓷基体（1）第五层，采用一字型结构分别与第一并联谐振电容CC1第六层极板和第五并联谐振电容CC5第六层极板形成耦合；所述并联电感L24位于陶瓷基体（1）第三层，采用C型结构，分别与第二电感孔柱H21和第四电感孔柱H41连接。
  8. 根据权利要求1所述的一种基于LTCC工艺的超宽通带五阶带通滤波器，其特征在于：所述第一电感L1、第二电感L2、第三电感L3、第四电感L4、第五电感L5的孔柱均采用柱型金属孔柱结构；第一并联谐振电容CC1、第二并联谐振电容CC2、第三并联谐振电容CC3、第四并联谐振电容CC4、第五并联谐振电容CC5及交叉耦合电容C15均采用对平板式电容极板的结构；第一串联电容C12、第一串联电容C45采用垂直直插式电容极板结构。
  9. 根据权利要求1所述的一种基于LTCC工艺的超宽通带五阶带通滤波器，其特征在于：所述第一并联谐振与第五并联谐振、第二并联谐振与第四并联谐振、第一串联电容C12与第二串联电容C45、第一串联电感L23与第二串联电感L34的结构呈镜像对称，第三并联谐振、交叉耦合电容C15、并联电感L24结构呈中心对称。
  10. 根据权利要求1所述的一种基于LTCC工艺的超宽通带五阶带通滤波器，其特征在于：所述陶瓷基体的材料的介电常数为9.8，损耗角正切0.003的陶瓷材料，底部接地电极、底部输入电极、底部输出电极均采用银材料印刷，所述滤波器的通带范围为3.64-7.04GHz，通带最大插入损耗为1.75dB，在低端阻带0-3GHz抑制大于30dB；在高端阻带7.8GHz-12.5GHz抑制大于30dB；三倍频12.5-17GHz抑制大于15dB。
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