WO2022078265A1 - 一种用于乘法器零标志位的产生电路、乘法器和检测方法 - Google Patents

一种用于乘法器零标志位的产生电路、乘法器和检测方法 Download PDF

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WO2022078265A1
WO2022078265A1 PCT/CN2021/122874 CN2021122874W WO2022078265A1 WO 2022078265 A1 WO2022078265 A1 WO 2022078265A1 CN 2021122874 W CN2021122874 W CN 2021122874W WO 2022078265 A1 WO2022078265 A1 WO 2022078265A1
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input value
input
zero
multiplier
gate
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PCT/CN2021/122874
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English (en)
French (fr)
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黄鹏
丁晓兵
朱少华
冯潮斌
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上海芯旺微电子技术有限公司
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Priority to EP21879310.7A priority Critical patent/EP4231136A4/en
Publication of WO2022078265A1 publication Critical patent/WO2022078265A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G06F7/523—Multiplying only
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/74—Selecting or encoding within a word the position of one or more bits having a specified value, e.g. most or least significant one or zero detection, priority encoders
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/76—Arrangements for rearranging, permuting or selecting data according to predetermined rules, independently of the content of the data
    • G06F7/768—Data position reversal, e.g. bit reversal, byte swapping

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  • the invention relates to the technical field of integrated circuits, in particular to a generation circuit, a multiplier and a detection method for a zero flag bit of a multiplier.
  • a common multiplier In a MCU with a 32-bit architecture, a common multiplier is a 32 ⁇ 32 structure with a low 32-bit result. In order to improve the operation efficiency, the multiplier is usually implemented in a single cycle. Due to the long critical path of the multiplier, the multiplier usually takes a long time. Compared with other instructions, the result of limiting the operating frequency occurs. Therefore, in the actual design process, it is necessary to speed up the operation result of the multiplier as much as possible.
  • the invention provides a generation circuit, a multiplier and a detection method for a zero flag bit of a multiplier, which solves the problems that the operation time of the existing multiplier is long and the operating frequency of the MCU is limited.
  • a circuit for generating zero flag bits of a multiplier which is used for multiplier applications requiring the same number of digits as the multiplier and multiplicand, including a low-order zero detection module, a bitwise AND module, and a result judgment module.
  • the low-order zero detection module is used to find the first input value from the low-order to the high-order first occurrence of the value 1, and replace all the bits to the highest position with 1;
  • the bitwise AND module is used to replace the The first input value is reversed by bit, and then the reversed first input value and the second input value are subjected to a bitwise AND logical operation;
  • the result determination module is used to determine whether the result after the logical AND operation is All zero, if all zero, the zero flag output is 1, otherwise the output is 0.
  • the low-position zero detection module includes a plurality of detection units that are cascaded together, and the cascade ports of the latter-level detection units are connected with the flag ports of all the previous detection units through the OR gate, and each detection unit has the same number.
  • the input port and input port are used to determine whether there is a value 1 in the input value. If so, the output of the flag bit is 1, and the output of the detection unit is the value after the bit corresponding to the value 1 is set to the highest position 1, otherwise the flag bit The output is 0, and the output of the detection unit is directly the input value.
  • the detection unit includes four input ports and four output ports from low position to high position, which are respectively In0, In1, In2, In3 and Out0, Out1, Out2, Out3,
  • the input port In0 is connected with the output port Out0 through two NOT gates and one OR gate in series in sequence to form the first path;
  • the input port In1 is connected with the output port Out1 through the NOR gate, the NOT gate, or the OR gate in series in sequence together, forming a The second path;
  • the input port In2 is connected to the output port Out2 through the series-connected NOT gate, NAND gate, or OR gate to form a third path;
  • the input port In3 is connected to the output through the serially-connected NOR gate, AND gate, or OR gate.
  • the ports Out2 are connected to form a fourth channel;
  • the input port of the NOR gate in the second path is also connected with the input port In0, and the output port is also connected with the input port of the NAND gate in the third path and the fourth path;
  • the input port of the NOR gate in the fourth path is also connected with the input port In2;
  • the output port of the NOR gate in the second path and the fourth path is also connected with the flag port through the NAND gate;
  • the input ports of the OR gates in the first path, the second path, the third path and the fourth path are all connected to the cascade ports.
  • the result determination module is provided with a NOR gate.
  • a multiplier based on the above-mentioned generating circuit for the zero flag bit of the multiplier, comprising the generating circuit for the zero flag bit of the multiplier and the multiplication circuit according to one of claims 1-4.
  • a detection method for the zero flag bit of fixed-length multiplication which is used for multiplier applications requiring that the multiplication result has the same number of digits as the multiplier and the multiplicand, comprising the following steps:
  • Step 1 Perform bit-by-bit detection on the first input value from the low position to the high position, until the first position with a value of 1 is found, and all the positions to the highest position are replaced with 1;
  • Step 2 Reverse the order of the first input value after the replacement in the step 1, and then perform a bitwise AND logical operation with the second input value;
  • Step 3 Judging the result of the logical operation in Step 2, if all are zero, the output of the zero flag bit is 1, otherwise the output is 0.
  • the digits of the first input value and the second input value are processed by means of high-order zero-filling or low-order truncation, so that the three digits are the same.
  • the first input value and the second input value are the same, but different from the digits of the required multiplication result, according to the required digits of the multiplication result, the first input value and the The high-order zero-filling method of the second input value, or intercepting the same number of digits as the required multiplication result from the low-order of the two, so that the three digits are the same;
  • the first input value or/and the second input When the first input value, the second input value and the required number of digits of the multiplication result are different, according to the required number of digits of the multiplication result, the first input value or/and the second input The high-order zero-filling method of the value, or truncating the same number of digits as the required multiplication result from the low-order of the first input value or/and the second input value, so that the three have the same number of digits.
  • the low-order zero detection module uses the low-order zero detection module to detect the low-order continuous zero bits in the first input value, and then use the bitwise AND module to retain the low-order continuous zero bits in the first input value and the second input value.
  • the result judgment module uses the calculation result of the zero flag bit when the first input value and the second input value are multiplied to be output.
  • the two can be calculated in parallel, thereby improving the operation speed of the multiplier.
  • the whole circuit has a compact structure, strong practicability, and is easy to popularize and popularize.
  • FIG. 1 is a schematic diagram of the overall circuit structure of the present invention.
  • FIG. 2 is a schematic structural diagram of a low-position zero detection module of the present invention
  • FIG. 3 is a schematic structural diagram of a detection unit of the present invention.
  • FIG. 4 is a schematic structural diagram of a result determination module of the present invention.
  • the operation result of the multiplier consists of two parts, one is the multiplication operation itself, and the other is the generation of the flag bit.
  • the time required for the two determines the time used to finally obtain the multiplication result.
  • the present invention proposes a method of rapidly generating a zero flag bit based on the input of a multiplier to provide a multiplication operation speed, that is, the serial calculation method of calculating the zero flag bit after the original multiplication operation result is generated is improved to a parallel calculation method that can run at the same time. way to improve the multiplier operation speed.
  • the present invention provides a generation circuit for a zero flag bit of a multiplier, including a low-order zero detection module, a bitwise AND module and a result judgment module, and the low-order zero detection module is used to find the first input value.
  • the first bit with a value of 1 appears from the low order to the high order, and all the bits to the highest order are replaced with 1;
  • the bitwise AND module is used to reverse the first input value after the replacement, and then replace The first input value and the second input value after the reverse order are subjected to a bitwise AND logical operation;
  • the result determination module is used to determine whether the result of the logical AND operation is all zero, if all zero, the zero flag bit output is 1, otherwise the output is 0.
  • the low-order zero bits in the first input value are detected by the low-order zero detection module, and then the low-order consecutive zero bits in the first input value and the second input value are retained by the bitwise AND module.
  • the result judgment module the calculation result of the zero flag bit when the first input value and the second input value are multiplied can be output. Calculate the result to calculate the zero flag bit, and the two can be calculated in parallel, thereby improving the operation speed of the multiplier.
  • the low-bit zero detection module includes multiple detection units that are cascaded together.
  • the cascade port of the latter detection unit is connected to the flag port of all the previous detection units through an OR gate.
  • Each detection unit is It has the same number of input ports and input ports, and is used to determine whether there is a value 1 in the input value. If there is, the output of the flag bit is 1, and the output of the detection unit is the value after the bit corresponding to the value 1 is set to the highest position 1, Otherwise, the output of the flag bit is 0, and the output of the detection unit is directly the input value. In this way, the first input value is divided into multiple parts by multiple detection units, and each part is used as input.
  • the corresponding detection unit is input to judge whether it contains the value 1, and with the help of the OR gate, all the previous detection units are combined.
  • the detection results are introduced into the next-level detection unit for auxiliary judgment, thereby improving the calculation speed of the entire low-bit zero detection module.
  • the detection unit includes four input ports and four output ports from low to high, namely In0, In1, In2, In3 and Out0, Out1, Out2, Out3, the input port In0 passes through Two NOT gates in series and one OR gate are connected with the output port Out0 to form the first path; the input port In1 is connected with the output port Out1 through the serially connected NOR gate, the NOT gate, or the OR gate together to form the second path; The input port In2 is connected to the output port Out2 through the series-connected NOT gate, the NAND gate, and the OR gate to form a third path; the input port In3 is connected to the output port Out2 through the series-connected NOR gate, AND gate, or OR gate, A fourth path is formed; and the input port of the NOR gate in the second path is also connected with the input port In0, and the output port is also connected with the input port of the NAND gate in the third path and the fourth path; The input port of the NOR gate is also connected with the input port In2; the output port of the NOR gate is also connected with
  • the input ports of the OR gates in the four paths are all connected to the cascade ports, the input ports correspond to the output ports of the four paths, and the cascade ports are connected to the flag ports of all the previous detection units through the OR gate, so as long as all the previous detection units are detected
  • the output of one of the flag bit ports of the unit is a value of 1. No matter what the calculation of the previous circuit in the four paths corresponding to the detection unit is, the output of the detection unit will also be a value of 1.
  • the truth table is as follows: Therefore, the first bit with a value of 1 can be quickly output to the highest position 1, and the low-order zero detection of the first input value can be quickly completed.
  • the input port of the bitwise AND module is connected from low to high with the output port of the low zero detection module from high to low to realize the bitwise reverse operation of the first input value after the replacement of 1.
  • the method does not require additional modules, and only needs to be routed to achieve the function of inversion in sequence, which is simple and reliable, and then uses multiple AND gates to perform a bitwise AND logical operation with the second input value.
  • the low-order consecutive zeros of one input value have been transferred to the high-order bits, while the low-order consecutive zeros of the second input value are still in the low-order bits, so that the low-order consecutive zero bits of the two input values are reserved for subsequent judgments.
  • the result judgment module is provided with a NOR gate, and each output port of the bitwise AND module is connected to the input port of the NOR gate, as shown in Figure 4, the output judgment of the zero flag bit can be completed by using the function of the NOR gate, When its output is 1, it means that the input of the NOR gate is all 0, that is, the low-order consecutive zero digits in the first input value and the second input value and the number of digits greater than or equal to any input value, the two are multiplied.
  • the operation result is 0; when the output is 0, it means that the input of the NOR gate is not all 0, that is, the low-order consecutive zero digits in the first input value and the second input value and the number of digits less than any input value , the result of the multiplication of the two is not 0.
  • the generating circuit of the present invention is used for multiplier applications requiring that the multiplication result is the same as the number of digits of the multiplier and the multiplicand.
  • the input is two 32-bit binary values, and the normal multiplication result is a 64-bit multiplier, or the input is two 64-bit binary values, and only the lower 32-bit multiplier of the multiplication result is taken, or
  • the input is a binary value with two different digits, and the number of digits of the multiplication result is also different from that of the two input multipliers, etc.
  • the generation circuit of the present invention can be directly used
  • the binary values of the two inputs are processed into the same number of digits as the required multiplication result, and can be used as input again.
  • the present invention also provides a multiplier based on the above-mentioned generating circuit for the zero mark bit of the multiplier, including the above-mentioned generating circuit for the zero mark bit of the multiplier and a multiplication circuit.
  • the present invention also provides a kind of detection method that is used for the fixed-length multiplication zero mark bit, comprises the following steps:
  • Step 1 Perform bit-by-bit detection on the first input value from low bits to high bits until the first bit with a value of 1 is found, and replace all the bits to the highest bit with 1.
  • the number of digits of the first input value and the second input value should be the same.
  • the number of digits is the same.
  • Step 2 Reverse the first input value in step 1, and then perform a bitwise AND logical operation with the second input value; The continuous zero has been transferred to the high position, and the low continuous zero of the second input value is still in the low position. Through the bitwise AND logical operation, the low continuous zero positions in the two input values can be reserved to prepare for the subsequent judgment. .
  • Step 3 Judging the result after the logical operation, if all are zero, the output of the zero flag bit is 1, otherwise the output is 0.
  • the zero flag bit is output. is 1; if its input is not all 0, that is, the low-order consecutive zero digits and the digits less than any input value in the first input value and the second input value, the multiplication result of the two is not 0, then The zero flag bit is output as 0.
  • the detection method of the present invention is also used for multiplier applications where the multiplication result is required to have the same number of digits as the multiplier and the multiplicand.
  • the number of digits of the input value and the second input value are processed so that all three have the same number of digits.
  • the first input value, the second input value and the required number of digits of the multiplication result are different, according to the required number of digits of the multiplication result, by combining the first input value or/and the second input value The high-order zero-filling method, or intercepting the same number of digits as the required multiplication result from the low-order digit of the first input value or/and the second input value, so that the three digits are the same.

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Abstract

本发明涉及集成电路的技术领域，公开了一种用于乘法器零标志位的产生电路，用于要求乘法运算结果与乘数、被乘数位数相同的乘法器应用，包括低位零检测模块、按位与模块和结果判定模块，所述低位零检测模块用于发现第一个输入值中从低位向高位第一个出现数值1的位，并将所述位至最高位全部用1替换；所述按位与模块用于将替换后的第一个输入值按位反序，再将反序后的第一输入值与第二输入值做按位与的逻辑运算；所述结果判定模块用于判定逻辑与运算后的结果是否全部为零，若全部为零，则零标志位输出为1，否则输出为0。本发明的电路结构紧凑，控制方便，便于普及和推广。

Description

一种用于乘法器零标志位的产生电路、乘法器和检测方法 技术领域
本发明涉及集成电路的技术领域，特别是一种用于乘法器零标志位的产生电路、乘法器和检测方法。
背景技术
在32位架构的MCU中，常见的乘法器为32×32结果为低32位的结构，为提高运算效率，乘法器通常使用单周期实现。由于乘法器的关键路径较长，通常乘法器需要较长的时间，相比其他指令会出现限制运行频率的结果，所以实际设计过程中需要尽可能加快乘法器的运算结果。
发明内容
本发明提供一种用于乘法器零标志位的产生电路、乘法器和检测方法，解决了现有乘法器的运算时间较长，会限制MCU运行频率等问题。
本发明可以通过以下技术方案实现：
一种用于乘法器零标志位的产生电路，用于要求乘法运算结果与乘数、被乘数位数相同的乘法器应用，包括低位零检测模块、按位与模块和结果判定模块，所述低位零检测模块用于发现第一个输入值中从低位向高位第一个出现数值1的位，并将所述位至最高位全部用1替换；所述按位与模块用于将替换后的第一个输入值按位反序，再将反序后的第一输入值与第二输入值做按位与的逻辑运算；所述结果判定模块用于判定逻辑与运算后的结果是否全部为零，若全部为零，则零标志位输出为1，否则输出为0。
进一步，所述低位零检测模块包括级联在一起的多个检测单元，后一级检测单元的级联端口通过或门与前面所有检测单元的标志位端口连接，每个检测单元均具有相同数量的输入端口和输入端口，用于判定输入数值中是否有数值1，若有，标志位输出为1，其检测单元的输出为将数值1对应的位至最高位置1后的数值，否则标志位输出为0，且检测单元的输出直接为输入数值。
进一步，所述检测单元包括从低位到高位的四个输入端口和四个输出端口，分别为In0、In1、In2、In3和Out0、Out1、Out2、Out3，
输入端口In0通过依次串联的两个非门和一个或门与输出端口Out0相连，形成第一通路；输入端口In1一起通过依次串联的或非门、非门、或门与输出端口Out1相连，形成第二通路；输入端口In2通过依次串联的非门、与非门、或门与输出端口Out2相连，形成第三通路；输入端口In3一起通过依次串联的或非门、与门、或门与输出端口Out2相连，形成第四通路；
所述第二通路中的或非门的输入端口还与输入端口In0连接，输出端口还与第三通路、第四通路中的与非门的输入端口连接；
所述第四通路中的或非门的输入端口还与输入端口In2连接；
所述第二通路、第四通路中的或非门的输出端口还通过与非门与标志位端口连接；
所述第一通路、第二通路、第三通路和第四通路中的或门的输入端口均与级联端口相连。
进一步，所述结果判定模块设置有或非门。
一种基于上文所述的用于乘法器零标志位的产生电路的乘法器，包括权利要求1-4之一所述的用于乘法器零标志位的产生电路和乘法运算电路。
一种用于定长乘法零标志位的检测方法，用于要求乘法运算结果与乘数、被乘数位数相同的乘法器应用，包括以下步骤：
步骤一、从低位向高位对第一个输入值进行逐位检测，直至发现第一个出现数值1的位，并将所述位至最高位全部用1替换；
步骤二、将所述步骤一中替换后的第一个输入值按位反序，再与第二个输入值进行按位与逻辑运算；
步骤三、对步骤二中逻辑运算后的结果进行判定，若全部为零，则零标志位输出为1，否则输出为0。
进一步，根据要求乘法运算结果的位数，通过高位补零或者低位截取的方式，对所述第一个输入值和第二个输入值的位数进行处理，使三者的位数相同。
进一步，当所述第一个输入值和第二个输入值的位数相同，但与要求乘法运算结果的位数不同时，根据要求乘法运算结果的位数，通过将第一个输入值和 第二个输入值的高位补零方式，或者从两者的低位截取与要求乘法运算结果的位数相同的位数，使三者的位数相同；
当所述第一个输入值、第二个输入值以及要求乘法运算结果的位数均不相同时，根据要求乘法运算结果的位数，通过将第一个输入值或/和第二个输入值的高位补零方式，或者从第一个输入值或/和第二个输入值的低位截取与要求乘法运算结果的位数相同的位数，使三者的位数相同。
本发明有益的技术效果在于：
利用低位零检测模块将第一个输入值中的低位连续零位检测出来，然后利用按位与模块将第一个输入值、第二个输入值中的低位连续零位都保留下来，最后，通过结果判定模块即可输出第一个输入值、第二个输入值做乘法运算时的零标志位计算结果，不需要根据第一个输入值、第二个输入值做乘法运算后的计算结果来计算零标志位，两者可以并行计算，从而提高乘法器的运算速度。另外，整个电路结构紧凑，实用性强，便于普及和推广。
附图说明
图1为本发明的总体电路结构示意图；
图2为本发明的低位零检测模块的结构示意图；
图3为本发明的检测单元的结构示意图；
图4为本发明的结果判定模块的结构示意图。
具体实施方式
下面结合附图对本发明的具体实施例进一步详细说明。
一般情况下，乘法器的运算结果有两部分组成，一个是乘法运算本身，一个是标志位的产生，这两者需要的时间决定了最后得到乘法结果所使用的时间。而乘法器的标志位主要有两个，即负标志位和是零标志位，其中，负标志位判断较为简单，零标志位会在乘法运算完成之后再产生，这样不利于提高乘法器运算速度。本发明提出一种基于乘法器输入快速产生零标志位的方式来提供乘法运算速度，即将原来的乘法运算结果产生后再计算零标志位的串行计算方式 改进为两者能够同时运行的并行计算方式，从而提高乘法器运算速度。
参照附图1，本发明提供了一种用于乘法器零标志位的产生电路，包括低位零检测模块、按位与模块和结果判定模块，该低位零检测模块用于发现第一个输入值中从低位向高位第一个出现数值1的位，并将所述位至最高位全部用1替换；该按位与模块用于将替换后的第一个输入值按位反序，再将反序后的第一输入值与第二输入值做按位与的逻辑运算；该结果判定模块用于判定逻辑与运算后的结果是否全部为零，若全部为零，则零标志位输出为1，否则输出为0。这样，利用低位零检测模块将第一个输入值中的低位连续零位检测出来，然后利用按位与模块将第一个输入值、第二个输入值中的低位连续零位都保留下来，最后，通过结果判定模块即可输出第一个输入值、第二个输入值做乘法运算时的零标志位计算结果，不需要根据第一个输入值、第二个输入值做乘法运算后的计算结果来计算零标志位，两者可以并行计算，从而提高乘法器的运算速度。
如图2所示，该低位零检测模块包括级联在一起的多个检测单元，后一级检测单元的级联端口通过或门与前面所有检测单元的标志位端口连接，每个检测单元均具有相同数量的输入端口和输入端口，用于判定输入数值中是否有数值1，若有，标志位输出为1，其检测单元的输出为将数值1对应的位至最高位置1后的数值，否则标志位输出为0，且检测单元的输出直接为输入数值。这样，通过多个检测单元将第一个输入值均分为多个部分，各个部分均作为输入，同时输入对应的检测单元进行是否包含数值1的判断，并且借助或门，将前面所有检测单元的检测结果引入至下一级检测单元辅助判断，从而提高整个低位零检测模块的计算速度。
具体地，如图3所示，该检测单元包括从低位到高位的四个输入端口和四个输出端口，分别为In0、In1、In2、In3和Out0、Out1、Out2、Out3，输入端口In0通过依次串联的两个非门和一个或门与输出端口Out0相连，形成第一通路；输入端口In1一起通过依次串联的或非门、非门、或门与输出端口Out1相连，形成第二通路；输入端口In2通过依次串联的非门、与非门、或门与输出端口Out2相连，形成第三通路；输入端口In3一起通过依次串联的或非门、与门、或门与输出端口Out2相连，形成第四通路；并且第二通路中的或非门的输入端口还与输入端口In0连接，输出端口还与第三通路、第四通路中的与非门的输 入端口连接；第四通路中的或非门的输入端口还与输入端口In2连接；第二通路、第四通路中的或非门的输出端口还通过与非门与标志位端口连接；第一通路、第二通路、第三通路和第四通路中或门的输入端口均与级联端口相连。
由于四条通路中或门的输入端口均与级联端口相连，输入端口对应四条通路的输出端口，而级联端口又通过或门与前面所有检测单元的标志位端口连接，因此，只要前面所有检测单元的标志位端口中的一个输出为数值1，无论该检测单元对应的四条通路中前面电路的计算是什么，该检测单元的输出也将是全部为数值1，其真值表如下所示，从而可以快速地将第一个出现数值1的位至最高位置1输出，快速完成第一个输入值的低位零检测。
检测单元的真值表
Figure PCTCN2021122874-appb-000001
该按位与模块的输入端口从低位至高位分别与低位零检测模块的输出端口从高位至低位连接起来，实现对置1替换后的第一个输入值按位反序操作，通过这种连接方式不需要额外的模块，只需要通过走线即可实现按序取反的功能，简单可靠，然后利用多个与门，将其与第二个输入值做按位与的逻辑运算，由于第一个输入值的低位连续零已经转移到高位，而第二个输入值的低位连续零依然在低位，从而将两个输入值中的低位连续零位都保留下来，为后续判断做 准备。
该结果判定模块设置有或非门，将按位与模块的各个输出端口连接至或非门的输入端口，如图4所示，利用或非门的功能即可完成零标志位的输出判断，其输出为1时，表示该或非门的输入全部为0，即第一个输入值和第二个输入值中的低位连续零位数和大于等于任一输入值的位数，两者乘法运算结果为0；输出为0时，表示该或非门的输入不全部为0，即第一个输入值和第二个输入值中的低位连续零位数和小于任一输入值的位数，两者乘法运算结果不为0。
本发明的产生电路用于要求乘法运算结果与乘数、被乘数位数相同的乘法器应用，例如输入为两个32位数的二进制数值、只取乘法运算结果低32位的乘法器，或者输入为两个32位数的二进制数值、取正常的乘法运算结果即64位的乘法器，或者输入为两个64位数的二进制数值、只取乘法运算结果低32位的乘法器，或者输入为两个位数不同的二进制数值、且取乘法运算结果的位数也与两个输入不同的乘法器等等，在使用本发明的产生电路时，具体处理如下：
对于第一种情况，可以直接使用本发明的产生电路；
对于第二种情况，只需将输入为两个32位数的二进制数值的高位补零扩展成64位数即可；
对于第三种情况，只需截取输入的两个64位数的二进制数值中低32位重新作为输入即可；
对于第四种情况，参考上述三种情况，将两个输入的二进制数值处理成和要求的乘法运算结果相同的位数，重新作为输入即可。
本发明还提供了一种基于上文所述的用于乘法器零标志位的产生电路的乘法器，包括上文所述的用于乘法器零标志位的产生电路和乘法运算电路。
本发明还提供了一种用于定长乘法零标志位的检测方法，包括以下步骤：
步骤一、从低位向高位对第一个输入值进行逐位检测，直至发现第一个出现数值1的位，并将所述位至最高位全部用1替换。
为了确保检测的一致性，第一个输入值和第二个输入值的位数要相同，当两者位数不相同时，通过将位数少的输入值的高位补零方式，使两者的位数达到相同。
步骤二、将步骤一中替换后的第一个输入值按位反序，再与第二个输入值进 行按位与逻辑运算；由于采用按位反序操作，将第一个输入值的低位连续零已经转移到高位，而第二个输入值的低位连续零依然在低位，通过按位与逻辑运算，就可以将两个输入值中的低位连续零位都保留下来，为后续判断做准备。
步骤三、对逻辑运算后的结果进行判定，若全部为零，则零标志位输出为1，否则输出为0。
若其输入全部为0，即第一个输入值和第二个输入值中的低位连续零位数和大于等于任一输入值的位数，两者乘法运算结果为0，则零标志位输出为1；若其输入不全部为0，即第一个输入值和第二个输入值中的低位连续零位数和小于任一输入值的位数，两者乘法运算结果不为0，则零标志位输出为0。
本发明的检测方法也是用于要求乘法运算结果与乘数、被乘数位数相同的乘法器应用，根据要求乘法运算结果的位数，通过高位补零或者低位截取的方式，对第一个输入值和第二个输入值的位数进行处理，使三者的位数相同。
具体地，当第一个输入值和第二个输入值的位数相同，但与要求乘法运算结果的位数不同时，根据要求乘法运算结果的位数，通过将第一个输入值和第二个输入值的高位补零方式，或者从两者的低位截取与要求乘法运算结果的位数相同的位数，使三者的位数相同；
当第一个输入值、第二个输入值以及要求乘法运算结果的位数均不相同时，根据要求乘法运算结果的位数，通过将第一个输入值或/和第二个输入值的高位补零方式，或者从第一个输入值或/和第二个输入值的低位截取与要求乘法运算结果的位数相同的位数，使三者的位数相同。
虽然以上描述了本发明的具体实施方式，但是本领域的技术人员应当理解，这些仅是举例说明，在不背离本发明的原理和实质的前提下，可以对这些实施方式做出多种变更或修改，因此，本发明的保护范围由所附权利要求书限定。

Claims (8)

  1. 一种用于乘法器零标志位的产生电路，其特征在于：用于要求乘法运算结果与乘数、被乘数位数相同的乘法器应用，包括低位零检测模块、按位与模块和结果判定模块，所述低位零检测模块用于发现第一个输入值中从低位向高位第一个出现数值1的位，并将所述位至最高位全部用1替换；所述按位与模块用于将替换后的第一个输入值按位反序，再将反序后的第一输入值与第二输入值做按位与的逻辑运算；所述结果判定模块用于判定逻辑与运算后的结果是否全部为零，若全部为零，则零标志位输出为1，否则输出为0。
  2. 根据权利要求1所述的用于乘法器零标志位的产生电路，其特征在于：所述低位零检测模块包括级联在一起的多个检测单元，后一级检测单元的级联端口通过或门与前面所有检测单元的标志位端口连接，每个检测单元均具有相同数量的输入端口和输入端口，用于判定输入数值中是否有数值1，若有，标志位输出为1，其检测单元的输出为将数值1对应的位至最高位置1后的数值，否则标志位输出为0，且检测单元的输出直接为输入数值。
  3. 根据权利要求2所述的用于乘法器零标志位的产生电路，其特征在于：所述检测单元包括从低位到高位的四个输入端口和四个输出端口，分别为In0、In1、In2、In3和Out0、Out1、Out2、Out3，
    输入端口In0通过依次串联的两个非门和一个或门与输出端口Out0相连，形成第一通路；输入端口In1一起通过依次串联的或非门、非门、或门与输出端口Out1相连，形成第二通路；输入端口In2通过依次串联的非门、与非门、或门与输出端口Out2相连，形成第三通路；输入端口In3一起通过依次串联的或非门、与门、或门与输出端口Out2相连，形成第四通路；
    所述第二通路中的或非门的输入端口还与输入端口In0连接，输出端口还与第三通路、第四通路中的与非门的输入端口连接；
    所述第四通路中的或非门的输入端口还与输入端口In2连接；
    所述第二通路、第四通路中的或非门的输出端口还通过与非门与标志位端口连接；
    所述第一通路、第二通路、第三通路和第四通路中的或门的输入端口均与级联端口相连。
  4. 根据权利要求1所述的用于乘法器零标志位的产生电路，其特征在于： 所述结果判定模块设置有或非门。
  5. 一种基于权利要求1所述的用于乘法器零标志位的产生电路的乘法器，其特征在于：包括权利要求1-4之一所述的用于乘法器零标志位的产生电路和乘法运算电路。
  6. 一种用于定长乘法零标志位的检测方法，其特征在于，用于要求乘法运算结果与乘数、被乘数位数相同的乘法器应用，包括以下步骤：
    步骤一、从低位向高位对第一个输入值进行逐位检测，直至发现第一个出现数值1的位，并将所述位至最高位全部用1替换；
    步骤二、将所述步骤一中替换后的第一个输入值按位反序，再与第二个输入值进行按位与逻辑运算；
    步骤三、对步骤二中逻辑运算后的结果进行判定，若全部为零，则零标志位输出为1，否则输出为0。
  7. 根据权利要求6所述的定长乘法零标志位的检测方法，其特征在于：根据要求乘法运算结果的位数，通过高位补零或者低位截取的方式，对所述第一个输入值和第二个输入值的位数进行处理，使三者的位数相同。
  8. 根据权利要求7所述的定长乘法零标志位的检测方法，其特征在于：当所述第一个输入值和第二个输入值的位数相同，但与要求乘法运算结果的位数不同时，根据要求乘法运算结果的位数，通过将第一个输入值和第二个输入值的高位补零方式，或者从两者的低位截取与要求乘法运算结果的位数相同的位数，使三者的位数相同；
    当所述第一个输入值、第二个输入值以及要求乘法运算结果的位数均不相同时，根据要求乘法运算结果的位数，通过将第一个输入值或/和第二个输入值的高位补零方式，或者从第一个输入值或/和第二个输入值的低位截取与要求乘法运算结果的位数相同的位数，使三者的位数相同。
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