WO2022077971A1 - 存储器测试方法 - Google Patents

存储器测试方法 Download PDF

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Publication number
WO2022077971A1
WO2022077971A1 PCT/CN2021/105582 CN2021105582W WO2022077971A1 WO 2022077971 A1 WO2022077971 A1 WO 2022077971A1 CN 2021105582 W CN2021105582 W CN 2021105582W WO 2022077971 A1 WO2022077971 A1 WO 2022077971A1
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attack
target
lines
rows
row
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French (fr)
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许小峰
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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Priority to US17/647,997 priority Critical patent/US11599646B2/en
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/50—Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems
    • G06F21/57—Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities
    • G06F21/577—Assessing vulnerabilities and evaluating computer system security
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/78—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure storage of data
    • G06F21/79—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure storage of data in semiconductor storage media, e.g. directly-addressable memories
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/52—Protection of memory contents; Detection of errors in memory contents
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/50—Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems
    • G06F21/55—Detecting local intrusion or implementing counter-measures
    • G06F21/554—Detecting local intrusion or implementing counter-measures involving event detection and direct action
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G11C11/40611—External triggering or timing of internal or partially internal refresh operations, e.g. auto-refresh or CAS-before-RAS triggered refresh
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4078—Safety or protection circuits, e.g. for preventing inadvertent or unauthorised reading or writing; Status cells; Test cells
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2221/00—Indexing scheme relating to security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F2221/03—Indexing scheme relating to G06F21/50, monitoring users, programs or devices to maintain the integrity of platforms
    • G06F2221/034—Test or assess a computer or a system

Definitions

  • the present disclosure relates to, but is not limited to, a memory testing method.
  • the row hammer effect means that if a row of memory cells is read multiple times in a short period of time in a DRAM refresh cycle, the physically connected adjacent rows of memory cells will have a bit flip phenomenon, resulting in abnormal data.
  • Hackers often use the hammer effect of memory to attack.
  • memory manufacturers usually use monitoring programs to determine whether the memory is under attack, and then activate active refresh when it is judged to be attacked to avoid the hammer effect.
  • the attack test program In order to test whether the protection program of the memory is strong enough, it is necessary to use the attack test program to attack the memory. Since the protection programs set by different memories are different, the method for testing the ability of the memory to resist attacks in the related art has fewer protection programs set in the memory settings, resulting in a high success rate of the attack test. In this case, the memory that passes the test may actually be unable to resist more flexible attack strategies, and cannot guarantee that it can face most of the improved attack scenarios, that is, insufficient reliability verification.
  • the purpose of the present disclosure is to provide a memory testing method for overcoming, at least to a certain extent, the problem of inability to effectively verify the ability of a DRAM to resist a row hammer attack due to limitations and defects of the related art.
  • a memory testing method including: determining a refresh period T of a target memory bank, a design attack resistance frequency F, and a single-row read time t; according to the refresh period T, the design attack resistance frequency F And the single-line reading time t determines the number of attack lines N; according to the value of the number of attack lines N, a group of target attack lines is determined in the target repository, and the group of target attack lines includes N target attack lines, and the N There is a line between at least two target attack lines in the target attack lines; after reading the N target attack lines X times in a row, check whether all adjacent lines of the target attack line have abnormal data to complete an attack Test: complete MT/NXt times of the attack test on the target repository within the M refresh cycles, and when no data abnormality occurs in the attack tests, determine that the target repository has an attack-resistant capability up to the standard.
  • the embodiments of the present disclosure can implement an attack test on the memory with an attack frequency higher than the designed attack resistance capability of the memory, so as to effectively verify whether the memory has the line hammer effect attack resistance that meets the nominal frequency. ability.
  • FIG. 1 is a flowchart of a memory testing method in an exemplary embodiment of the present disclosure.
  • FIG. 2 is a schematic diagram of a group of target attack lines in one embodiment of the present disclosure.
  • FIG. 3 is a schematic diagram of a group of target attack lines in another embodiment of the present disclosure.
  • FIG. 4 is a schematic diagram of a group of target attack lines in yet another embodiment of the present disclosure.
  • FIG. 5 is a schematic diagram of a group of target attack lines in yet another embodiment of the present disclosure.
  • FIG. 6 is a flow chart of testing the memory under test in the embodiment shown in FIG. 2 .
  • FIG. 7 is a flow chart of testing the memory under test in the embodiment shown in FIG. 3 .
  • FIG. 8 is a flow chart of testing the memory under test in the embodiment shown in FIG. 4 or FIG. 5 .
  • FIG. 9 is a schematic diagram of an implementation environment of an embodiment of the present disclosure.
  • Example embodiments will now be described more fully with reference to the accompanying drawings.
  • Example embodiments can be embodied in various forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art.
  • the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.
  • numerous specific details are provided in order to give a thorough understanding of the embodiments of the present disclosure.
  • those skilled in the art will appreciate that the technical solutions of the present disclosure may be practiced without one or more of the specific details, or other methods, components, devices, steps, etc. may be employed.
  • well-known solutions have not been shown or described in detail to avoid obscuring aspects of the present disclosure.
  • FIG. 1 schematically shows a flowchart of a memory testing method in an exemplary embodiment of the present disclosure.
  • a memory testing method 100 may include:
  • Step S1 determine the refresh period T of the target storage library, the design defense attack frequency F and the single-line reading time t;
  • Step S2 according to the refresh period T, the design resisting attack frequency F and the single-line reading time t to determine the number N of attack lines;
  • Step S3 according to the value of the number N of attack lines, determine a group of target attack lines in the target repository, the group of target attack lines includes N target attack lines, and at least two of the N target attack lines One line between target attack lines;
  • Step S4 after continuously reading the N target attack rows for X times, detect whether data abnormality occurs in all adjacent rows of the target attack row to complete an attack test;
  • Step S5 complete MT/NXt times of the attack test on the target repository within the M refresh cycles, and when no data abnormality occurs in the attack test, determine that the target repository has an attack-resistant capability up to the standard.
  • the embodiments of the present disclosure can test the memory at an attack frequency higher than the designed attack resistance capability of the memory, thereby effectively verifying whether the memory has the hammer effect attack resistance capability that meets the nominal frequency.
  • each storage bank of the memory under test is tested one by one.
  • Steps S1 to S5 are the steps of testing a memory bank, and the test of the memory to be tested can be completed by performing the operations of steps S1 to S5 for each memory bank of the memory to be tested.
  • step S1 the refresh period T of the target memory bank, the frequency F designed to resist attacks, and the time t for reading a single row are determined.
  • the set refresh cycle of the memory is 64ms. Between two refreshes, the state of a row of memory cells hardly changes autonomously (there will be a small amount of leakage) without being operated. If the two adjacent rows (the previous row and the next row) of the target row are read in a short period of time, the memory cells of the target row have a certain probability of bit flip phenomenon (Bit Flip), which is called the target row. Produces a row hammer effect (Row Hammer).
  • the row hammer effect is used to cause bit flips in one or more rows of memory cells in the memory.
  • the number of times the memory is read that is, the read frequency
  • active refresh is triggered to quickly restore the memory cells that may have bit flips to resist attacks.
  • the frequency of attacks that can be resisted by the memory itself is different. Therefore, for different memories, it is necessary to obtain the designed anti-attack frequency F before testing its anti-attack ability, so as to establish an attack scheme with an attack frequency greater than F, and effectively verify the ability of the memory to resist attacks.
  • the memory is designed to withstand an attack frequency F of 200k times or 50k times.
  • the attack time is different.
  • the single row read time of the memory is 85ns.
  • step S2 the number N of attacked rows is determined according to the refresh period T, the frequency F designed to resist attacks, and the reading time t of a single row.
  • the number N of attack lines can be determined according to the following formula:
  • the N value determined by formula (1) can be used directly to design an attack scheme , so as to maximize the number of target attack lines that can be read by one attack operation, thereby maximizing the attack capability.
  • a group of target attack rows is determined in the target repository according to the value of the number of attack rows N, the set of target attack rows includes N target attack rows, and at least two of the N target attack rows One line between each target attack line.
  • the protection mechanism of DRAM is generally probabilistic sampling protection. If only a certain row is attacked, the probability of being discovered by the DRAM protection mechanism will be high, resulting in a low attack difficulty and unable to effectively test the true ability of DRAM to resist attacks. Therefore, in the embodiment of the present disclosure, N target attack rows are set, and the arrangement of the N target attack rows is set in various ways, so as to form a variety of attack schemes and comprehensively test the attack resistance capability of the DRAM.
  • each attack scheme in order to induce at least one memory cell to generate a bit flip as soon as possible, the embodiment of the present disclosure sets a row between at least two target attack rows in the target attack row, so as to induce a row in the middle of the two target attack rows A hammer effect occurs.
  • the attack scheme is determined according to the maximum number of attack lines N that can be read per attack.
  • N the maximum number of attack lines
  • the number of attack lines is small, that is, when the test frequency is high, there are fewer attack schemes that can be used.
  • a fixed attack line can be set, that is, in each attack test, all attack lines are attacked. (Reading) several identical lines to increase the possibility of line hammer effect on adjacent lines of the fixed attack line.
  • the number of attack lines is large, that is, when the test frequency is relatively low, the number of attacks is large in a single attack test. At this time, multiple random reading or cyclic reading schemes can be used to induce the row hammer effect in the memory.
  • FIG. 2 is a schematic diagram of a group of target attack lines in one embodiment of the present disclosure.
  • the difference between the row number of the fixed attack row 21 and the row number of the mobile attack row 22 can be set to be small, for example, 4.
  • FIG. 3 is a schematic diagram of a group of target attack lines in another embodiment of the present disclosure.
  • the n fixed attack lines are separated by one line, the minimum line number corresponding to the n fixed attack lines is randomly determined, and the line number of the n fixed attack lines is the same in each group of target attack lines corresponding to the target repository.
  • the line numbers of the m mobile attack lines are all determined randomly, and the line numbers of the m mobile attack lines are not exactly the same in each group of target attack lines corresponding to the target repository.
  • the difference between the row number of the fixed attack row 31 with the smallest row number and the row number of the mobile attack row 32 can be set to be smaller, for example, 6.
  • FIG. 4 is a schematic diagram of a group of target attack lines in yet another embodiment of the present disclosure.
  • the i-th group of target attack lines corresponding to the target repository includes N mobile attack lines 41, and each mobile attack line is spaced from at least one other mobile attack line.
  • One line, the minimum line number of N mobile attack lines in the i-th target attack line is x-1+i, x is the minimum line number of N mobile attack lines in the first group of target attack lines, and x is randomly determined.
  • each mobile attack line can be set to at least One other attack line is separated by one line, as shown in Figure 4.
  • the row number of the mobile attack row with the smallest row number may be determined randomly.
  • the value of the number of attacked lines N may be updated in response to a modification instruction of the number of attacked lines from the user. That is, the calculated number of attack lines N can be recommended to the user.
  • the user wants to increase the attack frequency he can reduce the number of attack lines N on the basis of the number of attack lines, and implement the attack by entering a smaller updated N value. increase in frequency.
  • the value of the number of attack lines N in the present disclosure is calculated according to the minimum requirement that meets the attack condition (the attack frequency is not less than the frequency of the design to resist the attack of the memory to be tested)
  • the attack frequency is not less than the frequency of the design to resist the attack of the memory to be tested
  • the attack frequency cannot be achieved More than or equal to the design to resist the attack of the attack frequency, therefore, in this case, the user is only allowed to decrease the N value to increase the attack frequency, and the user is not allowed to increase the N value to reduce the attack frequency.
  • FIG. 5 is a schematic diagram of a group of target attack lines in yet another embodiment of the present disclosure.
  • the i-th group of target attack lines corresponding to the target repository includes N mobile attack lines 51. Move one line between attack lines.
  • the positions of the moving attacking rows are set more compactly, and it is easier to induce the row hammer effect in the rows between the moving attacking rows.
  • step S4 after reading the N target attack rows X times in a row, it is detected whether data abnormality occurs in all adjacent rows of the target attack row to complete an attack test.
  • the mobile attack lines with the same form and changing line numbers can be read.
  • the row number of the fixed attack row in the first group of target attack rows corresponding to the first attack test can be randomly determined as z1
  • the minimum line number of the mobile attack line is randomly determined to be x
  • the first group of target attack lines is continuously read X times to detect whether all adjacent lines of these target attack lines have abnormal data to complete an attack test.
  • the form of the second group of target attack lines is the same as that of the first group, the line number of the fixed attack line is still z1, and the minimum line number of the mobile attack line is x+1; the third attack test is performed.
  • the row number of the fixed attack row in the third group of target attack rows is still z1, and the minimum row number of the mobile attack row is x+2.
  • the row number of the fixed attack row in the i-th target attack row is still z, and the minimum row number of the mobile attack row is x-1+i.
  • the line number of the target attack line can be re-determined to provide a richer attack scenario.
  • the row number of the fixed attack row corresponding to the first attack test may be set as z2
  • the minimum row number of the mobile attack row may be set as y in the second refresh cycle.
  • the row number of the fixed attack row is still z2
  • the minimum row number of the mobile attack row is y-1+i.
  • the minimum row number of the fixed attack row of the first group of target attack rows can be randomly set to z1, and the mobile attack row can be set to z1.
  • the row number of the row is randomly set to x, so that in the i-th attack test in the same refresh cycle, the minimum row number of the fixed attack row in the i-th target attack row is still z1, and the row number of the mobile attack row is x- 1+i.
  • the minimum line number of the fixed attack line in the first group of target attack lines corresponding to the first group of attack tests is randomly set to z2, and the line number of the mobile attack line is randomly determined to be y;
  • the minimum line number of the fixed attack line in the first group of target attack lines corresponding to the attack test is still z2, and the line number of the mobile attack line is changed to y-1+i.
  • the minimum row number of the mobile attack row corresponding to the first group of tests in one refresh cycle is x
  • the i-th group of tests corresponds to The minimum line number of the mobile attack line is x-1+i.
  • the minimum line number of the mobile attack line is randomly determined again.
  • each attack scheme can be fully tested and more abundant attack schemes can be set.
  • each attack test includes not only the time of normal attack (reading), but also the time of verifying whether the adjacent row has the row hammer effect.
  • the attack frequency it is necessary to minimize the time occupied by the verification row hammer effect, that is, reduce the adjacent rows for verification; in order to improve the verification accuracy, it is necessary to increase the time occupied by the verification row hammer effect as much as possible. Therefore, the number of adjacent rows to be verified in an attack test can be set by those skilled in the art according to the actual situation.
  • the number of adjacent rows to be verified is set to 1, and the adjacent row to be verified is the row between two mobile attack rows.
  • the number of attack tests in one refresh cycle, the X value corresponding to each attack test, and the number of adjacent rows to be verified can be set according to the value of N.
  • N 15 and the designed attack frequency is 50k times
  • one refresh cycle is 64ms, there are 250us available for verification in one refresh cycle.
  • Adjacent rows that is, 250000/85 ⁇ 2941 adjacent rows can be verified. If a verify adjacent row operation (ie the end of an attack test) requires verification of 14 adjacent rows (the total number of rows between each two target attack rows), then in this attack scheme, at most one refresh cycle can be Set 2941/14 ⁇ 210 attack tests.
  • step S5 complete MT/NXt times of the attack tests on the target repository within M refresh cycles, and when no data abnormality occurs in the attack tests, determine that the target repository has an attack-resistant capability up to the standard .
  • the test time of an attack test is at least NXt, and the test time does not include the time to verify whether adjacent lines have the hammer effect. That is, within one refresh period T, at most T/NXt attack tests can be performed. If the target repository is tested for M refresh cycles, the number of times the attack is tested on the target repository is MT/NXt times.
  • FIG. 6 is a flow chart of testing the memory under test in the embodiment shown in FIG. 2 .
  • test flow may include:
  • Step S601 read the i-th row of repository k
  • Step S602 read the jth row of the repository k;
  • Step S603 read the j+2th row of the repository k;
  • Step S604 determine whether the sequence number read in this round, that is, the number of times of reading reaches X, if not, go to step S605, if so, go to step S606;
  • Step S605 add one to the number of readings and return to step S601;
  • Step S606 read the j+1th row of the storage bank k to verify whether the row hammer effect occurs;
  • Step S607 judging whether the preset number of attack tests in a single cycle is reached, if not, go to step S608, if yes, go to step S609;
  • Step S608 add one to the number of attacks, clear the number of reads, add one to j, and then return to step S601;
  • Step S609 determine whether the number of test cycles reaches M, if not, go to step S610, if yes, go to step S611;
  • Step S610 add one to the number of test cycles, i, and j, and return to step S601 after clearing the number of attack tests and the number of readings;
  • Step S611 determine whether k is the maximum serial number of the storage library in the memory to be tested, if not, go to step S612, if so, go to step S613;
  • Step S612 clear the number of test cycles, the number of attack tests, and the number of readings, add one to k, re-determine i and j randomly, and then return to step S601;
  • Step S613 determine the test result.
  • steps S601 to S606 are the test flow of a single attack test
  • steps S601 to S608 are the test flow of a single refresh cycle
  • steps S601 to S610 are the test flow of a single repository
  • steps S600 to S613 are Test flow for a single memory.
  • FIG. 7 is a flow chart of testing the memory under test in the embodiment shown in FIG. 3 .
  • test flow may include:
  • Step S701 read the i-th row of repository k
  • Step S702 read the i+2th row of the storage bank k;
  • Step S703 read the jth row of the repository k;
  • Step S704 determine whether the sequence number read in the current round, that is, the number of times of reading reaches X, if not, go to step S705, if so, go to step S707;
  • Step S705 add one to the number of readings and return to step S701;
  • Step S706 read the i+1th row of the storage bank k to verify whether the row hammer effect occurs;
  • Step S707 determine whether the preset number of attack tests in a single cycle is reached, if not, go to step S708, if yes, go to step S709;
  • Step S708 add one to the number of attacks, clear the number of reads, add one to j, and then return to step S701;
  • Step S709 determine whether the number of test cycles reaches M, if not, go to step S710, if yes, go to step S711;
  • Step S710 add one to the number of test cycles, i, and j, and return to step S701 after clearing the number of attack tests and the number of readings;
  • Step S711 determine whether k is the maximum serial number of the storage library in the memory to be tested, if not, go to step S712, if so, go to step S713;
  • Step S712 clear the number of test cycles, the number of attack tests, and the number of readings, add one to k, re-determine i and j randomly, and then return to step S701;
  • Step S713 determine the test result.
  • steps S701-S706 are the test flow of a single attack test
  • steps S701-S708 are the test flow of a single refresh cycle
  • steps S701-S710 are the test flow of a single repository
  • steps S700-S713 are Test flow for a single memory.
  • FIG. 8 is a flow chart of testing the memory under test in the embodiment shown in FIG. 4 or FIG. 5 .
  • test flow may include:
  • Step S801 read N target attack rows in the storage bank k in sequence, and the minimum row number of the target attack row is i;
  • Step S802 judging whether the sequence number read in the current round, that is, the number of times of reading, reaches X, if not, go to step S803, if yes, go to step S804;
  • Step S803 add one to the number of readings and return to step S801;
  • Step S804 read the adjacent row of the target attack row to verify whether the row hammer effect occurs;
  • Step S805 determine whether the preset number of attack tests in a single cycle is reached, if not, go to step S806, if yes, go to step S807;
  • Step S806 add one to the number of attacks, clear the number of reads, add one to j, and then return to step S801;
  • Step S807 determine whether the number of test cycles reaches M, if not, go to step S808, if yes, go to step S809;
  • Step S808 add one to the number of test cycles, i, and j, and return to step S801 after clearing the number of attack tests and the number of readings;
  • Step S809 determine whether k is the maximum serial number of the storage library in the memory to be tested, if not, go to step S810, if so, go to step S811;
  • Step S810 clear the number of test cycles, the number of attack tests, and the number of readings, add one to k, re-determine i and j randomly, and then return to step S801;
  • Step S811 determine the test result.
  • steps S801 to S804 are the test flow of a single attack test
  • steps S801 to S806 are the test flow of a single refresh cycle
  • steps S801 to S808 are the test flow of a single repository
  • steps S800 to S811 are Test flow for a single memory.
  • the embodiments of the present disclosure can be implemented based on an EFI (Extensible Firmware Interface, Extensible Firmware Interface) environment, so as to bypass address addressing defects and memory fragmentation defects existing in an OS (Operating System, operating system) environment.
  • EFI Extensible Firmware Interface
  • the EFI environment is an upgrade scheme introduced by Intel to replace the BIOS (Basic Input Output System) in future PC-like computer systems.
  • EFI is conceptually similar to a low-level operating system, an interface specification between hardware and pre-boot software, with the ability to manipulate all hardware resources.
  • the EFI environment does not provide complex memory protection functions. It only has a simple memory management mechanism. Specifically, it means running in the segment protection mode of the x86 processor and dividing the memory into a flat segment limited by the maximum addressing capability. , all programs have permission to access any location, and do not provide real protection services.
  • the system can open a command interpretation environment similar to the operating system Shell, where the user can call in to execute any EFI application.
  • the method provided by the embodiments of the present disclosure can be implemented in the form of an EFI application program to directly test the memory.
  • FIG. 9 is a schematic diagram of an implementation environment of an embodiment of the present disclosure.
  • the attack test application 91 is set on the EFI environment 92, and the EFI environment 92 is based on the CPU 93 and is provided with a BIOS function.
  • the CPU 93 is connected to the DRAM 94 , and the DRAM 94 includes a plurality of memory banks 941 .
  • the attack test application 91 executes the method shown in FIG. 1 to read the rows in the memory bank 941 to test the ability of the DRAM 94 to resist attacks.
  • the embodiments of the present disclosure can effectively improve the attack intensity of attacking the DRAM by using the line hammer effect by determining various attack schemes according to the parameters of the DRAM, and make the test result of the DRAM attack resistance ability test more accurate.
  • the memory testing method by determining the attack scheme according to the characteristic value of the memory itself, it is possible to perform the attack test on the memory at an attack frequency higher than the designed attack resistance capability of the memory, so as to effectively verify whether the memory has the capacity to meet the nominal value. Frequency of hammer effect attack resistance.

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Abstract

一种存储器测试方法，所述方法包括：确定目标存储库的刷新周期T、设计抵御攻击频率F以及单行读取时间t（S1）；根据刷新周期T、设计抵御攻击频率F以及单行读取时间t确定攻击行数N（S2）；根据所述攻击行数N的值在目标存储库中确定一组目标攻击行，所述一组目标攻击行包括N个目标攻击行，所述N个目标攻击行中的至少两个目标攻击行之间间隔一行（S3）；连续X次读取所述N个目标攻击行后，检测所述目标攻击行的全部相邻行是否发生数据异常以完成一次攻击测试（S4）；在M个所述刷新周期内对所述目标存储库完成MT/NXt次所述攻击测试，在所述攻击测试均未发生数据异常时，判断所述目标存储库抵御攻击能力达标（S5）。

Description

存储器测试方法
本公开要求在2020年10月16日提交中国专利局、申请号为202011111033.5、发明名称为“存储器测试方法”的中国专利申请的优先权，其全部内容通过引用结合在本公开中。
技术领域
本公开涉及但不限于一种存储器测试方法。
背景技术
行锤效应是指在DRAM的一个刷新周期中如果一行存储单元在短时间内被多次读取，其物理相连的相邻行的存储单元会出现位翻转(BitFlip)现象，导致数据异常。黑客常常利用存储器的行锤效应做攻击，为了防止攻击产生的行锤效应，存储器生产厂商通常通过监控程序判断存储器是否遭受攻击，进而在判断遭受攻击时激活主动刷新，避免出现行锤效应。
为了测试存储器的保护程序是否足够强壮，需要使用攻击测试程序对存储器进行攻击测试。由于不同存储器设置的保护程序不同，相关技术中测试存储器抵御攻击能力的方法能够突破的存储器设置的保护程序较少，导致攻击测试的成功率很高。这种情况下通过测试的存储器实际上可能无法抵抗较为灵活的攻击策略，无法保证能够面对绝大部分改进后的攻击场景，即可靠性验证不足。
需要说明的是，在上述背景技术部分公开的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。
发明内容
以下是对本公开详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本公开的目的在于提供一种存储器测试方法，用于至少在一定程度上克 服由于相关技术的限制和缺陷而导致的无法有效验证DRAM抵抗行锤效应攻击的能力的问题。
根据本公开实施例的第一方面，提供一种存储器测试方法，包括：确定目标存储库的刷新周期T、设计抵御攻击频率F以及单行读取时间t；根据刷新周期T、设计抵御攻击频率F以及单行读取时间t确定攻击行数N；根据所述攻击行数N的值在目标存储库中确定一组目标攻击行，所述一组目标攻击行包括N个目标攻击行，所述N个目标攻击行中的至少两个目标攻击行之间间隔一行；连续X次读取所述N个目标攻击行后，检测所述目标攻击行的全部相邻行是否发生数据异常以完成一次攻击测试；在M个所述刷新周期内对所述目标存储库完成MT/NXt次所述攻击测试，在所述攻击测试均未发生数据异常时，判断所述目标存储库抵御攻击能力达标。
本公开实施例通过根据存储器自身特征数值确定攻击方案，可以实现以高于存储器设计抵御攻击能力的攻击频率对存储器进行攻击测试，从而可以有效验证存储器是否具有符合标称频率的行锤效应攻击抵抗能力。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
并入到说明书中并且构成说明书的一部分的附图示出了本申请的实施例，并且与描述一起用于解释本公开实施例的原理。在这些附图中，类似的附图标记用于表示类似的要素。下面描述中的附图是本公开的一些实施例，而不是全部实施例。对于本领域技术人员来讲，在不付出创造性劳动的前提下，可以根据这些附图获得其他的附图。
一个或多个实施例通过与之对应的附图中的图片进行示例性说明，这些示例性说明并不构成对实施例的限定，附图中具有相同参考数字标号的元件表示为类似的元件，除非有特别申明，附图中的图不构成比例限制。
图1是本公开示例性实施例中存储器测试方法的流程图。
图2是本公开一个实施例中一组目标攻击行的示意图。
图3是本公开另一个实施例中一组目标攻击行的示意图。
图4是本公开再一个实施例中一组目标攻击行的示意图。
图5是本公开再一个实施例中一组目标攻击行的示意图。
图6是图2所示实施例中对待测存储器进行测试的流程图。
图7是图3所示实施例中对待测存储器进行测试的流程图。
图8是图4或图5所示实施例中对待测存储器进行测试的流程图。
图9是本公开实施例的实现环境的一个示意图。
具体实施方式
现在将参考附图更全面地描述示例实施方式。然而，示例实施方式能够以多种形式实施，且不应被理解为限于在此阐述的范例；相反，提供这些实施方式使得本公开将更加全面和完整，并将示例实施方式的构思全面地传达给本领域的技术人员。所描述的特征、结构或特性可以以任何合适的方式结合在一个或更多实施方式中。在下面的描述中，提供许多具体细节从而给出对本公开的实施方式的充分理解。然而，本领域技术人员将意识到，可以实践本公开的技术方案而省略所述特定细节中的一个或更多，或者可以采用其它的方法、组元、装置、步骤等。在其它情况下，不详细示出或描述公知技术方案以避免喧宾夺主而使得本公开的各方面变得模糊。
此外，附图仅为本公开的示意性图解，图中相同的附图标记表示相同或类似的部分，因而将省略对它们的重复描述。附图中所示的一些方框图是功能实体，不一定必须与物理或逻辑上独立的实体相对应。可以采用软件形式来实现这些功能实体，或在一个或多个硬件模块或集成电路中实现这些功能实体，或在不同网络和/或处理器装置和/或微控制器装置中实现这些功能实体。
下面结合附图对本公开示例实施方式进行详细说明。
图1示意性示出本公开示例性实施例中存储器测试方法的流程图。
参考图1，存储器测试方法100可以包括：
步骤S1，确定目标存储库的刷新周期T、设计抵御攻击频率F以及单行读取时间t；
步骤S2，根据刷新周期T、设计抵御攻击频率F以及单行读取时间t确定攻击行数N；
步骤S3，根据所述攻击行数N的值在目标存储库中确定一组目标攻击行，所述一组目标攻击行包括N个目标攻击行，所述N个目标攻击行中的至少两个目标攻击行之间间隔一行；
步骤S4，连续X次读取所述N个目标攻击行后，检测所述目标攻击行的全部相邻行是否发生数据异常以完成一次攻击测试；
步骤S5，在M个所述刷新周期内对所述目标存储库完成MT/NXt次所述攻击测试，在所述攻击测试均未发生数据异常时，判断所述目标存储库抵御攻击能力达标。
本公开实施例通过根据存储器自身特征数值确定攻击方案，可以实现以高于存储器设计抵御攻击能力的攻击频率测试存储器，从而可以有效验证存储器是否具有符合标称频率的行锤效应攻击抵抗能力。
下面，对存储器测试方法100的各步骤进行详细说明。
在本公开实施例中，对待测存储器的各存储库进行逐一测试。步骤S1～步骤S5是对一个存储库进行测试的步骤，对待测存储器的每个存储库进行如步骤S1～步骤S5的操作，即可完成对待测存储器的测试。
在步骤S1，确定目标存储库的刷新周期T、设计抵御攻击频率F以及单行读取时间t。
一般而言，存储器的设定刷新周期为64ms。在两次刷新之间，在不被操作的情况下，一行存储单元的状态几乎不自主改变(会存在少量漏电现象)。如果在短时间内对目标行的两个相邻行(上一行和下一行)进行读取，则该目标行的存储单元存在一定概率出现位翻转现象(Bit Flip)，此时称该目标行产生行锤效应(Row Hammer)。
为了防止非法程序在短时间内迅速读取存储器的相近多行，利用行锤效应使存储器中的一行或多行存储单元出现位翻转，存储器在设计时，通常采取保护机制，即在检测到两次刷新之间存储器被读取次数(即读取频率)超过预设值时，触发主动刷新以使可能出现位翻转的存储单元迅速还原，抵御攻击。存储器自身程序设计能够抵御的攻击频率不同，因此对于不同的存储器，在测试其抵御攻击能力之前需要获取其设计抵御攻击频率F，以便确立攻击频率大于F的攻击方案，有效验证存储器抵御攻击的能力。在一些实施例中，存储器的设计抵御攻击频率F为200k次或50k次。
此外，不同种类存储器的单行读取时间不同，即攻击耗时不同，为了计算出在刷新周期内攻击频率大于F的攻击方案，还需要获取该存储器的单行读取时间。在一个实施例中，存储器的单行读取时间为85ns。
在步骤S2，根据刷新周期T、设计抵御攻击频率F以及单行读取时间t确定攻击行数N。
为了在刷新周期内实现频率大于F的攻击方案，首先需要确定每次攻击能够读取的行数。在一个实施例中，可以根据以下公式确定攻击行数N：
N＝[T/Ft]           (1)
公式(1)的含义是对T/Ft的结果进行取整。
例如，当T＝64ms，F＝200k次，t＝85ns时，为了在64ms内完成超过200k次的攻击测试，每次攻击测试的允许时间为T/F＝64ms/200k＝320ns，在这个允许时间内最多能够读取320/85≈3.76行，由于只能读取整数行，对该结果取整，即可得到N＝3，即对于该存储器，每次攻击测试最多能够完整读取3行。
同理，当T＝64ms，F＝50k次，t＝85ns时，为了在64ms内完成超过50k次的攻击测试，每次攻击测试的允许时间为T/F＝64ms/50k＝1280ns，在这个允许时间内最多能够读取1280/85≈15.1行，由于只能读取整数行，对该结果取整，即可得到N＝15，即对于该存储器，每次攻击测试最多能够完整读取15行。
每次攻击的行数越多，越能够增加破坏DRAM防御机制的概率，即攻击强度较大，因此，在本公开的一些实施例中，可以直接使用公式(1)确定的N值设计攻击方案，以实现一次攻击操作能够读取的目标攻击行的数量的最大化，进而实现攻击能力最大化。
在步骤S3，根据所述攻击行数N的值在目标存储库中确定一组目标攻击行，所述一组目标攻击行包括N个目标攻击行，所述N个目标攻击行中的至少两个目标攻击行之间间隔一行。
DRAM的保护机制一般是概率性的采样保护，如果仅攻击某一行，被DRAM保护机制发现的概率会较高，导致攻击难度低，无法有效测试出DRAM的真实抵御攻击能力。因此，本公开实施例设置N个目标攻击行，并使用多种方式设置N个目标攻击行的排布，以形成多种攻击方案，全方位地 测试DRAM的抵御攻击能力。
在每个攻击方案中，为了尽快诱导至少一个存储单元产生位翻转，本公开实施例设置目标攻击行中的至少两个目标攻击行之间间隔一行，以诱导这两个目标攻击行中间的行出现行锤效应。
根据每次攻击最多能够读取的攻击行数N来确定攻击方案。在攻击行数较少，即测试频率较高时，可以采用的攻击方案较少，为了尽可能增加攻破存储器自身防御方案的能力，可以设置固定攻击行，即在每次攻击测试中，均攻击(读取)若干相同行，以增加该固定攻击行的相邻行出现行锤效应的可能。在攻击行数较多，即测试频率相对较低时，在单次攻击测试中攻击次数较多，此时可以使用多次随机读取或循环读取方案诱导存储器出现行锤效应。
图2是本公开一个实施例中一组目标攻击行的示意图。
参考图2，在攻击行数N小于预设值时，目标存储库对应的第i组目标攻击行包括n个固定攻击行和m个移动攻击行，N＝m+n；其中，n个固定攻击行的行号为随机确定，固定攻击行的行号在目标存储库对应的每组目标攻击行中均相同；m个移动攻击行之间均间隔一行，第i组目标攻击行中m个移动攻击行的最小行号为x-1+i，x为第1组目标攻击行中m个移动攻击行的最小行号，x为随机确定。
图2所示实施例中，T＝64ms，F＝200k次，t＝85ns，N＝3，n＝1，m＝2，预设值例如可以为3～15之间的任意整数。固定攻击行21的行号为随机确定。由于两个移动攻击行22之间间隔一行，仅需确定行号最小的移动攻击行22的行号即可。移动攻击行22的行号也可以为随机确定。
为了尽可能增强攻击效果，提高目标攻击行的相邻行出现行锤效应的概率，可以设置固定攻击行21的行号和移动攻击行22的行号差值较小，例如为4。
图3是本公开另一个实施例中一组目标攻击行的示意图。
参考图3，在另一个实施例中，在攻击行数N小于预设值时，目标存储库对应的第i组目标攻击行包括n个固定攻击行和m个移动攻击行，N＝m+n；其中，n个固定攻击行之间均间隔一行，n个固定攻击行对应的最小行号为随机确定，n个固定攻击行的行号在目标存储库对应的每组目标攻 击行中均相同；m个移动攻击行的行号均为随机确定，m个移动攻击行的行号在目标存储库对应的每组目标攻击行中不完全相同。
在图3所示实施例中，T＝64ms，F＝200k次，t＝85ns，N＝3，n＝2，m＝1，预设值例如可以为3～15之间的任意整数。由于两个固定攻击行31之间间隔一行，仅需确定行号最小的固定攻击行31的行号即可，在一个实施例中，固定攻击行31的行号为随机确定。移动攻击行32的行号也可以为随机确定。为了尽可能增强攻击效果，提高目标攻击行的相邻行出现行锤效应的概率，可以设置行号最小的固定攻击行31的行号和移动攻击行32的行号差值较小，例如为6。
图4是本公开再一个实施例中一组目标攻击行的示意图。
参考图4，在攻击行数N大于等于预设值时，目标存储库对应的第i组目标攻击行包括N个移动攻击行41，每个移动攻击行与至少一个其他移动攻击行之间间隔一行，第i组目标攻击行中N个移动攻击行的最小行号为x-1+i，x为第1组目标攻击行中N个移动攻击行的最小行号，x为随机确定。
图4所示实施例中，T＝64ms，F＝50k次，t＝85ns，N＝15(未完全示出)，预设值例如可以为3～15之间的任意整数。由于单次攻击测试中可以利用的攻击行数较多，正常读取即能够实现攻击目的，但是为了提高目标攻击行的相邻行出现行锤效应的概率，可以设置每个移动攻击行至少与一个其他攻击行之间间隔一行，如图4所示。由于各移动攻击行之间的相对位置关系确定，因此在确定一组移动攻击行时，仅需确定行号最小的移动攻击行的行号，即可确定全组移动攻击行的行号。在一个实施例中，行号最小的移动攻击行的行号可以为随机确定。
当攻击行数N较大时，可选择的攻击方案更多。在一个实施例中，可以在N大于等于预设值时，响应来自于用户的攻击行数修改指令，更新攻击行数N的值。即，可以将计算出的攻击行数N推荐给用户，当用户想要增加攻击频率的时候，可以在攻击行数N的基础上减小，通过输入较小的更新后的N值，实现攻击频率的增加。但是，由于本公开中攻击行数N的值是根据满足攻击条件(攻击频率不小于待测存储器的设计抵御攻击频率)的最低要求来计算的，如果用户增加N的值，则无法实现攻击频率大于等于设计抵御攻击频率的攻击，因此，在这种情况下，仅允许用户减小N值以增加攻击频 率，不允许用户增加N值降低攻击频率。
图5是本公开再一个实施例中一组目标攻击行的示意图。
参考图5，在攻击行数N大于等于预设值时，目标存储库对应的第i组目标攻击行包括N个移动攻击行51，此时可以设置在N个移动攻击行中，每两个移动攻击行之间间隔一行。相比于图4所示实施例，图5所示实施例中移动攻击行的位置设置更紧凑，更容易诱导各移动攻击行之间的行出现行锤效应。
在步骤S4，连续X次读取所述N个目标攻击行后，检测所述目标攻击行的全部相邻行是否发生数据异常以完成一次攻击测试。
确定一组目标攻击行的组成形式后，在多次攻击测试中，可以对相同形式、行号变化的移动攻击行进行读取。
例如，对于图2所示实施例，如果确定在一个刷新周期内完成i次攻击测试，则可以将第1次攻击测试对应的第1组目标攻击行中的固定攻击行的行号随机确定为z1，移动攻击行的最小行号随机确定为x，连续读取X次该第1组目标攻击行，检测这些目标攻击行的全部相邻行是否发生数据异常以完成一次攻击测试。进行第2次攻击测试时，第2组目标攻击行的形式与第1组相同，固定攻击行的行号仍旧为z1，移动攻击行的最小行号为x+1；进行第3次攻击测试时，第3组目标攻击行中的固定攻击行的行号仍旧为z1，移动攻击行的最小行号为x+2。以此类推，进行第i次攻击测试时，第i组目标攻击行中的固定攻击行的行号仍旧为z，移动攻击行的最小行号为x-1+i。
在第二个刷新周期内进行测试时，可以重新确定目标攻击行的行号，以提供更丰富的攻击方案。例如，在图2所示实施例中，可以在第二个刷新周期内设置第1次攻击测试对应的固定攻击行的行号为z2，移动攻击行的最小行号为y。按照上述逻辑，在第二个刷新周期内，进行第i次攻击测试时，固定攻击行的行号仍旧为z2，移动攻击行的最小行号为y-1+i。
同理，对于图3所示实施例，在一个刷新周期内，可以在进行第1次攻击测试时，将第1组目标攻击行的固定攻击行的最小行号随机设置为z1，将移动攻击行的行号随机设置为x，从而在同一刷新周期内的第i次攻击测试中，第i组目标攻击行中固定攻击行的最小行号仍旧为z1，移动攻击行的行号为x-1+i。在第二个刷新周期内，第1组攻击测试对应的第1组目标攻击行 中固定攻击行的最小行号被随机设置为z2，移动攻击行的行号被随机确定为y；第i组攻击测试对应的第1组目标攻击行中固定攻击行的最小行号仍旧为z2，移动攻击行的行号变更为y-1+i。
对于图4和图5所示实施例，在移动攻击行之间的间距确定的情况下，一个刷新周期内的第1组测试对应的移动攻击行的最小行号为x，第i组测试对应的移动攻击行的最小行号为x-1+i。第二个刷新周期内，重新随机确定移动攻击行的最小行号。图4和图5所示实施例适用于长时间的纯随机测试。
通过在刷新周期内变更移动攻击行的行号、在刷新周期之间变更全部目标攻击行的行号，可以对每一种攻击方案进行充分的测试，并设置更丰富的攻击方案。
在步骤S4，每次攻击测试不但包括正常攻击(读取)的时间，还包括验证相邻行是否出现行锤效应的时间。为了增加攻击频率，需要尽量减少验证行锤效应占用的时间，即减少验证的相邻行；为了提高验证准确率，需要尽量增加验证行锤效应占用的时间。因此，一次攻击测试需要验证的相邻行的行数可以由本领域技术人员根据实际情况自行设置。
在图2所示实施例中，N＝3时，则设置验证的相邻行的行数为1，被验证的相邻行是两个移动攻击行之间的行。在图3所示实施例中，N＝3时，则设置被验证的相邻行是两个固定攻击行之间的行。由于在图2和图3所示实施例中，N＝3，施加200k次攻击操作，满足测试需求的单纯攻击时间是3*85ns*200k＝51ms，由于一个刷新周期为64ms，可以利用中间多出的13ms设置更多次的攻击操作，以及设置每次验证相邻行的数量和验证相邻行操作的次数(即设置X的值)。
在图4或图5所示实施例中，可以根据N的值设置一个刷新周期内攻击测试的数量、每次攻击测试对应的X值和验证的相邻行的数量。例如，当N＝15，设计抵御攻击频率为50k次时，满足测试需求的单纯攻击时间是15*85ns*50k＝63.75ms，由于一个刷新周期为64ms，一个刷新周期内有250us可供验证相邻行，即能验证250000/85≈2941个相邻行。如果一次验证相邻行操作(即一次攻击测试的结尾)需要验证14个相邻行(每两个目标攻击行之间的行的总数)，则该攻击方案中，最多可以在一个刷新周期内设置 2941/14≈210次攻击测试。
以上确定X值、每次攻击测试验证的相邻行的数量的方案仅为示例，本领域技术人员可以根据实际情况自行设置。
在步骤S5，在M个所述刷新周期内对所述目标存储库完成MT/NXt次所述攻击测试，在所述攻击测试均未发生数据异常时，判断所述目标存储库抵御攻击能力达标。
由上述分析可知，一次攻击测试为X次读取N个目标攻击行，则一次攻击测试的测试时间至少为NXt，该测试时间不包括验证相邻行是否出现行锤效应的时间。即，在一个刷新周期T内，可以最多进行T/NXt次攻击测试。如果对目标存储库进行M个刷新周期的测试，则对目标存储库施加的攻击测试的次数为MT/NXt次。
对目标存储库进行M个刷新周期的攻击测试后，如果每次攻击测试均未发现数据异常，则可以判断目标存储库抵御攻击能力达标。如果有一次攻击测试发现数据异常，则可以停止后续攻击测试，直接判断目标存储库抵御攻击能力不达标；或者，如果在MT/NXt次刷新测试中有至少预设值次(例如3次)出现数据异常，判断目标存储库抵御攻击能力不达标。
测试一个目标存储库后，继续测试待测存储器的其他存储库，直至完成对待测存储器中全部存储库的测试。
图6是图2所示实施例中对待测存储器进行测试的流程图。
在图6所示实施例中，测试流程可以包括：
步骤S600，设置目标存储库序号z＝0，根据步骤S1～步骤S3随机确定固定攻击行的行号i和移动攻击行的最小行号j；
步骤S601，读取存储库k的第i行；
步骤S602，读取存储库k的第j行；
步骤S603，读取存储库k的第j+2行；
步骤S604，判断本轮读取的序号即读取次数是否达到X，如果否，进入步骤S605，如果是，进入步骤S606；
步骤S605，将读取次数加一返回步骤S601；
步骤S606，读取存储库k的第j+1行以验证是否出现行锤效应；
步骤S607，判断是否达到单周期预设攻击测试次数，如果否，进入步骤 S608，如果是，进入步骤S609；
步骤S608，对攻击次数加一、将读取次数清零、对j加一后返回步骤S601；
步骤S609，判断测试周期数是否达到M，如果否，进入步骤S610，如果是，进入步骤S611；
步骤S610，对测试周期数、i、j均加一，对攻击测试次数和读取次数清零后返回步骤S601；
步骤S611，判断k是否为待测存储器中存储库的最大序号，如果否，进入步骤S612，如果是，进入步骤S613；
步骤S612，清零测试周期数、攻击测试次数、读取次数，将k加一，重新随机确定i和j后返回步骤S601；
步骤S613，确定测试结果。
在图6所示实施例中，步骤S601～S606是单个攻击测试的测试流程，步骤S601～S608是单个刷新周期的测试流程，步骤S601～S610是单个存储库的测试流程，步骤S600～S613是单个存储器的测试流程。
图7是图3所示实施例中对待测存储器进行测试的流程图。
在图7所示实施例中，测试流程可以包括：
步骤S700，设置目标存储库序号z＝0，根据步骤S1～步骤S3随机确定固定攻击行的行号i和移动攻击行的最小行号j；
步骤S701，读取存储库k的第i行；
步骤S702，读取存储库k的第i+2行；
步骤S703，读取存储库k的第j行；
步骤S704，判断本轮读取的序号即读取次数是否达到X，如果否，进入步骤S705，如果是，进入步骤S707；
步骤S705，将读取次数加一返回步骤S701；
步骤S706，读取存储库k的第i+1行以验证是否出现行锤效应；
步骤S707，判断是否达到单周期预设攻击测试次数，如果否，进入步骤S708，如果是，进入步骤S709；
步骤S708，对攻击次数加一、将读取次数清零、对j加一后返回步骤S701；
步骤S709，判断测试周期数是否达到M，如果否，进入步骤S710，如果是，进入步骤S711；
步骤S710，对测试周期数、i、j均加一，对攻击测试次数和读取次数清零后返回步骤S701；
步骤S711，判断k是否为待测存储器中存储库的最大序号，如果否，进入步骤S712，如果是，进入步骤S713；
步骤S712，清零测试周期数、攻击测试次数、读取次数，将k加一，重新随机确定i和j后返回步骤S701；
步骤S713，确定测试结果。
在图7所示实施例中，步骤S701～S706是单个攻击测试的测试流程，步骤S701～S708是单个刷新周期的测试流程，步骤S701～S710是单个存储库的测试流程，步骤S700～S713是单个存储器的测试流程。
图8是图4或图5所示实施例中对待测存储器进行测试的流程图。
在图8所示实施例中，测试流程可以包括：
步骤S800，设置目标存储库序号z＝0，根据步骤S1～步骤S3随机确定固定攻击行的行号i和移动攻击行的最小行号j；
步骤S801，顺次读取存储库k中的N个目标攻击行，目标攻击行的最小行号为i；
步骤S802，判断本轮读取的序号即读取次数是否达到X，如果否，进入步骤S803，如果是，进入步骤S804；
步骤S803，将读取次数加一返回步骤S801；
步骤S804，读取目标攻击行的相邻行以验证是否出现行锤效应；
步骤S805，判断是否达到单周期预设攻击测试次数，如果否，进入步骤S806，如果是，进入步骤S807；
步骤S806，对攻击次数加一、将读取次数清零、对j加一后返回步骤S801；
步骤S807，判断测试周期数是否达到M，如果否，进入步骤S808，如果是，进入步骤S809；
步骤S808，对测试周期数、i、j均加一，对攻击测试次数和读取次数清零后返回步骤S801；
步骤S809，判断k是否为待测存储器中存储库的最大序号，如果否，进入步骤S810，如果是，进入步骤S811；
步骤S810，清零测试周期数、攻击测试次数、读取次数，将k加一，重新随机确定i和j后返回步骤S801；
步骤S811，确定测试结果。
在图8所示实施例中，步骤S801～S804是单个攻击测试的测试流程，步骤S801～S806是单个刷新周期的测试流程，步骤S801～S808是单个存储库的测试流程，步骤S800～S811是单个存储器的测试流程。
本公开实施例中方法的有效性已经在攻击Intel coffee lake 9th处理器的测试中得到验证，通过使用Cache off(缓存关闭)的访问方式直接访问内存，攻破了coffee lake的存储器保护机制，通过各实施例对应的攻击方案诱导存储器出现了行锤效应。
本公开实施例可以基于EFI(Extensible Firmware Interface，可扩展固件接口)环境实现，以绕过OS(Operating System，操作系统)环境存在的地址寻址缺陷和内存碎片缺陷。EFI环境是英特尔公司推出的一种在未来的类PC电脑系统中替代BIOS(Basic Input Output System，基本输入输出系统)的升级方案。
EFI在概念上类似于一个低阶的操作系统，是硬件和预启动软件间的接口规范，具有操控所有硬件资源的能力。EFI环境不提供复杂的存储器保护功能，它只具备简单的存储器管理机制，具体来说就是指运行在x86处理器的段保护模式下，以最大寻址能力为限把存储器分为一个平坦的段，所有的程序都有权限存取任何一段位置，并不提供真实的保护服务。当EFI所有组件加载完毕时，系统可以开启一个类似于操作系统Shell的命令解释环境，在这里，用户可以调入执行任何EFI应用程序。
本公开实施例提供的方法可以通过EFI应用程序的形式实现，以直接对存储器进行测试。
图9是本公开实施例的实现环境的一个示意图。
参考图9，攻击测试应用程序91设置在EFI环境92上，EFI环境92以CPU93为基础，设置有BIOS功能。CPU93连接DRAM94，DRAM94包括多个存储库941。攻击测试应用程序91执行如图1所示的方法读取存储库941 中的行，实现对DRAM94抵御攻击能力的测试。
本公开实施例提供的方法还可以通过其他方式实现，本公开对此不作特殊限制。
综上所述，本公开实施例通过根据DRAM的参数确定多种攻击方案，可以有效提高利用行锤效应攻击DRAM的攻击强度，使DRAM抵御攻击能力测试的测试结果更为准确。
上述附图仅是根据本公开示例性实施例的方法所包括的处理的示意性说明，而不是限制目的。易于理解，上述附图所示的处理并不表明或限制这些处理的时间顺序。另外，也易于理解，这些处理可以是例如在多个模块中同步或异步执行的。
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本公开的其它实施方案。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和构思由权利要求指出。
最后应说明的是：以上各实施例仅用以说明本公开的技术方案，而非对其限制；尽管参照前述各实施例对本公开进行了详细的说明，本领域技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本公开各实施例技术方案的范围。
工业实用性
本公开实施例所提供的存储器测试方法，通过根据存储器自身特征数值确定攻击方案，可以实现以高于存储器设计抵御攻击能力的攻击频率对存储器进行攻击测试，从而可以有效验证存储器是否具有符合标称频率的行锤效应攻击抵抗能力。

Claims (11)

  1. 一种存储器测试方法，包括：
    确定目标存储库的刷新周期T、设计抵御攻击频率F以及单行读取时间t；
    根据刷新周期T、设计抵御攻击频率F以及单行读取时间t确定攻击行数N；
    根据所述攻击行数N的值在目标存储库中确定一组目标攻击行，所述一组目标攻击行包括N个目标攻击行，所述N个目标攻击行中的至少两个目标攻击行之间间隔一行；
    连续X次读取所述N个目标攻击行后，检测所述目标攻击行的全部相邻行是否发生数据异常以完成一次攻击测试；
    在M个所述刷新周期内对所述目标存储库完成MT/NXt次所述攻击测试，在所述攻击测试均未发生数据异常时，判断所述目标存储库抵御攻击能力达标。
  2. 如权利要求1所述的存储器测试方法，其中，所述根据刷新周期T、设计抵御攻击频率F以及单行读取时间t确定攻击行数N包括：N＝[T/Ft]。
  3. 如权利要求1所述的存储器测试方法，其中，所述根据所述攻击行数N的值在目标存储库中确定一组目标攻击行包括：
    在所述攻击行数N小于预设值时，所述目标存储库对应的第i组目标攻击行包括n个固定攻击行和m个移动攻击行，N＝m+n；
    其中，所述n个固定攻击行的行号为随机确定，所述固定攻击行的行号在所述目标存储库对应的每组目标攻击行中均相同；所述m个移动攻击行之间均间隔一行，第i组目标攻击行中所述m个移动攻击行的最小行号为x-1+i，x为第1组目标攻击行中所述m个移动攻击行的最小行号，x为随机确定。
  4. 如权利要求1所述的存储器测试方法，其中，所述根据所述攻击行数N的值在目标存储库中确定一组目标攻击行包括：
    在所述攻击行数N小于预设值时，所述目标存储库对应的第i组目标攻击行包括n个固定攻击行和m个移动攻击行，N＝m+n；
    其中，所述n个固定攻击行之间均间隔一行，所述n个固定攻击行对应的最小行号为随机确定，所述n个固定攻击行的行号在所述目标存储库对应的每组目标攻击行中均相同；所述m个移动攻击行的行号均为随机确定，所述m个移动攻击行的行号在所述目标存储库对应的每组目标攻击行中不完全相同。
  5. 如权利要求1所述的存储器测试方法，其中，所述根据所述攻击行数N的值在目标存储库中确定一组目标攻击行包括：
    在所述攻击行数N大于等于预设值时，所述目标存储库对应的第i组目标攻击行包括N个移动攻击行，每个所述移动攻击行与至少一个其他移动攻击行之间间隔一行，第i组目标攻击行中所述N个移动攻击行的最小行号为x-1+i，x为第1组目标攻击行中所述N个移动攻击行的最小行号，x为随机确定。
  6. 如权利要求4所述的存储器测试方法，其中，在所述N个移动攻击行中，每两个移动攻击行之间间隔一行。
  7. 如权利要求3所述的存储器测试方法，其中，N＝3，n＝1，m＝2。
  8. 如权利要求4所述的存储器测试方法，其中，N＝3，n＝2，m＝1。
  9. 如权利要求5或6所述的存储器测试方法，其中，N＝15。
  10. 如权利要求5或6所述的存储器测试方法，所述存储器测试方法还包括：
    在所述攻击行数N大于等于所述预设值时，响应来自于用户的攻击行数修改指令更新所述攻击行数N的值。
  11. 如权利要求1所述的存储器测试方法，其中，所述方法基于EFI环境实现。
PCT/CN2021/105582 2020-10-16 2021-07-09 存储器测试方法 Ceased WO2022077971A1 (zh)

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