WO2022068263A1 - 存储器和存储器的测试方法 - Google Patents

存储器和存储器的测试方法 Download PDF

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Publication number
WO2022068263A1
WO2022068263A1 PCT/CN2021/099988 CN2021099988W WO2022068263A1 WO 2022068263 A1 WO2022068263 A1 WO 2022068263A1 CN 2021099988 W CN2021099988 W CN 2021099988W WO 2022068263 A1 WO2022068263 A1 WO 2022068263A1
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Prior art keywords
data
read
write
storage module
module
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English (en)
French (fr)
Inventor
王佳
孙圆圆
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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Priority to US17/409,987 priority Critical patent/US20220100409A1/en
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/38—Response verification devices
    • G11C29/42—Response verification devices using error correcting codes [ECC] or parity check
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the present application relates to the field of semiconductors, and in particular, to a memory and a method for testing the memory.
  • ECC Error checking and correcting
  • an additional storage area needs to be set in the storage area to store the ECC check bit data. Therefore, when testing the storage area of the memory, the storage area storing the ECC check bit data also needs to be tested to prevent Errors also occur in the memory area where the ECC check bit data is stored during the memory manufacturing process.
  • the testing of the storage area used to store valid data that is, the data input from outside the memory
  • the storage area used to store ECC check bit data in the memory are separate, that is, the storage areas of valid data are tested separately.
  • ECC parity bit data storage area the existing test process is complicated and the test efficiency is low.
  • the embodiments of the present application provide a memory and a test method for the memory, so as to efficiently test a storage area used to store valid data and a storage area used to store ECC check bit data in the memory.
  • a memory comprising: a storage module for storing data information, the storage module including a main storage module and a parity bit storage module, the main storage module for storing valid data,
  • the check digit storage module is used to store the check digit data
  • the read-write drive module is connected to the storage module and used to read data information from the storage module, or write data information into the storage module
  • the data processing module is connected to the read-write module.
  • the drive module is connected, and is used for performing error detection and error correction decoding operations on data information output by the read-write drive module, or an encoding operation for error detection and error correction on data information input to the read-write drive module.
  • the memory further includes: a data pad, which interacts with the external controller for the first write valid data and the fourth read valid data; a write data conversion unit, which interacts with the data pad and data processing The modules are connected to serial-to-parallel conversion of the first write valid data, and output the second write valid data to the data processing module; the read data conversion unit is connected to both the data pad and the data processing module, and is used to convert the data The third read valid data output by the processing module is subjected to parallel-serial conversion, and the fourth read valid data is output to the data pad.
  • the data processing module includes: a write encoding unit, connected to both the read/write drive module and the write data conversion unit, and used for performing error detection and error correction on the second write valid data.
  • the writing coding unit outputs the third writing valid data and the first writing parity bit data;
  • the reading decoding unit is connected with the read-write drive module and the read data conversion unit, and is used for the output of the read-write drive module.
  • the second read valid data and the second read check bit data perform error detection and error correction decoding operations, and the read decoding unit outputs the third read valid data.
  • the read/write drive module includes: a write drive unit, configured to enhance the drive capability of the third write valid data and the first write check bit data, and output the fourth write valid data data and the second write parity bit data, and write the fourth write valid data and the second write parity bit data into the main storage module and the parity bit storage module respectively; the read drive unit is used to write the output data from the storage module.
  • the driving capability of the first read valid data and the first read check bit data is enhanced, and the second read valid data and the second read check bit data are output.
  • the memory further includes: a compression reading module, connected to both the reading driving unit and the reading data converting unit, for compressing the data information in the test mode to output compressed data Process data to read data conversion unit.
  • a compression reading module connected to both the reading driving unit and the reading data converting unit, for compressing the data information in the test mode to output compressed data Process data to read data conversion unit.
  • the first write valid data when no error is found in the decoding operation of error detection and correction, the first write valid data is equal to the fourth read valid data; when the decoding operation of error detection and correction finds a one-bit error , the first write effective data is equal to the fourth read effective data; when a multi-bit error is found in the decoding operation of error detection and error correction, the first write effective data is not equal to the fourth read effective data.
  • the read decoding unit when entering the test mode, the read decoding unit is turned off, the compression read module is turned on, and the read drive unit sends the second read valid data and the second read check bit data into the Compression reading module, the compressed data is output to the data pad through the read data conversion unit.
  • the read-write drive module and the data processing module exchange data information through a valid data bus and a check bit bus;
  • the data bus exchanges data information.
  • the valid data bus has a width of 128 bits
  • the parity bus has a width of 8 bits
  • the masked data bus has a width of 8 bits.
  • the memory further includes: a test case register, which is used for storing test data and is connected to the writing driving unit.
  • test case register and the read-write driver module perform data information interaction through a valid data bus and a parity bus.
  • the valid data bus has a width of 128 bits
  • the parity bus has a width of 8 bits.
  • the test data before entering the test mode, is stored in the test case register; when entering the test mode, the writing coding unit is closed, the test case register is opened, and the test case register outputs the test data , used to test the main storage module and the parity storage module.
  • An embodiment of the present application also provides a method for testing a memory, which is applied to the above-mentioned memory, including: inputting test data into the memory based on a data pad; writing the test data into the main storage module and the parity bit storage module; The retrieval module reads the test data stored in the main storage module and the parity storage module, and outputs the compressed data; judges whether the storage module is in a normal working state based on the compressed data.
  • the embodiment of the present application also provides a method for testing a memory, which is applied to the above-mentioned memory, including: storing test data in a test case register; writing test data output from the test case register into a main storage module and a parity bit storage module; The test data stored in the main storage module and the parity bit storage module is read by the compression reading module, and the compressed processing data is output; based on the compression processing data, it is judged whether the storage module is in a normal working state.
  • the embodiment of the present application has the following advantages: in the test mode, the data reading channel of the memory is closed, and the valid data and check bit data stored in the memory are compressed by an additionally set compression processing unit to obtain the compressed data, and It is judged by compressing the processed data whether there is an error in the main storage module and the parity bit storage module of the memory, and by simultaneously testing the storage data and the parity bit data, the efficiency of the memory test is improved; and the test results are obtained by compressing the processed data, The efficiency of memory testing is further mentioned.
  • test data is stored in the test case register, and when the memory is tested, the writing of the main storage module and the parity bit storage module in the memory is completed directly through the test data output by the test case register, which speeds up the writing speed of the test data. Thereby, the test efficiency of the memory is further improved.
  • 1 and 2 are schematic structural diagrams of a memory provided by the first embodiment of the application
  • 3 and 4 are schematic structural diagrams of a memory provided by a second embodiment of the application.
  • FIG. 5 and FIG. 6 are schematic flowcharts of a method for testing a memory according to a third embodiment of the present application.
  • ECC Error checking and correcting
  • an additional storage area needs to be set in the storage area to store the ECC check bit data. Therefore, when testing the storage area of the memory, the storage area storing the ECC check bit data also needs to be tested to prevent Errors also occur in the memory area where the ECC check bit data is stored during the memory manufacturing process.
  • test flow for testing the storage area of valid data and the storage area of ECC check bit data in the memory is complicated, and the test efficiency is low.
  • the first embodiment of the present application provides a memory, including: a storage module for storing data information, the storage module includes a main storage module and a parity bit storage module, the main storage module is used for storing valid data, The check digit storage module is used to store the check digit data; the read-write drive module is connected to the storage module and used to read data information from the storage module, or write data information into the storage module; the data processing module is connected to the read-write module.
  • the drive module is connected, and is used for performing error detection and error correction decoding operations on data information output by the read-write drive module, or an encoding operation for error detection and error correction on data information input to the read-write drive module.
  • FIG. 1 and FIG. 2 are schematic structural diagrams of a memory provided by an embodiment of the application, and the memory of this embodiment will be described in detail below. It should be noted that the purpose of introducing the binary digits of each stored data in this embodiment is to make the technical means of this embodiment clear to those skilled in the art, and does not constitute a limitation to this application.
  • the memory includes:
  • the storage module 102 is used for storing data information, the data information includes: valid data and check digit data, the valid data is the externally input data that needs to be stored in the storage module 102; acquired data.
  • the storage module 102 includes: a main storage module and a parity bit storage module 220 .
  • the main storage module is used to store valid data
  • the check digit storage module 220 is used to store the check digit data.
  • the main storage modules include: main storage module 1 (201), main storage module 2 (202), main storage module 3 (203), main storage module 4 (204), main storage module 5 (205) ...the main storage module 15 (215) and the main storage module 16 (216); it should be noted that this embodiment takes 16 main storage modules as an example to introduce the storage module 102 in detail, in order to make it clear to those skilled in the art The technical means of this embodiment do not constitute a limitation to the present application.
  • the memory further includes: a data pad 101 and a read-write data conversion module 105 .
  • the read-write data conversion module 105 includes a write data conversion unit 501 and a read data conversion unit 502 .
  • the data pad 101 communicates with the external controller the first write valid data WDATA1 ⁇ 127:0> and the first write mask data WDM1 ⁇ 7 corresponding to the first write valid data WDATA1 ⁇ 127:0> transmitted through the masked data bus :0>, and the fourth read valid data RDATA4 ⁇ 127:0>, and the second read mask data RDM2 ⁇ 7:0> corresponding to the fourth read valid data RDATA4 ⁇ 7:0> transmitted through the masked data bus.
  • WDATA1 ⁇ 127:0> indicates that the first write valid data is a 128-bit binary number
  • WDM1 ⁇ 7:0> is used to characterize whether the first write valid data is valid according to the result; in an example, when WDM1 ⁇ 7:0 When a bit in > is 0, it is used to represent the corresponding 8-bit binary number in WDATA1 ⁇ 127:0> is invalid.
  • RDATA4 ⁇ 127:0> indicates that the fourth read valid data is a 128-bit binary number
  • RDM2 ⁇ 7:0> is used to characterize whether the fourth read valid data is valid according to its result.
  • RDM2 ⁇ 7:0 When a bit in > is 0, it is used to represent the corresponding 8-bit binary number in RDATA4 ⁇ 127:0> is invalid.
  • the data pad 101 is used to obtain the first write valid data WDATA1 ⁇ 127:0> to be stored externally, and output the fourth read valid data RDATA4 ⁇ 127:0> stored in the memory to the outside.
  • the write data conversion unit 501 is connected to the data pad 101 and the data processing module 104, and is used to perform serial-parallel conversion on the first write valid data WDATA1 ⁇ 127:0>, and output the second write valid data WDATA2 ⁇ 127: 0> to the data processing module 104, the second write valid data WDATA2 ⁇ 127:0> is 16 parallel 8-bit binary numbers.
  • the write data conversion unit 501 is configured to convert the serial first write valid data WDATA1 ⁇ 127:0> into a plurality of parallel second write valid data WDATA2 ⁇ 127:0>, so as to improve subsequent data information Efficiency in storage module 102.
  • the write data conversion unit 501 is further configured to perform serial-to-parallel conversion on the first write WDM1 ⁇ 7:0>, and output the second write mask data WDM2 ⁇ 7:0> to the data processing module 104, and the second write mask data WDM2 ⁇ 7:0>
  • the write mask data WDM2 ⁇ 7:0> are eight 1-bit binary numbers in parallel.
  • the read data conversion unit 502 is connected to both the data pad 101 and the data processing module 104, and is used to perform parallel-serial conversion on the third read valid data RDATA3 ⁇ 127:0> output by the data processing module 104, and output the fourth read
  • the valid data RDATA4 ⁇ 127:0> is sent to the data pad 101, and the third read valid data RDATA3 ⁇ 127:0> is 16 parallel 8-bit binary numbers.
  • the read data conversion unit 502 is configured to convert a plurality of parallel third read valid data RDATA3 ⁇ 127:0> into one serial fourth read valid data RDATA4 ⁇ 127:0>, for the memory to output a Completed storage of data, thereby avoiding loss of output data.
  • the read data conversion unit 502 is further configured to perform parallel-serial conversion on the first read mask data RDM1 ⁇ 7:0>, and output the second read mask data RDM2 ⁇ 7:0> to the data processing module 104,
  • the second read mask data RDM2 ⁇ 7:0> is a serial 8-bit binary number.
  • the data processing module 104 is connected to the read-write drive module 103, and is used to perform a decoding operation of detecting and correcting errors on the data information output by the read-write drive module 103, or to perform error detection on the data information input to the read-write drive module 103 Error-correcting encoding operations.
  • the data processing module 104 includes: a writing encoding unit 401 and a reading decoding unit 402 .
  • the writing coding unit 401 is connected with the read-write driving module 103 and the writing data converting unit 501, and is used for performing the coding operation of error detection and error correction on the second write valid data WDATA2 ⁇ 127:0>, and the writing coding unit 401 Output the third write valid data WDATA3 ⁇ 127:0> and the first write parity data WPARITY1 ⁇ 7:0>, the third write valid data WDATA3 ⁇ 127:0> are 16 parallel 8-bit binary numbers, the first Write parity data WPARITY1 ⁇ 7:0> is an 8-bit binary number.
  • the write encoding unit 401 is configured to perform ECC detection on the received second write valid data WDATA2 ⁇ 127:0> to obtain the first write parity bit data WPARITY1 of the second write valid data WDATA2 ⁇ 127:0> ⁇ 7:0>, the second write valid data WDATA2 ⁇ 127:0> after ECC detection is changed to the third write valid data WDATA3 ⁇ 127:0> together with the first write parity data WPARITY1 ⁇ 7:0> It is sent to the read-write driver module 103 .
  • the read decoding unit 402 is connected to the read and write drive module 103 and the read data conversion unit 502, and is used for the second read valid data RDATA2 ⁇ 127:0> and the second read check bit output by the read write drive module 103
  • the data RPARITY2 ⁇ 7:0> performs the decoding operation of error detection and correction, and the read decoding unit 402 outputs the third read valid data RDATA3 ⁇ 127:0>.
  • the read decoding unit 402 is configured to perform ECC detection and decoding on the second read valid data RDATA2 ⁇ 127:0> according to the second read parity data RPARITY2 ⁇ 7:0> to obtain the second read parity data
  • the corresponding third read valid data RDATA3 ⁇ 127:0> is transmitted, and the third read valid data RDATA3 ⁇ 127:0> is transmitted to the read data conversion unit 502, and the second read valid data RDATA2 ⁇ 127:0> is 16 8-bit binary numbers in parallel, and the second read parity bit data RPARITY2 ⁇ 7:0> is one 8-bit binary number.
  • the read-write drive module 103 is connected to the storage module 102 and is used for reading data information from the storage module 102 or writing data information into the storage module 102 .
  • the read/write drive module 103 includes: a read drive unit 302 and a write drive unit 301 .
  • the writing driving unit 301 is used to enhance the driving capability of the third writing valid data WDATA3 ⁇ 127:0> and the first writing parity data WPARITY1 ⁇ 7:0>, and output the fourth writing valid data WDATA4 ⁇ 127: 0> and the second write parity data WPARITY2 ⁇ 7:0>, and respectively write the fourth write valid data WDATA4 ⁇ 127:0> and the second write parity data WPARITY2 ⁇ 7:0> into the main storage module
  • the fourth write valid data WDATA4 ⁇ 127:0> is 16 parallel 8-bit binary numbers
  • the second write check bit data WPARITY2 ⁇ 7:0> is one 8-bit binary number.
  • the write driving unit 301 is used to amplify the third write valid data WDATA3 ⁇ 127:0> and the first write parity data WPARITY1 ⁇ 7:0> to enhance the third write valid data WDATA3 ⁇ 127:0> and the driving ability of the first write parity data WPARITY1 ⁇ 7:0>, used to turn on or off the switch transistor of the corresponding memory cell, and the amplified third write valid data WDATA3 ⁇ 127:0> as the fourth write
  • the valid data WDATA4 ⁇ 127:0> is stored in the main storage module, and the amplified first write parity data WPARITY1 ⁇ 7:0> is stored in the parity bit storage module as the second write parity data WPARITY2 ⁇ 7:0> 220.
  • the read drive unit 302 is used to enhance the drive capability of the first read valid data RDATA1 ⁇ 127:0> and the first read parity data RPARITY1 ⁇ 7:0> output by the storage module 102, and output the second read valid data
  • the data RDATA2 ⁇ 127:0> and the second read parity data RPARITY2 ⁇ 7:0>, the first read parity data RPARITY1 ⁇ 7:0> is the ECC detection of the first read valid data RDATA1 ⁇ 127:0> Data
  • the first read valid data RDATA1 ⁇ 127:0> is 16 8-bit binary numbers in parallel
  • the first read parity data RPARITY1 ⁇ 7:0> is one 8-bit binary number.
  • the read driving unit 302 is configured to amplify the first read valid data RDATA1 ⁇ 127:0> and the first read parity bit RPARITY1 ⁇ 7:0> data to enhance the first read valid data RDATA1 ⁇ 127:0> and the driving capability of the first read parity bit data RPARITY1 ⁇ 7:0>, used to turn on or off the switch transistors of the corresponding memory cells to ensure the first read valid data RDATA1 ⁇ 127:0> and the first read checksum
  • the bit data RPARITY1 ⁇ 7:0> can be read from the storage module 102, the amplified first read valid data RDATA1 ⁇ 127:0> is used as the second read valid data RDATA2 ⁇ 127:0>, and the amplified first read valid data RDATA1 ⁇ 127:0>
  • the read parity data RPARITY1 ⁇ 7:0> is transmitted to the read-write driving module 103 together as the second parity data RPARITY2 ⁇ 7:0>.
  • the data pad 101 exchanges data with the external controller to obtain the first write valid data WDATA1 ⁇ 127:0>
  • the first write valid data WDATA1 ⁇ 127:0> is the externally input data to be stored in the memory; the data pad 101 transfers the acquired first write valid data WDATA1 ⁇ 127:0> to the write data conversion unit 501, and writes
  • the input data conversion unit 501 performs serial-to-parallel conversion on the first write valid data WDATA1 ⁇ 127:0>, so as to convert the serial first write valid data WDATA1 ⁇ 127:0> into a plurality of parallel second write valid data WDATA2 ⁇ 127:0>, and transmits the second write valid data WDATA2 ⁇ 127:0> to the write coding unit 401; the write coding unit 401 performs ECC detection on the second write valid data WDATA2 ⁇ 127:0> to obtain The first write parity data WPARITY1 ⁇ 7:0> of the second
  • the storage module 102 when the memory is in a normal working state and performs a read operation through a data read channel, the storage module 102 stores the first read valid data RDATA1 ⁇ 127:0> and the first read parity bit data RPARITY1 ⁇ 7:0>, the first read parity bit data RPARITY1 ⁇ 7:0> is the ECC detection data of the first read valid data RDATA1 ⁇ 127:0>.
  • the read driving unit 302 is used for amplifying the first read valid data RDATA1 ⁇ 127:0> and the first read parity bit data RPARITY1 ⁇ 7:0>, so as to increase the first read valid data RDATA1 ⁇ 127:0> and the first read parity bit data RPARITY1 ⁇ 7:0>.
  • the driving ability of the read parity data RPARITY1 ⁇ 7:0> ensures that the first read valid data RDATA1 ⁇ 127:0> and the first read parity data RPARITY1 ⁇ 7:0> can be read from the storage module 102,
  • the amplified first read valid data RDATA1 ⁇ 127:0> is used as the second read valid data RDATA2 ⁇ 127:0>
  • the amplified first read parity bit data RPARITY1 ⁇ 7:0> is used as the second read check
  • the bit data RPARITY2 ⁇ 7:0> is transmitted to the read decoding unit 402 together; the read decoding unit 402 performs the second read valid data RDATA2 ⁇ 127:0> according to the second read check bit data RPARITY2 ⁇ 7:0>
  • ECC detects and decodes to obtain the decoded third read valid data RDATA3 ⁇ 127:0> of the second read parity data RPARITY2 ⁇ 7:0>, and transmits the third read valid data RDATA3 ⁇ 127:0>
  • the memory further includes a compression reading module 106, which is connected to both the reading driving unit 302 and the reading data converting unit 502, and is used for compressing the data information in the test mode, so as to output the compressed processing data to the reading data conversion unit 502. Take the data conversion unit 502 .
  • a compression reading module 106 which is connected to both the reading driving unit 302 and the reading data converting unit 502, and is used for compressing the data information in the test mode, so as to output the compressed processing data to the reading data conversion unit 502. Take the data conversion unit 502 .
  • the test mode is to test each storage unit in the storage module 102, by writing a high level to all storage units, and according to the data read from the storage module 102, it is judged whether there is any problem in the storage module 102.
  • Closing the reading and decoding unit 402 means closing the data reading channel of the memory, and correspondingly, opening the compression reading module 106 so that the data is checked by the compression reading module 106 .
  • the purpose of writing a high level to the storage unit is to determine whether each storage unit in the storage module 102 can normally store high-level data.
  • the data processing module 104 converts the serial data on the data pad 101 into parallel data, and then transfers the parallel data allocated Data ⁇ 127:0> to In the read-write drive module 103, the corresponding ECC detection data is allocated to Dm ⁇ 7:0>, and written into the parity storage module 220 of the storage module 102; the read-write drive module 103 receives Data ⁇ 127:0>, Store in sequence in main storage module 1 (201), main storage module 2 (202)...
  • main storage module 15 (215) and main storage module 16 (216), each main storage module stores an 8-bit parallel data , and write Dm ⁇ 7:0> into the parity bit storage module 220; for the read operation, the data processing module 104 compresses the data, obtains the compressed data, and detects whether the storage module 102 is in normal operation through the compressed data. state, and then the parallel compression processing is converted from parallel data to serial data, and then output to the outside through the data pad 101; The data is read sequentially into Data ⁇ 127:0> and Dm ⁇ 7:0>.
  • the reading and decoding unit 402 when entering the test mode, the reading and decoding unit 402 is turned off, the compression reading module 106 is turned on, and a high level is written into each storage unit in the storage module 102, and the reading driving unit 302 will
  • the second read valid data RDATA2 ⁇ 127:0> and the second read parity data RPARITY2 ⁇ 7:0> are sent to the compression reading module 106 as test data TDATA ⁇ 135:0>, and the compression reading module 106 interprets the received
  • the test data TDATA ⁇ 135:0> is compressed to generate compressed data, and the compressed data is output to the data pad 101 through the read data conversion unit 502, thereby realizing the output of the compressed data to the outside.
  • the first write valid data WDATA1 ⁇ 127:0> is equal to the fourth read valid data RDATA4 ⁇ 127:0>; when the decoding operation of error detection and correction finds a one-bit error , the first write valid data WDATA1 ⁇ 127:0> is equal to the fourth read valid data RDATA4 ⁇ 127:0>; when the decoding operation of error detection and correction finds a multi-bit error, the first write valid data WDATA1 ⁇ 127:0> Not equal to the fourth read valid data RDATA4 ⁇ 127:0>.
  • each storage unit in the storage module 102 is used to store one bit of data, and an error of one bit of data indicates that there is a faulty storage capacitor in the storage module 102 .
  • the error detection and error correction operation is used to perform error checking on the read stored data, and when the error data is one-bit data, the error detection and error correction operation is also used to adjust the error data, that is, when the error detection and error correction decoding operation
  • the first write valid data WDATA1 ⁇ 127:0> is equal to the fourth read valid data RDATA4 ⁇ 127:0>
  • the decoding operation of error detection and correction finds a bit error the first write valid data WDATA1 ⁇ 127:0> is equal to the fourth read valid data RDATA4 ⁇ 127:0>; but when the error data is multi-bit data, the error detection and correction operation cannot adjust the error data, that is, when the error detection and error correction decoding operation finds that multiple bits are When an error occurs, the first write valid data WDATA1 ⁇ 127:0> is not equal to the fourth read
  • the read-write driving module 103 and the data processing module 104 exchange data information through the valid data bus and the parity bus.
  • the valid data bus is used to transmit valid data, and the valid data includes the third write valid data WDATA3 ⁇ 127:0> and the second read valid data RDATA2 ⁇ 127:0>;
  • the check bit bus is used to transmit check bit data, check the The bit data includes first write parity data WPARITY1 ⁇ 7:0> and second read parity data RPARITY2 ⁇ 7:0>.
  • the valid data bus has a width of 128 bits and the check bit bus has a width of 8 bits. That is, the valid data bus is used to transmit 128-bit valid data, and the 128-bit valid data is subjected to error detection and correction operations to generate 8-bit parity data, and the parity bus is used to transmit the 8-bit parity data.
  • the valid data bus is used to transmit data of any bit width.
  • the bit width of the valid data bus and the bit width of the check bit bus can be specifically set according to the bit width of the specific transmission data.
  • the read-write driving module 103 and the compression-reading module 106 exchange data information through the valid data bus and the shielded data bus.
  • the valid data bus is used to transmit the second read valid data RDATA2 ⁇ 127:0>
  • the masked data bus is used to transmit the second read parity bit data RPARITY2 ⁇ 7:0>.
  • the shielded data bus is the bus used by the memory during normal operation.
  • the memory designed in this embodiment transmits part of data through the shielded data bus in the test mode, thereby avoiding the introduction of an external bus and improving the stability of the test mode of the memory.
  • the valid data bus is 128 bits wide and the mask data bus is 8 bits wide.
  • the write drive unit 301 combines the 128-bit second read valid data and the 8-bit second read parity bit data to send a 136-bit data to the compression reading module 106. At this time, the 128-bit valid data bus and 8 A bit-masked data bus is used to transfer the 136 bits of data together.
  • the valid data bus is used to transmit data of any bit width.
  • the bit width of the corresponding check bit bus needs to be increased by one bit.
  • the bit width of the masked data bus also needs to be increased by one bit.
  • the bit width of the effective data bus and the bit width of the masked data bus can be specifically set according to the bit width of the specific transmission data.
  • the data reading channel of the memory is closed, and the valid data and check bit data stored in the memory are compressed by the additionally set compression processing unit to obtain the compressed data, and pass the compression processing unit.
  • the compression processing data judges whether the main storage module and the parity bit storage module of the memory have errors, and by simultaneously testing the storage data and the parity bit data, the efficiency of the storage test is improved; and the test results are obtained by compressing the processing data, and further The efficiency of memory testing is mentioned.
  • a logical unit may be a physical unit, a part of a physical unit, or multiple physical units.
  • a composite implementation of the unit in order to highlight the innovative part of the present application, this embodiment does not introduce units that are not closely related to solving the technical problem raised by the present application, but this does not mean that there are no other units in this embodiment.
  • the second embodiment of the present application relates to a memory. Compared with the first embodiment, the second embodiment completes the data writing to the storage module by adding a new test case register, which speeds up the test data writing speed of the memory , thereby improving the test efficiency of the memory.
  • FIG. 3 and FIG. 4 are schematic structural diagrams of a memory provided by an embodiment of the present application.
  • the memory of this embodiment will be described in detail below, and the parts that are the same as or corresponding to the first embodiment will not be described in detail below.
  • the memory also includes:
  • the test case register 107 is used to store test data, and is connected to the write drive unit 301 .
  • Test case refers to the description of the test task for a specific software product, which reflects the test plan, method, technology and strategy. Its content includes test objectives, test environment, input data, test steps, expected results, test scripts, etc., and finally forms a document.
  • test case is used to output test data to indicate that each storage unit of the storage module stores a high level.
  • test case register 107 Before entering the test mode, the test case is stored in the test case register 107; when entering the test mode, the write coding unit is closed, the test case register 107 is opened, and the test case register 107 outputs the test data, which is used for the main storage module and the calibration
  • the verification storage module 220 performs the test.
  • the data processing module 104 when testing the storage module 102, the data processing module 104 turns off the data writing channel of the read-write drive module 103; the test case register 107 outputs test data, and the test data includes Data ⁇ 127:0 > and Dm ⁇ 7:0>; the read-write drive module 103 stores the received Data ⁇ 127:0> in the main storage module 1 (201), the main storage module 2 (202)...the main storage module 15 ( 215) and the main storage module 16 (216), each main storage module stores an 8-bit parallel data, and Dm ⁇ 7:0> is written in the parity bit storage module 220; for read operations, data processing The module 104 performs compression processing on the data, obtains the compressed processing data, detects whether the storage module 102 is in a normal working state through the compressed processing data, and then converts the parallel compression processing from parallel data into serial data, and outputs through the data pad 101 to the outside; the read-write drive module 103 sequentially reads the data in each main storage module and the data in the par
  • the test case is stored in the test case register 107, and the test case is used for outputting test data to indicate that a high level is stored in the main storage module and the parity bit storage module 220;
  • the purpose of writing a high level to a memory cell is to determine whether each memory cell in the memory module can normally store high level data.
  • close the write coding unit that is, close the data writing channel of the memory
  • open the test case register 107 the test case register 107 outputs the pre-stored test data, and completes the verification of the main memory module and the main memory module through the test data.
  • the data of the bit storage module 220 is written, so as to realize the test of the main storage module and the check bit storage module 220 .
  • test case register 107 and the read/write driver module perform data information interaction through the valid data bus and the parity bus.
  • the valid data bus has a width of 128 bits and the check bit bus has a width of 8 bits. That is, the valid data bus is used to transmit 128-bit valid data, and the 128-bit valid data is subjected to error detection and correction operations to generate 8-bit parity data, and the parity bus is used to transmit the 8-bit parity data.
  • the valid data and the parity bit data are saved through the test case.
  • the test case register 107 inputs 128 as valid data to the storage module through the valid data bus based on the test case, and sends the valid data to the storage module through the check bit bus.
  • the input 8 of the storage module is the parity bit data
  • the valid data is stored in the main storage module of the storage module
  • the 8-bit parity bit data is stored in the parity bit storage module 220 of the storage module.
  • the valid data bus is used to transmit data of any bit width.
  • the bit width of the valid data bus and the bit width of the check bit bus can be specifically set according to the bit width of the specific transmission data.
  • the data reading channel of the memory is closed, and the valid data and check bit data stored in the memory are compressed by the additionally set compression processing unit to obtain the compressed data, and pass the compression processing unit.
  • the compression processing data judges whether the main storage module and the parity bit storage module of the memory have errors, and by simultaneously testing the storage data and the parity bit data, the efficiency of the storage test is improved; and the test results are obtained by compressing the processing data, further The efficiency of memory testing is mentioned.
  • the test data is stored in the test case register, and when the memory is tested, the writing of the main storage module and the parity bit storage module in the memory is completed directly through the test data output by the test case register, which speeds up the writing speed of the test data. Thereby, the test efficiency of the memory is further improved.
  • a logical unit may be a physical unit, a part of a physical unit, or multiple physical units.
  • a composite implementation of the unit in order to highlight the innovative part of the present application, this embodiment does not introduce units that are not closely related to solving the technical problem raised by the present application, but this does not mean that there are no other units in this embodiment.
  • the third embodiment of the present application relates to a method for testing a memory.
  • a method for testing a memory includes: inputting test data into the memory based on a data pad; writing the test data into a main storage module and a parity bit storage module; The test data stored in the storage module and the parity storage module is output, and the compressed data is output; based on the compressed data, it is judged whether the storage module is in a normal working state.
  • test method of the memory includes:
  • Step 601 Write data into the storage module of the memory through the data writing channel of the memory.
  • the data pad 101 exchanges data with an external controller to obtain the first write valid data WDATA1 ⁇ 127:0>, the first write valid data WDATA1 ⁇ 127:0> is the externally input data to be stored in the memory.
  • the data pad 101 transmits the acquired first write valid data WDATA1 ⁇ 127:0> to the write data conversion unit 501, and the write data conversion unit 501 performs serial-parallel conversion on the first write valid data WDATA1 ⁇ 127:0>, to convert the serial first write valid data WDATA1 ⁇ 127:0> into a plurality of parallel second write valid data WDATA2 ⁇ 127:0>, and transmit the second write valid data WDATA2 ⁇ 127:0> to the write into the encoding unit 401.
  • the write encoding unit 401 performs ECC detection on the second write valid data WDATA2 ⁇ 127:0> to obtain the first write parity data WPARITY1 ⁇ 7:0> of the second write valid data WDATA2 ⁇ 127:0>, and performs The second write valid data WDATA2 ⁇ 127:0> after the ECC detection is transmitted to the write driving unit 301 as the third write valid data WDATA3 ⁇ 127:0> together with the first write parity data WPARITY1 ⁇ 7:0> .
  • the write driving unit 301 is used to amplify the third write valid data WDATA3 ⁇ 127:0> and the first write check bit data, so as to improve the third write valid data WDATA3 ⁇ 127:0> and the first write check bit data
  • the driving capability of WPARITY1 ⁇ 7:0>, the third write valid data WDATA3 ⁇ 127:0> is amplified and written to the main storage module as the fourth write valid data WDATA4 ⁇ 127:0>, the first write parity data WPARITY1 ⁇ 7:0> is amplified and written into the parity storage module as the second write parity data WPARITY2 ⁇ 7:0>.
  • step 602 close the data reading channel of the memory, and open the compression reading module of the memory; step 603, obtain the compressed processing data based on the compression reading module; step 604, output the compressed processing data to the data welding of the memory plate.
  • the read driving unit 302 sends the second read valid data RDATA2 ⁇ 127:0> and the second read parity data WPARITY2 ⁇ 7:0> as test data TDATA ⁇ 135:0> into compression
  • the reading module 106 the compression reading module 106 performs compression processing on the received test data TDATA ⁇ 135:0>, generates compressed processing data, and outputs the compressed processing data to the data pad 101 through the read data conversion unit 502, thereby Realize that the compressed data is output to the outside.
  • step 105 based on the compressed data, it is determined whether the storage module of the memory is in a normal working state.
  • each storage unit in the storage module 102 is used to store one-bit high-level data, and one-bit data error indicates that there is a faulty storage capacitor in the storage module 102 .
  • the error detection and error correction operation is used to perform error checking on the read stored data 102, and when the error data is one-bit data, the error detection and error correction operation is also used to adjust the error data, that is, when the error detection and error correction is decoded
  • the first write valid data WDATA1 ⁇ 127:0> is equal to the fourth read valid data RDATA4 ⁇ 127:0>
  • the first write valid data WDATA1 ⁇ 127:0> is equal to the fourth read valid data RDATA4 ⁇ 127:0>
  • the error detection and error correction operation cannot adjust the error data, that is, when the error detection and error correction decoding operation finds more When a bit error occurs, the first
  • a method for testing a memory includes: storing test data in a test case register; writing test data output from the test case register into a main storage module and a parity bit storage module; reading the module through compression Read the test data stored in the main storage module and the check bit storage module, and output the compressed data; judge whether the storage module is in a normal working state based on the compressed data.
  • test method of the memory includes:
  • step 701 the data writing channel of the memory is closed, and data is written into the storage module of the memory through the test case register.
  • the test data is stored in the test case register 107 of the memory, the test data is used to test the memory module 102, the test case register 107 is opened, and the test case register 107 outputs the test data to the memory module 102.
  • the test data is stored in the test case register 107, and the test data is used to indicate that a high level is stored in the main storage module and the check bit storage module 220;
  • the purpose of the module 220 writing the high level is to determine whether the storage module 102 can normally store the high level data.
  • close the write coding unit 401 that is, close the data writing channel of the memory, and open the test case register 107
  • the test case register 107 outputs the pre-stored test data, and completes the calibration of the main memory module and the calibration through the test data.
  • the data writing of the storage module 220 is checked, so as to realize the test of the storage module 102 .
  • step 702 closing the data reading channel of the memory, and opening the compression reading module of the memory; step 703, obtaining the compressed processing data based on the compression reading module; step 704, outputting the compressed processing data to the data welding of the memory plate.
  • the read driving unit 302 sends the second read valid data RDATA2 ⁇ 127:0> and the second read parity data WPARITY2 ⁇ 7:0> into compression as test data TDATA ⁇ 135:0>
  • the reading module 106 performs compression processing on the received test data TDATA ⁇ 135:0>, generates compressed processing data, and outputs the compressed processing data to the data pad 101 through the read data conversion unit 502, thereby Realize that the compressed data is output to the outside.
  • step 705 it is determined whether the storage module of the memory is in a normal working state based on the compressed data.
  • each storage unit in the storage module 102 is used to store one-bit high-level data, and one-bit data error indicates that there is a faulty storage capacitor in the storage module 102 .
  • the error detection and error correction operation is used to perform error checking on the read stored data, and when the error data is one-bit data, the error detection and error correction operation is also used to adjust the error data, that is, when the error detection and error correction decoding operation
  • the first write valid data WDATA1 ⁇ 127:0> is equal to the fourth read valid data RDATA4 ⁇ 127:0>
  • the decoding operation of error detection and correction finds a bit error the first write valid data WDATA1 ⁇ 127:0> is equal to the fourth read valid data RDATA4 ⁇ 127:0>; but when the error data is multi-bit data, the error detection and correction operation cannot adjust the error data, that is, when the error detection and error correction decoding operation finds that multiple bits are When an error occurs, the first write valid data WDATA1 ⁇ 127:0
  • the data reading channel of the memory is closed, and the valid data and check bit data stored in the memory are compressed by the additionally set compression processing unit to obtain the compressed data, and the memory is judged by the compressed data.
  • the efficiency of the memory test is improved by simultaneously testing the storage data and the parity bit data; and the efficiency of the memory test is further mentioned by compressing the data to obtain the test results.
  • test data is stored in the test case register 107, and when the memory is tested, the writing of the main storage module and the parity bit storage module in the memory is completed directly through the test data output by the test case register 107, which speeds up the writing of the test data speed, thereby further improving the test efficiency of the memory.
  • first embodiment and the second embodiment correspond to this embodiment, this embodiment can be implemented in cooperation with the first embodiment and the second embodiment.
  • the relevant technical details mentioned in the first embodiment and the second embodiment are still valid in this embodiment, and the technical effects that can be achieved in the first embodiment and the second embodiment can also be realized in this embodiment. , in order to reduce repetition, no further description will be given here.
  • the related technical details mentioned in this embodiment can also be applied to the first embodiment and the second embodiment.

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Abstract

本申请实施例提供一种存储器和存储器的测试方法，其中，存储器包括：存储模块，用于存储数据信息，存储模块包括主存储模块和校验位存储模块，主存储模块用于存储有效数据，校验位存储模块用于存储校验位数据；读写驱动模块，与存储模块连接，用于从存储模块中读取数据信息，或将数据信息写入存储模块；数据处理模块，与读写驱动模块连接，用于对读写驱动模块输出的数据信息进行检错纠错的解码操作，或用于对输入到读写驱动模块的数据信息进行检错纠错的编码操作。

Description

存储器和存储器的测试方法
相关申请的交叉引用
本申请基于申请号为202011058602.4、申请日为2020年09月30日的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本申请作为参考。
技术领域
本申请涉及半导体领域，特别涉及一种存储器和存储器的测试方法。
背景技术
目前对存储器的应用中，通过引入错误检查和纠正技术(Error checking and correcting，ECC)能够检测并纠正存储器的存储数据出现的一比特错误。
引入ECC的存储器中需要在存储区域额外设置一存储区域用于存储ECC校验位数据，因此在对存储器的存储区域进行测试时，存储ECC校验位数据的存储区域也需要进行测试，以防止存储器制造过程中存储ECC校验位数据的存储区域也出现错误。
然而，相关技术中对存储器中用来存储有效数据的存储区域(即存储器外部输入的数据)和用来存储ECC校验位数据的存储区域的测试是分开的，即分别测试有效数据的存储区域和ECC校验位数据的存储区域，现有测试流程复杂，测试效率低。
发明内容
本申请实施例提供一种存储器和存储器的测试方法，实现高效测试存储器中用来存储有效数据的存储区域和用来存储ECC校验位数据的存储区 域。
为解决上述技术问题，本申请的实施例提供了一种存储器，包括：存储模块，用于存储数据信息，存储模块包括主存储模块和校验位存储模块，主存储模块用于存储有效数据，校验位存储模块用于存储校验位数据；读写驱动模块，与存储模块连接，用于从存储模块中读取数据信息，或将数据信息写入存储模块；数据处理模块，与读写驱动模块连接，用于对读写驱动模块输出的数据信息进行检错纠错的解码操作，或用于对输入到读写驱动模块的数据信息进行检错纠错的编码操作。
在本申请的一种可选实施例中，存储器还包括：数据焊盘，与外部控制器交互第一写有效数据和第四读有效数据；写入数据转换单元，与数据焊盘和数据处理模块均连接，用于将第一写有效数据进行串并转换，并输出第二写有效数据至数据处理模块；读取数据转换单元，与数据焊盘和数据处理模块均连接，用于将数据处理模块输出的第三读有效数据进行并串转换，并输出第四读有效数据至数据焊盘。
在本申请的一种可选实施例中，数据处理模块包括：写入编码单元，与读写驱动模块和写入数据转换单元均连接，用于对第二写有效数据执行检错纠错的编码操作，写入编码单元输出第三写有效数据和第一写校验位数据；读取解码单元，与读写驱动模块和读取数据转换单元均连接，用于对读写驱动模块输出的第二读有效数据和第二读校验位数据执行检错纠错的解码操作，读取解码单元输出第三读有效数据。
在本申请的一种可选实施例中，读写驱动模块包括：写入驱动单元，用于将第三写有效数据和第一写校验位数据的驱动能力进行增强，输出第四写有效数据和第二写校验位数据，并分别将第四写有效数据和第二写校验位数据写入主存储模块和校验位存储模块；读取驱动单元，用于将存储模块输出的第一读有效数据和第一读校验位数据的驱动能力进行增强，输 出第二读有效数据和第二读校验位数据。
在本申请的一种可选实施例中，存储器还包括：压缩读取模块，与读取驱动单元和读取数据转换单元均连接，用于在测试模式将数据信息进行压缩处理，以输出压缩处理数据至读取数据转换单元。
在本申请的一种可选实施例中，当检错纠错的解码操作没有发现错误时，第一写有效数据等于第四读有效数据；当检错纠错的解码操作发现一比特错误时，第一写有效数据等于第四读有效数据；当检错纠错的解码操作发现多比特错误时，第一写有效数据不等于第四读有效数据。
在本申请的一种可选实施例中，当进入测试模式时，关闭读取解码单元，开启压缩读取模块，读取驱动单元将第二读有效数据和第二读校验位数据送入压缩读取模块，压缩处理数据经过读取数据转换单元输出到数据焊盘。
在本申请的一种可选实施例中，读写驱动模块与数据处理模块通过有效数据总线和校验位总线进行数据信息的交互；读写驱动模块与压缩读取模块通过有效数据总线和屏蔽数据总线进行数据信息的交互。
在本申请的一种可选实施例中，有效数据总线具有128位宽度，校验位总线具有8位宽度，屏蔽数据总线具有8位宽度。
在本申请的一种可选实施例中，存储器还包括：测试用例寄存器，用于存储测试数据，与写入驱动单元连接。
在本申请的一种可选实施例中，测试用例寄存器与读写驱动模块通过有效数据总线和校验位总线进行数据信息的交互。
在本申请的一种可选实施例中，有效数据总线具有128位宽度，校验位总线具有8位宽度。
在本申请的一种可选实施例中，在进入测试模式之前，将测试数据存入测试用例寄存器；在进入测试模式时，关闭写入编码单元，开启测试用 例寄存器，测试用例寄存器输出测试数据，用于对主存储模块和校验位存储模块进行测试。
本申请实施例还提供了一种存储器的测试方法，应用于上述存储器，包括：基于数据焊盘向存储器中输入测试数据；将测试数据写入主存储模块和校验位存储模块；通过压缩读取模块读取主存储模块和校验位存储模块储存的测试数据，并输出压缩处理数据；基于压缩处理数据判断存储模块是否处于正常工作状态。
本申请实施例还提供了一种存储器的测试方法，应用于上述存储器，包括：将测试数据存入测试用例寄存器；将测试用例寄存器输出的测试数据写入主存储模块和校验位存储模块；通过压缩读取模块读取主存储模块和校验位存储模块储存的测试数据，并输出压缩处理数据；基于压缩处理数据判断存储模块是否处于正常工作状态。
本申请实施例具有以下优点：在测试模式时，关闭存储器的数据读取通道，通过额外设置的压缩处理单元对存储器存储的有效数据和校验位数据进行压缩处理，以获取压缩处理数据，并通过压缩处理数据判断所述存储器的主存储模块和校验位存储模块是否出现错误，通过对存储数据和校验位数据同时测试，提高了存储器测试的效率；且通过压缩处理数据获取测试结果，进一步提到了存储器测试的效率。
另外，通过测试用例寄存器存储测试数据，在存储器进行测试时，直接通过测试用例寄存器输出的测试数据完成对存储器中主存储模块和校验位存储模块的写入，加快了测试数据写入速度，从而进一步提高存储器的测试效率。
附图说明
一个或多个实施例通过与之对应的附图中的图片进行示例性说明，除非有特别申明，附图中的图不构成比例限制。
图1和图2为本申请第一实施例提供的存储器的结构示意图；
图3和图4为本申请第二实施例提供的存储器的结构示意图；
图5和图6为本申请第三实施例提供的存储器的测试方法的流程示意图。
具体实施方式
目前对存储器的应用中，通过引入错误检查和纠正技术(Error checking and correcting，ECC)能够检测并纠正存储器的存储数据出现的一比特错误。
引入ECC的存储器中需要在存储区域额外设置一存储区域用于存储ECC校验位数据，因此在对存储器的存储区域进行测试时，存储ECC校验位数据的存储区域也需要进行测试，以防止存储器制造过程中存储ECC校验位数据的存储区域也出现错误。
然而，用于测试存储器中有效数据的存储区域和ECC校验位数据的存储区域的测试流程复杂，测试效率低。
为解决上述问题，本申请第一实施例提供了一种存储器，包括：存储模块，用于存储数据信息，存储模块包括主存储模块和校验位存储模块，主存储模块用于存储有效数据，校验位存储模块用于存储校验位数据；读写驱动模块，与存储模块连接，用于从存储模块中读取数据信息，或将数据信息写入存储模块；数据处理模块，与读写驱动模块连接，用于对读写驱动模块输出的数据信息进行检错纠错的解码操作，或用于对输入到读写驱动模块的数据信息进行检错纠错的编码操作。
为使本申请实施例的目的、技术方案和优点更加清楚，下面将结合附图对本申请的各实施例进行详细的阐述。然而，本领域的普通技术人员可以理解，在本申请各实施例中，为了使读者更好地理解本申请而提出了许多技术细节。但是，即使没有这些技术细节和基于以下各实施例的种种变化和修改，也可以实现本申请所要求保护的技术方案。以下各个实施例的 划分是为了描述方便，不应对本申请的具体实现方式构成任何限定，各个实施例在不矛盾的前提下可以相互结合，相互引用。
图1和图2为本申请实施例提供的存储器的结构示意图，下面对本实施例的存储器进行具体说明。需要说明的是，本实施例中对各存储数据的二进制位数介绍，目的在于让本领域技术人员清楚本实施例的技术手段，并不构成对本申请的限定。
参考图1和图2，存储器，包括：
存储模块102，用于存储数据信息，数据信息包括：有效数据和校验位数据，有效数据即外部输入的需要存储在存储模块102中的数据；校验位数据即对有效数据进行ECC检测而获取的数据。
具体地，存储模块102包括：主存储模块和校验位存储模块220。主存储模块用于存储有效数据，校验位存储模块220用于存储校验位数据。
在本实施例中，主存储模块包括：主存储模块1(201)、主存储模块2(202)、主存储模块3(203)、主存储模块4(204)、主存储模块5(205)……主存储模块15(215)和主存储模块16(216)；需要说明的是，本实施例以16个主存储模块为例对存储模块102进行详细介绍，目的在于让本领域技术人员清楚本实施例的技术手段，并不构成对本申请的限定。
在本实施例中，存储器还包括：数据焊盘101和读写数据转换模块105，具体地，读写数据转换模块105包括：写入数据转换单元501和读取数据转换单元502。
数据焊盘101，与外部控制器交互第一写有效数据WDATA1<127:0>以及通过屏蔽数据总线传输的对应于第一写有效数据WDATA1<127:0>的第一写屏蔽数据WDM1<7:0>，和第四读有效数据RDATA4<127:0>，以及通过屏蔽数据总线传输的对应于第四读有效数据RDATA4<7:0>的第二读屏蔽数据RDM2<7:0>。
WDATA1<127:0>表征第一写有效数据是一个128位二进制数，WDM1<7:0>根据其结果用于表征第一写有效数据是否有效；在一个例子中，当WDM1<7:0>中某一位为0时，用于表征WDATA1<127:0>中对应的8位二进制数无效。
RDATA4<127:0>表征第四读有效数据是一个128位二进制数，RDM2<7:0>根据其结果用于表征第四读有效数据是否有效，在一个例子中，当RDM2<7:0>中某一位为0时，用于表征RDATA4<127:0>中对应的8位二进制数无效。
具体地，数据焊盘101用于获取外部待存储的第一写有效数据WDATA1<127:0>，以及将存储器存储的第四读有效数据RDATA4<127:0>输出到外部。
写入数据转换单元501，与数据焊盘101和数据处理模块104均连接，用于将第一写有效数据WDATA1<127:0>进行串并转换，并输出第二写有效数据WDATA2<127:0>至数据处理模块104，第二写有效数据WDATA2<127:0>为并行的16个8位二进制数。具体地，写入数据转换单元501用于将串行的第一写有效数据WDATA1<127:0>转换成多个并行的第二写有效数据WDATA2<127:0>，以提高后续将数据信息存入存储模块102的效率。
需要说明的是，写入数据转换单元501还用于将第一写WDM1<7:0>进行串并转换，并输出第二写屏蔽数据WDM2<7:0>至数据处理模块104，第二写屏蔽数据WDM2<7:0>为并行的8个1位二进制数。
读取数据转换单元502，与数据焊盘101和数据处理模块104均连接，用于将数据处理模块104输出的第三读有效数据RDATA3<127:0>进行并串转换，并输出第四读有效数据RDATA4<127:0>至数据焊盘101，第三读有效数据RDATA3<127:0>为并行的16个8位二进制数。
具体地，读取数据转换单元502用于将并行的多个第三读有效数据RDATA3<127:0>转换成一个串行的第四读有效数据RDATA4<127:0>，用于存储器输出一个完成的存储数据，从而避免输出数据的丢失。
需要说明的是，读取数据转换单元502还用于将第一读屏蔽数据RDM1<7:0>进行并串转换，并输出第二读屏蔽数据RDM2<7:0>至数据处理模块104，第二读屏蔽数据RDM2<7:0>为串行的1个8位二进制数。
数据处理模块104，与读写驱动模块103连接，用于对读写驱动模块103输出的数据信息进行检测纠错的解码操作，或用于对输入到读写驱动模块103的数据信息进行检错纠错的编码操作。
在本实施例中，数据处理模块104包括：写入编码单元401和读取解码单元402。
写入编码单元401，与读写驱动模块103和写入数据转换单元501均连接，用于对第二写有效数据WDATA2<127:0>执行检错纠错的编码操作，写入编码单元401输出第三写有效数据WDATA3<127:0>和第一写校验位数据WPARITY1<7:0>，第三写有效数据WDATA3<127:0>为并行的16个8位二进制数，第一写校验位数据WPARITY1<7:0>为1个8位二进制数。
具体地，写入编码单元401用于对接收的第二写有效数据WDATA2<127:0>进行ECC检测，以获取第二写有效数据WDATA2<127:0>的第一写校验位数据WPARITY1<7:0>，经过ECC检测后的第二写有效数据WDATA2<127:0>变更为第三写有效数据WDATA3<127:0>与第一写校验位数据WPARITY1<7:0>一同被传送至读写驱动模块103。
读取解码单元402，与读写驱动模块103和读取数据转换单元502均连接，用于对读写驱动模块103输出的第二读有效数据RDATA2<127:0>和第二读校验位数据RPARITY2<7:0>执行检错纠错的解码操作，读取解码单元402输出第三读有效数据RDATA3<127:0>。
具体地，读取解码单元402用于根据第二读校验位数据RPARITY2<7:0>对第二读有效数据RDATA2<127:0>进行ECC检测解码，以获取第二读校验位数据RPARITY2<7:0>解码后对应的第三读有效数据RDATA3<127:0>，并将第三读有效数据RDATA3<127:0>传输至读取数据转换单元502，第二读有效数据RDATA2<127:0>为并行的16个8位二进制数，第二读校验位数据RPARITY2<7:0>为1个8位二进制数。
读写驱动模块103，与存储模块102连接，用于从存储模块102中读取数据信息，或将数据信息写入存储模块102。
在本实施例中，读写驱动模块103包括：读取驱动单元302和写入驱动单元301。
写入驱动单元301，用于将第三写有效数据WDATA3<127:0>和第一写校验位数据WPARITY1<7:0>的驱动能力进行增强，输出第四写有效数据WDATA4<127:0>和第二写校验位数据WPARITY2<7:0>，并分别将第四写有效数据WDATA4<127:0>和第二写校验位数据WPARITY2<7:0>写入主存储模块和校验位存储模块220，第四写有效数据WDATA4<127:0>为并行的16个8位二进制数，第二写校验位数据WPARITY2<7:0>为1个8位二进制数。
具体地，写入驱动单元301用于放大第三写有效数据WDATA3<127:0>和第一写校验位数据WPARITY1<7:0>，以增强第三写有效数据WDATA3<127:0>和第一写校验位数据WPARITY1<7:0>的驱动能力，用于导通或关断相应存储单元的开关三极管，放大后的第三写有效数据WDATA3<127:0>作为第四写有效数据WDATA4<127:0>存入主存储模块，放大后的第一写校验数据WPARITY1<7:0>作为第二写校验位数据WPARITY2<7:0>存入校验位存储模块220。
读取驱动单元302，用于将存储模块102输出的第一读有效数据 RDATA1<127:0>和第一读校验位数据RPARITY1<7:0>的驱动能力进行增强，输出第二读有效数据RDATA2<127:0>和第二读校验位数据RPARITY2<7:0>，第一读校验位数据RPARITY1<7:0>为第一读有效数据RDATA1<127:0>的ECC检测数据，第一读有效数据RDATA1<127:0>为并行的16个8位二进制数，第一读校验位数据RPARITY1<7:0>为1个8位二进制数。
具体地，读取驱动单元302用于放大第一读有效数据RDATA1<127:0>和第一读校验位RPARITY1<7:0>数据，以增强第一读有效数据RDATA1<127:0>和第一读校验位数据RPARITY1<7:0>的驱动能力，用于导通或关断相应存储单元的开关三极管，保证第一读有效数据RDATA1<127:0>和第一读校验位数据RPARITY1<7:0>可以从存储模块102中读出，放大后的第一读有效数据RDATA1<127:0>作为第二读有效数据RDATA2<127:0>，和放大后的第一读校验位数据RPARITY1<7:0>作为第二校验位数据RPARITY2<7:0>一同被传输至读写驱动模块103。
在一个具体的例子中，当存储器处于正常工作状态下通过数据写入通道进行写入操作时，数据焊盘101与外部控制器进行数据交互，获取第一写有效数据WDATA1<127:0>，第一写有效数据WDATA1<127:0>即外部输入的待存入存储器的数据；数据焊盘101将获取的第一写有效数据WDATA1<127:0>传输至写入数据转换单元501，写入数据转换单元501对第一写有效数据WDATA1<127:0>进行串并转换，以将串行的第一写有效数据WDATA1<127:0>转换成多个并行的第二写有效数据WDATA2<127:0>，并将第二写有效数据WDATA2<127:0>传输至写入编码单元401；写入编码单元401对第二写有效数据WDATA2<127:0>进行ECC检测，以获取第二写有效数据WDATA2<127:0>的第一写校验位数据WPARITY1<7:0>，进行ECC检测后的第二写有效数据WDATA2<127:0>作为第三写有效数据 WDATA3<127:0>与第一写校验位数据WPARITY1<7:0>一同被传输至写入驱动单元301；写入驱动单元301，用于放大第三写有效数据WDATA3<127:0>和第一写校验位数据WPARITY1<7:0>，以提高第三写有效数据WDATA3<127:0>和第一写校验位数据WPARITY1<7:0>的驱动能力，第三写有效数据WDATA3<127:0>放大后作为第四写有效数据WDATA4<127:0>写入主存储模块中，第一写校验位数据WPARITY1<7:0>放大后作为第二写校验位数据WPARITY2<7:0>写入校验位存储模块220。
在另一个具体的例子中，当存储器处于正常工作状态下通过数据读取通道进行读取操作时，存储模块102存储有第一读有效数据RDATA1<127:0>和第一读校验位数据RPARITY1<7:0>，第一读校验位数据RPARITY1<7:0>为第一读有效数据RDATA1<127:0>的ECC检测数据。读取驱动单元302用于放大第一读有效数据RDATA1<127:0>和第一读校验位数据RPARITY1<7:0>，以提高第一读有效数据RDATA1<127:0>和第一读校验位数据RPARITY1<7:0>的驱动能力，保证第一读有效数据RDATA1<127:0>和第一读校验位数据RPARITY1<7:0>可以从存储模块102中读出，放大后的第一读有效数据RDATA1<127:0>作为第二读有效数据RDATA2<127:0>，和放大后的第一读校验位数据RPARITY1<7:0>作为第二读校验位数据RPARITY2<7:0>一同被传输至读取解码单元402；读取解码单元402根据第二读校验位数据RPARITY2<7:0>对第二读有效数据RDATA2<127:0>进行ECC检测解码，以获取第二读校验位数据RPARITY2<7:0>解码后的第三读有效数据RDATA3<127:0>，并将第三读有效数据RDATA3<127:0>传输至读取数据转换单元；读取数据转换单元对第三读有效数据RDATA3<127:0>进行并串转换，已经并行的多个第三读有效数据RDATA3<127:0>转换成一个串行的第四读有效数据RDATA4<127:0>，并将第四读有效数据RDATA4<127:0>传输至数据焊盘101，数据焊盘101 与外部控制器进行数据交互，以输出读取的第四读有效数据RDATA4<127:0>。
在本实施例中，存储器还包括压缩读取模块106，与读取驱动单元302和读取数据转换单元502均连接，用于在测试模式将数据信息进行压缩处理，以输出压缩处理数据至读取数据转换单元502。
测试模式即对存储模块102中的每一个存储单元进行测试，通过向所有的存储单元写入高电平，并根据从存储模块102中读取的数据判断，存储模块102中是否存在有问题的存储单元。关闭读取解码单元402即关闭存储器的数据读取通道，相应的，开启压缩读取模块106，使数据通过压缩读取模块106进行检验。向所述存储单元写入高电平的目的在于判断存储模块102中的每一个存储单元是否能够正常存储高电平数据。
参考图1，对于写操作，对存储模块102进行测试时，数据处理模块104将数据焊盘101上的串行数据转化成并行数据，然后将并行数据分配的Data<127:0>并传输至读写驱动模块103，相应的ECC检测数据分配到Dm<7:0>，写入存储模块102的校验位存储模块220中；读写驱动模块103对接收到的Data<127:0>，依次存储到主存储模块1(201)、主存储模块2(202)……主存储模块15(215)和主存储模块16(216)中，每个主存储模块中存储一个8位的并行数据，并将Dm<7:0>写入校验位存储模块220中；对于读操作，数据处理模块104对数据进行压缩处理，获取压缩处理数据，通过压缩处理数据检测存储模块102是否处于正常工作状态，然后将并行的压缩处理处理由并行数据转换成串行数据后，通过数据焊盘101输出到外部；读写驱动模块103将各个主存储模块中的数据和校验位存储模块220中的数据依次读取到Data<127:0>和Dm<7:0>中。
具体地，参考图2，当进入测试模式时，关闭读取解码单元402，开启压缩读取模块106，向存储模块102中的每一个存储单元中写入高电平，读 取驱动单元302将第二读有效数据RDATA2<127:0>和第二读校验位数据RPARITY2<7:0>作为测试数据TDATA<135:0>送入压缩读取模块106，压缩读取模块106对接收的测试数据TDATA<135:0>进行压缩处理，生成压缩处理数据，并将压缩处理数据经过读取数据转换单元502输出到数据焊盘101，从而实现将压缩处理数据输出到外部。
当检错纠错的解码操作没有发现错误时，第一写有效数据WDATA1<127:0>等于第四读有效数据RDATA4<127:0>；当检错纠错的解码操作发现一比特错误时，第一写有效数据WDATA1<127:0>等于第四读有效数据RDATA4<127:0>；当检错纠错的解码操作发现多比特错误时，第一写有效数据WDATA1<127:0>不等于第四读有效数据RDATA4<127:0>。
具体地，存储模块102中每一个存储单元都用于存储一比特的数据，一比特的数据错误表征存储模块102中存在一个有问题的存储电容。而检错纠错操作用于对读取的存储数据进行错误检验，且当错误数据为一比特的数据时，检错纠错操作还用于调整错误数据，即当检错纠错的解码操作没有发现错误时，第一写有效数据WDATA1<127:0>等于第四读有效数据RDATA4<127:0>，当检错纠错的解码操作发现一比特错误时，第一写有效数据WDATA1<127:0>等于第四读有效数据RDATA4<127:0>；但当错误数据为多比特的数据时，检错纠错操作无法调整错误数据，即当检错纠错的解码操作发现多比特错误时，第一写有效数据WDATA1<127:0>不等于第四读有效数据RDATA4<127:0>。
在本实施例中，读写驱动模块103与数据处理模块104通过有效数据总线和校验位总线进行数据信息的交互。有效数据总线用于传输有效数据，有效数据包括第三写有效数据WDATA3<127:0>和第二读有效数据RDATA2<127:0>；校验位总线用于传输校验位数据，校验位数据包括第一写校验位数据WPARITY1<7:0>和第二读校验位数据RPARITY2<7:0>。
在一个例子中，有效数据总线具有128位宽度，检验位总线具有8位宽度。即有效数据总线用于传输128位的有效数据，而128位的有效数据经过检错纠错操作产生8位的校验位数据，校验位总线用于传输这8位的校验位数据。
需要说明的是，在其他实施例中，有效数据总线用于传输任意位宽的数据，在128位的基础上，有效数据的宽度每增加一倍，相应检验位总线的位宽需要增加一位，有效数据总线的位宽和校验位总线的位宽可以根据具体传输数据的位宽进行具体设置。
在本实施例中，读写驱动模块103与压缩读取模块106通过有效数据总线和屏蔽数据总线进行数据信息的交互。有效数据总线用于传输第二读有效数据RDATA2<127:0>，屏蔽数据总线用于传输第二读校验位数据RPARITY2<7:0>。屏蔽数据总线为存储器正常工作时使用的总线，本实施例设计的存储器在测试模式时通过屏蔽数据总线进行部分数据的传输，从而避免了引入外部总线，提高了存储器的测试模式的稳定性。
在一个例子中，有效数据总线具有128位宽度，屏蔽数据总线具有8位宽度。写入驱动单元301将128位的第二读有效数据和8位的第二读校验位数据结合后一个136位的数据发送至压缩读取模块106，此时128位的有效数据总线和8位的屏蔽数据总线一起用于传输该136位的数据。
需要说明的是，在其他实施例中，有效数据总线用于传输任意位宽的数据，在128位的基础上，有效数据的宽度每增加一倍，相应检验位总线的位宽需要增加一位，相应地屏蔽数据总线的位宽也需要增加一位，有效数据总线的位宽和屏蔽数据总线的位宽可以根据具体传输数据的位宽进行具体设置。
相对于相关技术而言，在测试模式时，关闭存储器的数据读取通道，通过额外设置的压缩处理单元对存储器存储的有效数据和校验位数据进行 压缩处理，以获取压缩处理数据，并通过压缩处理数据判断所述存储器的主存储模块和校验位存储模块是否出现错误，通过对存储数据和校验位数据同时测试，提高了存储器测试的效率；且通过压缩处理数据获取测试结果，进一步提到了存储器测试的效率。
值得一提的是，本实施例中所涉及到的各模块均为逻辑模块，在实际应用中，一个逻辑单元可以是一个物理单元，也可以是一个物理单元的一部分，还可以以多个物理单元的组合实现。此外，为了突出本申请的创新部分，本实施例中并没有将与解决本申请所提出的技术问题关系不太密切的单元引入，但这并不表明本实施例中不存在其它的单元。
本申请第二实施例涉及一种存储器，相比于第一实施例而言，第二实施例通过新增测试用例寄存器来完成对存储模块的数据写入，加快了存储器的测试数据写入速度，从而提高存储器的测试效率。
图3和图4为本申请实施例提供的存储器的结构示意图，下面对本实施例的存储器进行具体说明，与第一实施例相同或相应的部分，以下将不做详细赘述。
参考图3和图4，存储器，还包括：
测试用例寄存器107，用于存储测试数据，与写入驱动单元301连接。
测试用例(Test Case)是指对一项特定的软件产品进行测试任务的描述，体现测试方案、方法、技术和策略。其内容包括测试目标、测试环境、输入数据、测试步骤、预期结果、测试脚本等，最终形成文档。
在本实施例中，测试用例用于输出测试数据指示存储模块的每一个存储单元存储高电平。
在进行测试模式之前，将测试用例存储在测试用例寄存器107；在进入测试模式时，关闭写入编码单元，开启测试用例寄存器107，测试用例寄存器107输出测试数据，用于对主存储模块和校验位存储模块220进行测试。
参考图1，对于写操作，对存储模块102进行测试时，数据处理模块104关断与读写驱动模块103的数据写入通道；测试用例寄存器107输出测试数据，测试数据包括Data<127:0>和Dm<7:0>；读写驱动模块103对接收到的Data<127:0>，依次存储到主存储模块1(201)、主存储模块2(202)……主存储模块15(215)和主存储模块16(216)中，每个主存储模块中存储一个8位的并行数据，并将Dm<7:0>写入校验位存储模块220中；对于读操作，数据处理模块104对数据进行压缩处理，获取压缩处理数据，通过压缩处理数据检测存储模块102是否处于正常工作状态，然后将并行的压缩处理处理由并行数据转换成串行数据后，通过数据焊盘101输出到外部；读写驱动模块103将各个主存储模块中的数据和校验位存储模块220中的数据依次读取到Data<127:0>和Dm<7:0>中。
具体地，参考图2，在进行测试模式之前，将测试用例存储测试用例寄存器107，测试用例用于输出测试数据指示向主存储模块和校验位存储模块220存入高电平；向所述存储单元写入高电平的目的在于判断存储模块中的每一个存储单元是否能够正常存储高电平数据。在进入测试模式时，关闭写入编码单元，即关闭存储器的数据写入通道，并开启测试用例寄存器107，测试用例寄存器107输出预先存储的测试数据，通过测试数据完成对主存储模块和校验位存储模块220的数据写入，从而实现对主存储模块和校验位存储模块220的测试。
在本实施例中，测试用例寄存器107与读写驱动模块通过有效数据总线和校验位总线进行数据信息的交互。
在一个例子中，有效数据总线具有128位宽度，检验位总线具有8位宽度。即有效数据总线用于传输128位的有效数据，而128位的有效数据经过检错纠错操作产生8位的校验位数据，校验位总线用于传输这8位的校验位数据。
具体地，有效数据和校验位数据的通过测试用例保存，在进入测试模式时，测试用例寄存器107基于测试用例，通过有效数据总线向存储模块输入128为有效数据，并通过校验位总线向存储模块输入8为校验位数据，有效数据存储器在存储模块的主存储模块中，8位校验位数据存储在存储模块的校验位存储模块220中。
需要说明的是，在其他实施例中，有效数据总线用于传输任意位宽的数据，在128位的基础上，有效数据的宽度每增加一倍，相应检验位总线的位宽需要增加一位，有效数据总线的位宽和校验位总线的位宽可以根据具体传输数据的位宽进行具体设置。
相对于相关技术而言，在测试模式时，关闭存储器的数据读取通道，通过额外设置的压缩处理单元对存储器存储的有效数据和校验位数据进行压缩处理，以获取压缩处理数据，并通过压缩处理数据判断所述存储器的主存储模块和校验位存储模块是否出现错误，通过对存储数据和校验位数据同时测试，提高了存储器测试的效率；且通过压缩处理数据获取测试结果，进一步提到了存储器测试的效率。另外，通过测试用例寄存器存储测试数据，在存储器进行测试时，直接通过测试用例寄存器输出的测试数据完成对存储器中主存储模块和校验位存储模块的写入，加快了测试数据写入速度，从而进一步提高存储器的测试效率。
值得一提的是，本实施例中所涉及到的各模块均为逻辑模块，在实际应用中，一个逻辑单元可以是一个物理单元，也可以是一个物理单元的一部分，还可以以多个物理单元的组合实现。此外，为了突出本申请的创新部分，本实施例中并没有将与解决本申请所提出的技术问题关系不太密切的单元引入，但这并不表明本实施例中不存在其它的单元。
本申请第三实施例涉及一种存储器的测试方法。
以下将结合附图对本实施例提供的存储器的测试方法进行详细说明， 与第一实施例和第二实施例相同或相应的部分，以下将不做详细赘述。
存储器的测试方法，应用于第一实施例的存储器，包括：基于数据焊盘向存储器中输入测试数据；将测试数据写入主存储模块和校验位存储模块；通过压缩读取模块读取主存储模块和校验位存储模块储存的测试数据，并输出压缩处理数据；基于压缩处理数据判断存储模块是否处于正常工作状态。
参考图5，存储器的测试方法包括：
步骤601，通过存储器的数据写入通道向存储器的存储模块中写入数据。
具体地，参考图2，通过数据写入通道进行写入操作时，数据焊盘101与外部控制器进行数据交互，获取第一写有效数据WDATA1<127:0>，第一写有效数据WDATA1<127:0>即外部输入的待存入存储器的数据。
数据焊盘101将获取的第一写有效数据WDATA1<127:0>传输至写入数据转换单元501，写入数据转换单元501对第一写有效数据WDATA1<127:0>进行串并转换，以将串行的第一写有效数据WDATA1<127:0>转换成多个并行的第二写有效数据WDATA2<127:0>，并将第二写有效数据WDATA2<127:0>传输至写入编码单元401。
写入编码单元401对第二写有效数据WDATA2<127:0>进行ECC检测，以获取第二写有效数据WDATA2<127:0>的第一写校验位数据WPARITY1<7:0>，进行ECC检测后的第二写有效数据WDATA2<127:0>作为第三写有效数据WDATA3<127:0>和第一写校验位数据WPARITY1<7:0>一同被传输至写入驱动单元301。
写入驱动单元301，用于放大第三写有效数据WDATA3<127:0>和第一写校验位数据，以提高第三写有效数据WDATA3<127:0>和第一写校验位数据WPARITY1<7:0>的驱动能力，第三写有效数据WDATA3<127:0>放大后 作为第四写有效数据WDATA4<127:0>写入主存储模块，第一写校验位数据WPARITY1<7:0>放大后作为第二写校验位数据WPARITY2<7:0>写入校验位存储模块。
继续参考图5，步骤602，关闭存储器的数据读取通道，开启存储器的压缩读取模块；步骤603，基于压缩读取模块获取压缩处理数据；步骤604，将压缩处理数据输出至存储器的数据焊盘。
参考图2，具体地，读取驱动单元302将第二读有效数据RDATA2<127:0>和第二读校验位数据WPARITY2<7:0>作为测试数据TDATA<135:0>送入压缩读取模块106，压缩读取模块106对接收的测试数据TDATA<135:0>进行压缩处理，生成压缩处理数据，并将压缩处理数据经过读取数据转换单元502输出到数据焊盘101，从而实现将压缩处理数据输出到外部。
继续参考图5，步骤105，基于压缩处理数据判断存储器的存储模块是否处于正常工作状态。
参考图2，具体地，存储模块102中每一个存储单元都用于存储一比特的高电平数据，一比特的数据错误表征存储模块102中存在一个有问题的存储电容。而检错纠错操作用于对读取的存储数据102进行错误检验，且当错误数据为一比特的数据时，检错纠错操作还用于调整错误数据，即当检错纠错的解码操作没有发现错误时，第一写有效数据WDATA1<127:0>等于第四读有效数据RDATA4<127:0>，当检错纠错的解码操作发现一比特错误时，第一写有效数据WDATA1<127:0>等于第四读有效数据RDATA4<127:0>；但当错误数据为多比特的数据时，检错纠错操作无法调整错误数据，即当检错纠错的解码操作发现多比特错误时，第一写有效数据WDATA1<127:0>不等于第四读有效数据RDATA4<127:0>。
存储器的测试方法，应用于第二实施例的存储器，包括：将测试数据 存入测试用例寄存器；将测试用例寄存器输出的测试数据写入主存储模块和校验位存储模块；通过压缩读取模块读取主存储模块和校验位存储模块储存的测试数据，并输出压缩处理数据；基于压缩处理数据判断存储模块是否处于正常工作状态。
参考图6，存储器的测试方法包括：
步骤701，关闭存储器的数据写入通道，通过测试用例寄存器向存储器的存储模块中写入数据。
参考图4，将测试数据存入存储器的测试用例寄存器107，测试数据用于对存储器的存储模块102进行测试，开启测试用例寄存器107，测试用例寄存器107向存储模块102输出测试数据。
具体地，在进行测试模式之前，将测试数据存入测试用例寄存器107，测试数据用于指示向主存储模块和校验位存储模块220存入高电平；向主存储模块和校验位存储模块220写入高电平的目的在于判断存储模块102是否能够正常存储高电平数据。在进入测试模式时，关闭写入编码单元401，即关闭存储器的数据写入通道，并开启测试用例寄存器107，测试用例寄存器107输出预先存储的测试数据，通过测试数据完成对主存储模块和校验位存储模块220的数据写入，从而实现对存储模块102的测试。
继续参考图6，步骤702，关闭存储器的数据读取通道，开启存储器的压缩读取模块；步骤703，基于压缩读取模块获取压缩处理数据；步骤704，将压缩处理数据输出至存储器的数据焊盘。
参考图5，具体地，读取驱动单元302将第二读有效数据RDATA2<127:0>和第二读校验位数据WPARITY2<7:0>作为测试数据TDATA<135:0>送入压缩读取模块106，压缩读取模块106对接收的测试数据TDATA<135:0>进行压缩处理，生成压缩处理数据，并将压缩处理数据经过读取数据转换单元502输出到数据焊盘101，从而实现将压缩处理数据输 出到外部。
继续参考图6，步骤705，基于压缩处理数据判断存储器的存储模块是否处于正常工作状态。
参考图5，具体地，存储模块102中每一个存储单元都用于存储一比特的高电平数据，一比特的数据错误表征存储模块102中存在一个有问题的存储电容。而检错纠错操作用于对读取的存储数据进行错误检验，且当错误数据为一比特的数据时，检错纠错操作还用于调整错误数据，即当检错纠错的解码操作没有发现错误时，第一写有效数据WDATA1<127:0>等于第四读有效数据RDATA4<127:0>，当检错纠错的解码操作发现一比特错误时，第一写有效数据WDATA1<127:0>等于第四读有效数据RDATA4<127:0>；但当错误数据为多比特的数据时，检错纠错操作无法调整错误数据，即当检错纠错的解码操作发现多比特错误时，第一写有效数据WDATA1<127:0>不等于第四读有效数据RDATA4<127:0>。
与相关技术相比，
在测试模式时，关闭存储器的数据读取通道，通过额外设置的压缩处理单元对存储器存储的有效数据和校验位数据进行压缩处理，以获取压缩处理数据，并通过压缩处理数据判断所述存储器的主存储模块和校验位存储模块是否出现错误，通过对存储数据和校验位数据同时测试，提高了存储器测试的效率；且通过压缩处理数据获取测试结果，进一步提到了存储器测试的效率。另外，通过测试用例寄存器107存储测试数据，在存储器进行测试时，直接通过测试用例寄存器107输出的测试数据完成对存储器中主存储模块和校验位存储模块的写入，加快了测试数据写入速度，从而进一步提高存储器的测试效率。
上面各种步骤划分，只是为了描述清楚，实现时可以合并为一个步骤或者对某些步骤进行拆分，分解为多个步骤，只要包括相同的逻辑关系， 都在本专利的保护范围内；对流程中添加无关紧要的修改或者引入无关紧要的设计，但不改变其流程的核心设计都在该专利的保护范围内。
由于第一实施例和第二实施例与本实施例相互对应，因此本实施例可与第一实施例和第二实施例互相配合实施。第一实施例和第二实施例中提到的相关技术细节在本实施例中依然有效，在第一实施例和第二实施例中所能达到的技术效果在本实施例中也同样可以实现，为了减少重复，这里不再赘述。相应地，本实施例中提到的相关技术细节也可应用在第一实施例和第二实施例中。
本领域的普通技术人员可以理解，上述各实施例是实现本申请的具体实施例，而在实际应用中，可以在形式上和细节上对其作各种改变，而不偏离本申请的精神和范围。

Claims (15)

  1. 一种存储器，包括：
    存储模块，用于存储数据信息，所述存储模块包括主存储模块和校验位存储模块，所述主存储模块用于存储有效数据，所述校验位存储模块用于存储校验位数据；
    读写驱动模块，与所述存储模块连接，用于从所述存储模块中读取所述数据信息，或将所述数据信息写入所述存储模块；
    数据处理模块，与所述读写驱动模块连接，用于对所述读写驱动模块输出的所述数据信息进行检错纠错的解码操作，或用于对输入到所述读写驱动模块的所述数据信息进行检错纠错的编码操作。
  2. 根据权利要求1所述的存储器，其中，还包括：
    数据焊盘，与外部控制器交互第一写有效数据和第四读有效数据；
    写入数据转换单元，与所述数据焊盘和所述数据处理模块均连接，用于将所述第一写有效数据进行串并转换，并输出第二写有效数据至所述数据处理模块；
    读取数据转换单元，与所述数据焊盘和所述数据处理模块均连接，用于将所述数据处理模块输出的第三读有效数据进行并串转换，并输出所述第四读有效数据至所述数据焊盘。
  3. 根据权利要求2所述的存储器，其中，所述数据处理模块包括：
    写入编码单元，与所述读写驱动模块和所述写入数据转换单元均连接，用于对所述第二写有效数据执行所述检错纠错的编码操作，所述写入编码单元输出第三写有效数据和第一写校验位数据；
    读取解码单元，与所述读写驱动模块和所述读取数据转换单元均连接，用于对所述读写驱动模块输出的第二读有效数据和第二读校验位数据执行所述检错纠错的解码操作，所述读取解码单元输出所述第三读有 效数据。
  4. 根据权利要求3所述的存储器，其中，所述读写驱动模块包括：
    写入驱动单元，用于将所述第三写有效数据和所述第一写校验位数据的驱动能力进行增强，输出第四写有效数据和第二写校验位数据，并分别将所述第四写有效数据和第二写校验位数据写入所述主存储模块和校验位存储模块；
    读取驱动单元，用于将所述存储模块输出的第一读有效数据和第一读校验位数据的驱动能力进行增强，输出所述第二读有效数据和所述第二读校验位数据。
  5. 根据权利要求4所述的存储器，其中，还包括：
    压缩读取模块，与所述读取驱动单元和所述读取数据转换单元均连接，用于在测试模式将所述数据信息进行压缩处理，以输出压缩处理数据至所述读取数据转换单元。
  6. 根据权利要求5所述的存储器，其中，当所述检错纠错的解码操作没有发现错误时，所述第一写有效数据等于所述第四读有效数据；当所述检错纠错的解码操作发现一比特错误时，所述第一写有效数据等于所述第四读有效数据；当所述检错纠错的解码操作发现多比特错误时，所述第一写有效数据不等于所述第四读有效数据。
  7. 根据权利要求5所述的存储器，其中，当进入所述测试模式时，关闭所述读取解码单元，开启所述压缩读取模块，所述读取驱动单元将所述第二读有效数据和所述第二读校验位数据送入所述压缩读取模块，所述压缩处理数据经过所述读取数据转换单元输出到所述数据焊盘。
  8. 根据权利要求5所述的存储器，其中，所述读写驱动模块与所述数据处理模块通过有效数据总线和校验位总线进行所述数据信息的交互；所述读写驱动模块与所述压缩读取模块通过所述有效数据总线和屏 蔽数据总线进行所述数据信息的交互。
  9. 根据权利要求8所述的存储器，其中，所述有效数据总线具有128位宽度，所述校验位总线具有8位宽度，所述屏蔽数据总线具有8位宽度。
  10. 根据权利要求5至9任一所述的存储器，其中，还包括：测试用例寄存器，用于存储测试数据，与所述写入驱动单元连接。
  11. 根据权利要求10所述的存储器，其中，所述测试用例寄存器与所述读写驱动模块通过有效数据总线和校验位总线进行所述数据信息的交互。
  12. 根据权利要求11所述的存储器，其中，所述有效数据总线具有128位宽度，所述校验位总线具有8位宽度。
  13. 根据权利要求10所述的存储器，其中，在进入所述测试模式之前，将所述测试数据存入所述测试用例寄存器；在进入所述测试模式时，关闭写入编码单元，开启测试用例寄存器，所述测试用例寄存器输出测试数据，用于对所述主存储模块和所述校验位存储模块进行测试。
  14. 一种存储器的测试方法，应用于权利要求5～9任一项所述的存储器，包括：
    基于数据焊盘向存储器中输入测试数据；
    将所述测试数据写入所述主存储模块和校验位存储模块；
    通过所述压缩读取模块读取所述主存储模块和校验位存储模块储存的测试数据，并输出所述压缩处理数据；
    基于所述压缩处理数据判断所述存储模块是否处于正常工作状态。
  15. 一种存储器的测试方法，应用于权利要求10～13任一项所述的存储器，包括：
    将测试数据存入测试用例寄存器；
    将所述测试用例寄存器输出的所述测试数据写入所述主存储模块和校验位存储模块；
    通过所述压缩读取模块读取所述主存储模块和校验位存储模块储存的测试数据，并输出所述压缩处理数据；
    基于所述压缩处理数据判断所述存储模块是否处于正常工作状态。
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