WO2022067877A1 - 像素驱动电路、其驱动方法、显示基板及显示装置 - Google Patents

像素驱动电路、其驱动方法、显示基板及显示装置 Download PDF

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Publication number
WO2022067877A1
WO2022067877A1 PCT/CN2020/120484 CN2020120484W WO2022067877A1 WO 2022067877 A1 WO2022067877 A1 WO 2022067877A1 CN 2020120484 W CN2020120484 W CN 2020120484W WO 2022067877 A1 WO2022067877 A1 WO 2022067877A1
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Prior art keywords
control
circuit
light
node
terminal
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PCT/CN2020/120484
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English (en)
French (fr)
Inventor
邱远游
黄耀
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Priority to CN202080002277.1A priority Critical patent/CN114730540A/zh
Priority to US17/426,681 priority patent/US11978380B2/en
Publication of WO2022067877A1 publication Critical patent/WO2022067877A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0852—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor being a dynamic memory with more than one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/028—Generation of voltages supplied to electrode drivers in a matrix display other than LCD
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2340/00—Aspects of display data processing
    • G09G2340/04—Changes in size, position or resolution of an image
    • G09G2340/0407—Resolution change, inclusive of the use of different resolutions for different screen areas
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/14—Detecting light within display terminals, e.g. using a single or a plurality of photosensors
    • G09G2360/145—Detecting light within display terminals, e.g. using a single or a plurality of photosensors the light originating from the display screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a pixel driving circuit, a driving method thereof, a display substrate and a display device.
  • the camera is arranged below the display area of the display substrate, and light can pass through the display area of the display substrate to shoot towards the camera, so that the camera can capture the picture, however, part of the display area with the camera There will be uneven brightness at low gray levels.
  • the present disclosure provides a display substrate, wherein the display substrate includes: a display area and a frame area;
  • the display area includes: a first display area and a second display area; the first display area includes a plurality of first light emitting devices, and the second display area includes a plurality of second light emitting devices;
  • the display substrate includes: a plurality of pixel driving circuits respectively coupled to each of the second light emitting devices;
  • the pixel drive circuit includes: a first drive control circuit located in the frame area, and a second drive control circuit located in the second display area; the first drive control circuit communicates with the first drive control circuit through a first wire two driving control circuits are coupled, and the second driving control circuit is coupled with the corresponding second light emitting device;
  • the first drive control circuit is configured to generate a drive current for driving the corresponding second light emitting device
  • the second drive control circuit is configured to connect the first drive control circuit to the corresponding second drive control circuit when the drive current is conducted between the second drive control circuit and the first wire After the light-emitting device is turned off for a period of time, the first driving control circuit is turned on with the corresponding second light-emitting device.
  • the first drive control circuit includes:
  • the first drive control sub-circuit is respectively coupled to the first node, the second node, the third node, the first power supply terminal and the second power supply terminal, and is configured according to the first node, the second node and all the generating a driving current for driving the second light-emitting device by the signal of the third node;
  • a first threshold compensation sub-circuit respectively coupled to the first scan signal terminal, the first node and the third node, and configured to control the first drive under the control of the first scan signal terminal
  • the sub-circuit performs threshold compensation
  • a first lighting control sub-circuit respectively coupled to the first power supply terminal, the fourth node, the first lighting control signal terminal, the second node and the third node, and configured to emit light at the first Under the control of the control signal terminal, the first power supply terminal and the second node are turned on, and the third node and the fourth node are turned on;
  • a first data writing subcircuit respectively coupled to the first scan signal terminal, the first data signal terminal and the second node, is configured to write the first scan signal terminal under the control of the first scan signal terminal.
  • a data signal of a data signal terminal is provided to the second node;
  • a first storage sub-circuit respectively coupled to the first power supply terminal and the first node, is configured to store data signals.
  • the first drive control sub-circuit includes: a first switch transistor
  • the control terminal of the first switching transistor is coupled to the first node, the first electrode is coupled to the second node, and the second electrode is coupled to the third node.
  • the first threshold compensation sub-circuit includes: a second switch transistor
  • the control terminal of the second switching transistor is coupled to the first scan signal terminal, the first electrode is coupled to the first node, and the second electrode is coupled to the third node.
  • the first light-emitting control sub-circuit includes: a third switch transistor and a fourth switch transistor;
  • a control terminal of the third switching transistor is coupled to the first light-emitting control signal terminal, a first pole is coupled to the first power supply terminal, and a second pole is coupled to the second node;
  • the control terminal of the fourth switching transistor is coupled to the first light-emitting control signal terminal, the first electrode is coupled to the third node, and the second electrode is coupled to the fourth node.
  • the first data writing sub-circuit includes: a fifth switch transistor;
  • the control terminal of the fifth switch transistor is coupled to the first scan signal terminal, the first electrode is coupled to the first data signal terminal, and the second electrode is coupled to the second node.
  • the first storage sub-circuit includes: a first capacitor
  • the first electrode of the first capacitor is coupled to the first power supply terminal, and the second electrode is coupled to the first node.
  • the first drive control circuit further includes: a first reset sub-circuit and a second reset sub-circuit;
  • the first reset sub-circuit is respectively coupled to the first node, the first reset control terminal and the first reference signal terminal, and is configured to, under the control of the first reset control terminal, convert the first reference the signal of the signal terminal is provided to the first node;
  • the second reset sub-circuit is respectively coupled to the second light-emitting device, the second reset control terminal and the second reference signal terminal, and is configured to, under the control of the second reset control terminal, reset the second reset control terminal.
  • the signal of the reference signal terminal is provided to the second light emitting device;
  • the second drive control circuit includes:
  • the second light-emitting control sub-circuit is respectively coupled to the first light-emitting control sub-circuit, the second light-emitting device and the second light-emitting control signal terminal, and is configured to, under the control of the second light-emitting control signal terminal, convert the The first light-emitting control circuit is in conduction with the second light-emitting device.
  • the first drive control circuit includes:
  • the first reset sub-circuit is respectively coupled to the first node, the first reset control terminal and the first reference signal terminal, and is configured to, under the control of the first reset control terminal, convert the first reference signal terminal a signal is provided to the first node;
  • the second drive control circuit includes: a second reset sub-circuit and a second light-emitting control sub-circuit;
  • the second reset sub-circuit is respectively coupled to the second light-emitting device, the second reset control terminal and the second reference signal terminal, and is configured to, under the control of the second reset control terminal, reset the second reset control terminal.
  • the signal of the reference signal terminal is provided to the second light emitting device;
  • the second lighting control sub-circuit is respectively coupled to the first lighting control sub-circuit, the second lighting device and the second lighting control signal terminal, and is configured to be under the control of the second lighting control signal terminal , conducting the first light-emitting control sub-circuit with the second light-emitting device.
  • the first reset sub-circuit includes: a sixth switch transistor
  • the control terminal of the sixth switch transistor is coupled to the first reset control terminal, the first electrode is coupled to the first reference signal terminal, and the second electrode is coupled to the first node.
  • the second reset sub-circuit includes: a seventh switch transistor
  • the control terminal of the seventh switch transistor is coupled to the second reset control terminal, the first electrode is coupled to the second reference signal terminal, and the second electrode is coupled to the second light emitting device.
  • the second light-emitting control sub-circuit includes: an eighth switch transistor;
  • the control terminal of the eighth switch transistor is coupled to the second light control signal terminal, the first electrode is coupled to the first light-emitting control sub-circuit, and the second electrode is coupled to the second light-emitting device.
  • it further includes: a plurality of third driving control circuits respectively coupled to each of the first light emitting devices correspondingly;
  • the third drive control circuit is located in the first display area
  • the third driving control circuit is configured to generate a driving current for driving the corresponding first light emitting device.
  • the third drive control circuit includes:
  • the second driving control sub-circuit is respectively coupled to the sixth node, the seventh node, the eighth node, the third power supply terminal and the fourth power supply terminal, and is configured according to the sixth node, the seventh node and the fourth power supply terminal. generating a driving current for driving the first light-emitting device by using the signal of the eighth node;
  • a second threshold compensation sub-circuit respectively coupled to the second scan signal terminal, the sixth node and the eighth node, is configured to control the second drive under the control of the second scan signal terminal
  • the sub-circuit performs threshold compensation
  • a third lighting control sub-circuit respectively coupled to the third power supply terminal, the fourth power supply terminal, the third lighting control signal terminal, the seventh node and the eighth node, is configured to connect to the third Under the control of the light-emitting control signal terminal, the third power supply terminal is coupled to the seventh node, and the eighth node is coupled to the fourth power supply terminal;
  • the second data writing sub-circuit is respectively coupled to the second scan signal terminal, the second data signal terminal and the seventh node, and is configured to write the second scan signal terminal under the control of the second scan signal terminal.
  • the data signals of the two data signal terminals are provided to the seventh node;
  • a second storage sub-circuit respectively coupled to the third power supply terminal and the sixth node, configured to store data signals
  • a third reset sub-circuit which is respectively coupled to the sixth node, the third reset control terminal and the third reference signal terminal, is configured to, under the control of the third reset control terminal, reset the voltage of the third reference signal terminal to a signal is provided to the sixth node;
  • a fourth reset sub-circuit which is respectively coupled to the first light-emitting device, the fourth reset control terminal and the fourth reference signal terminal, and is configured to convert the fourth reference signal under the control of the fourth reset control terminal
  • the signal of the terminal is provided to the first light emitting device.
  • an embodiment of the present disclosure also provides a display device, which includes: any of the above-mentioned display substrates.
  • it further includes: an image collector;
  • the image collector is located at the position of the second display area of the display substrate, and the image collector is located on the side of the display substrate away from the light emitting surface.
  • an embodiment of the present disclosure further provides a pixel driving circuit, wherein the pixel driving circuit is configured to drive the second light-emitting device; the pixel driving circuit includes:
  • a first drive control circuit configured to generate a drive current for driving the corresponding second light emitting device
  • a second drive control circuit coupled to the first drive control circuit through a first wire, and the second drive control circuit is coupled to the corresponding second light emitting device; configured to conduct the drive current when the drive current is conducted When between the second drive control circuit and the first wire, disconnect the first drive control circuit from the corresponding second light-emitting device for a period of time, and then connect the first drive control circuit to the corresponding second light-emitting device for a period of time.
  • the corresponding second light emitting device is turned on.
  • an embodiment of the present disclosure also provides a driving method for the above pixel driving circuit, which includes:
  • the first drive control circuit is controlled to generate a drive current for driving the corresponding second light-emitting device, and when the drive current is conducted between the second drive control circuit and the first wire, the first drive is controlled
  • the control circuit is disconnected from the corresponding second light-emitting device;
  • the first driving control circuit is controlled to be turned on with the corresponding second light emitting device.
  • controlling the first drive control circuit to disconnect from the corresponding second light-emitting device includes:
  • the first scan signal terminal, the second reset control terminal and the second light-emitting control signal terminal are loaded with a valid signal
  • the valid signal is stopped from being applied to the second light-emitting control signal terminal, and the valid signal is applied to the first light-emitting control signal terminal.
  • the first lighting control signal terminal is loaded with the valid signal.
  • the controlling the first driving control circuit to conduct conduction with the corresponding second light emitting device during the second time period includes:
  • a valid signal is applied to the first lighting control signal terminal and the second lighting control signal terminal.
  • FIG. 1 is a schematic plan view of a display device with an under-screen camera structure in the related art
  • FIG. 2 is a schematic diagram of a light-emitting principle of a second light-emitting device in a second display area
  • FIG. 3 is a schematic diagram of a current curve of the second light-emitting device during low grayscale display
  • FIG. 4 is a schematic plan view of a display substrate according to an embodiment of the present disclosure.
  • FIG. 5 is a schematic structural diagram of a pixel driving circuit according to an embodiment of the disclosure.
  • FIG. 6 is a schematic diagram of a specific structure of a pixel driving circuit corresponding to FIG. 5;
  • FIG. 7 is another schematic structural diagram of a pixel driving circuit according to an embodiment of the disclosure.
  • FIG. 8 is a schematic diagram of a specific structure of a pixel driving circuit corresponding to FIG. 7;
  • FIG. 9 is a schematic structural diagram of a third drive control circuit in an embodiment of the disclosure.
  • FIG. 10 is a schematic structural diagram of a third drive control circuit corresponding to FIG. 9;
  • FIG. 11 is a flowchart of the above-mentioned pixel driving circuit provided by an embodiment of the present disclosure.
  • FIG. 12 is a circuit timing diagram of a pixel driving circuit according to an embodiment of the disclosure.
  • the display device includes: a display area A and a frame area B connected to the display area A, wherein the display area A includes In the first display area A1 and the second display area A2, the camera may be arranged at the position of the second display area A2.
  • a plurality of pixel circuits P are arranged in the first display area A1, and each pixel circuit P includes a first light-emitting device and a corresponding driving circuit, that is, the driving circuit in the pixel circuit P is located near the first light-emitting device.
  • the second display area A2 is provided with a plurality of second light-emitting devices EL, the pixel driving circuits (eg D_1 and D_2 in FIG. 1 ) for controlling the light emission of the second light-emitting devices EL are located in the border area B, and the pixel driving circuits
  • the first wire L is coupled with the second light emitting device EL, because the load of the first wire L is relatively large and the lengths of the first wires L are different, resulting in uneven brightness of the second display area A2 at low gray scales The phenomenon.
  • FIG. 2 is a schematic diagram of the light-emitting principle of the second light-emitting device in the second display area.
  • the pixel driving circuit D_1 is used to drive the corresponding second light-emitting device EL as an example for illustration.
  • R_L represents the resistance of the first wire L.
  • C_L represents the parasitic capacitance generated by the first wire L, wherein the parasitic capacitance is generated by the first wire L and other conductive film layers, and/or the parasitic capacitance is generated between the first wires L.
  • the pixel driving circuit D_1 generates a driving current for driving the second light-emitting device EL.
  • the driving current is relatively small
  • the voltage of the fifth node N5 is relatively slow to raise
  • the charge Q 2 is charged into the first wire to generate the charging speed of the parasitic capacitance C_L. Slowly, therefore, most of the charge Q 2 is charged into the parasitic capacitance C_L.
  • the brightness of the second light-emitting device EL decreases greatly when the second light-emitting device EL is displayed at a low gray scale, and the second light-emitting device EL is displayed at a high gray scale
  • the driving current is larger, the voltage of the fifth node N5 is raised faster, and the charge Q 2 is charged into the parasitic capacitance C_L generated by the first wire, and the charging speed is faster. Therefore, the charge Q in the parasitic capacitance C_L generated by the first wire is charged 2 is less, therefore, the luminance reduction of the second light emitting device EL is smaller when displaying high gray scales.
  • FIG. 3 is a schematic diagram of the current curve of the second light-emitting device during low grayscale display.
  • the curve S1 represents the current curve of the second light-emitting device corresponding to the first wire with a shorter length
  • the curve S2 represents a longer length.
  • the current curve of the second light-emitting device corresponding to the first wire, the upper inflection point in the curve S1 and the curve S2 represents the lighting time of the second light-emitting device. It can be clearly seen from FIG. 3 that the longer the length of the first wire is. , the longer the lighting time of the corresponding second light-emitting device, the lower the brightness of the second light-emitting device.
  • an embodiment of the present disclosure provides a pixel driving circuit, which drives Method, display substrate and display device.
  • FIG. 4 is a schematic plan view of the display substrate provided by an embodiment of the present disclosure.
  • the display substrate includes: a display area A and a frame area B; Area B can be connected to the edge of the display area A side;
  • the display area A includes: a first display area A1 and a second display area A2; the first display area A1 includes a plurality of first light-emitting devices EL', in FIG. 4, a plurality of pixel circuits P are arranged in the first display area A1, Each pixel circuit P includes a first light-emitting device EL' and a corresponding third driving control circuit 30, and the second display area A2 includes a plurality of second light-emitting devices EL (a plurality of second light-emitting devices are respectively located in each area W);
  • the display substrate includes: a plurality of pixel driving circuits respectively coupled to the second light emitting devices EL correspondingly;
  • the pixel driving circuit includes: a first driving control circuit 10 located in the frame area B, and a first driving control circuit 10 located in the second display area A2
  • Two drive control circuits 20 (in FIG. 4 , the second drive control circuit 20 is located in the area W, that is, the area W is provided with the second drive control circuit 20 and the corresponding second light-emitting device EL); the first drive control circuit 10 passes through The first wire L is coupled to the second driving control circuit 20, and the second driving control circuit 20 is coupled to the corresponding second light emitting device EL;
  • the first driving control circuit 10 is configured to generate a driving current for driving the corresponding second light emitting device EL;
  • the second drive control circuit 20 is configured to connect the first drive control circuit 10 to the corresponding After the second light emitting device EL is turned off for a period of time, the first driving control circuit 10 and the corresponding second light emitting device EL are turned on.
  • the second drive control circuit drives the first drive
  • the control circuit disconnects one end of the corresponding second light-emitting device for a period of time, and charges the parasitic capacitance generated by the first wire to raise the potential of the fifth node.
  • the second drive control circuit connects the first drive control circuit with the corresponding one.
  • the conduction of the second light-emitting devices can make the currents flowing to the second light-emitting devices basically the same, thereby improving the brightness uniformity of the second display area.
  • the display substrate provided by the embodiment of the present disclosure may be an organic electroluminescence display substrate, that is, the above-mentioned first light-emitting device and the second light-emitting device may be organic light-emitting diode devices, and the above-mentioned display substrate may also be other types of display substrates. Do limit.
  • the image collector can be set at the position of the second display area A2, and the image collector can be set on the side of the display substrate away from the light-emitting surface.
  • the image collector can be For the camera, during the image acquisition time period, the light passes through the gap between the adjacent second light-emitting devices in the display substrate and shoots toward the image collector, and the image collector receives the light passing through the display substrate, thereby collecting the corresponding picture.
  • the pattern of the opaque film layers such as the metal film layer and the black matrix in the display substrate can be improved, and a light-transmitting area is formed in the gap between the adjacent second light-emitting devices, so that light can pass through. over the display substrate.
  • a fingerprint recognition sensor can also be used to replace the image collector to realize the fingerprint recognition function under the screen, or, the image collector and the fingerprint recognition sensor can be set in the second display area at the same time, or the second display area can also be set up.
  • Other photosensitive components are set in the device, which is not limited here.
  • the first wire may be made of a transparent conductive oxide material such as indium tin oxide (Indium tin oxide, ITO), or other transparent conductive materials, which are not limited herein.
  • a transparent conductive oxide material such as indium tin oxide (Indium tin oxide, ITO), or other transparent conductive materials, which are not limited herein.
  • RC_L in FIG. 5 represents the resistance and parasitic capacitance of the first wire.
  • the first drive control circuit 10 is coupled to the second drive control circuit 20 through RC_L. Specifically, the first drive control circuit 10 is in the fourth The node N4 is coupled to RC_L, and the RC_L is coupled to the second driving control circuit 20 at the fifth node N5, one end of the second light emitting device EL is coupled to the second light emitting control circuit 20, and the other end is coupled to the second power supply end VSS1 is coupled.
  • the second drive control circuit 20 disconnects the first drive control circuit 10 from the corresponding second light emitting device EL for a period of time, so that the drive current can be used for the first drive current.
  • the parasitic capacitance generated by the wire is charged to raise the potential of the fifth node N5, and the potential of the fifth node N5 continues to rise, so that the potentials at the N5 nodes in different pixel driving circuits tend to be consistent.
  • the second driving control The circuit 20 turns on the first drive control circuit 10 and the corresponding second light-emitting device EL.
  • the voltage difference between the fifth node N5 and the second power supply terminal VSS1 in different pixel drive circuits is basically Therefore, the currents flowing to the second light emitting devices EL are basically consistent, and the luminance uniformity of the second display area is improved.
  • the first driving control circuit 10 may include:
  • the first driving control sub-circuit 101 is respectively coupled to the first node N1, the second node N2, the third node N3, the first power supply terminal VDD1 and the second power supply terminal VSS1, and is configured according to the first node N1, the second power supply terminal
  • the signals of the node N2 and the third node N3 generate a driving current for driving the second light-emitting device EL;
  • the first threshold compensation sub-circuit 102 is respectively coupled to the first scan signal terminal Ga1, the first node N1 and the third node N3, and is configured to control the first drive control sub-circuit under the control of the first scan signal terminal Ga1 101 Perform threshold compensation;
  • the first lighting control sub-circuit 103 is respectively coupled to the first power supply terminal VDD1, the fourth node N4, the first lighting control signal terminal EM1, the second node N2 and the third node N3, and is configured to be connected to the first lighting control signal Under the control of the terminal EM1, the first power terminal VDD1 and the second node N2 are turned on, and the third node N3 and the fourth node N4 are turned on; the fourth node N4 is the connection between the first light-emitting control sub-circuit 103 and the first wire. between nodes;
  • the first data writing sub-circuit 104 is respectively coupled to the first scan signal terminal Ga1, the first data signal terminal Da1 and the second node N2, and is configured to write the first data under the control of the first scan signal terminal Ga1.
  • the data signal of the signal terminal Da1 is provided to the second node N2;
  • the first storage sub-circuit 105 is coupled to the first power supply terminal VDD1 and the first node N1 respectively, and is configured to store data signals.
  • the first driving control circuit 10 can be made to generate a driving current for driving the second light emitting device EL.
  • FIG. 6 is a schematic diagram of a specific structure of a pixel driving circuit corresponding to FIG. 5 .
  • the first driving control sub-circuit 101 may include: a first switch transistor T1;
  • the control terminal g of the first switching transistor T1 is coupled to the first node N1, the first electrode s is coupled to the second node N2, and the second electrode d is coupled to the third node N3.
  • the above is only an example to illustrate the specific structure of the first driving control sub-circuit in the display substrate provided by the embodiment of the present disclosure.
  • the specific structure of the first driving control sub-circuit is not limited to the above-mentioned structure provided by the embodiment of the present disclosure. It can be other structures known to those skilled in the art, which are not limited here.
  • the first threshold compensation sub-circuit 102 may include: a second switch transistor T2;
  • the control terminal g of the second switching transistor T2 is coupled to the first scanning signal terminal Ga1, the first electrode s is coupled to the first node N1, and the second electrode d is coupled to the third node N3.
  • the above is only an example to illustrate the specific structure of the first threshold compensation sub-circuit in the display substrate provided by the embodiment of the present disclosure.
  • the specific structure of the first threshold compensation sub-circuit is not limited to the above-mentioned structure provided by the embodiment of the present disclosure. It can be other structures known to those skilled in the art, which are not limited here.
  • the first light emission control sub-circuit 103 may include: a third switch transistor T3 and a fourth switch transistor T4;
  • the control terminal g of the third switch transistor T3 is coupled to the first light emission control signal terminal EM1, the first electrode s is coupled to the first power supply terminal VDD1, and the second electrode d is coupled to the second node N2;
  • the control terminal g of the fourth switching transistor T4 is coupled to the first lighting control signal terminal EM1, the first electrode s is coupled to the third node N3, and the second electrode d is coupled to the fourth node N4.
  • the above is only an example to illustrate the specific structure of the first light-emitting control sub-circuit in the display substrate provided by the embodiment of the present disclosure.
  • the specific structure of the first light-emitting control sub-circuit is not limited to the above-mentioned structure provided by the embodiment of the present disclosure. It can be other structures known to those skilled in the art, which are not limited here.
  • the first data writing sub-circuit 104 may include: a fifth switch transistor T5;
  • the control terminal g of the fifth switch transistor T5 is coupled to the first scan signal terminal Ga1, the first electrode s is coupled to the first data signal terminal Da1, and the second electrode d is coupled to the second node N2.
  • the above is only an example to illustrate the specific structure of the first data writing sub-circuit in the display substrate provided by the embodiment of the present disclosure.
  • the specific structure of the first data writing sub-circuit is not limited to the above-mentioned structure provided by the embodiment of the present disclosure. , and other structures known to those skilled in the art, which are not limited here.
  • the first storage sub-circuit 105 may include: a first capacitor C1;
  • the first electrode c1 of the first capacitor C1 is coupled to the first power supply terminal VDD1, and the second electrode c2 is coupled to the first node N1.
  • the above is only an example to illustrate the specific structure of the first storage sub-circuit in the display substrate provided by the embodiment of the present disclosure.
  • the specific structure of the first storage sub-circuit is not limited to the above-mentioned structure provided by the embodiment of the present disclosure, and may also be Other structures known to those skilled in the art are not limited here.
  • the first drive control circuit 10 may further include: a first reset sub-circuit 106 and a second reset sub-circuit Fw;
  • the first reset sub-circuit 106 is respectively coupled to the first node N1, the first reset control terminal Re1 and the first reference signal terminal Vi1, and is configured to convert the first reference signal terminal under the control of the first reset control terminal Re1.
  • the signal of Vi1 is provided to the first node N1 to realize the reset of the first drive control sub-circuit 101;
  • the second reset sub-circuit Fw is respectively coupled to the second light emitting device EL, the second reset control terminal Re2 and the second reference signal terminal Vi2, and is configured to convert the second reference signal to the second reference signal terminal under the control of the second reset control terminal Re2.
  • the signal of the terminal Vi2 is provided to the second light-emitting device EL to realize resetting of the second light-emitting device EL;
  • the second drive control circuit 20 includes:
  • the second light-emitting control sub-circuit 201 is respectively coupled to the first light-emitting control sub-circuit 103, the second light-emitting device EL and the second light-emitting control signal terminal EM2, and is configured to, under the control of the second light-emitting control signal terminal EM2, convert the The first light-emitting control sub-circuit 103 is turned on with the second light-emitting device EL.
  • the conduction relationship between the first light-emitting control circuit 103 and the second light-emitting device EL can be controlled under the control of the second light-emitting control signal terminal EM2, so that the driving current flows to the second light-emitting device EL.
  • the parasitic capacitance of the first wire is precharged, and after the parasitic capacitance is charged, the driving current is controlled to flow to the second light emitting device EL.
  • the second light-emitting control sub-circuit 201 and the corresponding second light-emitting device EL may be arranged in the area W as shown in FIG. 4 .
  • the second reset sub-circuit Fw is coupled to the fourth node N4, that is, the second reset sub-circuit Fw and the second light-emitting control sub-circuit 201 are coupled through the first wire. Therefore, in the structure shown in FIG. 5 , , the second reset sub-circuit Fw is located in the frame area.
  • FIG. 7 is another schematic structural diagram of a pixel driving circuit in an embodiment of the present disclosure.
  • the first driving control circuit 10 includes:
  • the first reset sub-circuit 106 is respectively coupled to the first node N1, the first reset control terminal Re1 and the first reference signal terminal Vi1, and is configured to convert the first reference signal terminal under the control of the first reset control terminal Re1.
  • the signal of Vi1 is provided to the first node N1 to realize the reset of the first drive control sub-circuit 101;
  • the second drive control circuit 20 includes: a second reset sub-circuit Fw and a second light-emitting control sub-circuit 201;
  • the second reset sub-circuit Fw is respectively coupled to the second light emitting device EL, the second reset control terminal Re2 and the second reference signal terminal Vi2, and is configured to convert the second reference signal to the second reference signal terminal under the control of the second reset control terminal Re2.
  • the signal of the terminal Vi2 is provided to the second light-emitting device EL to realize resetting of the second light-emitting device EL;
  • the second light-emitting control sub-circuit 201 is respectively coupled to the first light-emitting control sub-circuit 103, the second light-emitting device EL and the second light-emitting control signal terminal EM2, and is configured to, under the control of the second light-emitting control signal terminal EM2, convert the The first light-emitting control sub-circuit 103 is turned on with the second light-emitting device EL.
  • the conduction relationship between the first light-emitting control circuit 103 and the second light-emitting device EL can be controlled under the control of the second light-emitting control signal terminal EM2, so that the driving current flows to the second light-emitting device EL.
  • the parasitic capacitance of the first wire is precharged, and after the parasitic capacitance is charged, the driving current is controlled to flow to the second light emitting device EL.
  • the second reset sub-circuit Fw is coupled to the fifth node N5, that is, the second reset sub-circuit Fw and the first light-emitting control sub-circuit 103 are coupled through the first wire. Therefore, in the structure shown in FIG. 7 , , the second reset sub-circuit Fw is located in the second display area, for example, the second reset sub-circuit Fw, the second light-emitting control sub-circuit 201 and the corresponding second light-emitting device EL can all be arranged in the area W shown in FIG. 4 .
  • FIG. 8 is a schematic diagram of a specific structure of the pixel driving circuit corresponding to FIG. 7 .
  • the first reset sub-circuit 106 may include: a sixth switch transistor T6;
  • the control terminal g of the sixth switch transistor T6 is coupled to the first reset control terminal Re1, the first electrode s is coupled to the first reference signal end Vi1, and the second electrode d is coupled to the first node N1.
  • the above is only an example to illustrate the specific structure of the first reset sub-circuit in the display substrate provided by the embodiment of the present disclosure.
  • the specific structure of the first reset sub-circuit is not limited to the above-mentioned structure provided by the embodiment of the present disclosure, and may also be Other structures known to those skilled in the art are not limited here.
  • the second reset sub-circuit Fw may include: a seventh switch transistor T7;
  • the control terminal g of the seventh switch transistor T7 is coupled to the second reset control terminal Re2, the first electrode s is coupled to the second reference signal terminal Vi2, and the second electrode d is coupled to the second light emitting device EL.
  • the above is only an example to illustrate the specific structure of the second reset sub-circuit in the display substrate provided by the embodiment of the present disclosure.
  • the specific structure of the second reset sub-circuit is not limited to the above-mentioned structure provided by the embodiment of the present disclosure, and may also be Other structures known to those skilled in the art are not limited here.
  • the second light-emitting control sub-circuit 201 may include: an eighth switch transistor T8;
  • the control terminal g of the eighth switch transistor T8 is coupled to the second light control signal terminal EM2, the first electrode s is coupled to the first light emission control sub-circuit 103, and the second electrode d is coupled to the second light emitting device EL.
  • the above is only an example to illustrate the specific structure of the second light-emitting control sub-circuit in the display substrate provided by the embodiment of the present disclosure.
  • the specific structure of the second light-emitting control sub-circuit is not limited to the above-mentioned structure provided by the embodiment of the present disclosure. It can be other structures known to those skilled in the art, which are not limited here.
  • the first reset sub-circuit 106 and the second reset sub-circuit Fw are connected to different reference signal terminals, that is, the first reset sub-circuit 106 and the first reference signal The terminal Vi1 is coupled, and the second reset sub-circuit Fw is coupled to the second reference signal terminal Vi2.
  • the first reset sub-circuit 106 and the second reset sub-circuit Fw can also be coupled to the same reference signal terminal, and As a matter of fact, the first reset sub-circuit 106 and the second reset sub-circuit Fw may also be coupled to the same reset control terminal, which is not limited here.
  • the above-mentioned display substrate may further include: a plurality of third driving control circuits 30 respectively coupled to each of the first light emitting devices EL' correspondingly;
  • the third drive control circuit 30 is located in the first display area A1, for example, the third drive control circuit 30 may be located in the pixel circuit P, that is, the third drive control circuit 30 is located in the vicinity of the corresponding first light-emitting device EL';
  • the third driving control circuit 30 is configured to generate a driving current for driving the corresponding first light emitting device EL'.
  • the corresponding first light emitting devices can be driven to emit light, and a display effect with better image quality can be achieved.
  • FIG. 9 is a schematic structural diagram of the third driving control circuit in the embodiment of the present disclosure.
  • the third driving control circuit 30 may include:
  • the second driving control sub-circuit 301 is respectively coupled to the sixth node N6, the seventh node N7, the eighth node N8, the third power supply terminal VDD2 and the fourth power supply terminal VSS2, and is configured according to the sixth node N6, the seventh
  • the signals of the node N7 and the eighth node N8 generate a driving current for driving the first light-emitting device EL';
  • the second threshold compensation sub-circuit 302 is respectively coupled to the second scanning signal terminal Ga2, the sixth node N6 and the eighth node N8, and is configured to control the second driving control sub-circuit under the control of the second scanning signal terminal Ga2 301 Perform threshold compensation;
  • the third lighting control sub-circuit 303 is respectively coupled to the third power supply terminal VDD2, the fourth power supply terminal VSS2, the third lighting control signal terminal EM3, the seventh node N7 and the eighth node N8, and is configured to control the third lighting Under the control of the signal terminal EM3, the third power terminal VDD2 is coupled to the seventh node N7, and the eighth node N8 is coupled to the fourth power terminal VSS2;
  • the second data writing sub-circuit 304 is respectively coupled to the second scan signal terminal Ga2, the second data signal terminal Da2 and the seventh node N7, and is configured to write the second data under the control of the second scan signal terminal Ga2.
  • the data signal of the signal terminal Da2 is provided to the seventh node N7;
  • the second storage sub-circuit 305 is respectively coupled to the third power supply terminal VDD2 and the sixth node N6, and is configured to store data signals;
  • the third reset sub-circuit 306 is respectively coupled to the sixth node N6, the third reset control terminal Re3 and the third reference signal terminal Vi3, and is configured to, under the control of the third reset control terminal Re3, convert the third reference signal terminal The signal of Vi3 is provided to the sixth node N6;
  • the fourth reset sub-circuit 307 is respectively coupled to the first light emitting device EL', the fourth reset control terminal Re4 and the fourth reference signal terminal Vi4, and is configured to, under the control of the fourth reset control terminal Re4, convert the fourth reference The signal of the signal terminal Vi4 is provided to the first light emitting device EL'.
  • the fourth reset sub-circuit 307 in the figure is coupled to the first light emitting device EL' at the ninth node N9.
  • the second driving control sub-circuit 301 through the second driving control sub-circuit 301, the second threshold compensation sub-circuit 302, the third lighting control sub-circuit 303, the second data writing sub-circuit 304, the second storage sub-circuit 305, the third reset
  • the cooperation of the sub-circuit 306 and the fourth reset sub-circuit 307 enables the second driving control circuit 30 to generate a driving current for driving the first light emitting device EL'.
  • FIG. 10 is a schematic structural diagram of the third drive control circuit corresponding to FIG. 9 .
  • the second drive control sub-circuit 301 may include: Eleven switch transistors T11;
  • the control terminal g of the eleventh switching transistor T11 is coupled to the sixth node N6, the first electrode s is coupled to the seventh node N7, and the second electrode d is coupled to the eighth node N8.
  • the second threshold compensation sub-circuit 302 may include: a twelfth switch transistor T12;
  • the control terminal g of the twelfth switching transistor T12 is coupled to the second scanning signal terminal Ga2, the first electrode s is coupled to the sixth node N6, and the second electrode d is coupled to the eighth node N8.
  • the third lighting control sub-circuit 303 may include: a thirteenth switch transistor T13 and a fourteenth switch transistor T14;
  • the control terminal g of the thirteenth switch transistor T13 is coupled to the third light-emitting control signal terminal EM3, the first pole s is coupled to the third power supply terminal VDD2, and the second pole d is coupled to the seventh node N7;
  • the control terminal g of the fourteenth switching transistor T14 is coupled to the third lighting control signal terminal EM3, the first electrode s is coupled to the eighth node N8, and the second electrode d is coupled to the fourth power supply terminal VSS2.
  • the second data writing sub-circuit 304 may include: a fifteenth switch transistor T15;
  • the control terminal g of the fifteenth switch transistor T15 is coupled to the second scan signal terminal Ga2, the first electrode s is coupled to the second data signal terminal Da2, and the second electrode d is coupled to the seventh node N7.
  • the second storage sub-circuit 305 may include: a second capacitor C2;
  • the first electrode c3 of the second capacitor C2 is coupled to the third power supply terminal VDD2, and the second electrode c4 is coupled to the sixth node N6.
  • the third reset sub-circuit 306 is respectively coupled to the sixth node N6, the third reset control terminal Re3 and the third reference signal terminal Vi3, and is configured to, under the control of the third reset control terminal Re3, convert the third reference signal terminal
  • the signal of Vi3 is provided to the sixth node N6 to realize the reset of the second drive control sub-circuit 301;
  • the second reset sub-circuit 307 is respectively coupled to the first light emitting device EL', the fourth reset control terminal Re4 and the fourth reference signal terminal Vi4, and is configured to, under the control of the fourth reset control terminal Re4, convert the fourth reference
  • the signal of the signal terminal Vi4 is provided to the first light emitting device EL', so as to realize the reset of the first light emitting device EL'.
  • the specific structures of the three reset sub-circuits and the fourth reset sub-circuit are not limited to the above-mentioned structures provided by the embodiments of the present disclosure, and may also be other structures known to those skilled in the art. This is not limited.
  • the third reset sub-circuit 306 and the fourth reset sub-circuit 307 are connected to different reference signal terminals, that is, the third reset sub-circuit 306 and the third reset sub-circuit 306 are connected to different reference signal terminals.
  • the reference signal terminal Vi3 is coupled
  • the fourth reset sub-circuit 307 is coupled to the fourth reference signal terminal Vi4.
  • the third reset sub-circuit 306 and the fourth reset sub-circuit 307 can also be coupled to the same reference signal terminal.
  • the third reset sub-circuit 306 and the fourth reset sub-circuit 307 may also be coupled to the same reset control terminal, which is not limited here.
  • an embodiment of the present disclosure also provides a display device, including the above-mentioned display substrate, the display device can be applied to any mobile phone, tablet computer, TV, monitor, notebook computer, digital photo frame, navigator, etc. functional product or component. Since the principle of solving the problem of the display device is similar to that of the above-mentioned display substrate, the implementation of the display device can refer to the implementation of the above-mentioned display substrate, and the repetition will not be repeated.
  • the above-mentioned display device may further include: an image collector;
  • the image collector is located at the position of the second display area of the display substrate, and the image collector is located on the side of the display substrate away from the light emitting surface.
  • the image collector may be a camera.
  • the light passes through the gap between the adjacent second light-emitting devices in the display substrate and shoots toward the image collector, and the image collector receives the light passing through the display substrate.
  • the pattern of opaque film layers such as metal film layers and black matrices in the display substrate can be improved, and the gap between adjacent second light-emitting devices can be improved.
  • a light-transmitting area is formed in the display substrate so that light can pass through the display substrate.
  • a fingerprint recognition sensor can also be used to replace the image collector to realize the under-screen fingerprint recognition function, or, an image collector and a fingerprint recognition sensor can be simultaneously set in the second display area, which is not limited here.
  • an embodiment of the present disclosure also provides a pixel driving circuit. Since the principle of solving the problem of the pixel driving circuit is similar to that of the above-mentioned display substrate, the implementation of the pixel driving circuit can refer to the implementation of the above-mentioned display substrate, and repeat the following It is not repeated here.
  • the pixel driving circuit is configured to drive the second light-emitting device EL; the pixel driving circuit may include:
  • the first driving control circuit 10 is configured to generate a driving current for driving the corresponding second light emitting device EL;
  • the second drive control circuit 20 is coupled to the first drive control circuit 10 through the first wire, and the second drive control circuit 20 is coupled to the corresponding second light emitting device EL; it is configured to conduct the drive current to the second drive control circuit EL. Between the control circuit 20 and the first wire, after the first driving control circuit 10 and the corresponding second light emitting device EL are disconnected for a period of time, the first driving control circuit 10 and the corresponding second light emitting device 20 are turned on.
  • the second drive control circuit by setting the second drive control circuit, when the drive current generated by the first drive control circuit is conducted to the fifth node, the second drive control circuit disconnects the first drive control circuit from the corresponding second light-emitting device When one end is turned on, the parasitic capacitance generated by the first wire is charged to raise the potential of the fifth node. After that, the second drive control circuit conducts the first drive control circuit and the corresponding second light-emitting device, which can make the flow direction
  • the current of each second light-emitting device is basically the same, which improves the brightness uniformity of the second display area.
  • an embodiment of the present disclosure also provides a driving method for the above-mentioned pixel driving circuit. Since the principle of solving the problem of the driving method is similar to that of the above-mentioned pixel driving circuit, the implementation of the driving method can refer to the above-mentioned pixel driving circuit. Implementation, the repetition will not be repeated.
  • the driving method of the above-mentioned pixel driving circuit provided by the embodiment of the present disclosure, as shown in FIG. 11 includes:
  • control the first drive control circuit to generate a drive current for driving the corresponding second light-emitting device, and control the first drive control circuit when the drive current is conducted between the second drive control circuit and the first wire disconnected from the corresponding second light emitting device;
  • the first driving control circuit and the corresponding The second light-emitting device is disconnected to charge the parasitic capacitance generated by the first wire to raise the potential of the fifth node.
  • the first driving control circuit is controlled to be turned on with the corresponding second light-emitting device, which can The currents flowing to each of the second light emitting devices are basically consistent, thereby improving the luminance uniformity of the second display area.
  • the above-mentioned step S401 may include:
  • the first reset control terminal Re1 is loaded with a valid signal, so as to provide the signal of the first reference signal terminal Vi1 to the first node N1, so as to realize the reset of the first drive control sub-circuit 101;
  • the first scan signal terminal Ga1, the second reset control terminal Re and the second light emission control signal terminal EM2 are loaded with valid signals.
  • the first scan signal terminal Ga1 is loaded with a valid signal, and under the control of the first scan signal terminal Ga1, the first threshold compensation sub-circuit 102 performs threshold compensation on the first drive control sub-circuit 101, and converts the data of the first data signal terminal Da1.
  • the signal is provided to the second node N2.
  • the second reset control terminal Re2 and the second light-emitting control signal terminal EM2 are loaded with valid signals, and under the control of the second light-emitting control signal terminal EM2, the fourth node N4 (or the fifth node N5) is turned on with the second light-emitting device EL, Under the control of the second reset control terminal Re2, the signal of the second reference signal terminal Vi2 is provided to the second light-emitting device EL to reset the second light-emitting device EL;
  • the second light-emitting control signal terminal EM2 is stopped from being loaded with a valid signal, and the first light-emitting control signal terminal EM1 is loaded with a valid signal, thereby disconnecting the first light-emitting control circuit 103 from the second light-emitting device EL , so as to charge the parasitic capacitance generated by the first wire to raise the potential of the fifth node N5.
  • the first light-emitting control signal terminal EM1 is loaded with a valid signal, so that the parasitic capacitance generated by the first wire can be prevented from being charged. Leakage occurs during the process of emitting light, otherwise, within a short period of time when the first light-emitting control signal terminal EM1 starts to load a valid signal, the current will flow through the second light-emitting device EL to emit light, especially in high gray-scale display, due to the relatively high driving current If it is large, it is obvious that the second light emitting device EL lights up a little in the first time period.
  • the second light-emitting control signal terminal EM2 can be stopped from being loaded with a valid signal, and the second light-emitting control signal terminal EM2 can be loaded again in the third sub-time period t3.
  • the first lighting control signal terminal EM1 is loaded with a valid signal, or, in the third sub-period t3, the second lighting control signal terminal EM2 is stopped from loading a valid signal, and then the first lighting control signal terminal EM1 is loaded with a valid signal.
  • the above-mentioned step S402 may include:
  • a valid signal is applied to the first light-emitting control signal terminal EM1 and the second light-emitting control signal terminal EM2, so as to control the first driving control circuit to conduct conduction with the corresponding second light-emitting device, so as to make the second light-emitting device glow.
  • each switching transistor in FIG. 6 to FIG. 8 is a P-type transistor, that is, taking a low level as an effective signal.
  • re1 represents the signal loaded by the first reset control terminal Re1
  • re2 represents the signal loaded by the second reset control terminal Re2
  • ga represents the signal loaded by the first scanning signal terminal Ga1
  • em1 represents the first light emission control signal terminal EM1 loaded
  • em2 represents the signal loaded by the second light-emitting control signal terminal EM2.
  • the signal re1 loaded by the first reset control terminal Re1 is at a low level, so that the sixth switching transistor T6 is turned on, and the signal of the first reference signal terminal Vi1 is provided to the first node N1 to The control terminal of the first switching transistor T1 is reset.
  • the signal ga loaded by the first scanning signal terminal Ga1 is at a low level, so that the second switching transistor T2 and the fifth switching transistor T5 are turned on, and the fifth switching transistor T5 is turned on, so that the first switching transistor T2 and the fifth switching transistor T5 are turned on.
  • the data signal of the data signal terminal Da1 is provided to the second node N2, and the second switching transistor T2 is turned on, so that the first node N1 and the third node N3 are turned on, and then the first switching transistor T1 is turned on, so that the data signal is charged.
  • the first node N1, and the signal re2 loaded by the second reset control terminal Re2 is at a low level, so that the seventh switch transistor T7 is turned on, and the signal of the second reference signal terminal Vi2 is provided to the fourth node N4 and the fifth node N5 , to reset the fourth node N4 and the fifth node N5, at the same time, the signal em2 loaded by the second light-emitting control signal terminal EM2 is also low level, so that the eighth switch transistor T8 is turned on, and the second reference signal terminal Vi2 The signal is supplied to the second light emitting device EL to realize resetting of the second light emitting device EL.
  • the signal em1 loaded by the first lighting control signal terminal EM1 is at a low level, and the third lighting transistor T3 and the fourth switching transistor T4 are turned on, so that the first power terminal VDD1 and the second node are turned on.
  • the third switch transistor T3 provides the voltage of the first power supply terminal VDD1 to the first pole s of the first switch transistor T1, so that the first switch transistor T1 is driven current, and the signal em2 loaded by the second light-emitting control signal terminal EM2 is at a high level, the eighth light-on transistor T8 is turned off, so that the driving current continues to rush into the parasitic capacitance generated by the first wire, the fourth node N4 and the fifth node
  • the voltage of N5 keeps rising, and after the parasitic capacitance is full, the voltages of the fourth node N4 (or the fifth node N5 ) in each pixel driving circuit tend to be the same.
  • the second light-emitting The control signal terminal EM2 is loaded with a high-level signal, and in the third sub-period t3, a low-level signal is loaded on the first light-emitting control signal terminal EM1; or, in the third sub-period t3, the second The light-emitting control signal terminal EM2 is loaded with a high-level signal, and then loaded with a low-level signal to the first light-emitting control signal terminal EM1.
  • the signal em1 loaded by the first light-emitting control signal terminal EM1 is at a low level
  • the signal em2 loaded by the second light-emitting control signal terminal EM2 is at a low level, so that the driving current flows to the second light-emitting device EM, so that the second light emitting device EM emits light.
  • the parasitic capacitance generated by the first wire is precharged in the third sub-period t3, the voltage difference between the fourth node N4 (or the fifth node N5) and the second power supply terminal VSS1 is relatively large, so that one frame of The average current in time is relatively large, which avoids the phenomenon that the second light-emitting device EL is lit up with a delay, and improves the uneven display of the second display area in the low-gray-scale picture.
  • the display substrate, the driving method and the display device provided by the embodiments of the present disclosure will not affect the display effect of the high gray scale in the second display area on the basis of improving the uneven display brightness of the low gray scale in the second display area.
  • the following two comparative examples are used for comparative analysis.
  • Comparative Example 1 Due to the high luminous efficiency of green pixels, under the same gray scale, the current of green pixels is the smallest. Therefore, the display effect of green pixels is used to reflect the display effect of low gray scale.
  • the duration of the third sub-period t3 When changing between 200 ⁇ s and 2ms, the resistance of the first wire is different, the difference of the current of the second light-emitting device does not exceed 2%, within the debugging range of the gamma (Gamma) voltage, the duration of the third sub-period t3 When it is 0, the current difference of the second light-emitting device is obvious, and the reaction is that the brightness uniformity of the second display area is poor when it is displayed at a low gray scale.
  • the third sub is used to improve the uneven brightness of the second display area caused by the first wire, and on the basis of improving the brightness uniformity of the second display area, the duration of the third sub-period t3 is shortened as much as possible, Avoid affecting the lighting effect of the fourth sub-period t4.
  • Comparative Example 2 Due to the low luminous efficiency of the blue pixel, the current of the blue pixel is larger under the same gray scale. Therefore, the display effect of the blue pixel is used to reflect the high gray scale display effect.
  • Table 2 shows the first The corresponding relationship between the duration of the three sub-periods, the load of the first wire and the current of the second light-emitting device are shown in Table 2.
  • the maximum resistance of the first wire in Table 2 is 896k ⁇ , that is, the resistance corresponding to 100% is 896k ⁇
  • the maximum value of the parasitic capacitance of the first wire is 3.6pF.
  • the third sub-time When the duration of segment t3 varies between 0 and 2ms, the resistance of the first wire is different, the difference in the current of the second light-emitting device is not more than 2%, which is within the debugging range of the gamma (Gamma) voltage, and, although, The duration of the third sub-period t3 is different, and the current of the second light-emitting device is different, but when the duration of the third sub-period t3 is fixed, the current uniformity of the second light-emitting device is better. Therefore, the third sub-period t3 will not affect the display effect of the high gray scale in the second display area.
  • the driving current generated in the first driving control circuit is conducted to the fifth node
  • the second drive control circuit disconnects the first drive control circuit from the corresponding second light-emitting device for a period of time
  • the parasitic capacitance generated by the first wire is charged to raise the potential of the fifth node.
  • the second drive The control circuit conducts the first drive control circuit and the corresponding second light-emitting device, so that the currents flowing to the second light-emitting devices are basically consistent, and the brightness uniformity of the second display area is improved.

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Abstract

一种像素驱动电路（D_1, D_2）、其驱动方法、显示基板及显示装置，显示基板的显示区域（A）包括第一显示区域（A1）和第二显示区域（A2）；显示基板包括分别与各第二发光器件（EL）对应耦接的多个像素驱动电路（D_1, D_2）；像素驱动电路（D_1, D_2）包括：位于边框区域（B）的第一驱动控制电路（10），以及位于第二显示区域（A2）的第二驱动控制电路（20）；第一驱动控制电路（10）通过第一导线（L）与第二驱动控制电路（20）耦接，第二驱动控制电路（20）与对应的第二发光器件（EL）耦接；第一驱动控制电路（10），被配置为产生驱动对应的第二发光器件（EL）的驱动电流；第二驱动控制电路（20），被配置为在驱动电流传导至第二驱动控制电路（20）与第一导线（L）之间时，将第一驱动控制电路（10）与对应的第二发光器件（EL）断开一段时间后，将第一驱动控制电路（10）与对应的第二发光器件（EL）导通。

Description

像素驱动电路、其驱动方法、显示基板及显示装置
本公开要求在2020年09月29日提交的、优先权号为PCT/CN2020/118657、申请名称为“显示面板及其像素电路的驱动方法、显示装置”的专利申请的优先权，其全部内容通过引用结合在本公开中。
技术领域
本公开涉及显示技术领域，尤指一种像素驱动电路、其驱动方法、显示基板及显示装置。
背景技术
随着显示技术的飞速发展，显示装置除了传统的信息展示等作用外，在外形上的要求也在逐步提升，更大屏占比是未来市场的趋势，因而，具有屏下摄像头结构的显示装置备受消费者青睐。
在具有屏下摄像头结构的显示装置中，摄像头设置于显示基板的显示区域下方，光线可穿过显示基板的显示区域射向摄像头，以使摄像头拍摄到画面，然而，设有摄像头的部分显示区域在低灰阶下会出现亮度不均的现象。
发明内容
本公开实施提供的显示基板，其中，所述显示基板包括：显示区域以及边框区域；
所述显示区域包括：第一显示区域和第二显示区域；所述第一显示区域包括多个第一发光器件，所述第二显示区域包括多个第二发光器件；
所述显示基板包括：分别与各所述第二发光器件对应耦接的多个像素驱动电路；
所述像素驱动电路，包括：位于所述边框区域的第一驱动控制电路，以及位于所述第二显示区域的第二驱动控制电路；所述第一驱动控制电路通过 第一导线与所述第二驱动控制电路耦接，所述第二驱动控制电路与对应的所述第二发光器件耦接；
所述第一驱动控制电路，被配置为产生驱动对应的所述第二发光器件的驱动电流；
所述第二驱动控制电路，被配置为在所述驱动电流传导至所述第二驱动控制电路与所述第一导线之间时，将所述第一驱动控制电路与对应的所述第二发光器件断开一段时间后，将所述第一驱动控制电路与对应的所述第二发光器件导通。
可选地，在本公开实施例中，所述第一驱动控制电路，包括：
第一驱动控制子电路，分别与第一节点、第二节点、第三节点、第一电源端以及第二电源端耦接，被配置为根据所述第一节点、所述第二节点以及所述第三节点的信号，产生驱动所述第二发光器件的驱动电流；
第一阈值补偿子电路，分别与第一扫描信号端、所述第一节点以及所述第三节点耦接，被配置为在所述第一扫描信号端的控制下，对所述第一驱动控制子电路进行阈值补偿；
第一发光控制子电路，分别与所述第一电源端、第四节点、第一发光控制信号端、所述第二节点以及所述第三节点耦接，被配置为在所述第一发光控制信号端的控制下，将所述第一电源端与所述第二节点导通，将所述第三节点与所述第四节点导通；
第一数据写入子电路，分别与所述第一扫描信号端、第一数据信号端以及所述第二节点耦接，被配置为在所述第一扫描信号端的控制下，将所述第一数据信号端的数据信号提供给所述第二节点；
第一存储子电路，分别与所述第一电源端以及所述第一节点耦接，被配置为存储数据信号。
可选地，在本公开实施例中，所述第一驱动控制子电路，包括：第一开关晶体管；
所述第一开关晶体管的控制端与所述第一节点耦接，第一极与所述第二 节点耦接，第二极与所述第三节点耦接。
可选地，在本公开实施例中，所述第一阈值补偿子电路，包括：第二开关晶体管；
所述第二开关晶体管的控制端与所述第一扫描信号端耦接，第一极与所述第一节点耦接，第二极与所述第三节点耦接。
可选地，在本公开实施例中，所述第一发光控制子电路，包括：第三开关晶体管以及第四开关晶体管；
所述第三开关晶体管的控制端与所述第一发光控制信号端耦接，第一极与所述第一电源端耦接，第二极与所述第二节点耦接；
所述第四开关晶体管的控制端与所述第一发光控制信号端耦接，第一极与所述第三节点耦接，第二极与所述第四节点耦接。
可选地，在本公开实施例中，所述第一数据写入子电路，包括：第五开关晶体管；
所述第五开关晶体管的控制端与所述第一扫描信号端耦接，第一极与所述第一数据信号端耦接，第二极与所述第二节点耦接。
可选地，在本公开实施例中，所述第一存储子电路，包括：第一电容；
所述第一电容的第一电极与所述第一电源端耦接，第二电极与所述第一节点耦接。
可选地，在本公开实施例中，所述第一驱动控制电路，还包括：第一复位子电路以及第二复位子电路；
所述第一复位子电路，分别与所述第一节点、第一复位控制端以及第一参考信号端耦接，被配置为在所述第一复位控制端的控制下，将所述第一参考信号端的信号提供给所述第一节点；
所述第二复位子电路，分别与所述第二发光器件、第二复位控制端以及第二参考信号端耦接，被配置为在所述第二复位控制端的控制下，将所述第二参考信号端的信号提供给所述第二发光器件；
所述第二驱动控制电路，包括：
第二发光控制子电路，分别与所述第一发光控制子电路、所述第二发光器件以及第二发光控制信号端耦接，被配置为在所述第二发光控制信号端的控制下，将所述第一发光控制电路与所述第二发光器件导通。
可选地，在本公开实施例中，所述第一驱动控制电路，包括：
第一复位子电路，分别与所述第一节点、第一复位控制端以及第一参考信号端耦接，被配置为在所述第一复位控制端的控制下，将所述第一参考信号端的信号提供给所述第一节点；
所述第二驱动控制电路，包括：第二复位子电路以及第二发光控制子电路；
所述第二复位子电路，分别与所述第二发光器件、第二复位控制端以及第二参考信号端耦接，被配置为在所述第二复位控制端的控制下，将所述第二参考信号端的信号提供给所述第二发光器件；
所述第二发光控制子电路，分别与所述第一发光控制子电路、所述第二发光器件以及第二发光控制信号端耦接，被配置为在所述第二发光控制信号端的控制下，将所述第一发光控制子电路与所述第二发光器件导通。
可选地，在本公开实施例中，所述第一复位子电路，包括：第六开关晶体管；
所述第六开关晶体管的控制端与所述第一复位控制端耦接，第一极与所述第一参考信号端耦接，第二极与所述第一节点耦接。
可选地，在本公开实施例中，所述第二复位子电路，包括：第七开关晶体管；
所述第七开关晶体管的控制端与所述第二复位控制端耦接，第一极与所述第二参考信号端耦接，第二极与所述第二发光器件耦接。
可选地，在本公开实施例中，所述第二发光控制子电路，包括：第八开关晶体管；
所述第八开关晶体管的控制端与所述第二光控制信号端耦接，第一极与所述第一发光控制子电路耦接，第二极与所述第二发光器件耦接。
可选地，在本公开实施例中，还包括：分别与各所述第一发光器件对应耦接的多个第三驱动控制电路；
所述第三驱动控制电路位于所述第一显示区域内；
所述第三驱动控制电路，被配置为产生驱动对应的所述第一发光器件的驱动电流。
可选地，在本公开实施例中，所述第三驱动控制电路，包括：
第二驱动控制子电路，分别与第六节点、第七节点、第八节点、第三电源端以及第四电源端耦接，被配置为根据所述第六节点、所述第七节点以及所述第八节点的信号，产生驱动所述第一发光器件的驱动电流；
第二阈值补偿子电路，分别与第二扫描信号端、所述第六节点以及所述第八节点耦接，被配置为在所述第二扫描信号端的控制下，对所述第二驱动控制子电路进行阈值补偿；
第三发光控制子电路，分别与所述第三电源端、第四电源端、第三发光控制信号端、所述第七节点以及所述第八节点耦接，被配置为在所述第三发光控制信号端的控制下，将所述第三电源端与所述第七节点耦接，将所述第八节点与所述第四电源端耦接；
第二数据写入子电路，分别与所述第二扫描信号端、第二数据信号端以及所述第七节点耦接，被配置为在所述第二扫描信号端的控制下，将所述第二数据信号端的数据信号提供给所述第七节点；
第二存储子电路，分别与所述第三电源端以及所述第六节点耦接，被配置为存储数据信号；
第三复位子电路，分别与所述第六节点、第三复位控制端以及第三参考信号端耦接，被配置为在所述第三复位控制端的控制下，将所述第三参考信号端的信号提供给所述第六节点；
第四复位子电路，分别与所述第一发光器件、第四复位控制端以及第四参考信号端耦接，被配置为在所述第四复位控制端的控制下，将所述第四参考信号端的信号提供给所述第一发光器件。
相应地，本公开实施例还提供了一种显示装置，其中，包括：上述任一显示基板。
可选地，在本公开实施例中，还包括：图像采集器；
所述图像采集器位于所述显示基板的第二显示区域的位置处，且所述图像采集器位于所述显示基板背离出光面的一侧。
相应地，本公开实施例还提供了一种像素驱动电路，其中，所述像素驱动电路被配置为驱动第二发光器件；所述像素驱动电路，包括：
第一驱动控制电路，被配置为产生驱动对应的所述第二发光器件的驱动电流；
第二驱动控制电路，通过第一导线与所述第一驱动控制电路耦接，且所述第二驱动控制电路与对应的所述第二发光器件耦接；被配置为在所述驱动电流传导至所述第二驱动控制电路与所述第一导线之间时，将所述第一驱动控制电路与对应的所述第二发光器件断开一段时间后，将所述第一驱动控制电路与对应的所述第二发光器件导通。
相应地，本公开实施例还提供了一种上述像素驱动电路的驱动方法，其中，包括：
在第一时间段，控制第一驱动控制电路产生驱动对应的第二发光器件的驱动电流，在所述驱动电流传导至第二驱动控制电路与第一导线之间时，控制所述第一驱动控制电路与对应的所述第二发光器件断开；
在第二时间段，控制所述第一驱动控制电路与对应的所述第二发光器件导通。
可选地，在本公开实施例中，所述在第一时间段，控制第一驱动控制电路产生驱动对应的第二发光器件的驱动电流，在所述驱动电流传导至第二驱动控制电路与第一导线之间的节点时，控制所述第一驱动控制电路与对应的所述第二发光器件断开，包括：
在第一子时间段，对第一复位控制端加载有效信号；
在第二子时间段，对第一扫描信号端、第二复位控制端以及第二发光控 制信号端加载有效信号；
在第三子时间段，停止对所述第二发光控制信号端加载有效信号，对第一发光控制信号端加载有效信号。
可选地，在本公开实施例中，在停止对所第二发光控制信号端加载有效信号之后，对所述第一发光控制信号端加载有效信号。
可选地，在本公开实施例中，所述在第二时间段，控制所述第一驱动控制电路与对应的所述第二发光器件导通，包括：
在第二时间段，对第一发光控制信号端和第二发光控制信号端加载有效信号。
附图说明
图1为相关技术中具有屏下摄像头结构的显示装置的平面结构示意图；
图2为第二显示区域中第二发光器件的发光原理示意图；
图3为第二发光器件在低灰阶显示时的电流曲线示意图；
图4为本公开实施例提供的显示基板的平面结构示意图；
图5为本公开实施例中像素驱动电路的结构示意图；
图6为与图5对应的像素驱动电路的具体结构示意图；
图7为本公开实施例中像素驱动电路的另一结构示意图；
图8为与图7对应的像素驱动电路的具体结构示意图；
图9为本公开实施例中第三驱动控制电路的结构示意图；
图10为与图9对应的第三驱动控制电路的具体结构示意图；
图11为本公开实施例提供的上述像素驱动电路流程图；
图12为本公开实施例中像素驱动电路的电路时序图。
具体实施方式
图1为相关技术中具有屏下摄像头结构的显示装置的平面结构示意图，如图1所示，该显示装置包括：显示区域A以及与显示区域A连接的边框区 域B，其中，显示区域A包括第一显示区域A1和第二显示区域A2，摄像头可以设置在第二显示区域A2的位置处。第一显示区域A1中设有多个像素电路P，每一个像素电路P包括第一发光器件及对应的驱动电路，即像素电路P中的驱动电路位于第一发光器件的附近。第二显示区域A2中设有多个第二发光器件EL，用来控制第二发光器件EL发光的像素驱动电路(例如图1中的D_1、D_2)位于边框区域B中，并且，像素驱动电路通过第一导线L与第二发光器件EL耦接，由于第一导线L的负载较大，且各第一导线L的长度不同，导致第二显示区域A2在低灰阶下会出现亮度不均的现象。
图2为第二显示区域中第二发光器件的发光原理示意图，且图2中以像素驱动电路D_1驱动对应的第二发光器件EL为例进行示意，图2中R_L表示第一导线L的电阻，C_L表示第一导线L产生的寄生电容，其中，该寄生电容由第一导线L与其他导电膜层产生，和/或，该寄生电容由第一导线L之间产生。如图2所示，像素驱动电路D_1产生驱动第二发光器件EL的驱动电流，该驱动电流流向第二电源端VSS1时，部分电荷Q 2会充入第一导线产生的寄生电容C_L中，导致流向第二电源端VSS1的电荷Q 1减小，第五节点N5与第二电源端VSS1的压差较小，使第二发光器件EL的亮度降低。第一导线的长度越长，则第一导线产生的寄生电容C_L越大，而第一导线产生的寄生电容C_L越大，在一帧的时间内流向第二电源端VSS1的电荷越少，第二发光器件EL的亮度降低的幅度越大，因此，由于各第一导线的长度不同，导致各第二发光器件EL的亮度降低的幅度不同，从而使第二显示区域的发光均匀性较差。
并且，同样参照图2，第二发光器件EL在低灰阶显示时，驱动电流较小，抬升第五节点N5的电压比较慢，电荷Q 2充入第一导线产生的寄生电容C_L的充电速度较慢，因而，大部分电荷Q 2充入寄生电容C_L中，因此，第二发光器件EL在低灰阶显示时亮度降低的幅度较大，而第二发光器件EL在高灰阶显示时，驱动电流较大，抬升第五节点N5的电压比较快，电荷Q 2充入第一导线产生的寄生电容C_L的充电速度较快，因而，充入第一导线产生的寄 生电容C_L中的电荷Q 2较少，因此，第二发光器件EL在高灰阶显示时亮度降低幅度较小。
图3为第二发光器件在低灰阶显示时的电流曲线示意图，如图3所示，曲线S1表示长度较短的第一导线对应的第二发光器件的电流曲线，曲线S2表示长度较长的第一导线对应的第二发光器件的电流曲线，曲线S1和曲线S2中靠上的拐点表示第二发光器件的起亮时间，从图3中可以明显看出，第一导线的长度越长，对应的第二发光器件的起亮时间越长，该第二发光器件的亮度越低。
基于此，针对相关技术中具有屏下摄像头结构的显示装置中，第二显示区域在低灰阶下会出现亮度不均的现象的问题，本公开实施例提供了一种像素驱动电路、其驱动方法、显示基板及显示装置。
下面结合附图，对本公开实施例提供的像素驱动电路、其驱动方法、显示基板及显示装置的具体实施方式进行详细地说明。附图中各结构的大小和形状不反映真实比例，目的只是示意说明本公开内容。
本公开实施例提供了一种显示基板，图4为本公开实施例提供的显示基板的平面结构示意图，如图4所示，该显示基板包括：显示区域A以及与边框区域B；其中，边框区域B可以与显示区域A一侧的边缘连接；
显示区域A包括：第一显示区域A1和第二显示区域A2；第一显示区域A1包括多个第一发光器件EL＇，图4中，第一显示区域A1中设有多个像素电路P，每一个像素电路P包括第一发光器件EL＇及对应的第三驱动控制电路30，第二显示区域A2包括多个第二发光器件EL(多个第二发光器件分别位于各区域W中)；
显示基板包括：分别与各第二发光器件EL对应耦接的多个像素驱动电路；
图5为本公开实施例中像素驱动电路的结构示意图，同时参照图4和图5，像素驱动电路，包括：位于边框区域B的第一驱动控制电路10，以及位于第二显示区域A2的第二驱动控制电路20(图4中，第二驱动控制电路20位于区域W中，即区域W中设有第二驱动控制电路20及对应的第二发光器件EL)； 第一驱动控制电路10通过第一导线L与第二驱动控制电路20耦接，第二驱动控制电路20与对应的第二发光器件EL耦接；
第一驱动控制电路10，被配置为产生驱动对应的第二发光器件EL的驱动电流；
第二驱动控制电路20，被配置为在驱动电流传导至第二驱动控制电路20与第一导线L之间(如图5中的第五节点N5)时，将第一驱动控制电路10与对应的第二发光器件EL断开一段时间后，将第一驱动控制电路10与对应的第二发光器件EL导通。
本公开实施例提供的显示基板中，通过在第二显示区域中设置第二驱动控制电路，在第一驱动控制电路产生的驱动电流传导至第五节点时，第二驱动控制电路将第一驱动控制电路与对应的第二发光器件断开一端时间，对第一导线产生的寄生电容进行充电，以抬高第五节点的电位，之后，第二驱动控制电路将第一驱动控制电路与对应的第二发光器件导通，可以使流向各第二发光器件的电流基本一致，提高了第二显示区域的亮度均匀性。
本公开实施例提供的显示基板可以为有机电致发光显示基板，即上述第一发光器件和第二发光器件可以为有机发光二极管器件，上述显示基板也可以为其他类型的显示基板，此处不做限定。
在具体实施时，如图4所示，可以将图像采集器设置在第二显示区域A2的位置处，且图像采集器设置在显示基板背离出光面的一侧，例如，该图像采集器可以为摄像头，在图像采集时间段，光线穿过显示基板中相邻的第二发光器件之间的间隙射向图像采集器，图像采集器接收穿过显示基板的光线，从而采集到相应的画面，在实际应用中，可以对显示基板中金属膜层、黑矩阵等不透光的膜层的图形进行改进，在相邻的第二发光器件之间的间隙中形成透光区域，以使光线能够穿过显示基板。此外，也可以采用指纹识别传感器替代图像采集器，以实现屏下指纹识别功能，或者，也可以在第二显示区域中同时设置图像采集器和指纹识别传感器，或者，也可以在第二显示区域中设置其他感光部件，此处不做限定。
可选地，本公开实施例中，上述第一导线可以氧化铟锡(Indium tin oxide，ITO)等透明导电氧化物材料制作，也可以采用其他透明导电材料，此处不做限定。
如图5所示，图5中RC_L表示第一导线的电阻和寄生电容，第一驱动控制电路10通过RC_L与第二驱动控制电路20耦接，具体地，第一驱动控制电路10在第四节点N4处与RC_L耦接，且RC_L在第五节点N5处与第二驱动控制电路20耦接，第二发光器件EL的一端与第二发光控制电路20耦接，另一端与第二电源端VSS1耦接。第一驱动控制电路10产生的驱动电流传导至第五节点N5时，第二驱动控制电路20将第一驱动控制电路10与对应的第二发光器件EL断开一端时间，使驱动电流对第一导线产生的寄生电容进行充电，以抬高第五节点N5的电位，第五节点N5的电位不断上升，使不同的像素驱动电路中的N5节点处的电位趋于一致，之后，第二驱动控制电路20将第一驱动控制电路10与对应的第二发光器件EL导通，由于预先对寄生电容进行了充电，使不同的像素驱动电路中第五节点N5与第二电源端VSS1的压差基本一致，从而使流向各第二发光器件EL的电流基本一致，提高了第二显示区域的亮度均匀性。
可选地，本公开实施例提供的上述显示基板中，如图5所示，第一驱动控制电路10，可以包括：
第一驱动控制子电路101，分别与第一节点N1、第二节点N2、第三节点N3、第一电源端VDD1以及第二电源端VSS1耦接，被配置为根据第一节点N1、第二节点N2以及第三节点N3的信号，产生驱动第二发光器件EL的驱动电流；
第一阈值补偿子电路102，分别与第一扫描信号端Ga1、第一节点N1以及第三节点N3耦接，被配置为在第一扫描信号端Ga1的控制下，对第一驱动控制子电路101进行阈值补偿；
第一发光控制子电路103，分别与第一电源端VDD1、第四节点N4、第一发光控制信号端EM1、第二节点N2以及第三节点N3耦接，被配置为在第 一发光控制信号端EM1的控制下，将第一电源端VDD1与第二节点N2导通，将第三节点N3与第四节点N4导通；第四节点N4为第一发光控制子电路103与第一导线之间的节点；
第一数据写入子电路104，分别与第一扫描信号端Ga1、第一数据信号端Da1以及第二节点N2耦接，被配置为在第一扫描信号端Ga1的控制下，将第一数据信号端Da1的数据信号提供给第二节点N2；
第一存储子电路105，分别与第一电源端VDD1以及第一节点N1耦接，被配置为存储数据信号。
本公开实施例中，通过第一驱动控制子电路101、第一阈值补偿子电路102、第一发光控制子电路103、第一数据写入子电路104及第一存储子电路105的相互配合，可以使第一驱动控制电路10产生驱动第二发光器件EL的驱动电流。
具体地，本公开实施例提供的上述显示基板中，图6为与图5对应的像素驱动电路的具体结构示意图，如图6所示，第一驱动控制子电路101，可以包括：第一开关晶体管T1；
第一开关晶体管T1的控制端g与第一节点N1耦接，第一极s与第二节点N2耦接，第二极d与第三节点N3耦接。
以上仅是举例说明本公开实施例提供的显示基板中第一驱动控制子电路的具体结构，在具体实施时，第一驱动控制子电路的具体结构不限于本公开实施例提供的上述结构，还可以是本领域技术人员可知的其他结构，在此不作限定。
在具体实施时，本公开实施例提供的上述显示基板，如图6所示，第一阈值补偿子电路102，可以包括：第二开关晶体管T2；
第二开关晶体管T2的控制端g与第一扫描信号端Ga1耦接，第一极s与第一节点N1耦接，第二极d与第三节点N3耦接。
以上仅是举例说明本公开实施例提供的显示基板中第一阈值补偿子电路的具体结构，在具体实施时，第一阈值补偿子电路的具体结构不限于本公开 实施例提供的上述结构，还可以是本领域技术人员可知的其他结构，在此不作限定。
可选地，本公开实施例提供的上述显示基板中，如图6所示，第一发光控制子电路103，可以包括：第三开关晶体管T3以及第四开关晶体管T4；
第三开关晶体管T3的控制端g与第一发光控制信号端EM1耦接，第一极s与第一电源端VDD1耦接，第二极d与第二节点N2耦接；
第四开关晶体管T4的控制端g与第一发光控制信号端EM1耦接，第一极s与第三节点N3耦接，第二极d与第四节点N4耦接。
以上仅是举例说明本公开实施例提供的显示基板中第一发光控制子电路的具体结构，在具体实施时，第一发光控制子电路的具体结构不限于本公开实施例提供的上述结构，还可以是本领域技术人员可知的其他结构，在此不作限定。
在实际应用中，本公开实施例提供的上述显示基板中，如图6所示，第一数据写入子电路104，可以包括：第五开关晶体管T5；
第五开关晶体管T5的控制端g与第一扫描信号端Ga1耦接，第一极s与第一数据信号端Da1耦接，第二极d与第二节点N2耦接。
以上仅是举例说明本公开实施例提供的显示基板中第一数据写入子电路的具体结构，在具体实施时，第一数据写入子电路的具体结构不限于本公开实施例提供的上述结构，还可以是本领域技术人员可知的其他结构，在此不作限定。
可选地，本公开实施例提供的上述显示基板中，如图6所示，第一存储子电路105，可以包括：第一电容C1；
第一电容C1的第一电极c1与第一电源端VDD1耦接，第二电极c2与第一节点N1耦接。
以上仅是举例说明本公开实施例提供的显示基板中第一存储子电路的具体结构，在具体实施时，第一存储子电路的具体结构不限于本公开实施例提供的上述结构，还可以是本领域技术人员可知的其他结构，在此不作限定。
在具体实施时，本公开实施例提供的上述显示基板中，如图5所示，第一驱动控制电路10，还可以包括：第一复位子电路106以及第二复位子电路Fw；
第一复位子电路106，分别与第一节点N1、第一复位控制端Re1以及第一参考信号端Vi1耦接，被配置为在第一复位控制端Re1的控制下，将第一参考信号端Vi1的信号提供给第一节点N1，以实现对第一驱动控制子电路101的复位；
第二复位子电路Fw，分别与第二发光器件EL、第二复位控制端Re2以及第二参考信号端Vi2耦接，被配置为在第二复位控制端Re2的控制下，将第二参考信号端Vi2的信号提供给第二发光器件EL，以实现对第二发光器件EL的复位；
第二驱动控制电路20，包括：
第二发光控制子电路201，分别与第一发光控制子电路103、第二发光器件EL以及第二发光控制信号端EM2耦接，被配置为在第二发光控制信号端EM2的控制下，将第一发光控制子电路103与第二发光器件EL导通。通过设置第二发光控制子电路201，可以在第二发光控制信号端EM2的控制下，控制第一发光控制电路103与第二发光器件EL之间的导通关系，从而，驱动电流流向第二发光器件EL之前，实现对第一导线的寄生电容进行预充电，以及在对该寄生电容充电后，控制驱动电流流向第二发光器件EL。在具体实施时，第二发光控制子电路201与对应的第二发光器件EL可以设置在如图4所示的区域W中。
在图5中，第二复位子电路Fw与第四节点N4耦接，即第二复位子电路Fw与第二发光控制子电路201通过第一导线耦接，因而，图5所示的结构中，第二复位子电路Fw位于边框区域中。
图7为本公开实施例中像素驱动电路的另一结构示意图，如图7所示，本公开实施例提供的上述显示基板中，第一驱动控制电路10，包括：
第一复位子电路106，分别与第一节点N1、第一复位控制端Re1以及第 一参考信号端Vi1耦接，被配置为在第一复位控制端Re1的控制下，将第一参考信号端Vi1的信号提供给第一节点N1，以实现对第一驱动控制子电路101的复位；
第二驱动控制电路20，包括：第二复位子电路Fw以及第二发光控制子电路201；
第二复位子电路Fw，分别与第二发光器件EL、第二复位控制端Re2以及第二参考信号端Vi2耦接，被配置为在第二复位控制端Re2的控制下，将第二参考信号端Vi2的信号提供给第二发光器件EL，以实现对第二发光器件EL的复位；
第二发光控制子电路201，分别与第一发光控制子电路103、第二发光器件EL以及第二发光控制信号端EM2耦接，被配置为在第二发光控制信号端EM2的控制下，将第一发光控制子电路103与第二发光器件EL导通。通过设置第二发光控制子电路201，可以在第二发光控制信号端EM2的控制下，控制第一发光控制电路103与第二发光器件EL之间的导通关系，从而，驱动电流流向第二发光器件EL之前，实现对第一导线的寄生电容进行预充电，以及在对该寄生电容充电后，控制驱动电流流向第二发光器件EL。
在图7中，第二复位子电路Fw与第五节点N5耦接，即第二复位子电路Fw与第一发光控制子电路103通过第一导线耦接，因而，图7所示的结构中，第二复位子电路Fw位于第二显示区域中，例如，第二复位子电路Fw、第二发光控制子电路201及对应的第二发光器件EL可以均设置在图4所示的区域W中。
图8为与图7对应的像素驱动电路的具体结构示意图，如图6和图8所示，本公开实施例提供的上述显示基板中，第一复位子电路106，可以包括：第六开关晶体管T6；
第六开关晶体管T6的控制端g与第一复位控制端Re1耦接，第一极s与第一参考信号端Vi1耦接，第二极d与第一节点N1耦接。
以上仅是举例说明本公开实施例提供的显示基板中第一复位子电路的具 体结构，在具体实施时，第一复位子电路的具体结构不限于本公开实施例提供的上述结构，还可以是本领域技术人员可知的其他结构，在此不作限定。
可选地，本公开实施例提供的上述显示基板中，如图6和图8所示，第二复位子电路Fw，可以包括：第七开关晶体管T7；
第七开关晶体管T7的控制端g与第二复位控制端Re2耦接，第一极s与第二参考信号端Vi2耦接，第二极d与第二发光器件EL耦接。
以上仅是举例说明本公开实施例提供的显示基板中第二复位子电路的具体结构，在具体实施时，第二复位子电路的具体结构不限于本公开实施例提供的上述结构，还可以是本领域技术人员可知的其他结构，在此不作限定。
在具体实施时，本公开实施例提供的上述显示基板中，如图6和图8所示，第二发光控制子电路201，可以包括：第八开关晶体管T8；
第八开关晶体管T8的控制端g与第二光控制信号端EM2耦接，第一极s与第一发光控制子电路103耦接，第二极d与第二发光器件EL耦接。
以上仅是举例说明本公开实施例提供的显示基板中第二发光控制子电路的具体结构，在具体实施时，第二发光控制子电路的具体结构不限于本公开实施例提供的上述结构，还可以是本领域技术人员可知的其他结构，在此不作限定。
应该说明的是，在本公开实施例中，上述像素驱动电路中，第一复位子电路106与第二复位子电路Fw连接不同的参考信号端，即第一复位子电路106与第一参考信号端Vi1耦接，第二复位子电路Fw与第二参考信号端Vi2耦接，在具体实施时，第一复位子电路106与第二复位子电路Fw也可以与同一参考信号端耦接，同理，第一复位子电路106与第二复位子电路Fw也可以与同一复位控制端耦接，此处不做限定。
可选地，本公开实施例提供的上述显示基板中，参照图4，还可以包括：分别与各第一发光器件EL＇对应耦接的多个第三驱动控制电路30；
第三驱动控制电路30位于第一显示区域A1内，例如，第三驱动控制电路30可以位于像素电路P内，即第三驱动控制电路30位于对应的第一发光 器件EL＇的附近；
第三驱动控制电路30，被配置为产生驱动对应的第一发光器件EL＇的驱动电流。
本公开实施例中，通过设置分别与各第一发光器件对应耦接的第三驱动控制电路，可以驱动对应的第一发光器件发光，实现画质较好的显示效果。
在具体实施时，本公开实施例提供的上述显示基板中，图9为本公开实施例中第三驱动控制电路的结构示意图，如图9所示，第三驱动控制电路30，可以包括：
第二驱动控制子电路301，分别与第六节点N6、第七节点N7、第八节点N8、第三电源端VDD2以及第四电源端VSS2耦接，被配置为根据第六节点N6、第七节点N7以及第八节点N8的信号，产生驱动第一发光器件EL＇的驱动电流；
第二阈值补偿子电路302，分别与第二扫描信号端Ga2、第六节点N6以及第八节点N8耦接，被配置为在第二扫描信号端Ga2的控制下，对第二驱动控制子电路301进行阈值补偿；
第三发光控制子电路303，分别与第三电源端VDD2、第四电源端VSS2、第三发光控制信号端EM3、第七节点N7以及第八节点N8耦接，被配置为在第三发光控制信号端EM3的控制下，将第三电源端VDD2与第七节点N7耦接，将第八节点N8与第四电源端VSS2耦接；
第二数据写入子电路304，分别与第二扫描信号端Ga2、第二数据信号端Da2以及第七节点N7耦接，被配置为在第二扫描信号端Ga2的控制下，将第二数据信号端Da2的数据信号提供给第七节点N7；
第二存储子电路305，分别与第三电源端VDD2以及第六节点N6耦接，被配置为存储数据信号；
第三复位子电路306，分别与第六节点N6、第三复位控制端Re3以及第三参考信号端Vi3耦接，被配置为在第三复位控制端Re3的控制下，将第三参考信号端Vi3的信号提供给第六节点N6；
第四复位子电路307，分别与第一发光器件EL＇、第四复位控制端Re4以及第四参考信号端Vi4耦接，被配置为在第四复位控制端Re4的控制下，将第四参考信号端Vi4的信号提供给第一发光器件EL＇，例如图中第四复位子电路307在第九节点N9与第一发光器件EL＇耦接。
本公开实施例中，通过第二驱动控制子电路301、第二阈值补偿子电路302、第三发光控制子电路303、第二数据写入子电路304、第二存储子电路305、第三复位子电路306及第四复位子电路307的相互配合，可以使第二驱动控制电路30产生驱动第一发光器件EL＇的驱动电流。
具体地，本公开实施例提供的上述显示基板中，图10为与图9对应的第三驱动控制电路的具体结构示意图，如图10所示，第二驱动控制子电路301，可以包括：第十一开关晶体管T11；
第十一开关晶体管T11的控制端g与第六节点N6耦接，第一极s与第七节点N7耦接，第二极d与第八节点N8耦接。
第二阈值补偿子电路302，可以包括：第十二开关晶体管T12；
第十二开关晶体管T12的控制端g与第二扫描信号端Ga2耦接，第一极s与第六节点N6耦接，第二极d与第八节点N8耦接。
第三发光控制子电路303，可以包括：第十三开关晶体管T13以及第十四开关晶体管T14；
第十三开关晶体管T13的控制端g与第三发光控制信号端EM3耦接，第一极s与第三电源端VDD2耦接，第二极d与第七节点N7耦接；
第十四开关晶体管T14的控制端g与第三发光控制信号端EM3耦接，第一极s与第八节点N8耦接，第二极d与第四电源端VSS2耦接。
第二数据写入子电路304，可以包括：第十五开关晶体管T15；
第十五开关晶体管T15的控制端g与第二扫描信号端Ga2耦接，第一极s与第二数据信号端Da2耦接，第二极d与第七节点N7耦接。
第二存储子电路305，可以包括：第二电容C2；
第二电容C2的第一电极c3与第三电源端VDD2耦接，第二电极c4与第 六节点N6耦接。
第三复位子电路306，分别与第六节点N6、第三复位控制端Re3以及第三参考信号端Vi3耦接，被配置为在第三复位控制端Re3的控制下，将第三参考信号端Vi3的信号提供给第六节点N6，以实现对第二驱动控制子电路301的复位；
第二复位子电路307，分别与第一发光器件EL＇、第四复位控制端Re4以及第四参考信号端Vi4耦接，被配置为在第四复位控制端Re4的控制下，将第四参考信号端Vi4的信号提供给第一发光器件EL＇，以实现对第一发光器件EL＇的复位。
以上仅是举例说明本公开实施例提供的显示基板中第二驱动控制子电路、第二阈值补偿子电路、第三发光控制子电路、第二数据写入子电路、第二存储子电路、第三复位子电路及第四复位子电路的具体结构，在具体实施时，上述各子电路的具体结构不限于本公开实施例提供的上述结构，还可以是本领域技术人员可知的其他结构，在此不作限定。
应该说明的是，在本公开实施例中，上述第三驱动控制电路中，第三复位子电路306与第四复位子电路307连接不同的参考信号端，即第三复位子电路306与第三参考信号端Vi3耦接，第四复位子电路307与第四参考信号端Vi4耦接，在具体实施时，第三复位子电路306与第四复位子电路307也可以与同一参考信号端耦接，同理，第三复位子电路306与第四复位子电路307也可以与同一复位控制端耦接，此处不做限定。
基于同一发明构思，本公开实施例还提供了一种显示装置，包括上述显示基板，该显示装置可以应用于手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。由于该显示装置解决问题的原理与上述显示基板相似，因此该显示装置的实施可以参见上述显示基板的实施，重复之处不再赘述。
可选地，本公开实施例提供的上述显示装置中，还可以包括：图像采集器；
图像采集器位于显示基板的第二显示区域的位置处，且图像采集器位于显示基板背离出光面的一侧。
在具体实施时，该图像采集器可以为摄像头，在图像采集时间段，光线穿过显示基板中相邻的第二发光器件之间的间隙射向图像采集器，图像采集器接收穿过显示基板的光线，从而采集到相应的画面，在实际应用中，可以对显示基板中金属膜层、黑矩阵等不透光的膜层的图形进行改进，在相邻的第二发光器件之间的间隙中形成透光区域，以使光线能够穿过显示基板。此外，也可以采用指纹识别传感器替代图像采集器，以实现屏下指纹识别功能，或者，也可以在第二显示区域中同时设置图像采集器和指纹识别传感器，此处不做限定。
基于同一发明构思，本公开实施例还提供了一种像素驱动电路，由于该像素驱动电路解决问题的原理与上述显示基板相似，因此该像素驱动电路的实施可以参见上述显示基板的实施，重复之处不再赘述。
本公开实施例提供的像素驱动电路，如图5所示，像素驱动电路被配置为驱动第二发光器件EL；该像素驱动电路，可以包括：
第一驱动控制电路10，被配置为产生驱动对应的第二发光器件EL的驱动电流；
第二驱动控制电路20，通过第一导线与第一驱动控制电路10耦接，且第二驱动控制电路20与对应的第二发光器件EL耦接；被配置为在驱动电流传导至第二驱动控制电路20与第一导线之间时，将第一驱动控制电路10与对应的第二发光器件EL断开一段时间后，将第一驱动控制电路10与对应的第二发光器件20导通。
本公开实施例中，通过设置第二驱动控制电路，在第一驱动控制电路产生的驱动电流传导至第五节点时，第二驱动控制电路将第一驱动控制电路与对应的第二发光器件断开一端时间，对第一导线产生的寄生电容进行充电，以抬高第五节点的电位，之后，第二驱动控制电路将第一驱动控制电路与对应的第二发光器件导通，可以使流向各第二发光器件的电流基本一致，提高 了第二显示区域的亮度均匀性。
基于同一发明构思，本公开实施例还提供了一种上述像素驱动电路的驱动方法，由于该驱动方法解决问题的原理与上述像素驱动电路相似，因此该驱动方法的实施可以参见上述像素驱动电路的实施，重复之处不再赘述。
本公开实施例提供的上述像素驱动电路的驱动方法，如图11所示，包括：
S401、在第一时间段，控制第一驱动控制电路产生驱动对应的第二发光器件的驱动电流，在驱动电流传导至第二驱动控制电路与第一导线之间时，控制第一驱动控制电路与对应的第二发光器件断开；
S402、在第二时间段，控制第一驱动控制电路与对应的第二发光器件导通。
本公开实施例提供的驱动方法中，在第一时间段，在驱动电流传导至第二驱动控制电路与第一导线之间(即第五节点)时，控制第一驱动控制电路与对应的第二发光器件断开，以对第一导线产生的寄生电容进行充电，以抬高第五节点的电位，在第二时间段，控制第一驱动控制电路与对应的第二发光器件导通，可以使流向各第二发光器件的电流基本一致，提高了第二显示区域的亮度均匀性。
下面以图5至图8所示的像素驱动电路为例，结合图12所示的电路时序图对本公开实施例提供的上述驱动方法进行详细说明。
在具体实施时，本公开实施例提供的上述驱动方法中，上述步骤S401，可以包括：
在第一子时间段t1，对第一复位控制端Re1加载有效信号，以将第一参考信号端Vi1的信号提供给第一节点N1，以实现对第一驱动控制子电路101的复位；
在第二子时间段t2，对第一扫描信号端Ga1、第二复位控制端Re以及第二发光控制信号端EM2加载有效信号。第一扫描信号端Ga1加载有效信号，在第一扫描信号端Ga1的控制下，第一阈值补偿子电路102对第一驱动控制子电路101进行阈值补偿，并将第一数据信号端Da1的数据信号提供给第二 节点N2。第二复位控制端Re2和第二发光控制信号端EM2加载有效信号，在第二发光控制信号端EM2的控制下，第四节点N4(或第五节点N5)与第二发光器件EL导通，在第二复位控制端Re2的控制下，第二参考信号端Vi2的信号提供给第二发光器件EL，使第二发光器件EL复位；
在第三子时间段t3，停止对第二发光控制信号端EM2加载有效信号，对第一发光控制信号端EM1加载有效信号，从而，使第一发光控制电路103与第二发光器件EL断开，以对第一导线产生的寄生电容进行充电，以抬高第五节点N5的电位。
进一步地，在上述步骤S401中，在停止对所第二发光控制信号端EM2加载有效信号之后，对第一发光控制信号端EM1加载有效信号，这样，可以避免对第一导线产生的寄生电容充电的过程中产生漏电，否则，开始对第一发光控制信号端EM1加载有效信号的一小段时间内，电流会流过第二发光器件EL而发光，尤其在高灰阶显示时，由于驱动电流较大，会明显看到第二发光器件EL在第一时间段中亮一下。具体地，可以在第二子时间段t2内，对第二发光控制信号端EM2加载有效信号一段时间后，停止对第二发光控制信号端EM2加载有效信号，在第三子时间段t3再对第一发光控制信号端EM1加载有效信号，或者，也可以在第三子时间段t3内，先停止对第二发光控制信号端EM2加载有效信号，再对第一发光控制信号端EM1加载有效信号。
在具体实施时，本公开实施例提供的上述驱动方法中，上述步骤S402，可以包括：
在第二时间段t4，对第一发光控制信号端EM1和第二发光控制信号端EM2加载有效信号，从而控制第一驱动控制电路与对应的第二发光器件导通，以使第二发光器件发光。
以下以图6和图8所示的像素驱动电路为例，结合图12所示的电路时序图，对本公开实施例提供的显示基板的工作过程进行描述。其中，以图6至图8中的各开关晶体管为P型晶体管为例，即以低电平为有效信号为例进行说明。
图12中，re1表示第一复位控制端Re1加载的信号，re2表示第二复位控制端Re2加载的信号，ga表示第一扫描信号端Ga1加载的信号，em1表示第一发光控制信号端EM1加载的信号，em2表示第二发光控制信号端EM2加载的信号。
在第一子时间段t1中，第一复位控制端Re1加载的信号re1为低电平，使第六开关晶体管T6导通，第一参考信号端Vi1的信号提供给第一节点N1，以对第一开关晶体管T1的控制端进行复位。
在第二子时间段t2中，第一扫描信号端Ga1加载的信号ga为低电平，使第二开关晶体管T2和第五开关晶体管T5导通，第五开关晶体管T5导通，使第一数据信号端Da1的数据信号提供给第二节点N2，第二开关晶体管T2导通，使第一节点N1与第三节点N3导通，进而使第一开关晶体管T1导通，使数据信号充入第一节点N1，并且，第二复位控制端Re2加载的信号re2为低电平，使第七开关晶体管T7导通，第二参考信号端Vi2的信号提供给第四节点N4和第五节点N5，以对第四节点N4和第五节点N5进行复位，同时，第二发光控制信号端EM2加载的信号em2也为低电平，使第八开关晶体管T8导通，第二参考信号端Vi2的信号提供给第二发光器件EL，以实现对第二发光器件EL的复位。
在第三子时间段t3中，第一发光控制信号端EM1加载的信号em1为低电平，第三开光晶体管T3和第四开关晶体管T4导通，以使第一电源端VDD1与第二节点N2导通，第三节点N3与第四节点N4导通，第三开关晶体管T3使第一电源端VDD1的电压提供给第一开关晶体管T1的第一极s，使第一开关晶体管T1产生驱动电流，并且，第二发光控制信号端EM2加载的信号em2为高电平，第八开光晶体管T8截止，使驱动电流持续冲入第一导线产生的寄生电容中，第四节点N4和第五节点N5的电压不断上升，寄生电容充满后，使各像素驱动电路中的第四节点N4(或第五节点N5)的电压趋于一致。
此外，为了避免对第一导线产生的寄生电容的充电过程中产生漏电，可以在第二子时间段t2中，对第二发光控制信号端EM2加载低电平信号一段时 间后，向第二发光控制信号端EM2加载高电平信号，在第三子时间段t3中，向第一发光控制信号端EM1加载低电平信号；或者，也可以在第三子时间段t3中，先对第二发光控制信号端EM2加载高电平信号，再向第一发光控制信号端EM1加载低电平信号。
在第四子时间段t4中，第一发光控制信号端EM1加载的信号em1为低电平，第二发光控制信号端EM2加载的信号em2为低电平，从而使驱动电流流向第二发光器件EM，使第二发光器件EM发光。由于在第三子时间段t3中对第一导线产生的寄生电容进行了预充电，使第四节点N4(或第五节点N5)与第二电源端VSS1的压差较大，从而使一帧时间内的平均电流较大，避免出现第二发光器件EL延迟起亮的现象，改善了第二显示区域在低灰阶画面显示不均匀的现象。
在具体实施时，也可以结合对第一导线的寄生电容进行补偿的其他方法，以进一步消除第一导线的电阻和寄生电容对显示效果的影响。
此外，本公开实施例提供的显示基板、其驱动方法及显示装置，在改善第二显示区域低灰阶显示亮度不均匀的基础上，不会对影响第二显示区域高灰阶的显示效果，以下以两个对比例进行对比分析。
对比例一：由于绿色像素的发光效率较高，在相同的灰阶下，绿色像素的电流最小，因而，以绿色像素的显示效果来反映低灰阶显示效果，表1表示第三子时间段的时长、第一导线的负载与第二发光器件的电流的对应关系，如表1所示，表1中“G＝5.1V”表示第一电源端与第二电源端的压差为5.1V，表1中第一导线的最大电阻为896kΩ，即100％对应的电阻为896kΩ，第一导线的寄生电容的最大值为3.6pF，从表1可以明显看出，第三子时间段t3的时长在200μs到2ms之间变化时，第一导线的电阻不同，则第二发光器件的电流的差异不超过2％，在伽马(Gamma)电压的调试范围内，第三子时间段t3的时长为0时，第二发光器件的电流差异明显，反应为第二显示区域在低灰阶显示时亮度均匀性较差，因此，第二显示区域在低灰阶显示时，可以通过调整第三子时间段t3的时长，来改善由于第一导线引起的第二显示区域 的亮度不均，并且，在改善第二显示区域的亮度均匀性的基础上，尽量缩短第三子时间段t3的时长，避免影响第四子时间段t4的发光效果。
表1
Figure PCTCN2020120484-appb-000001
对比例二：由于蓝色像素的发光效率较低，在相同的灰阶下，蓝色像素的电流较大，因而，以蓝色像素的显示效果来反映高灰阶显示效果，表2表示第三子时间段的时长、第一导线的负载与第二发光器件的电流的对应关系，如表2所示，表2中“B＝2.8V”表示第一电源端与第二电源端的压差为2.8V，表2中第一导线的最大电阻为896kΩ，即100％对应的电阻为896kΩ，第一导线的寄生电容的最大值为3.6pF，从表2可以明显看出，第三子时间段t3的时长在0到2ms之间变化时，第一导线的电阻不同，则第二发光器件的电流的差异不超过2％，在伽马(Gamma)电压的调试范围内，并且，虽然，第三子时间段t3的时长不同，第二发光器件的电流不同，但第三子时间段t3的时长固定时，第二发光器件的电流均一性较好。因此，第三子时间段t3不会影响第二显示区域高灰阶的显示效果。
表2
Figure PCTCN2020120484-appb-000002
本公开实施例提供的像素驱动电路、其驱动方法、显示基板及显示装置中，通过在第二显示区域中设置第二驱动控制电路，在第一驱动控制电路产 生的驱动电流传导至第五节点时，第二驱动控制电路将第一驱动控制电路与对应的第二发光器件断开一端时间，对第一导线产生的寄生电容进行充电，以抬高第五节点的电位，之后，第二驱动控制电路将第一驱动控制电路与对应的第二发光器件导通，可以使流向各第二发光器件的电流基本一致，提高了第二显示区域的亮度均匀性。
尽管已描述了本公开的优选实施例，但本领域内的技术人员一旦得知了基本创造性概念，则可对这些实施例作出另外的变更和修改。所以，所附权利要求意欲解释为包括优选实施例以及落入本公开范围的所有变更和修改。
显然，本领域的技术人员可以对本公开实施例进行各种改动和变型而不脱离本公开实施例的精神和范围。这样，倘若本公开实施例的这些修改和变型属于本公开权利要求及其等同技术的范围之内，则本公开也意图包含这些改动和变型在内。

Claims (21)

  1. 一种显示基板，其中，所述显示基板包括：显示区域以及边框区域；
    所述显示区域包括：第一显示区域和第二显示区域；所述第一显示区域包括多个第一发光器件，所述第二显示区域包括多个第二发光器件；
    所述显示基板包括：分别与各所述第二发光器件对应耦接的多个像素驱动电路；
    所述像素驱动电路，包括：位于所述边框区域的第一驱动控制电路，以及位于所述第二显示区域的第二驱动控制电路；所述第一驱动控制电路通过第一导线与所述第二驱动控制电路耦接，所述第二驱动控制电路与对应的所述第二发光器件耦接；
    所述第一驱动控制电路，被配置为产生驱动对应的所述第二发光器件的驱动电流；
    所述第二驱动控制电路，被配置为在所述驱动电流传导至所述第二驱动控制电路与所述第一导线之间时，将所述第一驱动控制电路与对应的所述第二发光器件断开一段时间后，将所述第一驱动控制电路与对应的所述第二发光器件导通。
  2. 如权利要求1所述的显示基板，其中，所述第一驱动控制电路，包括：
    第一驱动控制子电路，分别与第一节点、第二节点、第三节点、第一电源端以及第二电源端耦接，被配置为根据所述第一节点、所述第二节点以及所述第三节点的信号，产生驱动所述第二发光器件的驱动电流；
    第一阈值补偿子电路，分别与第一扫描信号端、所述第一节点以及所述第三节点耦接，被配置为在所述第一扫描信号端的控制下，对所述第一驱动控制子电路进行阈值补偿；
    第一发光控制子电路，分别与所述第一电源端、第四节点、第一发光控制信号端、所述第二节点以及所述第三节点耦接，被配置为在所述第一发光控制信号端的控制下，将所述第一电源端与所述第二节点导通，将所述第三 节点与所述第四节点导通；
    第一数据写入子电路，分别与所述第一扫描信号端、第一数据信号端以及所述第二节点耦接，被配置为在所述第一扫描信号端的控制下，将所述第一数据信号端的数据信号提供给所述第二节点；
    第一存储子电路，分别与所述第一电源端以及所述第一节点耦接，被配置为存储数据信号。
  3. 如权利要求2所述的显示基板，其中，所述第一驱动控制子电路，包括：第一开关晶体管；
    所述第一开关晶体管的控制端与所述第一节点耦接，第一极与所述第二节点耦接，第二极与所述第三节点耦接。
  4. 如权利要求2所述的显示基板，其中，所述第一阈值补偿子电路，包括：第二开关晶体管；
    所述第二开关晶体管的控制端与所述第一扫描信号端耦接，第一极与所述第一节点耦接，第二极与所述第三节点耦接。
  5. 如权利要求2所述的显示基板，其中，所述第一发光控制子电路，包括：第三开关晶体管以及第四开关晶体管；
    所述第三开关晶体管的控制端与所述第一发光控制信号端耦接，第一极与所述第一电源端耦接，第二极与所述第二节点耦接；
    所述第四开关晶体管的控制端与所述第一发光控制信号端耦接，第一极与所述第三节点耦接，第二极与所述第四节点耦接。
  6. 如权利要求2所述的显示基板，其中，所述第一数据写入子电路，包括：第五开关晶体管；
    所述第五开关晶体管的控制端与所述第一扫描信号端耦接，第一极与所述第一数据信号端耦接，第二极与所述第二节点耦接。
  7. 如权利要求2所述的显示基板，其中，所述第一存储子电路，包括：第一电容；
    所述第一电容的第一电极与所述第一电源端耦接，第二电极与所述第一 节点耦接。
  8. 如权利要求2所述的显示基板，其中，所述第一驱动控制电路，还包括：第一复位子电路以及第二复位子电路；
    所述第一复位子电路，分别与所述第一节点、第一复位控制端以及第一参考信号端耦接，被配置为在所述第一复位控制端的控制下，将所述第一参考信号端的信号提供给所述第一节点；
    所述第二复位子电路，分别与所述第二发光器件、第二复位控制端以及第二参考信号端耦接，被配置为在所述第二复位控制端的控制下，将所述第二参考信号端的信号提供给所述第二发光器件；
    所述第二驱动控制电路，包括：
    第二发光控制子电路，分别与所述第一发光控制子电路、所述第二发光器件以及第二发光控制信号端耦接，被配置为在所述第二发光控制信号端的控制下，将所述第一发光控制电路与所述第二发光器件导通。
  9. 如权利要求2所述的显示基板，其中，所述第一驱动控制电路，包括：
    第一复位子电路，分别与所述第一节点、第一复位控制端以及第一参考信号端耦接，被配置为在所述第一复位控制端的控制下，将所述第一参考信号端的信号提供给所述第一节点；
    所述第二驱动控制电路，包括：第二复位子电路以及第二发光控制子电路；
    所述第二复位子电路，分别与所述第二发光器件、第二复位控制端以及第二参考信号端耦接，被配置为在所述第二复位控制端的控制下，将所述第二参考信号端的信号提供给所述第二发光器件；
    所述第二发光控制子电路，分别与所述第一发光控制子电路、所述第二发光器件以及第二发光控制信号端耦接，被配置为在所述第二发光控制信号端的控制下，将所述第一发光控制子电路与所述第二发光器件导通。
  10. 如权利要求8或9所述的显示基板，其中，所述第一复位子电路，包括：第六开关晶体管；
    所述第六开关晶体管的控制端与所述第一复位控制端耦接，第一极与所述第一参考信号端耦接，第二极与所述第一节点耦接。
  11. 如权利要求8或9所述的显示基板，其中，所述第二复位子电路，包括：第七开关晶体管；
    所述第七开关晶体管的控制端与所述第二复位控制端耦接，第一极与所述第二参考信号端耦接，第二极与所述第二发光器件耦接。
  12. 如权利要求8或9所述的显示基板，其中，所述第二发光控制子电路，包括：第八开关晶体管；
    所述第八开关晶体管的控制端与所述第二光控制信号端耦接，第一极与所述第一发光控制子电路耦接，第二极与所述第二发光器件耦接。
  13. 如权利要求1～12任一项所述的显示基板，其中，还包括：分别与各所述第一发光器件对应耦接的多个第三驱动控制电路；
    所述第三驱动控制电路位于所述第一显示区域内；
    所述第三驱动控制电路，被配置为产生驱动对应的所述第一发光器件的驱动电流。
  14. 如权利要求13所述的显示基板，其中，所述第三驱动控制电路，包括：
    第二驱动控制子电路，分别与第六节点、第七节点、第八节点、第三电源端以及第四电源端耦接，被配置为根据所述第六节点、所述第七节点以及所述第八节点的信号，产生驱动所述第一发光器件的驱动电流；
    第二阈值补偿子电路，分别与第二扫描信号端、所述第六节点以及所述第八节点耦接，被配置为在所述第二扫描信号端的控制下，对所述第二驱动控制子电路进行阈值补偿；
    第三发光控制子电路，分别与所述第三电源端、第四电源端、第三发光控制信号端、所述第七节点以及所述第八节点耦接，被配置为在所述第三发光控制信号端的控制下，将所述第三电源端与所述第七节点耦接，将所述第八节点与所述第四电源端耦接；
    第二数据写入子电路，分别与所述第二扫描信号端、第二数据信号端以及所述第七节点耦接，被配置为在所述第二扫描信号端的控制下，将所述第二数据信号端的数据信号提供给所述第七节点；
    第二存储子电路，分别与所述第三电源端以及所述第六节点耦接，被配置为存储数据信号；
    第三复位子电路，分别与所述第六节点、第三复位控制端以及第三参考信号端耦接，被配置为在所述第三复位控制端的控制下，将所述第三参考信号端的信号提供给所述第六节点；
    第四复位子电路，分别与所述第一发光器件、第四复位控制端以及第四参考信号端耦接，被配置为在所述第四复位控制端的控制下，将所述第四参考信号端的信号提供给所述第一发光器件。
  15. 一种显示装置，其中，包括：如权利要求1～14任一项所述的显示基板。
  16. 如权利要求15所述的显示装置，其中，还包括：图像采集器；
    所述图像采集器位于所述显示基板的第二显示区域的位置处，且所述图像采集器位于所述显示基板背离出光面的一侧。
  17. 一种像素驱动电路，其中，所述像素驱动电路被配置为驱动第二发光器件；所述像素驱动电路，包括：
    第一驱动控制电路，被配置为产生驱动对应的所述第二发光器件的驱动电流；
    第二驱动控制电路，通过第一导线与所述第一驱动控制电路耦接，且所述第二驱动控制电路与对应的所述第二发光器件耦接；被配置为在所述驱动电流传导至所述第二驱动控制电路与所述第一导线之间时，将所述第一驱动控制电路与对应的所述第二发光器件断开一段时间后，将所述第一驱动控制电路与对应的所述第二发光器件导通。
  18. 一种如权利要求17所述的像素驱动电路的驱动方法，其中，包括：
    在第一时间段，控制第一驱动控制电路产生驱动对应的第二发光器件的 驱动电流，在所述驱动电流传导至第二驱动控制电路与第一导线之间时，控制所述第一驱动控制电路与对应的所述第二发光器件断开；
    在第二时间段，控制所述第一驱动控制电路与对应的所述第二发光器件导通。
  19. 如权利要求18所述的驱动方法，其中，所述在第一时间段，控制第一驱动控制电路产生驱动对应的第二发光器件的驱动电流，在所述驱动电流传导至第二驱动控制电路与第一导线之间的节点时，控制所述第一驱动控制电路与对应的所述第二发光器件断开，包括：
    在第一子时间段，对第一复位控制端加载有效信号；
    在第二子时间段，对第一扫描信号端、第二复位控制端以及第二发光控制信号端加载有效信号；
    在第三子时间段，停止对所述第二发光控制信号端加载有效信号，对第一发光控制信号端加载有效信号。
  20. 如权利要求19所述的驱动方法，其中，在停止对所第二发光控制信号端加载有效信号之后，对所述第一发光控制信号端加载有效信号。
  21. 如权利要求18所述的驱动方法，其中，所述在第二时间段，控制所述第一驱动控制电路与对应的所述第二发光器件导通，包括：
    在第二时间段，对第一发光控制信号端和第二发光控制信号端加载有效信号。
PCT/CN2020/120484 2020-09-29 2020-10-12 像素驱动电路、其驱动方法、显示基板及显示装置 WO2022067877A1 (zh)

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