WO2022062776A1 - 交流电阻检测电路及系统 - Google Patents

交流电阻检测电路及系统 Download PDF

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Publication number
WO2022062776A1
WO2022062776A1 PCT/CN2021/113288 CN2021113288W WO2022062776A1 WO 2022062776 A1 WO2022062776 A1 WO 2022062776A1 CN 2021113288 W CN2021113288 W CN 2021113288W WO 2022062776 A1 WO2022062776 A1 WO 2022062776A1
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Prior art keywords
signal
module
detection circuit
resistance detection
resistance
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PCT/CN2021/113288
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English (en)
French (fr)
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夏虎
吴春达
王冬峰
刘桂芝
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上海南麟电子股份有限公司
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Priority to US18/028,570 priority Critical patent/US11828778B2/en
Publication of WO2022062776A1 publication Critical patent/WO2022062776A1/zh

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R27/00—Arrangements for measuring resistance, reactance, impedance, or electric characteristics derived therefrom
    • G01R27/02—Measuring real or complex resistance, reactance, impedance, or other two-pole characteristics derived therefrom, e.g. time constant

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  • the invention relates to the field of circuit design, in particular to an alternating current resistance detection circuit and system.
  • the existing AC resistance detection circuit When the existing AC resistance detection circuit is used, it is necessary to distinguish between the neutral wire and the live wire. If two detection circuits are connected to the AC power grid in parallel, and the neutral and live wires are cross-connected, it may cause the current output by one detection circuit to enter the other detection circuit, causing the detection circuit to output an incorrect detection signal.
  • the current solution is to strictly distinguish between the neutral wire and the live wire when detecting the circuit wiring, so as to avoid the mixed connection of the neutral wire and the live wire. This often causes trouble for the user and increases the probability of error.
  • the purpose of the present invention is to provide an AC resistance detection circuit and system, which is used to solve the need to strictly distinguish between the neutral wire and the live wire when two detection circuits are connected in parallel to the power grid in the prior art, and then This causes trouble for the user and increases the probability of error.
  • the present invention provides an AC resistance detection circuit, the AC resistance detection circuit at least includes:
  • Working state control module sampling module, comparison module, counting signal generation module, clearing module and counting module;
  • the working state control module receives the oscillation signal and generates the working state control signal, and controls the working state to alternately switch between the detection state and the waiting state;
  • the first end and the second end of the sampling module are respectively connected to the neutral wire and the live wire, and the control end is connected to the output end of the working state control module.
  • the resistance between the neutral wire and the live wire is sampled and output. sampling signal;
  • the comparison module receives the reference signal and is connected to the output end of the sampling module, compares the sampling signal with the reference signal, and outputs a corresponding comparison result;
  • the counting signal generating module receives the oscillating signal and is connected to the output end of the working state control module, and outputs the oscillating signal as a counting signal in the detection state;
  • the clearing module is connected to the output end of the comparison module and the working state control module, and outputs an effective clearing signal when the resistance between the zero wire and the live wire is greater than a threshold in the detection state;
  • the counting module is connected to the output end of the counting signal generating module and the clearing module, realizes counting based on the counting signal and the clearing signal, and outputs a high level when the count value reaches a preset value;
  • the preset value is greater than the number of cycles of the oscillation signal in one cycle of the detection state.
  • the working state control module includes a frequency divider and an inverter; the frequency divider receives the oscillating signal and divides the frequency of the oscillating signal; the inverter is connected to the frequency dividing The output terminal of the frequency divider inverts the output signal of the frequency divider and outputs the working state control signal.
  • the counting signal generating module includes an AND logic unit, the input ends of the AND logic unit are respectively connected to the oscillation signal and the working state control signal, and the counting signal is generated after performing an AND operation.
  • the clearing module includes an OR logic unit, the input terminal of the OR logic unit is respectively connected to the inverse signal of the working state control signal and the comparison result, and the clearing signal is generated after an OR operation.
  • the sampling module includes a triode, a first resistor, a second resistor and a third resistor; the triode and the first resistor are connected in series between the power supply voltage and the first end of the sampling module, so The second resistor and the third resistor are connected in series between the second end of the sampling module and the ground; wherein, the base of the triode is connected to the working state control module, and the second resistor is connected to the ground.
  • the connection node of the third resistor outputs the sampling signal.
  • the reference signal satisfies the following relationship:
  • Vref is the reference signal
  • Vdd is the power supply voltage
  • R1 is the resistance value of the first resistor
  • R2 is the resistance value of the second resistor
  • R3 is the resistance value of the third resistor.
  • the AC resistance detection circuit further includes a frequency jittering module and an oscillator; the oscillator is connected to the output end of the frequency jittering module, and generates the oscillating signal, and the frequency of the oscillating signal is preset. jitter in the frequency range.
  • the present invention also provides an alternating current resistance detection system, the alternating current resistance detection system at least includes:
  • the present invention also provides an alternating current resistance detection system, the alternating current resistance detection system at least includes:
  • the AC resistance detection circuit and system of the present invention have the following beneficial effects:
  • FIG. 1 is a schematic structural diagram of an AC resistance detection circuit of the present invention.
  • FIG. 2 is a schematic diagram showing the working principle of the AC resistance detection circuit of the present invention.
  • FIG. 3 is a schematic structural diagram of an AC resistance detection circuit.
  • FIG. 4 is a schematic diagram showing the reverse mixed connection of the neutral wire and the live wire of the two AC resistance detection circuits of FIG. 3 .
  • FIG. 5 is a schematic structural diagram of the reverse mixed connection of the neutral wire and the live wire of the two AC resistance detection circuits of the present invention.
  • FIG. 6 is a schematic diagram showing the working principle of the reverse mixed connection of the neutral wire and the live wire of the two AC resistance detection circuits of the present invention.
  • this embodiment provides an AC resistance detection circuit 1 , and the AC resistance detection circuit 1 includes:
  • the working state control module 11 The working state control module 11 , the sampling module 12 , the comparison module 13 , the counting signal generating module 14 , the zero-clearing module 15 and the counting module 16 .
  • the working state control module 11 receives the oscillating signal CLK1 and generates the working state control signal CLK2N to control the working state to alternately switch between the detection state and the waiting state.
  • the working state control module 11 includes a frequency divider 111 and an inverter 112 .
  • the frequency divider 111 receives the oscillating signal CLK1 and divides the frequency of the oscillating signal CLK1.
  • the frequency divider is used to realize frequency division by sixteen.
  • the inverter 112 is connected to the output end of the frequency divider 111 , inverts the output signal CLK2 of the frequency divider 111 and outputs the working state control signal CLK2N.
  • the working state control signal CLK2N is at a high level, the AC resistance detection circuit 1 is controlled to work in the detection state, and the resistance Rx between the neutral wire and the live wire is detected, and Rx includes the power grid line and other connections.
  • Equivalent resistance of the electrical equipment connected to the power grid when the working state control signal CLK2N is at a low level, the AC resistance detection circuit 1 is controlled to work in a waiting state, and the resistance Rx between the neutral wire and the live wire is not detected.
  • the working state of the AC resistance detection circuit 1 is periodically switched between the detection state and the waiting state, and the duration of one detection state is equal to the duration of the low level of the output signal CLK2 of the frequency divider 111, which is denoted as a detection state. cycle.
  • the oscillation signal CLK1 is generated by an oscillator 17, and the input end of the oscillator 17 is connected to the output end of the frequency jittering module 18, and the frequency jittering module 18 is in A low-frequency variable is added to the oscillating signal generated by the oscillator 17, so that the frequency of the final output oscillating signal CLK1 is not always fixed, but jitters and changes within a preset frequency range; the low-frequency variable can be based on the preset frequency.
  • the frequency range is set for setting, which will not be repeated here.
  • the first terminal VL and the second terminal VN of the sampling module 12 are respectively connected to the neutral wire and the live wire, and the control terminal is connected to the output terminal of the working state control module 11 .
  • the resistance between the live wires is sampled, and the sampled signal Vdet is output.
  • the sampling module 12 includes a transistor Q1, a first resistor R1, a second resistor R2 and a third resistor R3.
  • the transistor Q1 and the first resistor R1 are connected in series between the power supply voltage Vdd and the first terminal VL of the sampling module 12 , and the base of the transistor Q1 is connected to the output end of the working state control module 11 ;
  • the collector of the transistor Q1 is connected to the power supply voltage Vdd
  • the emitter is connected to the first terminal VL of the sampling module 12 via the first resistor
  • the base is connected to the output of the working state control module 11 State control signal CLK2N; when the working state control signal CLK2N is at a high level, the transistor Q1 is turned on, and when the working state control signal CLK2N is at a low level, the transistor Q1 is turned off.
  • the second resistor R2 and the third resistor R3 are connected in series between the second terminal VN of the sampling module 12 and the ground, and the connection node of the
  • the sampling signal Vdet is 0.
  • the transistor Q1 is turned on, and it can be approximately considered that the collector and emitter voltages of the transistor Q1 are equal; at this time, the current output by the power supply voltage Vdd sequentially passes through the transistor Q1 and the resistors R1, Rx, R2, R3, The sampling signal Vdet satisfies:
  • the comparison module 13 receives the reference signal Vref and is connected to the output terminal of the sampling module 12 , compares the sampling signal Vdet with the reference signal Vref and outputs a corresponding comparison result CMP.
  • the non-inverting input terminal of the comparison module 13 is connected to the sampling signal Vdet, and the inverting input terminal is connected to the reference signal Vref.
  • the connection relationship between the input signal and the input terminals of different polarities can be adjusted by adding an inverter, so that the same logic relationship can be achieved, which is not limited to this embodiment.
  • the threshold Rth satisfies: If Vdet>Vref, the comparison result CMP is high level; if Rx>Rth, then Vdet ⁇ Vref, the comparison result CMP is low level.
  • the reference signal satisfies the following relationship:
  • the counting signal generating module 14 receives the oscillating signal CLK1 and is connected to the output terminal of the working state control module 11 , and outputs the oscillating signal as the counting signal CLK3 in the detection state.
  • the counting signal generating module 14 includes an AND logic unit, the input terminals of the AND logic unit are respectively connected to the oscillation signal CLK1 and the working state control signal CLK2N, and the counting signal CLK3 is generated after performing an AND operation.
  • the AND logic unit is implemented by a two-input AND gate. In actual use, any circuit structure or software code that can realize AND operation is applicable to the present invention.
  • the clearing module 15 is connected to the output terminals of the comparison module 13 and the working state control module 11 , and in the detection state, when the resistance between the neutral wire and the live wire is greater than the threshold Rth, it outputs an effective clearing Zero signal CLR.
  • the clearing module 15 includes an OR logic unit, and the input end of the OR logic unit is respectively connected to the inverse signal CLK2 of the working state control signal CLK2N and the comparison result CMP, and the clearing is generated after an OR operation.
  • the OR logic unit is implemented by a two-input OR gate. In actual use, any circuit structure or software code that can realize OR operation is applicable to the present invention.
  • the clearing signal CLR is consistent with the comparison result CMP; when the inverse signal CLK2 of the working state control signal CLK2N is When it is at a high level (waiting state), the clearing signal CLR is at a high level; in this embodiment, the clearing signal CLR is active at a low level (implementing a clearing function).
  • the counting module 16 is connected to the output terminals of the counting signal generating module 14 and the clearing module 15 , and realizes counting based on the counting signal CLK3 and the clearing signal CLR, and when the count value reaches A high level is output at a preset value, wherein the preset value is greater than the number of cycles of the oscillating signal in one cycle of the detection state.
  • the input end of the counting module 16 is connected to the counting signal CLK3, and the clearing end is connected to the clearing signal CLR.
  • the counting module 16 In the detection state, when the clearing signal CLR is at a high level, the counting module 16 counts the number of square waves of the counting signal CLK3, and when the count value reaches a preset value, the output of the counting module 16 The signal transitions from low to high.
  • the clearing signal CLR is valid (in this embodiment, the low level is valid)
  • the counting module 16 is cleared.
  • the working state control signal CLK2N is at a high level
  • the inverse signal CLK2 of the working state control signal CLK2N is at a low level
  • the counting signal CLK3 is a square wave signal.
  • the count signal CLK3 and the oscillation signal CLK1 have the same phase and frequency. If the comparison result CMP is at a low level at this time, the clearing signal CLR is at a low level, the counting module 16 is cleared, and the count value OUT becomes 0, as shown in the time period from t1 to t2. If the comparison result CMP is at a high level at this time, the clearing signal CLR is at a high level, and the counting module 16 will not be cleared. The number of square waves is counted, as shown in the time period from t3 to t4.
  • the inverse signal CLK2 of the working state control signal CLK2N is at a high level
  • the clearing signal CLR is at a high level
  • the counting module 16 will not be cleared.
  • the working state control signal CLK2N is at a low level
  • the counting signal CLK3 is at a low level
  • the clock signal of the counting module 16 is at a low level, so the count value OUT of the counting module 16 remains unchanged, such as shown in the time period from t2 to t3.
  • the counting module 16 counts, and after the count value reaches a preset value, the output of the counting module 16 changes from a low level to a high level.
  • the increment of the count value of the counting module 16 is determined by the number of square waves of the counting signal CLK3 in one detection period.
  • the count signal CLK3 includes 8 square waves.
  • the increment of the count value of the counting module 16 is less than the preset value, and at least 2 counting cycles are required, and the counting module 16 is not cleared, the counting of the counting module 16
  • the value increases to the preset value, and then the output signal of the counting module 16 changes from a low level to a high level, as shown at time t6. If in any detection period, the output signal CMP of the comparison module 13 is at a low level, the clearing signal CLR becomes a low level, and the counting module 16 is cleared.
  • the AC resistance detection circuit 1 works in a waiting state, the transistor Q1 is turned off, and the count value of the counting module 16 remains unchanged.
  • the AC resistance detection circuit 1 works in the detection state, and the triode Q1 is turned on. If the resistance Rx ⁇ Rth between the live wire and the neutral wire is detected, so that the comparison result CMP is a high level, the The counting module 16 counts.
  • the AC resistance detection circuit 1 works in the detection state, and the triode Q1 is turned on. If the resistance Rx>Rth between the live wire and the neutral wire is detected, so that the comparison result CMP is a low level, the The counting module 16 is cleared by the clearing signal CLR.
  • the AC resistance detection circuit 1 periodically switches between the detection state and the waiting state. In multiple consecutive detection cycles, the resistance between the live wire and the neutral wire satisfies Rx ⁇ Rth, and the count value of the counting module 16 After increasing to the preset value, the output signal of the counting module 16 changes from a low level to a high level.
  • an AC resistance detection circuit 2 includes a sampling module 21 and a comparator 22 .
  • the sampling module 21 includes resistors R1', R2' and R3', one end of the resistor R1' is connected to the power supply voltage Vdd, and the other end is connected to the live wire; one end of the resistor R2' is connected to the neutral wire, and the other end is connected to the ground via the resistor R3',
  • the connection node of the parallel resistors R2' and R3' outputs the sampling signal Vdet'.
  • the input terminal of the comparator 22 is connected to the sampling signal Vdet' and the reference signal Vref', and outputs a comparison result OUT'.
  • the working principle of the AC resistance detection circuit 2 is as follows:
  • the first terminal VL and the second terminal VN of the AC resistance detection circuit 2 are connected to the AC live wire and the neutral wire, and are used to detect the resistance Rx' between the neutral wire and the live wire when the AC power failure occurs (Rx' is the AC live wire and the neutral wire.
  • the resistance between them includes the equivalent resistance of the grid lines and other electrical equipment connected to the grid).
  • the comparator output signal OUT' When the impedance Rx' between the live wire and the neutral wire is less than a certain value, such that Vdet'>Vref', the comparator output signal OUT' is high; when the impedance Rx' between the live wire and the neutral wire is greater than a certain value, so that When Vdet' ⁇ Vref', the comparator output signal OUT' is low level.
  • the neutral wire and the live wire of the AC resistance detection circuit 2a and the AC resistance detection circuit 2b are reversely connected and connected in parallel to the AC live wire and the neutral wire, and there is no other resistance between the AC live wire and the neutral wire; at this time, the AC neutral wire and the neutral wire are connected in parallel.
  • the resistance Rx on the live wire is infinite, so the output signal OUTa' of the comparator 22a in the AC resistance detection circuit 2a should be at a low level. However, the output signal OUTa' obtained by the following calculation and analysis is at a high level.
  • the resistors R1a', R2b', R3b', the power supply Vddb', R1b', R2a', and R3a' then return to the negative pole of the power supply Vdda'.
  • the voltage of the first input terminal of the comparator 22a in the AC resistance detection circuit 2a is:
  • the voltage of the first input terminal of the comparator 22a is higher than the voltage of the second input terminal.
  • the output signal OUTa' of the comparator 22a is at a high level.
  • the output signal of the detection circuit is different from the output signal when a detection circuit is independently connected to the AC neutral wire and the live wire. At this time, the detection circuit outputs an error signal.
  • this embodiment provides an AC resistance detection system, and the AC resistance detection system includes:
  • the first AC resistance detection circuit 1a and the second AC resistance detection circuit 1b adopt the AC resistance detection circuit structure of the first embodiment.
  • Case 1 The first AC resistance detection circuit 1a is working in a waiting state.
  • the transistor Q1a in the first AC resistance detection circuit 1a is turned off, no matter what state the second AC resistance detection circuit 1b is in, the first AC resistance detection circuit 1a has no output current, and the second AC resistance detection circuit 1a has no output current.
  • the current output by the detection circuit 1b will not enter the first AC resistance detection circuit 1a.
  • the working state of the first AC resistance detection circuit 1a is the same as the working state when one AC resistance detection circuit is connected to the AC neutral wire and the live wire alone, and will not be repeated here.
  • the comparison result CMPa output by the comparison module 13a in the first AC resistance detection circuit 1a is a low level, the counting module 16a will not be cleared, and the counting module 16a keeps the counting result unchanged, as shown in t0-t1, shown in the time period from t3 to t4.
  • the comparison result CMPa in the first AC resistance detection circuit 1a is at a high level
  • the clearing signal CLRa of the counting module 16a is at a high level
  • the counting module 16a counts. As shown in the time periods from t1 to t2 and t4 to t5 in FIG. 6 .
  • Case 3 The first AC resistance detection circuit 1a works in a detection state, and the second AC resistance detection circuit 1b works in a waiting state.
  • the transistor Q1a in the first AC resistance detection circuit 1a is turned on, the transistor Q1b in the second AC resistance detection circuit 1b is turned off, and the current output by the first AC resistance detection circuit 1a will not enter the second AC resistance detection circuit 1a.
  • the AC resistance detection circuit 1b and the second AC resistance detection circuit 1b also have no output current entering the first AC resistance detection circuit 1a.
  • the working state of the first AC resistance detection circuit 1a is the same as that when one AC resistance detection circuit is connected to the AC neutral wire and the live wire alone.
  • the current through the resistors R1a, R2a, R3a in the first AC resistance detection circuit 1a is 0, the sampling signal Vdeta is 0V, and the comparison result CMPa is low level.
  • the inverse signal CLK2a of the working state control signal CLK2Na is also at a low level, the clearing signal CLRa is at a low level, and the counting module 16a is cleared. As shown in the time periods t2 to t3 and t5 to t6 in FIG. 6 .
  • the two oscillators in the first AC resistance detection circuit 1a and the second AC resistance detection circuit 1b are independent of each other, and the frequency jitter module makes the frequency of the oscillator change within a certain range, so the two AC resistances It is impossible for the detection circuit to have the same frequency and phase in many consecutive detection cycles, and the above-mentioned situation 3 is easy to occur. As long as the above-mentioned situation 3 occurs before the counting module reaches the preset value, the counting module will be cleared.
  • the preset value is large enough (greater than the number of cycles of the oscillation signal in one cycle of the detection state), for the first AC resistance detection circuit 1a, before the count value of the counting module 16a is increased to the preset value, the counting module 16a is reset. Repeated clearing, the output signal OUTa of the counting module 16a will not change from low level to high level.
  • This embodiment provides an AC resistance detection system, the AC resistance detection system includes:
  • Two AC resistance detection circuits wherein, the first end of the first AC resistance detection circuit is connected to the neutral wire, and the second end is connected to the live wire; the first end of the second AC resistance detection circuit is connected to the neutral wire, and the second end is connected to the live wire.
  • the first AC resistance detection circuit and the second AC resistance detection circuit adopt the AC resistance detection circuit structure of the first embodiment. At this time, since the live wire and the neutral wire of the two AC resistance detection circuits are not mixed, Therefore, the current in the first AC resistance detection circuit does not flow into the second AC resistance detection circuit, and the current in the second AC resistance detection circuit also does not flow into the first AC resistance detection circuit, and the output The result will not go wrong.
  • the present invention provides an AC resistance detection circuit and system, including: a working state control module, a sampling module, a comparison module, a counting signal generating module, a clearing module and a counting module;
  • the working state control module receives oscillation
  • the first and second ends of the sampling module are respectively connected to the neutral wire and the live wire, and the control end is connected to the working state.
  • the output end of the control module samples the resistance between the neutral wire and the live wire in the detection state, and outputs a sampling signal;
  • the comparison module receives the reference signal and connects the output end of the sampling module, and compares the sampling signal with the output end of the sampling module.
  • the counting signal generating module receives the oscillating signal and is connected to the output end of the working state control module, and outputs the oscillating signal in the detection state as a counting signal;
  • the clearing The module is connected to the output end of the comparison module and the working state control module, and when the resistance between the zero wire and the live wire in the detection state is greater than the threshold, an effective clearing signal is output;
  • the counting module is connected to the counting signal generating module and the output end of the clearing module, based on the counting signal and the clearing signal to achieve counting and output a high level when the count value reaches a preset value; wherein, the preset value is greater than one cycle of the detection state The number of cycles of the oscillating signal within.
  • the present invention effectively overcomes various shortcomings in the prior art and has high industrial application value.

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  • General Physics & Mathematics (AREA)
  • Measurement Of Resistance Or Impedance (AREA)
  • Measurement Of Current Or Voltage (AREA)
  • Testing Of Short-Circuits, Discontinuities, Leakage, Or Incorrect Line Connections (AREA)

Abstract

本发明提供一种交流电阻检测电路及系统，包括：工作状态控制模块，产生工作状态控制信号，以在检测状态及等待状态之间依次交替切换；采样模块，在检测状态下输出零线与火线之间的电阻的采样信号；比较模块，接收参考信号及采样信号，输出比较结果；计数信号产生模块，接收振荡信号及工作状态控制信号，在检测状态下输出振荡信号作为计数信号；清零模块，接收比较结果及工作状态控制信号，零线与火线之间的电阻大于阈值时输出有效的清零信号；计数模块，连接计数信号及清零信号，当计数值达到预设值时输出高电平。本发明在零线和火线接入端反向混接并且交流电火线和零线之间无其它电阻时，输出信号不会发生错误，提高了系统可靠性。

Description

交流电阻检测电路及系统 技术领域
本发明涉及电路设计领域，特别是涉及一种交流电阻检测电路及系统。
背景技术
在很多的应用场合，我们需要对交流电源的供电状态进行检测。现有技术是通过检测交流电网零线和火线之间的电阻来实现的。仅当检测电路检测到零线和火线之间的电阻小于一定阈值时，才会认为交流电网处于停电状态。
现有的交流电阻检测电路在使用时，是需要区分零线和火线的。如果两个检测电路并联接入到交流电网上，且发生零线和火线交叉混接的状况，则可能导致其中一个检测电路输出的电流进入到另外一个检测电路，使得检测电路输出错误的检测信号。目前的解决方案是，在检测电路布线时，严格区分零线和火线，避免零线和火线混接情况发生。这通常会给使用者造成麻烦，并增加了出错概率。
因此，如何解决零线和火线混接导致的检测错误问题，已成为本领域技术人员亟待解决的问题之一。
发明内容
鉴于以上所述现有技术的缺点，本发明的目的在于提供一种交流电阻检测电路及系统，用于解决现有技术中两个检测电路并联接入电网时需要严格区分零线和火线，进而导致给使用者造成麻烦、增加出错概率的问题。
为实现上述目的及其他相关目的，本发明提供一种交流电阻检测电路，所述交流电阻检测电路至少包括：
工作状态控制模块，采样模块，比较模块，计数信号产生模块，清零模块及计数模块；
所述工作状态控制模块接收振荡信号，并产生工作状态控制信号，控制工作状态在检测状态及等待状态之间依次交替切换；
所述采样模块的第一端及第二端分别连接零线及火线，控制端连接所述工作状态控制模块的输出端，在检测状态下对零线与火线之间的电阻进行采样，并输出采样信号；
所述比较模块接收参考信号并连接所述采样模块的输出端，比较所述采样信号与所述参考信号并输出相应比较结果；
所述计数信号产生模块接收所述振荡信号并连接所述工作状态控制模块的输出端，在检 测状态下输出所述振荡信号作为计数信号；
所述清零模块连接所述比较模块及所述工作状态控制模块的输出端，在检测状态下零线与火线之间的电阻大于阈值时输出有效的清零信号；
所述计数模块连接所述计数信号产生模块及所述清零模块的输出端，基于所述计数信号及所述清零信号实现计数并当计数值达到预设值时输出高电平；
其中，所述预设值大于检测状态的一个周期内所述振荡信号的周期数。
可选地，所述工作状态控制模块包括分频器及反相器；所述分频器接收所述振荡信号，并对所述振荡信号进行分频；所述反相器连接所述分频器的输出端，对所述分频器的输出信号取反并输出所述工作状态控制信号。
可选地，所述计数信号产生模块包括与逻辑单元，所述与逻辑单元的输入端分别连接所述振荡信号及所述工作状态控制信号，进行与运算后产生所述计数信号。
可选地，所述清零模块包括或逻辑单元，所述或逻辑单元的输入端分别连接所述工作状态控制信号的反信号及所述比较结果，进行或运算后产生所述清零信号。
可选地，所述采样模块包括三极管、第一电阻、第二电阻及第三电阻；所述三极管及所述第一电阻串联连接于电源电压与所述采样模块的第一端之间，所述第二电阻及所述第三电阻串联连接于所述采样模块的第二端与地之间；其中，所述三极管的基极连接所述工作状态控制模块，所述第二电阻与所述第三电阻的连接节点输出所述采样信号。
更可选地，所述参考信号满足如下关系式：
Figure PCTCN2021113288-appb-000001
其中，Vref为所述参考信号，Vdd为所述电源电压，R1为所述第一电阻的阻值，R2为所述第二电阻的阻值，R3为所述第三电阻的阻值。
更可选地，所述交流电阻检测电路还包括频率抖动模块及振荡器；所述振荡器连接所述频率抖动模块的输出端，并产生所述振荡信号，所述振荡信号的频率在预设频率范围内抖动。
为实现上述目的及其他相关目的，本发明还提供一种交流电阻检测系统，所述交流电阻检测系统至少包括：
两个上述交流电阻检测电路；其中，第一交流电阻检测电路的第一端连接零线，第二端连接火线；第二交流电阻检测电路的第一端连接火线，第二端连接零线。
为实现上述目的及其他相关目的，本发明还提供一种交流电阻检测系统，所述交流电阻检测系统至少包括：
两个上述交流电阻检测电路；其中，第一交流电阻检测电路的第一端连接零线，第二端连接火线；第二交流电阻检测电路的第一端连接零线，第二端连接火线。
如上所述，本发明的交流电阻检测电路及系统，具有以下有益效果：
本发明的交流电阻检测电路及系统在零线和火线接入端反向混接并且交流电火线和零线之间无其它电阻时，输出信号不会发生错误，提高了系统可靠性；且无需区分零线和火线，便于使用，提高客户体验度。
附图说明
图1显示为本发明的交流电阻检测电路的结构示意图。
图2显示为本发明的交流电阻检测电路的工作原理示意图。
图3显示为一种交流电阻检测电路的结构示意图。
图4显示为图3的两个交流电阻检测电路的零线和火线反向混接的结构示意图。
图5显示为本发明的两个交流电阻检测电路的零线和火线反向混接的结构示意图。
图6显示为本发明的两个交流电阻检测电路的零线和火线反向混接的工作原理示意图。
元件标号说明
1、1a、1b            交流电阻检测电路，第一、第二交流电阻检测电路
11、11a、11b         工作状态控制模块
111、111a、111b      分频器
112、112a、112b      反相器
12、12a、12b         采样模块
13、13a、13b         比较模块
14、14a、14b         计数信号产生模块
15、15a、15b         清零模块
16、16a、16b         计数模块
17、17a、17b         振荡器
18、18a、18b         频率抖动模块
具体实施方式
以下通过特定的具体实例说明本发明的实施方式，本领域技术人员可由本说明书所揭露的内容轻易地了解本发明的其他优点与功效。本发明还可以通过另外不同的具体实施方式加 以实施或应用，本说明书中的各项细节也可以基于不同观点与应用，在没有背离本发明的精神下进行各种修饰或改变。
请参阅图1～图6。需要说明的是，本实施例中所提供的图示仅以示意方式说明本发明的基本构想，遂图式中仅显示与本发明中有关的组件而非按照实际实施时的组件数目、形状及尺寸绘制，其实际实施时各组件的型态、数量及比例可为一种随意的改变，且其组件布局型态也可能更为复杂。
实施例一
如图1所示，本实施例提供一种交流电阻检测电路1，所述交流电阻检测电路1包括：
工作状态控制模块11，采样模块12，比较模块13，计数信号产生模块14，清零模块15及计数模块16。
如图1所示，所述工作状态控制模块11接收振荡信号CLK1，并产生工作状态控制信号CLK2N，控制工作状态在检测状态及等待状态之间依次交替切换。
具体地，在本实施例中，所述工作状态控制模块11包括分频器111及反相器112。所述分频器111接收所述振荡信号CLK1，并对所述振荡信号CLK1进行分频，作为示例，所述分频器用于实现十六分频。所述反相器112连接所述分频器111的输出端，对所述分频器111的输出信号CLK2取反并输出所述工作状态控制信号CLK2N。在本实施例中，所述工作状态控制信号CLK2N为高电平时控制所述交流电阻检测电路1工作于检测状态，对零线和火线之间的电阻Rx进行检测，Rx包括电网线路及其他接入电网的用电设备的等效电阻；所述工作状态控制信号CLK2N为低电平时控制所述交流电阻检测电路1工作于等待状态，不对零线和火线之间的电阻Rx进行检测。所述交流电阻检测电路1的工作状态在检测状态和等待状态之间周期性切换，一次检测状态持续时间与所述分频器111的输出信号CLK2的低电平持续时间相等，记为一个检测周期。
如图1所示，作为本发明的一种实现方式，所述振荡信号CLK1通过振荡器17产生，所述振荡器17的输入端连接频率抖动模块18的输出端，所述频率抖动模块18在所述振荡器17产生的振荡信号上增加一个低频变量,使得最终输出的振荡信号CLK1的频率并非一直固定不变，而是在预设频率范围内抖动变化；所述低频变量可基于所述预设频率范围进行设定，在此不一一赘述。
如图1所示，所述采样模块12的第一端VL及第二端VN分别连接零线及火线，控制端连接所述工作状态控制模块11的输出端，在检测状态下对零线与火线之间的电阻进行采样，并输出采样信号Vdet。
具体地，在本实施例中，所述采样模块12包括三极管Q1、第一电阻R1、第二电阻R2及第三电阻R3。所述三极管Q1及所述第一电阻R1串联连接于电源电压Vdd与所述采样模块12的第一端VL之间，所述三极管Q1的基极连接所述工作状态控制模块11的输出端；作为示例，所述三极管Q1的集电极连接所述电源电压Vdd，发射极经由所述第一电阻连接所述采样模块12的第一端VL，基极连接所述工作状态控制模块11输出的工作状态控制信号CLK2N；当所述工作状态控制信号CLK2N为高电平时所述三极管Q1导通，当所述工作状态控制信号CLK2N为低电平时所述三极管Q1关断。所述第二电阻R2及所述第三电阻R3串联连接于所述采样模块12的第二端VN与地之间，所述第二电阻R2与所述第三电阻R3的连接节点输出所述采样信号Vdet。
具体地，在等待状态下，由于所述三极管Q1关断，通过所述第一电阻R1、零线与火线之间的电阻Rx、所述第二电阻R2和所述第三电阻R3的电流为0，则所述采样信号Vdet为0。在检测状态下，所述三极管Q1导通，可以近似认为三极管Q1集电极和射极电压相等；此时，所述电源电压Vdd输出的电流依次经过三极管Q1和电阻R1、Rx、R2、R3，所述采样信号Vdet满足：
Figure PCTCN2021113288-appb-000002
当火线与零线之间的电阻Rx为无穷大时：
Vdet＝0，
当火线与零线之间的电阻Rx接近无穷小时：
Figure PCTCN2021113288-appb-000003
如图1所示，所述比较模块13接收参考信号Vref并连接所述采样模块12的输出端，比较所述采样信号Vdet与所述参考信号Vref并输出相应比较结果CMP。
具体地，在本实施例中，所述比较模块13的正相输入端连接所述采样信号Vdet，反相输入端连接所述参考信号Vref。在实际使用中，可通过增加反相器调整输入信号与不同极性输入端的连接关系，能实现相同的逻辑关系即可，不限于本实施例。在本实施例中，检测状态下，若Rx<Rth，(作为示例，阈值Rth满足：
Figure PCTCN2021113288-appb-000004
则Vdet>Vref，所述比较结果CMP为高电平；若Rx>Rth，则Vdet<Vref，所述比较结果CMP为低电平。
具体地，所述参考信号满足如下关系式：
Figure PCTCN2021113288-appb-000005
如图1所示，所述计数信号产生模块14接收所述振荡信号CLK1并连接所述工作状态控制模块11的输出端，在检测状态下输出所述振荡信号作为计数信号CLK3。
具体地，所述计数信号产生模块14包括与逻辑单元，所述与逻辑单元的输入端分别连接所述振荡信号CLK1及所述工作状态控制信号CLK2N，进行与运算后产生所述计数信号CLK3。作为示例，所述与逻辑单元采用两输入与门实现，在实际使用中，任意可实现与运算的电路结构或软件代码均适用于本发明。当所述工作状态控制信号CLK2N为高电平(检测状态)时，所述振荡信号输出作为所述计数信号CLK3；当所述工作状态控制信号CLK2N为低电平(等待状态)时，所述计数信号CLK3为低电平。
如图1所示，所述清零模块15连接所述比较模块13及所述工作状态控制模块11的输出端，在检测状态下零线与火线之间的电阻大于阈值Rth时输出有效的清零信号CLR。
具体地，所述清零模块15包括或逻辑单元，所述或逻辑单元的输入端分别连接所述工作状态控制信号CLK2N的反信号CLK2及所述比较结果CMP，进行或运算后产生所述清零信号CLR。作为示例，所述或逻辑单元采用两输入或门实现，在实际使用中，任意可实现或运算的电路结构或软件代码均适用于本发明。当所述工作状态控制信号CLK2N的反信号CLK2为低电平(检测状态)时，所述清零信号CLR与所述比较结果CMP保持一致；当所述工作状态控制信号CLK2N的反信号CLK2为高电平(等待状态)时，所述清零信号CLR为高电平；在本实施例中，所述清零信号CLR低电平有效(实现清零功能)。
如图1所示，所述计数模块16连接所述计数信号产生模块14及所述清零模块15的输出端，基于所述计数信号CLK3及所述清零信号CLR实现计数并当计数值达到预设值时输出高电平，其中，所述预设值大于检测状态的一个周期内所述振荡信号的周期数。
具体地，所述计数模块16的输入端连接所述计数信号CLK3，清零端连接所述清零信号CLR。在检测状态下，所述清零信号CLR为高电平时，所述计数模块16对所述计数信号CLK3的方波个数进行计数，当计数值达到预设值时所述计数模块16的输出信号从低电平跳变为高电平。当所述清零信号CLR有效(在本实施例中，低电平有效)时，所述计数模块16被清零。
如图2所示，检测状态下，所述工作状态控制信号CLK2N为高电平，所述工作状态控制信号CLK2N的反信号CLK2为低电平，所述计数信号CLK3为方波信号，此时所述计数信号CLK3与所述振荡信号CLK1的相位、频率相同。如果此时所述比较结果CMP为低电平， 则所述清零信号CLR为低电平，所述计数模块16被清零，计数值OUT变为0，如t1～t2时间段所示。如果此时所述比较结果CMP为高电平，则所述清零信号CLR为高电平，所述计数模块16不会被清零，此时所述计数模块16对所述计数信号CLK3的方波个数进行计数，如t3～t4时间段所示。
如图2所示，等待状态下，所述工作状态控制信号CLK2N的反信号CLK2为高电平，所述清零信号CLR为高电平，所述计数模块16不会被清零。所述工作状态控制信号CLK2N为低电平，所述计数信号CLK3为低电平，所述计数模块16的时钟信号为低电平，所以所述计数模块16的计数值OUT保持不变，如t2～t3时间段所示。
如图2所示，所述计数模块16进行计数，并且计数值达到预设值后，所述计数模块16的输出由低电平变为高电平。
如图2所示，在一个检测周期内，所述计数模块16的计数值增加量由一个检测周期内所述计数信号CLK3的方波个数决定，在本实施例中，一个检测周期内所述计数信号CLK3包括8个方波。在单次检测周期内，所述计数模块16的计数值增加量小于所述预设值，需要经过至少2个计数周期，并且所述计数模块16不被清零，所述计数模块16的计数值才会增加到所述预设值，然后所述计数模块16的输出信号由低电平变为高电平，如t6时刻所示。如果在任意一个检测周期内，所述比较模块13的输出信号CMP为低电平，则所述清零信号CLR变为低电平，所述计数模块16被清零。
综上所述，所述交流电阻检测电路1工作在等待状态下，所述三级管Q1关断，所述计数模块16的计数值保持不变。
所述交流电阻检测电路1工作在检测状态下，所述三级管Q1导通，若检测到火线与零线之间的电阻Rx<Rth，使得所述比较结果CMP为高电平，则所述计数模块16进行计数。
所述交流电阻检测电路1工作在检测状态下，所述三级管Q1导通，若检测到火线与零线之间的电阻Rx>Rth，使得所述比较结果CMP为低电平，则所述计数模块16被所述清零信号CLR清零。
所述交流电阻检测电路1在检测状态和等待状态之间周期性切换，在连续多个检测周期内，火线与零线之间的电阻都满足Rx<Rth，并且所述计数模块16的计数值增加到预设值后，所述计数模块16的输出信号由低电平变为高电平。
对比例
如图3所示为一种交流电阻检测电路2，包括采样模块21及比较器22。其中，所述采样 模块21包括电阻R1’、R2’及R3’，电阻R1’的一端连接电源电压Vdd，另一端连接火线；电阻R2’的一端连接零线，另一端经由电阻R3’接地，并电阻R2’和R3’的连接节点输出采样信号Vdet’。比较器22的输入端连接所述采样信号Vdet’及参考信号Vref’，并输出比较结果OUT’。
所述交流电阻检测电路2的工作原理如下：
交流电阻检测电路2的第一端VL和第二端VN连接到交流火线和零线上，用于在交流停电时检测零线和火线之间的电阻Rx’(Rx’为交流电火线和零线之间的电阻，该电阻包括电网线路及其他接入电网的用电设备的等效电阻)。当停电时，交流电阻检测电路2的第一端VL和第二端VN之间无交流电压信号，电源电压Vdd输出的电流依次经过电阻R1’、Rx’、R2’、R3’，得到采样信号Vdet’，满足：
Figure PCTCN2021113288-appb-000006
当火线与零线之间的阻抗Rx’小于一定值，使得Vdet'＞Vref'时，比较器输出信号OUT’为高电平；当火线与零线之间的阻抗Rx’大于一定值，使得Vdet'＜Vref'时，比较器输出信号OUT’为低电平。
如图4所示，将两个所述交流电阻检测电路2的零线和火线反向混接，并且交流电火线和零线之间无其它电阻时，一个交流电阻检测电路输出的电流会进入另外一个交流电阻检测电路，从而可能使得交流电阻检测电路的输出信号错误，原理分析如下：
交流电阻检测电路2a和交流电阻检测电路2b的零线和火线反向混接，并联连接到交流火线和零线上，并且交流电火线和零线之间无其它电阻；此时，交流零线和火线上的电阻Rx为无穷大，所以交流电阻检测电路2a中的比较器22a的输出信号OUTa’应该为低电平，然而，如下通过计算分析得到的输出信号OUTa’却为高电平。
2个交流电阻检测电路的零线和火线反向混接时，两个检测电路为串联连接关系，交流电阻检测电路2a输出的电流会进入交流电阻检测电路2b，电源Vdda’正极输出的电流经过电阻R1a’、R2b’、R3b’、电源Vddb’、R1b’、R2a’、R3a’后回到电源Vdda’的负极。交流电阻检测电路2a中比较器22a的第一输入端电压为：
Figure PCTCN2021113288-appb-000007
假设Vdda’＝Vddb’＝Vdd’，R1a’＝R1b’＝R1’，R2a’＝R2b’＝R2’，R3a’＝R3b’＝R3’。简化后：
Figure PCTCN2021113288-appb-000008
如以上计算结果，比较器22a的第一输入端电压高于第二输入端电压。比较器22a的输出信号OUTa’为高电平。此时检测电路的输出信号，与一个检测电路独立连接到交流零线和火线上时的输出信号不同，此时检测电路输出了错误信号。
实施例二
如图5所示，本实施例提供一种交流电阻检测系统，所述交流电阻检测系统包括：
两个交流电阻检测电路；其中，第一交流电阻检测电路1a的第一端VLa连接零线N，第二端VNa连接火线L；第二交流电阻检测电路1b的第一端VLb连接火线L，第二端VNb连接零线N。所述第一交流电阻检测电路1a及所述第二交流电阻检测电路1b采用实施例一的交流电阻检测电路结构。
如图5所示，所述第一交流电阻检测电路1a与所述第二交流电阻检测电路1b的零线和火线反向混接，并且交流电火线和零线之间无其它电阻时，一个交流电阻检测电路输出的电流可能会进入另外一个交流电阻检测电路。但是，本发明的交流电阻检测系统的各输出信号不会出现错误，交流电阻检测电路在检测状态和等待状态之间周期性切换，因为2个交流电阻检测电路的工作原理相同，所以只针对第一交流电阻检测电路1a进行分析说明；可以分为如下3种情况：
情况一：所述第一交流电阻检测电路1a工作在等待状态。所述第一交流电阻检测电路1a中的三极管Q1a关闭，无论所述第二交流电阻检测电路1b工作在什么状态下，所述第一交流电阻检测电路1a无输出电流，所述第二交流电阻检测电路1b输出的电流不会进入所述第一交流电阻检测电路1a。此时，所述第一交流电阻检测电路1a的工作状态与一个交流电阻检测电路单独连接到交流零线和火线上时的工作状态相同，在此不一一赘述。所述第一交流电阻检测电路1a中的比较模块13a输出的比较结果CMPa为低电平，计数模块16a不会被清零，计数模块16a保持计数结果不变，如图6中t0～t1、t3～t4时间段所示。
情况二：所述第一交流电阻检测电路1a和所述第二交流电阻检测电路1b都工作在检测状态下。所述第一交流电阻检测电路1a中的三极管Q1a和所述第二交流电阻检测电路1b中的三极管Q1b同时导通，两个交流电阻检测电路串联连接。所述第一交流电阻检测电路1a输出的电流会进入所述第二交流电阻检测电路1b，所述第二交流电阻检测电路1b输出的电 流也会进入所述第一交流电阻检测电路1a。所述第一交流电阻检测电路1a中的采样信号Vdeta满足：
Figure PCTCN2021113288-appb-000009
为简化分析，假设2个交流电阻检测电路中的电源和电阻值完全相等，Vdda＝Vddb＝Vdd，R1a＝R1b＝R1，R2a＝R2b＝R2，R3a＝R3b＝R3。简化后：
Figure PCTCN2021113288-appb-000010
此时，所述第一交流电阻检测电路1a中的比较结果CMPa为高电平，计数模块16a的清零信号CLRa为高电平，计数模块16a进行计数。如图6中t1～t2，t4～t5时间段所示。
情况三：所述第一交流电阻检测电路1a工作在检测状态下，所述第二交流电阻检测电路1b工作在等待状态下。所述第一交流电阻检测电路1a中的三极管Q1a导通，所述第二交流电阻检测电路1b中的三极管Q1b关闭，所述第一交流电阻检测电路1a输出的电流不会进入所述第二交流电阻检测电路1b，所述第二交流电阻检测电路1b也无输出电流进入所述第一交流电阻检测电路1a。此时，所述第一交流电阻检测电路1a的工作状态与一个交流电阻检测电路单独连接到交流零线和火线时的工作状态相同。因为交流零线和火线之间的无其它电阻，所以通过所述第一交流电阻检测电路1a中电阻R1a、R2a、R3a的电流为0，采样信号Vdeta为0V，比较结果CMPa为低电平。所述工作状态控制信号CLK2Na的反信号CLK2a也为低电平，清零信号CLRa为低电平，计数模块16a被清零。如图6中t2～t3,t5～t6时间段所示。
所述第一交流电阻检测电路1a和所述第二交流电阻检测电路1b中的2个振荡器相互独立，并且频率抖动模块使得振荡器的频率在一定的范围内抖动变化，所以两个交流电阻检测电路不可能在连续很多个检测周期内，频率和相位都完全一致，很容易出现如上所述的情况三。只要在计数模块计满预设值前，出现如上所述的情况三，计数模块就被清零。
预设值足够大(大于检测状态的一个周期内所述振荡信号的周期数)，对于所述第一交流电阻检测电路1a，计数模块16a的计数值增加到预设值前，计数模块16a被反复清零，计数模块16a的输出信号OUTa不会由低电平变为高电平。
实施例三
本实施例提供一种交流电阻检测系统，所述交流电阻检测系统包括：
两个交流电阻检测电路；其中，第一交流电阻检测电路的第一端连接零线，第二端连接火线；第二交流电阻检测电路的第一端连接零线，第二端连接火线。
具体地，所述第一交流电阻检测电路及所述第二交流电阻检测电路采用实施例一的交流电阻检测电路结构，此时，由于两个交流电阻检测电路的火线和零线没有混接，因此，所述第一交流电阻检测电路中的电流不会流入所述第二交流电阻检测电路，所述第二交流电阻检测电路中的电流也不会流入所述第一交流电阻检测电路，输出结果不会出错。
综上所述，本发明提供一种交流电阻检测电路及系统，包括：工作状态控制模块，采样模块，比较模块，计数信号产生模块，清零模块及计数模块；所述工作状态控制模块接收振荡信号，并产生工作状态控制信号，控制工作状态在检测状态及等待状态之间依次交替切换；所述采样模块的第一端及第二端分别连接零线及火线，控制端连接所述工作状态控制模块的输出端，在检测状态下对零线与火线之间的电阻进行采样，并输出采样信号；所述比较模块接收参考信号并连接所述采样模块的输出端，比较所述采样信号与所述参考信号并输出相应比较结果；所述计数信号产生模块接收所述振荡信号并连接所述工作状态控制模块的输出端，在检测状态下输出所述振荡信号作为计数信号；所述清零模块连接所述比较模块及所述工作状态控制模块的输出端，在检测状态下零线与火线之间的电阻大于阈值时输出有效的清零信号；所述计数模块连接所述计数信号产生模块及所述清零模块的输出端，基于所述计数信号及所述清零信号实现计数并当计数值达到预设值时输出高电平；其中，所述预设值大于检测状态的一个周期内所述振荡信号的周期数。本发明的交流电阻检测电路及系统在零线和火线接入端反向混接并且交流电火线和零线之间无其它电阻时，输出信号不会发生错误，提高了系统可靠性；且无需区分零线和火线，便于使用，提高客户体验度。所以，本发明有效克服了现有技术中的种种缺点而具高度产业利用价值。
上述实施例仅例示性说明本发明的原理及其功效，而非用于限制本发明。任何熟悉此技术的人士皆可在不违背本发明的精神及范畴下，对上述实施例进行修饰或改变。因此，举凡所属技术领域中具有通常知识者在未脱离本发明所揭示的精神与技术思想下所完成的一切等效修饰或改变，仍应由本发明的权利要求所涵盖。

Claims (9)

  1. 一种交流电阻检测电路，其特征在于，所述交流电阻检测电路至少包括：
    工作状态控制模块，采样模块，比较模块，计数信号产生模块，清零模块及计数模块；
    所述工作状态控制模块接收振荡信号，并产生工作状态控制信号，控制工作状态在检测状态及等待状态之间依次交替切换；
    所述采样模块的第一端及第二端分别连接零线及火线，控制端连接所述工作状态控制模块的输出端，在检测状态下对零线与火线之间的电阻进行采样，并输出采样信号；
    所述比较模块接收参考信号并连接所述采样模块的输出端，比较所述采样信号与所述参考信号并输出相应比较结果；
    所述计数信号产生模块接收所述振荡信号并连接所述工作状态控制模块的输出端，在检测状态下输出所述振荡信号作为计数信号；
    所述清零模块连接所述比较模块及所述工作状态控制模块的输出端，在检测状态下零线与火线之间的电阻大于阈值时输出有效的清零信号；
    所述计数模块连接所述计数信号产生模块及所述清零模块的输出端，基于所述计数信号及所述清零信号实现计数并当计数值达到预设值时输出高电平；
    其中，所述预设值大于检测状态的一个周期内所述振荡信号的周期数。
  2. 根据权利要求1所述的交流电阻检测电路，其特征在于：所述工作状态控制模块包括分频器及反相器；所述分频器接收所述振荡信号，并对所述振荡信号进行分频；所述反相器连接所述分频器的输出端，对所述分频器的输出信号取反并输出所述工作状态控制信号。
  3. 根据权利要求1所述的交流电阻检测电路，其特征在于：所述计数信号产生模块包括与逻辑单元，所述与逻辑单元的输入端分别连接所述振荡信号及所述工作状态控制信号，进行与运算后产生所述计数信号。
  4. 根据权利要求1所述的交流电阻检测电路，其特征在于：所述清零模块包括或逻辑单元，所述或逻辑单元的输入端分别连接所述工作状态控制信号的反信号及所述比较结果，进行或运算后产生所述清零信号。
  5. 根据权利要求1所述的交流电阻检测电路，其特征在于：所述采样模块包括三极管、第一电阻、第二电阻及第三电阻；所述三极管及所述第一电阻串联连接于电源电压与所述采样模块的第一端之间，所述第二电阻及所述第三电阻串联连接于所述采样模块的第二端与地 之间；其中，所述三极管的基极连接所述工作状态控制模块，所述第二电阻与所述第三电阻的连接节点输出所述采样信号。
  6. 根据权利要求5所述的交流电阻检测电路，其特征在于：所述参考信号满足如下关系式：
    Figure PCTCN2021113288-appb-100001
    其中，Vref为所述参考信号，Vdd为所述电源电压，R1为所述第一电阻的阻值，R2为所述第二电阻的阻值，R3为所述第三电阻的阻值。
  7. 根据权利要求1～6任意一项所述的交流电阻检测电路，其特征在于：所述交流电阻检测电路还包括频率抖动模块及振荡器；所述振荡器连接所述频率抖动模块的输出端，并产生所述振荡信号，所述振荡信号的频率在预设频率范围内抖动。
  8. 一种交流电阻检测系统，其特征在于，所述交流电阻检测系统至少包括：
    两个如权利要求1～7任意一项所述的交流电阻检测电路；其中，第一交流电阻检测电路的第一端连接零线，第二端连接火线；第二交流电阻检测电路的第一端连接火线，第二端连接零线。
  9. 一种交流电阻检测系统，其特征在于，所述交流电阻检测系统至少包括：
    两个如权利要求1～7任意一项所述的交流电阻检测电路；其中，第一交流电阻检测电路的第一端连接零线，第二端连接火线；第二交流电阻检测电路的第一端连接零线，第二端连接火线。
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CN116938193A (zh) * 2023-09-18 2023-10-24 上海莫秋环境技术有限公司 一种用于水处理的电磁波生成电路
CN116938193B (zh) * 2023-09-18 2023-12-01 上海莫秋环境技术有限公司 一种用于水处理的电磁波生成电路

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