WO2022062468A1 - 均衡电路、数据采集方法及存储器 - Google Patents

均衡电路、数据采集方法及存储器 Download PDF

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Publication number
WO2022062468A1
WO2022062468A1 PCT/CN2021/097401 CN2021097401W WO2022062468A1 WO 2022062468 A1 WO2022062468 A1 WO 2022062468A1 CN 2021097401 W CN2021097401 W CN 2021097401W WO 2022062468 A1 WO2022062468 A1 WO 2022062468A1
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Prior art keywords
circuit
sampling
data
input buffer
equalization
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PCT/CN2021/097401
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English (en)
French (fr)
Inventor
张志强
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长鑫存储技术有限公司
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Application filed by 长鑫存储技术有限公司 filed Critical 长鑫存储技术有限公司
Priority to EP21867897.7A priority Critical patent/EP4040439A4/en
Priority to KR1020227021257A priority patent/KR20220107005A/ko
Priority to JP2022539727A priority patent/JP7411811B2/ja
Priority to US17/400,491 priority patent/US11595234B2/en
Publication of WO2022062468A1 publication Critical patent/WO2022062468A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1057—Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1084—Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load

Definitions

  • the embodiments of the present application relate to the technical field of integrated circuits, and in particular, to an equalization circuit, a data acquisition method, and a memory.
  • ISI Inter Symbol Interference
  • the Continuous Time Linear Equalizer (CTLE) architecture is mainly used for equalization processing. Its function is to perform signal compensation according to the attenuation characteristics of the channel to improve the quality of the data signal.
  • Embodiments of the present application provide an equalization circuit, a data acquisition method, and a memory, which can effectively improve the quality of received data signals.
  • an embodiment of the present application provides an equalization circuit, including: a first input buffer circuit, a second input buffer circuit, and a selection sampling circuit, the first input buffer circuit and the second input buffer circuit are respectively connected to the selection sampling circuit , and the reference voltages used by the first input buffer circuit and the second input buffer circuit are different.
  • the selection sampling circuit selects to perform data sampling on the data signal output by the first input buffer circuit or the data signal output by the second input buffer circuit according to the data output by the equalization circuit last time, and uses the collected data as the current output data of the equalization circuit .
  • the equalization circuit provided by the embodiment of the present application includes two types of input buffer circuits using different reference voltages.
  • a suitable input buffer circuit is selected from the two input buffer circuits based on the previous output data of the equalization circuit.
  • the buffer circuit then performs data sampling on the data signal output by the selected input buffer circuit, which can effectively increase the input voltage margin of the equalization circuit, thereby improving the quality of the received data signal.
  • the above-mentioned equalization circuit further includes a dual reference voltage generator;
  • the dual reference voltage generator includes a first reference voltage output terminal and a second reference voltage output terminal, and the first reference voltage output terminal is connected to the reference voltage input terminal of the first input buffer circuit, and the second reference voltage output terminal is connected to the reference voltage input terminal of the second input buffer circuit.
  • the selection sampling circuit includes a selection circuit and a sampling circuit, the selection circuit is connected to the sampling circuit; the selection circuit is configured to select the selected sampling circuit according to the data sent by the sampling circuit.
  • the data signal output by the first input buffer circuit or the data signal output by the second input buffer circuit is input to the sampling circuit; the sampling circuit is configured to perform data sampling on the data signal input by the selection circuit.
  • the selection circuit includes a first selection circuit and a second selection circuit
  • the sampling circuit includes a first sampling circuit and a second sampling circuit
  • the two input terminals of the first selection circuit are respectively connected to the output terminal of the first input buffer circuit and the output terminal of the second input buffer circuit, and the two input terminals of the second selection circuit are respectively connected to the output terminal of the second input buffer circuit.
  • the output terminal of the first input buffer circuit is connected to the output terminal of the second input buffer circuit.
  • the output end of the first selection circuit is connected to the input end of the first sampling circuit, the control end of the first selection circuit is connected to the output end of the second sampling circuit, and the output end of the second selection circuit
  • the terminal is connected to the input terminal of the second sampling circuit, and the control terminal of the second selection circuit is connected to the output terminal of the first sampling circuit.
  • the first sampling circuit sends the currently collected data to the control terminal of the second selection circuit, and the second selection circuit is based on the data sent by the first sampling circuit, Select to input the data in the first input buffer circuit or the second input buffer circuit to the second sampling circuit; the second sampling circuit sends the currently collected data to the first selection circuit At the control end, the first selection circuit selects to input the data in the first input buffer circuit or the second input buffer circuit to the first sampling circuit based on the data sent by the second sampling circuit.
  • the second selection circuit selects the output data of the first input buffer circuit input to the second sampling circuit; when the data sent by the first sampling circuit to the control terminal of the second selection circuit is 0, the second selection circuit selects the output data of the second input buffer circuit input to the second sampling circuit.
  • the first selection circuit selects to input the output data of the first input buffer circuit to the first sampling circuit;
  • the first selection circuit selects to input the output data of the second input buffer circuit to the first sampling circuit.
  • the equalization circuit further includes a sampling clock input circuit, and the output ends of the sampling clock input circuit are respectively connected to the sampling clock input ends of the first sampling circuit and the second sampling circuit ;
  • the sampling clock input circuit is used to provide a sampling clock signal to the first sampling circuit and the second sampling circuit.
  • the first sampling circuit uses the rising edge of the sampling clock signal received by the equalization circuit to perform data sampling on the data input by the first selection circuit; the second sampling circuit Using the falling edge of the sampling clock signal received by the equalization circuit, data is sampled on the data input by the second selection circuit.
  • the equalization circuit will The output data is the data collected by the second sampling circuit using the sampling clock signal received by the equalization circuit as the preceding adjacent falling edge of the rising edge.
  • the data currently output by the equalization circuit is the data collected by the second sampling circuit using the falling edge of the sampling clock signal received by the equalization circuit
  • the data previously output by the equalization circuit is the first sample
  • the circuit uses the sampling clock signal received by the equalization circuit to be the data collected by the preceding adjacent rising edge of the falling edge.
  • the first input buffer circuit includes a first comparator circuit and a first delay circuit, the first comparator circuit is connected in series with the first delay circuit, and the first comparator circuit is connected in series with the first delay circuit.
  • a reference voltage input terminal of a comparator circuit is connected to the first reference voltage output terminal.
  • the second input buffer circuit includes a second comparator circuit and a second delay circuit, the second comparator circuit is connected in series with the second delay circuit, and the reference voltage input terminal of the second comparator circuit connected to the second reference voltage output terminal.
  • the signal input terminal of the first comparator circuit is connected to the same input data signal as the signal input terminal of the second comparator circuit.
  • the first comparator circuit and the second comparator circuit use the same circuit structure.
  • the first delay circuit and the second delay circuit adopt the same circuit structure.
  • the first selection circuit and the second selection circuit use the same circuit structure.
  • the first sampling circuit and the second sampling circuit adopt the same circuit structure.
  • the reference voltage used by the first input buffer circuit is greater than the reference voltage used by the second input buffer circuit.
  • an embodiment of the present application provides a data acquisition method, which is applied to an equalization circuit, where the equalization circuit includes two input buffer circuits, and the reference voltages used by the two input buffer circuits are different.
  • the above data collection methods include:
  • an appropriate input buffer circuit is selected from two different input buffer circuits based on the data outputted by the equalization circuit last time, and then the selected input buffer circuit is The data sampling of the output data signal can effectively increase the input voltage margin of the equalization circuit, thereby improving the quality of the received data signal.
  • an embodiment of the present application provides a memory, the memory includes an equalization circuit, and the equalization circuit is the equalization circuit provided in the first aspect of the embodiment of the application.
  • the equalization circuit includes two input buffer circuits with different reference voltages.
  • the sampling circuit is selected to collect data, it is necessary to select the sampling circuit according to the previous output data of the equalization circuit.
  • One of the output data signals of the above two input buffer circuits is selected for data collection, so as to perform data equalization processing in advance, thereby more effectively eliminating ISI and improving the quality of the received data signals.
  • 1 is a schematic diagram of a circuit structure of an equalization circuit provided in an embodiment of the application.
  • FIG. 2 is a schematic diagram of the circuit structure of another equalization circuit provided in an embodiment of the present application.
  • 3 is a waveform diagram of the equalization circuit provided in the embodiment of the application in the process of collecting data
  • FIG. 4 is a schematic diagram of an equalization processing effect of the equalization circuit provided in the embodiment of the present application.
  • the embodiments of the present application provide a novel equalization circuit, which can be applied to various types of memories, and specifically can be applied to receiver circuits in various memory products, for example, can be applied to receiver circuits in DDR4 memory.
  • the equalization circuit provided by the embodiments of the present application can also be used.
  • the CTLE architecture is mainly used for equalization processing, and its function is to perform signal compensation according to the attenuation characteristics of the channel to improve the quality of the signal.
  • the existing equalization processing method has been difficult to meet the signal quality requirements of DDR4-type memory.
  • the equalization circuit includes two input buffer circuits with different reference voltages.
  • the sampling circuit is selected to collect data, it is based on the data collected in the previous time.
  • a suitable input buffer circuit is selected in the buffer circuit, and data sampling is performed based on the data signal output by the selected input buffer circuit to perform data equalization processing in advance, so that ISI can be more effectively eliminated and the quality of the received data signal can be improved.
  • FIG. 1 is a schematic diagram of a circuit structure of an equalization circuit provided in an embodiment of the present application.
  • the above-mentioned equalization circuit includes: a first input buffer circuit 10 , a second input buffer circuit 20 and a selection sampling circuit 30 . in:
  • the first input buffer circuit 10 and the second input buffer circuit 20 are respectively connected to the selection sampling circuit 30 , and the reference voltages used by the first input buffer circuit 10 and the second input buffer circuit 20 are different.
  • the selection sampling circuit 30 selects to perform data sampling on the data signal output by the first input buffer circuit 10 or the data signal output by the second input buffer circuit 20 according to the data output by the equalization circuit last time, and uses the collected data as the current equalization circuit. output data.
  • the selection sampling circuit 30 selects to perform data sampling on the data signal output by the first input buffer circuit 10, and uses the collected data as the data currently output by the equalization circuit.
  • the selection sampling circuit 30 selects to sample the data signal output by the second input buffer circuit 20, and uses the collected data as the current output data of the equalization circuit.
  • the sampling circuit 30 When selecting the sampling circuit 30 to collect data, according to the previous output data of the equalization circuit, it is selected to perform data collection from the data signal output from the first input buffer circuit 10 or from the data signal output from the second input buffer circuit 20 Data collection is performed in the middle, so that the above-mentioned equalization circuit can perform data equalization processing in advance according to the data outputted last time, which helps to eliminate ISI and improve the quality of the received data signal.
  • FIG. 2 is a schematic circuit structure diagram of another equalization circuit provided in the embodiment of the present application.
  • the above-mentioned equalization circuit further includes a reference voltage generator 40, wherein:
  • the reference voltage generator 40 includes a first reference voltage output terminal H and a second reference voltage output terminal L.
  • the first reference voltage output by the first reference voltage output terminal H is different from the second reference voltage output by the second reference voltage output terminal L. .
  • the first reference voltage is greater than the second reference voltage.
  • the first reference voltage output terminal H is connected to the reference voltage input terminal of the first input buffer circuit 10
  • the second reference voltage output terminal L is connected to the reference voltage input terminal of the second input buffer circuit 20 .
  • the selection sampling circuit 30 includes a selection circuit and a sampling circuit, and the selection circuit is connected to the sampling circuit.
  • the above-mentioned selection circuit can be used to select and input the data signal output by the first input buffer circuit 10 or the data signal output by the second input buffer circuit 20 to the above-mentioned sampling circuit according to the data sent by the above-mentioned sampling circuit; the above-mentioned sampling circuit is used for Data sampling is performed on the data signal input from the selection circuit.
  • the above-mentioned selection circuit includes a first selection circuit 31 and a second selection circuit 32
  • the above-mentioned sampling circuit includes a first sampling circuit 33 and a second sampling circuit 34;
  • the two input terminals a and b of the first selection circuit 31 are respectively connected to the output terminal of the first input buffer circuit 10 and the output terminal of the second input buffer circuit 20, and the two input terminals a and b of the second selection circuit 32 are respectively connected It is connected to the output terminal of the first input buffer circuit 10 and the output terminal of the second input buffer circuit 20 .
  • the output terminal of the first selection circuit 31 is connected to the input terminal of the first sampling circuit 33, the control terminal c of the first selection circuit 31 is connected to the output terminal of the second sampling circuit 34, and the output terminal of the second selection circuit 32 is connected to the second sampling circuit 34.
  • the input terminal of the sampling circuit 34 is connected, and the control terminal c of the second selection circuit 32 is connected to the output terminal of the first sampling circuit 33 .
  • the first sampling circuit 33 is used to send the currently collected data DQ_RISE to the control terminal c of the second selection circuit 32 , and the second selection circuit 32 selects the first input buffer circuit 10 based on the data DQ_RISE sent by the first sampling circuit 33 . Or the data in the second input buffer circuit 20 is input to the second sampling circuit 34 .
  • the second sampling circuit 34 is used to send the currently collected data DQ_FALL to the control terminal c of the first selection circuit 31 .
  • the first selection circuit 31 selects the first input buffer circuit 10 based on the data DQ_FALL sent by the second sampling circuit 34 Or the data in the second input buffer circuit 20 is input to the first sampling circuit 33 .
  • the second selection circuit 32 selects to input the output data of the first input buffer circuit 10 to the second sampling circuit. 34 ; when the data DQ_RISE sent by the first sampling circuit 33 to the control terminal c of the second selection circuit 32 is 0, the second selection circuit 32 selects to input the output data of the second input buffer circuit 20 to the second sampling circuit 34 .
  • the first selection circuit 31 selects to input the output data of the first input buffer circuit 10 to the first sampling circuit 33;
  • the first selection circuit 31 selects to input the output data of the second input buffer circuit 20 to the first sampling circuit 33 .
  • the first selection circuit 31 and the second selection circuit 32 may adopt the same circuit structure, thereby improving the degree of circuit matching and saving circuit design costs.
  • the first sampling circuit 33 and the second sampling circuit 33 may also adopt the same circuit structure, so as to improve the degree of circuit matching and save the circuit design cost.
  • the above-mentioned equalization circuit also includes a sampling clock input circuit 50, the output ends of the sampling clock input circuit 50 are respectively connected with the sampling clock input ends of the first sampling circuit 33 and the second sampling circuit 34, and can be connected to the first sampling circuit 33.
  • a sampling clock signal is provided with the second sampling circuit 34 .
  • the sampling clock input circuit 50 can receive sampling clock signals DQS and DQSB which are opposite to each other.
  • sampling clock input circuit 50 also includes a comparator circuit and a delay circuit.
  • the delay circuit can be used to adjust the phase of the sampling clock signal output by the comparator circuit.
  • the first sampling circuit 33 performs data sampling based on the data signal output by the first selection circuit 31, collects and obtains the data DQ_RISE, and sends the data DQ_RISE to the second selection circuit.
  • the circuit 32 is used as the control signal of the second selection circuit 32; when the received sampling clock signal DQS is a falling edge, the second sampling circuit 34 performs data sampling based on the data signal output by the second selection circuit 32, and collects the data DQ_FALL, The data DQ_FALL is sent to the first selection circuit 31 as a control signal of the first selection circuit 31 .
  • the first input buffer circuit 10 includes a first comparator circuit 11 and a first delay circuit 12, the first comparator circuit 11 and the first delay circuit 12 are connected in series, and the first comparator circuit The reference voltage input terminal of 11 is connected to the first reference voltage output terminal H.
  • the second input buffer circuit 20 includes a second comparator circuit 21 and a second delay circuit 22, the second comparator circuit 21 and the second delay circuit 22 are connected in series, and the reference voltage input terminal of the second comparator circuit 21 is connected to the second delay circuit 22. Two reference voltage output terminals L are connected.
  • the signal input terminal of the first comparator circuit 11 and the signal input terminal of the second comparator circuit 21 are connected to the same input data signal DQ.
  • the first delay element 12 can be used to adjust the phase of the DQ signal, so that the DQ signal received by the first sampling circuit 33 can be synchronized with the sampling clock signal, so that the first sampling circuit 33 can collect the data according to the sampling clock signal. correct data.
  • the second delay element 22 is also used to adjust the phase of the DQ signal, so that the DQ signal received by the second sampling circuit 34 is synchronized with the sampling clock signal, so that the second sampling circuit 34 can collect correct data according to the sampling clock signal .
  • the first comparator circuit 11 and the second comparator circuit 21 may adopt the same circuit structure, thereby improving the degree of circuit matching and saving circuit design costs.
  • the first delay circuit 12 and the second delay circuit 22 may also adopt the same circuit structure, so as to improve the degree of circuit matching and save the cost of circuit design.
  • the data previously output by the equalization circuit is the data collected by the second sampling circuit 34 at the sampling clock.
  • the signal DQS is the data collected at the previous adjacent falling edge of the rising edge; if the data currently output by the equalization circuit is the data collected by the second sampling circuit 34 when the sampling clock signal DQS is at the falling edge, the equalization circuit
  • the data outputted by the circuit last time is the data collected by the first sampling circuit 33 when the sampling clock signal DQS is the preceding adjacent rising edge of the falling edge.
  • FIG. 3 is a waveform diagram of the equalization circuit provided in the embodiments of the present application in the process of collecting data.
  • DQ_VREFDQADD represents the data output by the first input buffer circuit 10 based on the DQ signal and the first reference voltage H, including DQ0, DQ1, DQ2...
  • DQ_VREFDQSUB represents the second input buffer circuit 20 based on the DQ signal and the second reference voltage.
  • L output data also including DQ0, DQ1, DQ2...
  • the sampling clock signal DQS received by the first sampling circuit 33 when the sampling clock signal DQS received by the first sampling circuit 33 is a rising edge, the data DQ0 is collected, and DQ0 is sent to the second selection circuit 32. If the value of the data DQ0 is 1, the second The selection circuit 32 outputs the data generated in the first input buffer circuit 10 to the second sampling circuit 34 through its input terminal a. When the sampling clock signal DQS received by the second sampling circuit 34 is a falling edge, the data can be collected.
  • the second sampling circuit 34 collects the data DQ1, it sends DQ1 to the first selection circuit 31. If the value of the above-mentioned data DQ1 is 1, the first selection circuit 31 sends the first selection circuit 31 to the first selection circuit 31 through its input terminal a. The data generated in the input buffer circuit 10 is output to the first sampling circuit 33.
  • the sampling clock signal DQS received by the first sampling circuit 33 is a rising edge
  • the data DQ2 output by the first input buffer circuit 10 can be collected; if If the value of the above data DQ1 is 0, the first selection circuit 31 outputs the data generated in the second input buffer circuit 20 to the first sampling circuit 33 through its input terminal b, and the sampling clock received by the first sampling circuit 33
  • the signal DQS is on the rising edge
  • the data DQ2 output by the second input buffer circuit 20 can be collected.
  • the first reference voltage is to enhance the reference reference voltage
  • the second reference voltage is to weaken the reference reference voltage. Therefore, when the previous output data of the equalization circuit is 1, the data signal output by the first input buffer circuit whose reference voltage is the first reference voltage is selected for data sampling; when the previous output data of the equalization circuit is 0, the selected The data sampling of the data signal output by the second input buffer circuit whose reference voltage is the second reference voltage can effectively improve the input voltage margin of the equalization circuit, thereby effectively eliminating ISI and improving the eye opening size of the written data.
  • FIG. 4 is a schematic diagram of an equalization processing effect of the equalization circuit provided in the embodiments of the present application.
  • the data signal output by the second input buffer circuit whose reference voltage is the second reference voltage VREFDQ_SUB is selected for data sampling, and the input voltage margin of the equalization circuit ( Black arrows) are significantly larger than the input voltage margin (grey arrows) of the equalization circuit when data sampling is performed through the data signal output by the input buffer circuit whose reference voltage is the reference reference voltage VREFDQ.
  • the equalization circuit provided by the embodiment of the present application includes two types of input buffer circuits using different reference voltages.
  • an appropriate input buffer circuit is selected from the two input buffer circuits based on the previous output data of the equalization circuit.
  • the buffer circuit then performs data sampling on the data signal output by the selected input buffer circuit, which can effectively increase the input voltage margin of the equalization circuit, thereby improving the quality of the received data signal.
  • the embodiment of the present application further provides a data acquisition method, which is applied to the equalization circuit described in the foregoing embodiment, and the method includes:
  • the above method may be performed by a selective sampling circuit in the equalization circuit.
  • the output data is sent to the selection sampling circuit, which, when the received sampling clock signal is a rising edge or a falling edge, according to the received data of the previous output of the equalization circuit , select to perform data sampling on the data signal output by one of the input buffer circuits in the two input buffer circuits, and use the collected data as the data currently output by the equalization circuit.
  • the data acquisition method when collecting data, it is necessary to select one of the output data signals from the two input buffer circuits of the equalization circuit according to the data outputted by the equalization circuit last time for data acquisition, so as to advance the data acquisition. Perform data equalization processing, thereby eliminating ISI more effectively and improving the quality of the received data signal.
  • an embodiment of the present application further provides a memory, where the memory includes the equalization circuit described in the above embodiments.
  • the memory includes the equalization circuit described in the above embodiments.

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Abstract

本申请提供一种均衡电路、数据采集方法及存储器，均衡电路包括第一输入缓冲电路、第二输入缓冲电路以及选择采样电路；其中，第一输入缓冲电路与第二输入缓冲电路分别与选择采样电路连接，且第一输入缓冲电路与第二输入缓冲电路采用的参考电压不同；选择采样电路根据均衡电路前一次输出的数据，选择对第一输入缓冲电路或第二输入缓冲电路输出的数据信号进行数据采样，并将采集到的数据作为均衡电路当前输出的数据。即上述均衡电路包括两个不同的输入缓冲电路，选择采样电路在采集数据时，需要根据均衡电路前一次输出的数据，从上述两个输入缓冲电路中选择其中一个所输出数据信号进行数据采集，由此可以更加有效的提升接收数据信号的质量。

Description

均衡电路、数据采集方法及存储器
本申请要求于2020年09月24日提交中国专利局、申请号为202011018885.X、申请名称为“均衡电路、数据采集方法及存储器”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请实施例涉及集成电路技术领域，尤其涉及一种均衡电路、数据采集方法及存储器。
背景技术
在计算机高速链路中，随着数据信号的传输速度变得越来越快，难免会产生明显的符号间干扰(Inter Symbol Interference，简称ISI)。因此需要对高速链路数据信号进行均衡处理，以重新获得可使用的数据信号。
在内存接收器电路设计中，主要采用连续时间线性均衡器(Continuous Time Linear Equalizer，CTLE)架构来进行均衡处理,其功能是根据信道的衰减特性进行信号补偿，以提高数据信号的质量。
然而，现有的均衡处理方式已经难以满足高速接收器对接收数据信号的质量的要求。因此，如何进一步提高接收数据信号的质量，目前亟需解决。
发明内容
本申请实施例提供一种均衡电路、数据采集方法及存储器，可以有效提高接收数据信号的质量。
第一方面，本申请实施例提供了一种均衡电路，包括：第一输入缓冲电路、第二输入缓冲电路以及选择采样电路，第一输入缓冲电路与第二输入缓冲电路分别与选择采样电路连接，且第一输入缓冲电路与第二输入缓冲电路采用的参考电压不同。
选择采样电路根据均衡电路前一次输出的数据，选择对第一输入缓冲电路输出的数据信号或第二输入缓冲电路输出的数据信号进行数据采样，并将采集到的数据作为均衡电路当前输出的数据。
本申请实施例所提供的均衡电路，包括两种采用不同参考电压的输入缓冲电路，在采集数据时，均基于均衡电路前一次输出的数据，从上述两个输入缓冲电路中选择合适的一个输入缓冲电路，然后对所选择的输入缓冲电路所输出的数据信号进行数据采样，可以有效增加均衡电路的输入电压裕度，进而提升接收数据信号的质量。
在一种可行的实施方式中，上述均衡电路还包括双参考电压产生器；所述双参考电压产生器包括第一参考电压输出端与第二参考电压输出端，所述第一参考电压输出端与所述第一输入缓冲电路的参考电压输入端连接，所述第二参考电压输出端与所述第二输入缓冲电路的参考电压输入端连接。
在一种可行的实施方式中，所述选择采样电路包括选择电路与采样电路，所述选择电路与所述采样电路连接；所述选择电路用于根据所述采样电路发送的数据，选择将所述第一输入缓冲电路输出的数据信号或所述第二输入缓冲电路输出的数据信号输入至所述采样电路；所述采样电路用于对所述选择电路输入的数据信号进行数据采样。
在一种可行的实施方式中，所述选择电路包括第一选择电路与第二选择电路，所述采样电路包括第一采样电路与第二采样电路。
所述第一选择电路的两个输入端分别与所述第一输入缓冲电路的输出端和所述第二输入缓冲电路的输出端连接，所述第二选择电路的两个输入端分别与所述第一输入缓冲电路的输出端和所述第二输入缓冲电路的输出端连接。
所述第一选择电路的输出端与所述第一采样电路的输入端连接，所述第一选择电路的控制端与所述第二采样电路的输出端连接，所述第二选择电路的输出端与所述第二采样电路的输入端连接，所述第二选择电路的控制端与所述第一采样电路的输出端连接。
在一种可行的实施方式中，所述第一采样电路将当前采集到的数据发送至所述第二选择电路的控制端，所述第二选择电路基于所述第一采样电路发送的数据，选择将所述第一输入缓冲电路或所述第二输入缓冲电路中的数据输入至所述第二采样电路；所述第二采样电路将当前采集到的数据发送至所述第一选择电路的控制端，所述第一选择电路基于所述第二采样电路发送的数据，选择将所述第一输入缓冲电路或所述第二输入缓冲电路 中的数据输入至所述第一采样电路。
在一种可行的实施方式中，当所述第一采样电路发送至所述第二选择电路的控制端的数据为1时，所述第二选择电路选择将所述第一输入缓冲电路的输出数据输入至所述第二采样电路；当所述第一采样电路发送至所述第二选择电路的控制端的数据为0时，所述第二选择电路选择将所述第二输入缓冲电路的输出数据输入至所述第二采样电路。
当所述第二采样电路发送至所述第一选择电路的控制端的数据为1时，所述第一选择电路选择将所述第一输入缓冲电路的输出数据输入至所述第一采样电路；当所述第二采样电路发送至所述第一选择电路的控制端的数据为0时，所述第一选择电路选择将所述第二输入缓冲电路的输出数据输入至所述第一采样电路。
在一种可行的实施方式中，所述均衡电路还包括采样时钟输入电路，所述采样时钟输入电路的输出端分别与所述第一采样电路和所述第二采样电路的采样时钟输入端连接；所述采样时钟输入电路用于向所述第一采样电路和所述第二采样电路提供采样时钟信号。
在一种可行的实施方式中，所述第一采样电路利用所述均衡电路接收到的采样时钟信号的上升沿，对所述第一选择电路输入的数据进行数据采样；所述第二采样电路利用所述均衡电路接收到的采样时钟信号的下降沿，对所述第二选择电路输入的数据进行数据采样。
在一种可行的实施方式中，若所述均衡电路当前输出的数据为所述第一采样电路利用均衡电路接收到的采样时钟信号的上升沿所采集到的数据，则所述均衡电路前一次输出的数据为所述第二采样电路利用均衡电路接收到的采样时钟信号为所述上升沿的前一个相邻下降沿所采集到的数据。
若所述均衡电路当前输出的数据为所述第二采样电路利用均衡电路接收到的采样时钟信号的下降沿所采集到的数据，则所述均衡电路前一次输出的数据为所述第一采样电路利用均衡电路接收到的采样时钟信号为所述下降沿的前一个相邻上升沿所采集到的数据。
在一种可行的实施方式中，所述第一输入缓冲电路中包括第一比较器电路与第一延时电路，所述第一比较器电路与所述第一延时电路串联，所述第一比较器电路的参考电压输入端与所述第一参考电压输出端连接。
所述第二输入缓冲电路中包括第二比较器电路与第二延时电路，所述第二比较器电路与所述第二延时电路串联，所述第二比较器电路的参考电压输入端与所述第二参考电压输出端连接。
所述第一比较器电路的信号输入端与所述第二比较器电路的信号输入端连接相同的输入数据信号。
在一种可行的实施方式中，所述第一比较器电路与所述第二比较器电路采用相同的电路结构。
在一种可行的实施方式中，所述第一延时电路与所述第二延时电路采用相同的电路结构。
在一种可行的实施方式中，所述第一选择电路与所述第二选择电路采用相同的电路结构。
在一种可行的实施方式中，所述第一采样电路与所述第二采样电路采用相同的电路结构。
在一种可行的实施方式中，所述第一输入缓冲电路采用的参考电压大于所述第二输入缓冲电路采用的参考电压。
第二方面，本申请实施例提供了一种数据采集方法，应用于均衡电路，该均衡电路包括两个输入缓冲电路，这两个输入缓冲电路采用的参考电压不同。
上述数据采集方法包括：
响应于采样时钟信号，根据所述均衡电路前一次输出的数据，选择对所述两个输入缓冲电路中的其中一个输入缓冲电路输出的数据信号进行数据采样，并将采集到的数据作为所述均衡电路当前输出的数据。
本申请实施例所提供的数据采集方法，在采集数据时，均基于均衡电路前一次输出的数据，从两个不同输入缓冲电路中选择合适的一个输入缓冲电路，然后对所选择的输入缓冲电路所输出的数据信号进行数据采样，可以有效增加均衡电路的输入电压裕度，进而提升接收数据信号的质量。
第三方面，本申请实施例提供了一种存储器，该存储器包括均衡电路，该均衡电路为本申请实施例第一方面所提供的均衡电路。
本申请实施例所提供的均衡电路、数据采集方法及存储器中，均衡电路包括两个具有不同参考电压的输入缓冲电路，选择采样电路在采集数据 时，需要根据均衡电路前一次输出的数据，从上述两个输入缓冲电路中选择其中一个所输出数据信号进行数据采集，以提前进行数据均衡处理，由此可以更加有效的消除ISI，提升接收数据信号的质量。
附图说明
为了更清楚地说明本申请实施例或现有技术中的技术方案，下面将对本申请实施例或现有技术描述中所需要使用的附图作一简单地介绍，显而易见地，下面描述中的附图是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其它的附图。
图1为本申请实施例中提供的一种均衡电路的电路结构示意图；
图2为本申请实施例中提供的另一种均衡电路的电路结构示意图；
图3为本申请实施例中提供的均衡电路在采集数据过程中的波形图；
图4为本申请实施例中所提供的均衡电路的均衡处理效果示意图。
具体实施方式
为使本申请实施例的目的、技术方案和优点更加清楚，下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
本申请实施例提供了一种新型的均衡电路，可以应用于各种类型的存储器，具体可以应用于各类存储器产品中的接收器电路，例如，可以应用于DDR4型内存中的接收器电路。
另外，在设计高速接收器时，也可采用本申请实施例提供的均衡电路。
目前在内存的接收器电路设计中，主要采用CTLE架构来进行均衡处理,其功能是根据信道的衰减特性进行信号补偿，以提高信号的质量。但是现有的这种均衡处理方式已经难以满足如DDR4型内存对信号质量的要求。
为了提高信号质量，本申请实施例所提供的均衡电路中包括两个具有不同参考电压的输入缓冲电路，选择采样电路在采集数据时，均基于前一 次所采集到的数据，从上述两个输入缓冲电路中选择合适的一个输入缓冲电路，并基于所选择的输入缓冲电路输出的数据信号进行数据采样，以提前进行数据均衡处理，从而可以更加有效的消除ISI，提升接收数据信号的质量。
参照图1，图1为本申请实施例中提供的一种均衡电路的电路结构示意图。上述均衡电路包括：第一输入缓冲电路10、第二输入缓冲电路20以及选择采样电路30。其中：
第一输入缓冲电路10与第二输入缓冲电路20分别与选择采样电路30连接，且第一输入缓冲电路10与第二输入缓冲电路20采用的参考电压不同。
选择采样电路30根据均衡电路前一次输出的数据，选择对第一输入缓冲电路10输出的数据信号或第二输入缓冲电路20输出的数据信号进行数据采样，并将采集到的数据作为均衡电路当前输出的数据。
示例性的，当均衡电路前一次输出的数据的值为1时，选择采样电路30选择对第一输入缓冲电路10输出的数据信号进行数据采样，并将采集到的数据作为均衡电路当前输出的数据；当均衡电路前一次输出的数据的值为0时，选择采样电路30选择对第二输入缓冲电路20输出的数据信号进行数据采样，并将采集到的数据作为均衡电路当前输出的数据。
可以理解的是，由于第一输入缓冲电路10与第二输入缓冲电路20所采用的参考电压不同，因此第一输入缓冲电路10与第二输入缓冲电路20对接收数据与参考电压进行比较时的电压裕度也会不同。当选择采样电路30在采集数据时，根据均衡电路前一次输出的数据，来选择从第一输入缓冲电路10所输出的数据信号中进行数据采集还是从第二输入缓冲电路20所输出的数据信号中进行数据采集，由此使上述均衡电路能够根据前一次输出的数据提前进行数据均衡处理，有助于消除ISI，提高接收数据信号的质量。
进一步的，基于上述实施例中所描述的内容，参照图2，图2为本申请实施例中提供的另一种均衡电路的电路结构示意图。本申请一种可行的实施方式中，上述均衡电路还包括参考电压产生器40，其中：
参考电压产生器40包括第一参考电压输出端H与第二参考电压输出 端L，第一参考电压输出端H输出的第一参考电压与第二参考电压输出端L输出的第二参考电压不同。
可选的，第一参考电压大于第二参考电压。
其中，第一参考电压输出端H与第一输入缓冲电路10的参考电压输入端连接，第二参考电压输出端L与第二输入缓冲电路20的参考电压输入端连接。
在本申请实施例中，选择采样电路30包括选择电路与采样电路，该选择电路与采样电路连接。其中，上述选择电路可以用于根据上述采样电路发送的数据，选择将第一输入缓冲电路10输出的数据信号或第二输入缓冲电路20输出的数据信号输入至上述采样电路；上述采样电路用于对该选择电路输入的数据信号进行数据采样。
具体的，仍参照图2，上述选择电路包括第一选择电路31与第二选择电路32，上述采样电路包括第一采样电路33与第二采样电路34；其中：
第一选择电路31的两个输入端a和b分别与第一输入缓冲电路10的输出端和第二输入缓冲电路20的输出端连接，第二选择电路32的两个输入端a和b分别与第一输入缓冲电路10的输出端和第二输入缓冲电路20的输出端连接。
第一选择电路31的输出端与第一采样电路33的输入端连接，第一选择电路31的控制端c与第二采样电路34的输出端连接，第二选择电路32的输出端与第二采样电路34的输入端连接，第二选择电路32的控制端c与第一采样电路33的输出端连接。
第一采样电路33用于将当前采集到的数据DQ_RISE发送至第二选择电路32的控制端c，第二选择电路32基于第一采样电路33发送的数据DQ_RISE，选择将第一输入缓冲电路10或第二输入缓冲电路20中的数据输入至第二采样电路34。
第二采样电路34用于将当前采集到的数据DQ_FALL发送至第一选择电路31的控制端c，第一选择电路31基于第二采样电路34发送的数据DQ_FALL，选择将第一输入缓冲电路10或第二输入缓冲电路20中的数据输入至第一采样电路33。
可选的，当第一采样电路33发送至第二选择电路32的控制端c的数 据DQ_RISE为1时，第二选择电路32选择将第一输入缓冲电路10的输出数据输入至第二采样电路34；当第一采样电路33发送至第二选择电路32的控制端c的数据DQ_RISE为0时，第二选择电路32选择将第二输入缓冲电路20的输出数据输入至第二采样电路34。
当第二采样电路34发送至第一选择电路31的控制端c的数据DQ_FALL为1时，第一选择电路31选择将第一输入缓冲电路10的输出数据输入至第一采样电路33；当第二采样电路34发送至第一选择电路31的控制端c的数据DQ_FALL为0时，第一选择电路31选择将第二输入缓冲电路20的输出数据输入至第一采样电路33。
可选的，第一选择电路31与第二选择电路32可以采用相同的电路结构，由此可以提高电路匹配程度，节省电路设计成本。
可选的，第一采样电路33与第二采样电路33也可以采用相同的电路结构，以提高电路匹配程度，节省电路设计成本。
进一步的，上述均衡电路还包括采样时钟输入电路50，该采样时钟输入电路50的输出端分别与第一采样电路33与第二采样电路34的采样时钟输入端连接，可以向第一采样电路33与第二采样电路34提供采样时钟信号。
其中，采样时钟输入电路50可以接收互为反向的采样时钟信号DQS和DQSB。
另外，采样时钟输入电路50中还包括比较器电路和延时电路。其中，延时电路可以用于调节比较器电路输出的采样时钟信号的相位。
示例性的，第一采样电路33在接收到的采样时钟信号DQS为上升沿时，基于第一选择电路31输出的数据信号进行数据采样，采集得到数据DQ_RISE，并将数据DQ_RISE发送至第二选择电路32，作为第二选择电路32的控制信号；第二采样电路34在接收到的采样时钟信号DQS为下降沿时，基于第二选择电路32输出的数据信号进行数据采样，采集得到数据DQ_FALL，并将数据DQ_FALL发送至第一选择电路31，作为第一选择电路31的控制信号。
进一步的，仍参照图2，第一输入缓冲电路10中包括第一比较器电路11与第一延时电路12，第一比较器电路11与第一延时电路12串联，第一 比较器电路11的参考电压输入端与第一参考电压输出端H连接。
第二输入缓冲电路20中包括第二比较器电路21与第二延时电路22，第二比较器电路21与第二延时电路22串联，第二比较器电路21的参考电压输入端与第二参考电压输出端L连接。
其中，第一比较器电路11的信号输入端与第二比较器电路21的信号输入端连接相同的输入数据信号DQ。
其中，第一延时元件12可以用于调节DQ信号的相位，使第一采样电路33接收到的DQ信号与采样时钟信号能够保持同步，从而使得第一采样电路33能够根据采样时钟信号采集到正确的数据。第二延时元件22同样用于调节DQ信号的相位，使第二采样电路34接收到的DQ信号与采样时钟信号保持同步，从而使得第二采样电路34能够根据采样时钟信号采集到正确的数据。
可选的，第一比较器电路11与第二比较器电路21可以采用相同的电路结构，由此可以提高电路匹配程度，节省电路设计成本。
可选的，第一延时电路12与第二延时电路22也可以采用相同的电路结构，以提高电路匹配程度，节省电路设计成本。
可以理解的是，若均衡电路当前输出的数据为第一采样电路33在采样时钟信号DQS为上升沿时所采集到的数据，则均衡电路前一次输出的数据为第二采样电路34在采样时钟信号DQS为该上升沿的前一个相邻下降沿时所采集到的数据；若均衡电路当前输出的数据为第二采样电路34在采样时钟信号DQS为下降沿时所采集到的数据，则均衡电路前一次输出的数据为第一采样电路33在采样时钟信号DQS为该下降沿的前一个相邻上升沿时所采集到的数据。
为了更好的理解本申请实施例，参照图3，图3为本申请实施例中提供的均衡电路在采集数据过程中的波形图。
在图3中，DQ_VREFDQADD表示第一输入缓冲电路10基于DQ信号与第一参考电压H输出的数据，包括DQ0、DQ1、DQ2……DQ_VREFDQSUB表示第二输入缓冲电路20基于DQ信号与第二参考电压L输出数据，同样包括DQ0、DQ1、DQ2……
本申请实施例中，当第一采样电路33接收到的采样时钟信号DQS为 上升沿时，采集数据DQ0，并将DQ0发送至第二选择电路32，若数据DQ0的值为1，则第二选择电路32通过其输入端a，将第一输入缓冲电路10中产生的数据输出至第二采样电路34，在第二采样电路34接收到的采样时钟信号DQS为下降沿时，即可采集到第一输入缓冲电路10输出的数据DQ1；若数据DQ0的值为0，则第二选择电路32通过其输入端b，将第二输入缓冲电路20中产生的数据输出至第二采样电路34，在第二采样电路34接收到的采样时钟信号DQS为下降沿时，即可采集到第二输入缓冲电路20输出的数据DQ1。
同理，在第二采样电路34采集到数据DQ1后，便将DQ1发送至第一选择电路31，若上述数据DQ1的值为1，则第一选择电路31通过其输入端a，将第一输入缓冲电路10中产生的数据输出至第一采样电路33，在第一采样电路33接收到的采样时钟信号DQS为上升沿时，即可采集到第一输入缓冲电路10输出的数据DQ2；若上述数据DQ1的值为0，则第一选择电路31通过其输入端b，将第二输入缓冲电路20中产生的数据输出至第一采样电路33，在第一采样电路33接收到的采样时钟信号DQS为上升沿时，即可采集到第二输入缓冲电路20输出的数据DQ2。
基于上述实施例中所描述的内容，在本申请一种可行的实施方式中，第一参考电压是对基准参考电压进行了增强，第二参考电压则是对基准参考电压进行了减弱。因此，当均衡电路前一次输出的数据为1时，选择参考电压为第一参考电压的第一输入缓冲电路所输出的数据信号进行数据采样；当均衡电路前一次输出的数据为0时，选择参考电压为第二参考电压的第二输入缓冲电路所输出的数据信号进行数据采样，能够有效提升均衡电路的输入电压裕度，从而有效的消除ISI，提高写入数据的眼图睁开大小。
为了更好的理解本申请实施例，参照图4，图4为本申请实施例中所提供的均衡电路的均衡处理效果示意图。
在图4中，可以明显的看出，当均衡电路前一次输出的数据Pre_Data的值为1时，选择参考电压为第一参考电压VREFDQ_ADD的第一输入缓冲电路所输出的数据信号进行数据采样，均衡电路的输入电压裕度(黑色箭头所示)明显大于通过参考电压为基准参考电压VREFDQ的输入缓冲电路所输出的数据信号进行数据采样时，上述均衡电路的输入电压裕度(灰 色箭头所示)。
同理，当均衡电路前一次输出的数据Pre_Data的值为0时，选择参考电压为第二参考电压VREFDQ_SUB的第二输入缓冲电路所输出的数据信号进行数据采样，均衡电路的输入电压裕度(黑色箭头所示)明显大于通过参考电压为基准参考电压VREFDQ的输入缓冲电路所输出的数据信号进行数据采样时，上述均衡电路的输入电压裕度(灰色箭头所示)。
本申请实施例所提供的均衡电路，包括两种采用不同参考电压的输入缓冲电路，在采集数据时，均基于均衡电路前一次输出的数据，从上述两个输入缓冲电路中选择合适的一个输入缓冲电路，然后对所选择的输入缓冲电路所输出的数据信号进行数据采样，可以有效增加均衡电路的输入电压裕度，进而提升接收数据信号的质量。
进一步的，基于上述实施例中所描述的均衡电路，本申请实施例中还提供一种数据采集方法，应用于上述实施例中所描述的均衡电路，该方法包括：
响应于采样时钟信号，根据均衡电路前一次输出的数据，选择对两个输入缓冲电路中的其中一个输入缓冲电路输出的数据信号进行数据采样，并将采集到的数据作为均衡电路当前输出的数据。
可选的，上述方法可以由均衡电路中的选择采样电路执行。例如，均衡电路在输出一次数据后，将输出的数据发送至选择采样电路，该选择采样电路在接收到的采样时钟信号为上升沿或下降沿时，根据接收到的均衡电路前一次输出的数据，选择对两个输入缓冲电路中的其中一个输入缓冲电路输出的数据信号进行数据采样，并将采集到的数据作为均衡电路当前输出的数据。
即本申请实施例所提供的数据采集方法，在采集数据时，需要根据均衡电路前一次输出的数据，从均衡电路的两个输入缓冲电路中选择其中一个所输出数据信号进行数据采集，以提前进行数据均衡处理，由此可以更加有效的消除ISI，提升接收数据信号的质量。
需要说明的是，上述数据采集方法所采用的处理方式可以参照上述实施例中所描述的均衡电路的工作原理，在此不再赘述。
进一步的，基于上述实施例中所描述的均衡电路，本申请实施例中还 提供一种存储器，该存储器包括上述实施例中所描述的均衡电路。具体可以参照上述实施例中所描述的均衡电路的工作原理，在此不再赘述。
最后应说明的是：以上各实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述各实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的范围。

Claims (17)

  1. 一种均衡电路，其特征在于，所述均衡电路包括：第一输入缓冲电路、第二输入缓冲电路以及选择采样电路，所述第一输入缓冲电路与所述第二输入缓冲电路分别与所述选择采样电路连接，且所述第一输入缓冲电路与所述第二输入缓冲电路采用的参考电压不同；
    所述选择采样电路根据所述均衡电路前一次输出的数据，选择对所述第一输入缓冲电路输出的数据信号或所述第二输入缓冲电路输出的数据信号进行数据采样，并将采集到的数据作为所述均衡电路当前输出的数据。
  2. 根据权利要求1所述的均衡电路，其特征在于，所述均衡电路还包括双参考电压产生器；
    所述双参考电压产生器包括第一参考电压输出端与第二参考电压输出端；所述第一参考电压输出端与所述第一输入缓冲电路的参考电压输入端连接，所述第二参考电压输出端与所述第二输入缓冲电路的参考电压输入端连接。
  3. 根据权利要求1所述的均衡电路，其特征在于，所述选择采样电路包括选择电路与采样电路，所述选择电路与所述采样电路连接；
    所述选择电路用于根据所述采样电路发送的数据，选择将所述第一输入缓冲电路输出的数据信号或所述第二输入缓冲电路输出的数据信号输入至所述采样电路；
    所述采样电路用于对所述选择电路输入的数据信号进行数据采样。
  4. 根据权利要求3所述的均衡电路，其特征在于，所述选择电路包括第一选择电路与第二选择电路，所述采样电路包括第一采样电路与第二采样电路；
    所述第一选择电路的两个输入端分别与所述第一输入缓冲电路的输出端和所述第二输入缓冲电路的输出端连接，所述第二选择电路的两个输入端分别与所述第一输入缓冲电路的输出端和所述第二输入缓冲电路的输出端连接；
    所述第一选择电路的输出端与所述第一采样电路的输入端连接，所述第一选择电路的控制端与所述第二采样电路的输出端连接，所述第二选择电路的输出端与所述第二采样电路的输入端连接，所述第二选择电路的控 制端与所述第一采样电路的输出端连接。
  5. 根据权利要求4所述的均衡电路，其特征在于，
    所述第一采样电路将当前采集到的数据发送至所述第二选择电路的控制端，所述第二选择电路基于所述第一采样电路发送的数据，选择将所述第一输入缓冲电路或所述第二输入缓冲电路中的数据输入至所述第二采样电路；
    所述第二采样电路将当前采集到的数据发送至所述第一选择电路的控制端，所述第一选择电路基于所述第二采样电路发送的数据，选择将所述第一输入缓冲电路或所述第二输入缓冲电路中的数据输入至所述第一采样电路。
  6. 根据权利要求5所述的均衡电路，其特征在于，
    当所述第一采样电路发送至所述第二选择电路的控制端的数据为1时，所述第二选择电路选择将所述第一输入缓冲电路的输出数据输入至所述第二采样电路；当所述第一采样电路发送至所述第二选择电路的控制端的数据为0时，所述第二选择电路选择将所述第二输入缓冲电路的输出数据输入至所述第二采样电路；
    当所述第二采样电路发送至所述第一选择电路的控制端的数据为1时，所述第一选择电路选择将所述第一输入缓冲电路的输出数据输入至所述第一采样电路；当所述第二采样电路发送至所述第一选择电路的控制端的数据为0时，所述第一选择电路选择将所述第二输入缓冲电路的输出数据输入至所述第一采样电路。
  7. 根据权利要求6所述的均衡电路，其特征在于，所述均衡电路还包括采样时钟输入电路，所述采样时钟输入电路的输出端分别与所述第一采样电路和所述第二采样电路的采样时钟输入端连接；
    所述采样时钟输入电路用于向所述第一采样电路和所述第二采样电路提供采样时钟信号。
  8. 根据权利要求7所述的均衡电路，其特征在于，所述第一采样电路利用所述均衡电路接收到的采样时钟信号的上升沿，对所述第一选择电路输入的数据进行数据采样；
    所述第二采样电路利用所述均衡电路接收到的采样时钟信号的下降沿， 对所述第二选择电路输入的数据进行数据采样。
  9. 根据权利要求8所述的均衡电路，其特征在于，
    若所述均衡电路当前输出的数据为所述第一采样电路利用所述均衡电路接收到的采样时钟信号的上升沿所采集到的数据，则所述均衡电路前一次输出的数据为所述第二采样电路利用所述均衡电路接收到的采样时钟信号为所述上升沿的前一个相邻下降沿所采集到的数据；
    若所述均衡电路当前输出的数据为所述第二采样电路利用所述均衡电路接收到的采样时钟信号的下降沿所采集到的数据，则所述均衡电路前一次输出的数据为所述第一采样电路利用所述均衡电路接收到的采样时钟信号为所述下降沿的前一个相邻上升沿所采集到的数据。
  10. 根据权利要求2所述的均衡电路，其特征在于，所述第一输入缓冲电路中包括第一比较器电路与第一延时电路，所述第一比较器电路与所述第一延时电路串联，所述第一比较器电路的参考电压输入端与所述第一参考电压输出端连接；
    所述第二输入缓冲电路中包括第二比较器电路与第二延时电路，所述第二比较器电路与所述第二延时电路串联，所述第二比较器电路的参考电压输入端与所述第二参考电压输出端连接；
    所述第一比较器电路的信号输入端与所述第二比较器电路的信号输入端连接相同的输入数据信号。
  11. 根据权利要求10所述的均衡电路，其特征在于，所述第一比较器电路与所述第二比较器电路采用相同的电路结构。
  12. 根据权利要求10所述的均衡电路，其特征在于，所述第一延时电路与所述第二延时电路采用相同的电路结构。
  13. 根据权利要求4至10任一项所述的均衡电路，其特征在于，所述第一选择电路与所述第二选择电路采用相同的电路结构。
  14. 根据权利要求4至10任一项所述的均衡电路，其特征在于，所述第一采样电路与所述第二采样电路采用相同的电路结构。
  15. 根据权利要求1至10任一项所述的均衡电路，其特征在于，所述第一输入缓冲电路采用的参考电压大于所述第二输入缓冲电路采用的参考电压。
  16. 一种数据采集方法，其特征在于，应用于均衡电路，所述均衡电路包括两个输入缓冲电路，所述两个输入缓冲电路采用的参考电压不同；
    所述方法包括：
    响应于采样时钟信号，根据所述均衡电路前一次输出的数据，选择对所述两个输入缓冲电路中的其中一个输入缓冲电路输出的数据信号进行数据采样，并将采集到的数据作为所述均衡电路当前输出的数据。
  17. 一种存储器，其特征在于，所述存储器包括均衡电路，所述均衡电路为权利要求1至15任一项所述的均衡电路。
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