WO2022057340A1 - 晶圆传送装置 - Google Patents

晶圆传送装置 Download PDF

Info

Publication number
WO2022057340A1
WO2022057340A1 PCT/CN2021/100186 CN2021100186W WO2022057340A1 WO 2022057340 A1 WO2022057340 A1 WO 2022057340A1 CN 2021100186 W CN2021100186 W CN 2021100186W WO 2022057340 A1 WO2022057340 A1 WO 2022057340A1
Authority
WO
WIPO (PCT)
Prior art keywords
wafer
placement slot
slot
placement
capacitance value
Prior art date
Application number
PCT/CN2021/100186
Other languages
English (en)
French (fr)
Inventor
傅荣
Original Assignee
长鑫存储技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 长鑫存储技术有限公司 filed Critical 长鑫存储技术有限公司
Priority to US17/451,528 priority Critical patent/US20220084854A1/en
Publication of WO2022057340A1 publication Critical patent/WO2022057340A1/zh

Links

Images

Classifications

    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B65—CONVEYING; PACKING; STORING; HANDLING THIN OR FILAMENTARY MATERIAL
    • B65D—CONTAINERS FOR STORAGE OR TRANSPORT OF ARTICLES OR MATERIALS, e.g. BAGS, BARRELS, BOTTLES, BOXES, CANS, CARTONS, CRATES, DRUMS, JARS, TANKS, HOPPERS, FORWARDING CONTAINERS; ACCESSORIES, CLOSURES, OR FITTINGS THEREFOR; PACKAGING ELEMENTS; PACKAGES
    • B65D85/00—Containers, packaging elements or packages, specially adapted for particular articles or materials
    • B65D85/30—Containers, packaging elements or packages, specially adapted for particular articles or materials for articles particularly sensitive to damage by shock or pressure
    • B65D85/48—Containers, packaging elements or packages, specially adapted for particular articles or materials for articles particularly sensitive to damage by shock or pressure for glass sheets
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/673—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere using specially adapted carriers or holders; Fixing the workpieces on such carriers or holders

Definitions

  • the present application relates to the technical field of semiconductor manufacturing, and in particular, to a wafer transfer device.
  • wafer transfer equipment plays a very important role, which is used to temporarily store wafers and transfer wafers between various stations.
  • the wafer transfer device can be an airtight container, so as to keep the environment inside the device stable and clean, and effectively avoid direct contact between the wafer and the external environment.
  • a Front Opening Unified Pod is a commonly used wafer transfer device.
  • a plurality of placement slots are provided in the FOUP, and each placement slot stores a wafer.
  • stacking refers to placing multiple wafers in one placement slot
  • oblique insertion refers to the situation where one wafer occupies two placement slots. Lamination, oblique insertion, etc. can easily cause damage to the wafer, affect the quality of the wafer, and may even lead to the scrapping of the wafer.
  • the present application provides a wafer transfer device, which can detect the state of the wafer in time when the wafer is loaded into the wafer transfer device, and take corresponding measures in time when the wafer state is abnormal.
  • a wafer transfer device comprising: a top plate and a bottom plate opposite to the top plate, a first side plate and a second side plate located between the top plate and the bottom plate and disposed opposite to the top plate, the A plurality of wafer slots are arranged between the top plate and the bottom plate, each wafer slot includes a first placement slot and a second placement slot, and the first placement slot is arranged on the first side plate toward the first placement slot. the surface of the two side plates, the second placement groove is arranged on the surface of the second side plate facing the first side plate;
  • the first placement slot and the second placement slot both include two oppositely arranged first and second polar plates, the first and second polar plates form a capacitor, and the first polar plate and the second polar plate form a capacitor.
  • the pole plate adopts a deformable pole plate, and when the wafer is placed on the first pole plate, the distance between the first pole plate and the second pole plate is reduced;
  • a detection circuit and a power supply are connected between the first pole plate and the second pole plate, and the power supply is used to provide voltage for the first pole plate and the second pole plate;
  • the detection circuit is used to detect the capacitance value corresponding to the first placement slot and the capacitance value corresponding to the second placement slot, according to the capacitance value corresponding to the first placement slot and the capacitance corresponding to the second placement slot.
  • the state of the wafers placed on the first placement slot and the second placement slot is determined according to the change of the value.
  • the detection circuit is specifically configured to: when the capacitance value corresponding to the first placement slot increases, determine that a wafer is placed in the first placement slot; or, when the second placement slot corresponds to When the capacitance value increases, it is determined that a wafer is placed in the second placement groove.
  • the detection circuit is specifically configured to: when the capacitance value corresponding to the first placement slot decreases, determine that the wafer placed in the first placement slot is taken away; or, when the second placement slot decreases When the capacitance value corresponding to the slot decreases, it is determined that the wafer placed in the second placement slot is taken away.
  • the detection circuit is specifically used for: when the capacitance value corresponding to the first placement slot or the second placement slot in the wafer slot increases, and the capacitance value corresponding to the other placement slot does not change, It is determined that the wafer in the wafer slot is skewed.
  • the detection circuit is specifically configured to: determine when the capacitance values corresponding to the first placement slot and the second placement slot in the wafer slot both increase, and the increase in the capacitance value is greater than the first threshold.
  • the wafers placed in the wafer slot are stacked.
  • the second pole plate is a deformable pole plate.
  • the detection circuit is further connected with a communication module
  • the communication module is used for sending the state of the wafer to a monitoring device.
  • the power supply is further connected with a switch, and the switch is used to control turning on and off of the power supply.
  • the device further includes: a display screen, connected to the detection circuit, for displaying the state of the wafer.
  • the device further includes: an alarm device, connected to the detection circuit, for outputting an alarm signal when the state of the wafer indicates that the wafer is stacked or inserted obliquely.
  • an alarm device connected to the detection circuit, for outputting an alarm signal when the state of the wafer indicates that the wafer is stacked or inserted obliquely.
  • a capacitor is formed by using two conductive electrode plates in the first placement slot and the second placement slot of the wafer slot, and a deformable material is used in the first electrode plate where the wafer is placed.
  • a detection circuit and a power supply are connected between the pole plates. The circuit is used to detect the capacitance value corresponding to the first placement slot and the capacitance value corresponding to the second placement slot. The change in the distance between the two plates will cause the capacitance value of the capacitor to change.
  • the change of the capacitance value and the capacitance value corresponding to the second placement slot determines the state of the wafers placed on the first placement slot and the second placement slot, and the wafer transfer device can load the wafer into the wafer transfer device in time. If the abnormal state of the wafer is found, corresponding measures should be taken in time.
  • FIG. 1 is a schematic structural diagram of a wafer transfer apparatus provided by an embodiment of the present application.
  • FIG. 2 is a schematic diagram of the overall structure of the wafer groove
  • Figure 3 is an enlarged side view of the placement slot
  • Figure 4 is a schematic diagram of the internal circuit of the placement slot
  • FIG. 5 is a schematic diagram of the state change of the placement groove being squeezed by the wafer.
  • top plate 11;
  • Second placement slot 16;
  • the first plate 151;
  • An embodiment of the present application provides a wafer transfer device with a detection function.
  • a deformable wafer groove By setting a deformable wafer groove, when a wafer is placed in the wafer groove, the wafer groove is pressed by the wafer. Deformation occurs, and the distance between the upper and lower plates of the wafer slot changes, resulting in a change in the capacitance value of the capacitor corresponding to the wafer slot. Therefore, the abnormal state of the wafer can be found in time when the wafer is loaded into the wafer transfer device, and corresponding measures can be taken in time.
  • FIG. 1 is a schematic structural diagram of a wafer transfer device provided by an embodiment of the present application
  • FIG. 2 is a schematic structural diagram of an overall wafer slot
  • FIG. 3 is an enlarged side view of a placement slot
  • FIG. 4 is a schematic diagram of an internal circuit of the placement slot. 1-FIG.
  • the wafer transfer device includes: a top plate 11 and a bottom plate 12 disposed opposite to the top plate 11, a first side plate 13 and a second side plate 14 located between the top plate 11 and the bottom plate 12 and oppositely disposed, and the top plate 11
  • a plurality of wafer slots are arranged between the bottom plate 12 and each wafer slot, and each wafer slot is used to place a wafer, and a plurality of wafers 20 are placed in the placement slot in sequence from top to bottom.
  • the direction refers to the direction from the top plate 11 to the bottom plate 12 .
  • the wafer transfer unit also includes a rear plate and a front door (not shown), which can be opened to open the front door during wafer loading to place wafers into the wafer slot.
  • Each wafer slot includes a first placement slot 15 and a second placement slot 16 , the first placement slot 15 is provided on the surface of the first side plate 13 facing the second side plate 14 , and the second placement slot 16 is provided on the second side plate 14 facing the surface of the first side plate 13, the first placement groove 15 and the second placement groove are in the same plane.
  • the first wafer groove 15 and the second wafer groove 16 may be rectangular, semicircular or elliptical, and the shapes of the first wafer groove 15 and the second wafer groove 16 are not limited in this embodiment.
  • the surface of the first side plate 13 facing the second side plate 14 is provided with a plurality of first placement grooves 15
  • the surface of the second side plate 14 facing the first side plate 13 is provided with a plurality of second placement grooves 16 .
  • a placement slot 15 is disposed in a one-to-one correspondence with the plurality of second placement slots 16 .
  • the first placement slot 15 and the second placement slot 16 both include two oppositely arranged first electrode plates 151 and second electrode plates 152, and the first electrode plates 151 and the second electrode plates 152 constitute a capacitor,
  • the polarities of the voltages applied to the first electrode plate 151 and the second electrode plate 152 are opposite, for example, when a positive voltage is applied to the first electrode plate 151, a negative voltage is applied to the second electrode plate 152, or, when the first electrode plate 152 is When a negative voltage is applied to the plate 151 , a positive voltage is applied to the second plate 152 .
  • the first electrode plate 151 is a deformable electrode plate, and the first electrode plate 151 is a electrode plate for placing the wafer 20.
  • the first electrode plate 151 is subjected to the The extrusion of the circle 20 is deformed, and the distance between the first electrode plate 151 and the second electrode plate 152 is reduced, thereby causing the capacitance value of the capacitor to change.
  • the second electrode plate 152 may adopt a deformable electrode plate, or may not use a deformable electrode plate.
  • the deformation material used for the first electrode plate 151 and the second electrode plate 152 is not limited in this embodiment.
  • the first placement slot 15 and the second placement slot 16 are equivalent to two parallel plate capacitors, and the capacitance formula of the parallel plate capacitor is:
  • ⁇ r is the relative permittivity
  • k is the electrostatic force constant
  • S is the facing area of the two pole plates of the capacitor
  • d is the distance between the two pole plates of the capacitor
  • U A - U B is the capacitor's The potential difference (ie voltage) between two plates.
  • FIG. 5 is a schematic diagram of the state change of the placement groove being squeezed by the wafer.
  • the distance between the two electrode plates is a constant value d1
  • the capacitance value corresponding to the first placement slot 15 and the capacitance value corresponding to the second placement slot 16 can be the same and a fixed value, and the fixed value can also be called the initial capacitance value corresponding to the first placement slot 15 The initial capacitance value corresponding to the second placement slot 16 .
  • the first electrode plate 151 of the first placement slot 15 or the second placement slot 16 is deformed due to being squeezed, resulting in the first electrode plate 151.
  • the distance between the second pole plate 152 and the first pole plate 152 is reduced, the distance between the first pole plate 151 and the second pole plate 152 is reduced to d2, d2 is smaller than d1, and d2 is reduced by ⁇ d relative to d1.
  • a detection circuit 153 and a power source 154 are connected between the first electrode plate 151 and the second electrode plate 152 , and the power source 154 is used to provide voltage for the first electrode plate 151 and the second electrode plate 152 .
  • the detection circuit 153 is used to detect the capacitance value corresponding to the first placement slot 15 and the capacitance value corresponding to the second placement slot 16. According to the change of the capacitance value corresponding to the first placement slot 15 and the capacitance value corresponding to the second placement slot 16, The states of the wafers placed on the first placement slot 15 and the second placement slot 16 are determined.
  • the capacitance value corresponding to the first placement slot 15 refers to the capacitance value of the capacitor formed by the two electrode plates included in the first placement slot 15
  • the capacitance value corresponding to the second placement slot 16 refers to the capacitance value of the capacitor formed by the two electrode plates included in the second placement slot 16 The capacitance value of the capacitor formed by the plates.
  • the detection circuit 153 can detect the capacitance value corresponding to the first placement slot 15 and the capacitance value corresponding to the second placement slot 16 in real time or periodically, and associate the detected capacitance value corresponding to the first placement slot 15 with the first placement slot 15
  • the initial capacitance value of the first placement slot 15 can be stored in the detection circuit 153 in advance. If the detected capacitance value corresponding to the first placement slot 15 is different from the initial capacitance value corresponding to the first placement slot 15 , it is determined that the capacitance value corresponding to the first placement slot 15 has changed, and the state of the wafer is determined according to the change.
  • the detection circuit 153 may further calculate the difference between the capacitance values according to the detected capacitance value corresponding to the first placement slot 15 and the initial capacitance value corresponding to the first placement slot 15 , and determine the state of the wafer according to the difference in the capacitance values .
  • the detection circuit 153 may also compare the capacitance value corresponding to the first placement slot 15 detected at the current moment with the capacitance value corresponding to the first placement slot 15 detected at the previous moment to determine the first placement slot 15 . Corresponding changes in capacitance value.
  • the detection circuit 153 may also compare the average capacitance value corresponding to the first placement slot 15 in the current detection cycle with the average capacitance value corresponding to the first placement slot 15 in the previous detection cycle to determine the first placement slot 15. The change of the capacitance value corresponding to the slot 15.
  • the state of the wafer 20 includes whether the wafer 20 is placed on the placement groove, or whether the wafer 20 is stacked, or whether the wafer 20 is obliquely inserted.
  • the wafer transfer device of this embodiment during the process of loading wafers into the wafer transfer device, it is possible to find out in time whether the wafer is in an abnormal state such as oblique insertion or stacking, and to deal with the abnormal state in time to avoid wafer The abnormal state causes wafer damage.
  • the wafer that is inserted obliquely may collide and damage the wafer during the process of transferring the wafer to the machine or other equipment by the wafer transfer device.
  • the oblique insertion of the wafer can be detected in time during the wafer loading process, and the staff can adjust the oblique insertion of the wafer in time to avoid damage to the wafer.
  • the first placement slot 15 and the second placement slot 16 further include a communication module 155, the communication module 155 is connected to the detection circuit 153, and the communication module 155 is used for sending the wafer status to the monitoring device.
  • the monitoring equipment is used to show the state of the wafer to the user, so that the user can know the state of the wafer in time.
  • the communication module 155 may communicate with the monitoring device in a wired or wireless manner.
  • the communication module 155 and the monitoring device may communicate with the wireless assurance (Wireless Fidelity, WIFI for short) technology or Bluetooth technology (bluetooth).
  • the wafer transfer device further includes a display screen, and the display screen is connected to the detection circuit 153.
  • each detection circuit 153 obtains the status of the wafer, it sends the status of the wafer to the display screen, and the status of the wafer is displayed through the display screen. .
  • the wafer transfer device further includes an alarm device, which is connected to the detection circuit 153 and outputs an alarm signal when the state of the wafer indicates that the wafer is slanted or stacked.
  • the alarm device may include Light Emitting Diode (LED for short) and/or a buzzer, the LED light notifies the staff that the wafer status is abnormal by flashing, and the buzzer informs the staff of the wafer status by issuing a specific sound signal An exception occurs.
  • LED Light Emitting Diode
  • the power supply 154 is further connected with a switch 156 , and the switch 156 is used to control the power supply 154 to be turned on and off.
  • wafers are typically loaded into wafer slots of wafer transfer devices by robotic arms, and typically, they are loaded sequentially from top to bottom.
  • the robot arm places the wafer 20 on the wafer groove, the distance between the two electrode plates decreases due to the deformation of the electrode plates of the first placing groove 15 and the second placing groove 16, and the distance between the electrode plates decreases.
  • the small value causes the capacitance value corresponding to the first placement slot 15 and the capacitance value corresponding to the second placement slot 16 to increase.
  • the detection circuit 153 When the detection circuit 153 detects that the capacitance value corresponding to the first placement slot 15 increases, it determines that a wafer is placed in the first placement slot 15, and when the detection circuit 153 detects that the capacitance value corresponding to the second placement slot 16 increases, it determines A wafer is placed in the second placement groove 16 . In this way, whether a wafer is placed in each wafer slot can be detected.
  • the detection circuit 153 detects that the capacitance value corresponding to the first placement slot 15 decreases, it determines that the wafer placed in the first placement slot 15 has been removed, and when the detection circuit 153 detects that the capacitance value corresponding to the second placement slot 16 decreases, it determines The wafers placed in the second placement slot 16 are removed.
  • the wafer should be placed in the first placement slot 15 and the second placement slot 16 of the same wafer slot, and the capacitance values corresponding to the first placement slot 15 and the second placement slot 16 of the wafer slot will increase. , it can be understood that due to the deviation of the wafer placement position 14 , a small deviation may occur in the increase of the capacitance values corresponding to the first placement groove 15 and the second placement groove 16 . If the wafer is inserted obliquely, for example, one end of the wafer is placed in the first placement slot 15 of the first wafer slot, and the other end of the wafer is placed in the second placement slot 16 of the second wafer slot, the first The wafer slot and the second wafer slot are two adjacent wafer slots.
  • the wafer can be determined whether the wafer is obliquely inserted according to the change of the capacitance values corresponding to the two placement slots in the first wafer slot, or it can be determined according to the capacitance values corresponding to the two placement slots in the second wafer slot. changes, to determine whether the wafer is skewed.
  • the capacitance value corresponding to the first placement slot 15 or the second placement slot 16 in the first wafer slot increases, and the capacitance value corresponding to the other placement slot does not change, determine Wafers in the first wafer slot are skewed.
  • the capacitance values corresponding to the first placement slot 15 and the second placement slot 16 in the first wafer slot both increase, it is determined that the wafer in the first wafer slot is not skewed.
  • Lamination means that two or more wafers are placed in one wafer slot. Under normal circumstances, only one wafer can be placed in one wafer slot.
  • Lamination refers to the first placement slot 15 and the first placement slot 15 and the second wafer placed opposite to each other. Two or more wafers are placed on the placement slots 16 . When the number of wafers placed in the wafer slot increases, the deformation of the first placement slot 15 and the second placement slot 16 of the wafer slot increases, and the two electrode plates of the first placement slot 15 and the second placement slot 16 increase. The distance between them is smaller, and correspondingly, the capacitance values corresponding to the first placement slot 15 and the second placement slot 16 also increase.
  • the deformation of the first placement slot 15 is 1 mm, that is, the distance between the two electrode plates is reduced by 1 mm, and the capacitance value corresponding to the first placement slot 15 is increased by 1 Farad (F);
  • F Farad
  • the shape of the first placement groove 15 is 1.5 mm, that is, the distance between the two plates is reduced by 1.5 mm, and the capacitance corresponding to the first placement groove 15 is reduced by 1.5 mm.
  • the value is increased by 1.3 Farads. Therefore, it can be determined whether the wafers placed in the wafer slot are stacked according to the increase in the capacitance values corresponding to the first placement slot 15 and the second placement slot 16 in the wafer slot.
  • the detection circuit 153 detects that the capacitance values corresponding to the first placement slot 15 and the second placement slot 16 in the wafer slot both increase, and the increase in the capacitance value is greater than the first threshold, it is determined that the wafer slot is in the wafer slot.
  • the placed wafers are stacked.
  • the detection circuit 153 determines whether the wafers are stacked according to changes in capacitance values corresponding to the first placement slot 15 and the second placement slot 16 in the wafer slot.
  • the detection circuit 153 can also determine whether the wafer is stacked according to the capacitance values corresponding to the first placement slot 15 and the second placement slot 16 in the wafer slot.
  • the capacitance values corresponding to the first placement slot 15 and the second placement slot 16 are both increased, and the capacitance values corresponding to the first placement slot 15 and the second placement slot 16 are both greater than the second threshold, the wafer placed in the wafer slot is determined. Lamination has occurred.
  • a capacitor is formed by using two conductive electrode plates in the first placement slot and the second placement slot of the wafer slot, and a deformable material is used in the first electrode plate where the wafer is placed.
  • a detection circuit and a power supply are connected between the plates.
  • the circuit is used to detect the capacitance value corresponding to the first placement slot and the capacitance value corresponding to the second placement slot. The change in the distance between the two plates will cause the capacitance value of the capacitor to change.
  • the change of the capacitance value and the capacitance value corresponding to the second placement slot determines the state of the wafers placed on the first placement slot and the second placement slot, and the wafer transfer device can load the wafer into the wafer transfer device in time. If the abnormal state of the wafer is found, corresponding measures should be taken in time.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Mechanical Engineering (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)

Abstract

本申请提供一种晶圆传送装置，通过将晶圆槽的第一放置槽和第二放置槽采用两个导电极板形成电容，并且将放置晶圆的第一极板采用形变材料，当晶圆放置到第一极板上时，第一极板和所述第二极板之间的距离减小，并在极板之间连接有检测电路和电源，电源用于为极板提供电压，检测电路用于检测第一放置槽对应的电容值以及第二放置槽对应的电容值，两个极板之间的距离变化，会导致电容的电容值发生变化，能够根据第一放置槽对应的电容值和第二放置槽对应的电容值的变化情况，确定第一放置槽和第二放置槽上放置的晶圆的状态，该晶圆传送装置能够在晶圆装载至晶圆传送装置中及时发现晶圆的异常状态，及时采取对应的措施。

Description

晶圆传送装置
本申请要求于2020年9月16日提交中国专利局、申请号为202010973763.X、申请名称为“晶圆传送装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及半导体制造技术领域，尤其涉及一种晶圆传送装置。
背景技术
在半导体制造过程中，晶圆传送装置起到了非常重要的作用，晶圆传送装置用于临时存储晶圆，以及在各个操作台之间传输晶圆。晶圆传输装置可以为密闭容器，以保持装置内的环境的稳定和洁净，有效避免晶圆与外界环境的直接接触。
前开式晶圆传送盒(Front Opening Unified Pod，FOUP)是常用的晶圆传送装置，FOUP中设置有多个放置槽，每个放置槽中存放一片晶圆。现有技术中，机械手臂将晶圆从操作台放置到晶圆传送装置的过程中，可能发生叠片、斜插等情况。叠片是指在一个放置槽中放了多片晶圆，斜插是指一片晶圆占用两个放置槽的情况。叠片、斜插等情况容易造成晶圆的损伤，影响晶圆的质量，甚至可能导致晶圆的报废。
因此，如何对晶圆传送装置中的晶圆状态进行检测，避免晶圆损伤，是目前亟待解决的技术问题。
发明内容
本申请提供一种晶圆传送装置，能够在晶圆装载至晶圆传送装置中及时检测到晶圆的状态，在晶圆状态发生异常时，及时采取对应措施。
本申请一方面提供一种晶圆传送装置，包括：顶板以及与所述顶板相对设置的底板，位于所述顶板与所述底板之间且相对设置的第一侧板和第二侧板，所述顶板和所述底板之间设置有多个晶圆槽，每个晶圆槽包括第一放置槽和第二放置槽，所述第一放置槽设置在所述第一侧板朝向所述第二侧板的表面，所述第二放置槽设置在所述第二侧板朝向所述第一侧板的表面；
所述第一放置槽和所述第二放置槽均包括两个相对设置的第一极板和第二极板，所述第一极板和所述第二极板形成电容器，所述第一极板采用形变极板，当晶圆放置到所述第 一极板上时，所述第一极板和所述第二极板之间的距离减小；
所述第一极板和所述第二极板之间连接有检测电路和电源，所述电源用于为所述第一极板和所述第二极板提供电压；
所述检测电路用于检测所述第一放置槽对应的电容值以及所述第二放置槽对应的电容值，根据所述第一放置槽对应的电容值和所述第二放置槽对应的电容值的变化情况，确定所述第一放置槽和所述第二放置槽上放置的晶圆的状态。
可选的，所述检测电路具体用于：当所述第一放置槽对应的电容值增大时，确定所述第一放置槽内放置有晶圆；或者，当所述第二放置槽对应的电容值增大时，确定所述第二放置槽内放置有晶圆。
可选的，所述检测电路具体用于：当所述第一放置槽对应的电容值减小时，确定所述第一放置槽内放置的晶圆被取走；或者，当所述第二放置槽对应的电容值减小时，确定所述第二放置槽内放置的晶圆被取走。
可选的，所述检测电路具体用于：当所述晶圆槽中的第一放置槽或者第二放置槽对应的电容值增大，另一个放置槽对应的电容值没有变化的情况下，确定所述晶圆槽中的晶圆发生了斜插。
可选的，所述检测电路具体用于：当所述晶圆槽中的第一放置槽和第二放置槽对应的电容值均增大，且电容值的增大量大于第一阈值时，确定所述晶圆槽中放置的晶圆发生了叠片。
可选的，所述第二极板采用形变极板。
可选的，所述检测电路还连接有通信模块；
所述通信模块，用于将所述晶圆的状态发送给监控设备。
可选的，所述电源还连接有开关，所述开关用于控制所述电源的开通和关闭。
可选的，所述装置还包括：显示屏，与所述检测电路连接，用于显示所述晶圆的状态。
可选的，所述装置还包括：报警装置，与所述检测电路连接，用于当所述晶圆的状态指示所述晶圆发生叠片或者斜插时，输出报警信号。
本申请提供的晶圆传送装置，通过将晶圆槽的第一放置槽和第二放置槽采用两个导电极板形成电容，并且将放置晶圆的第一极板采用形变材料，当晶圆放置到第一极板上时，第一极板和所述第二极板之间的距离减小，并在极板之间连接有检测电路和电源，电源用于为极板提供电压，检测电路用于检测第一放置槽对应的电容值以及第二放置槽对应的电容值，两个极板之间的距离变化，会导致电容的电容值发生变化，所以能够根据第一放置槽对应的电容值和第二放置槽对应的电容值的变化情况，确定第一放置槽和第二放置槽上 放置的晶圆的状态，该晶圆传送装置能够在晶圆装载至晶圆传送装置中及时发现晶圆的异常状态，及时采取对应的措施。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本申请的实施例，并与说明书一起用于解释本申请的原理。
图1为本申请实施例提供的晶圆传送装置的结构示意图；
图2为晶圆槽的整体结构示意图；
图3为放置槽的放大侧视图；
图4为放置槽的内部电路示意图；
图5为放置槽受到晶圆挤压的状态变化示意图。
附图标记说明：
顶板：11；
底板：12；
第一侧板13；
第二侧板14；
第一放置槽15；
第二放置槽：16；
第一极板：151；
第二极板152；
检测电路153；
电源：154；
通信模块：155；
开关：156；
晶圆：20。
通过上述附图，已示出本申请明确的实施例，后文中将有更详细的描述。这些附图和文字描述并不是为了通过任何方式限制本申请构思的范围，而是通过参考特定实施例为本领域技术人员说明本申请的概念。
具体实施方式
这里将详细地对示例性实施例进行说明，其示例表示在附图中。下面的描述涉及 附图时，除非另有表示，不同附图中的相同数字表示相同或相似的要素。以下示例性实施例中所描述的实施方式并不代表与本申请相一致的所有实施方式。相反，它们仅是与如所附权利要求书中所详述的、本申请的一些方面相一致的装置和方法的例子。
本申请实施例提供一种晶圆传送装置，该晶圆传送装置具有检测功能，通过设置可形变的晶圆槽，当晶圆放置到晶圆槽内时，晶圆槽受到晶圆的挤压发生形变，晶圆槽的上下极板之间的距离发生变化，导致晶圆槽对应的电容器的电容值发生变化，根据晶圆槽对应的电容值的变化，可以确定晶圆槽上放置的晶圆的状态，从而能够在晶圆装载至晶圆传送装置中及时发现晶圆的异常状态，及时采取对应的措施。
图1为本申请实施例提供的晶圆传送装置的结构示意图，图2为晶圆槽的整体结构示意图，图3为放置槽的放大侧视图，图4为放置槽的内部电路示意图，参照图1-图4，该晶圆传送装置包括：顶板11以及与顶板11相对设置的底板12，位于顶板11与底板12之间且相对设置的第一侧板13和第二侧板14，顶板11和底板12之间设置有多个晶圆槽，每个晶圆槽用于放置一片晶圆，多个晶圆20从上到下依次放入放置槽中，本申请实施例中从上到下的方向是指从顶板11到底板12的方向。该晶圆传送装置还包括后板和前门(图中未示出)，前门可打开，在晶圆装载过程中打开前门，将晶圆放置到晶圆槽中。
每个晶圆槽包括第一放置槽15和第二放置槽16，第一放置槽15设置在第一侧板13朝向第二侧板14的表面，第二放置槽16设置在第二侧板14朝向第一侧板13的表面，第一放置槽15和第二放置槽处于同一个平面内。第一晶圆槽15和第二晶圆槽16可以采用矩形、半圆形或者椭圆形，本实施例不对第一晶圆槽15和第二晶圆槽16的形状进行限定。
第一侧板13朝向第二侧板14的表面设置有多个第一放置槽15，第二侧板14朝向第一侧板13的表面设置有多个第二放置槽16，该多个第一放置槽15与该多个第二放置槽16一一对应设置。
参照图3所示，第一放置槽15和第二放置槽16均包括两个相对设置的第一极板151和第二极板152，第一极板151和第二极板152构成电容器，第一极板151和第二极板152上施加的电压的极性相反，例如，当第一极板151上施加正电压时，第二极板152上施加负电压，或者，当第一极板151上施加负电压时，第二极板152上施加正电压。
其中，第一极板151采用形变极板，第一极板151为用于放置晶圆20的极板，当将晶圆20放置到第一极板151上时，第一极板151受到晶圆20的挤压发生形变，第一极板151和第二极板152之间的距离减小，从而导致电容器的电容值发生变化。本实施例中，第二极板152可以采用形变极板，也可以不采用形变极板。第一极板151和第二极板152采用的形变材料本实施例不进行限制。
本申请实施例中，第一放置槽15和第二放置槽16相当于两个平行板电容器，平行板电容器的电容公式为：
Figure PCTCN2021100186-appb-000001
其中，ε r为相对介电常数，k为静电力常量，S为电容器的两个极板的正对面积，d为电容器的两个极板之间的距离，U A-U B为电容器的两个极板之间的电势差(即电压)。
图5为放置槽受到晶圆挤压的状态变化示意图，参考图5，当第一放置槽15和第二放置槽16上没有放置晶圆20时，两个极板之间的距离是一个固定值d1，此时，可以第一放置槽15对应的电容值和第二放置槽16对应的电容值相同且为一个固定值，该固定值也可以称为第一放置槽15对应的初始电容值和第二放置槽16对应的初始电容值。
当晶圆20放置到第一放置槽15或者第二放置槽16上时，第一放置槽15或者第二放置槽16的第一极板151由于受到挤压发生形变，导致第一极板151和第二极板152之间的距离减小，第一极板151和第二极板152之间的距离减小到d2，d2小于d1,d2相对于d1减小了Δd。
通过上述电容器的电容的计算公式可知，当两个极板之间的距离减小时，平行板电容器的电容值增大。
第一极板151和第二极板152之间连接有检测电路153和电源154，电源154用于为第一极板151和第二极板152提供电压。检测电路153用于检测第一放置槽15对应的电容值以及第二放置槽16对应的电容值，根据第一放置槽15对应的电容值和第二放置槽16对应的电容值的变化情况，确定第一放置槽15和第二放置槽16上放置的晶圆的状态。
其中，第一放置槽15对应的电容值是指第一放置槽15包括的两个极板形成的电容器的电容值，第二放置槽16对应的电容值是指第二放置槽16包括的两个极板形成的电容器的电容值。
检测电路153可以实时或者周期性的检测第一放置槽15对应的电容值和第二放置槽16对应的电容值，将检测到的第一放置槽15对应的电容值与第一放置槽15对应的初始电容值进行比较，其中，第一放置槽15对应的初始电容值可以预先存储在检测电路153中。如果检测到的第一放置槽15对应的电容值与第一放置槽15对应的初始电容值不同，则确定第一放置槽15对应的电容值发生了变化，根据该变化情况确定晶圆的状态，或者，检测电路153可以进一步根据检测到的第一放置槽15对应的电容值与第一放置槽15对应的 初始电容值计算电容值的差值，根据电容值的差值确定晶圆的状态。
可选的，检测电路153也可以将当前时刻检测到的第一放置槽15对应的电容值与上一时刻检测到的第一放置槽15对应的电容值进行比较，以确定第一放置槽15对应的电容值的变化情况。
可选的，检测电路153还可以将当前检测周期内的第一放置槽15对应的平均电容值与上一检测周期内的第一放置槽15对应的平均电容值进行比较，以确定第一放置槽15对应的电容值的变化情况。
示例性的，晶圆20的状态包括晶圆20是否放置在放置槽上，或者，晶圆20是否发生叠片，或者，晶圆20是否发生斜插等。通过本实施例的晶圆传送装置，在晶圆装载至晶圆传送装置的过程中，能够及时发现晶圆是否发生斜插或者叠片等异常状态，并及时对异常状态进行处理，避免晶圆的异常状态导致晶圆损伤。
例如，当晶圆发生斜插时，如果没有及时发现，那么在晶圆传输装置将晶圆传送至机台或者其他设备的过程中，发生斜插的晶圆可能会发生碰撞导致晶圆损伤，本实施例的晶圆传送装置，在晶圆装载过程中能够及时检测到晶圆的斜插情况，工作人员可以及时对发生斜插的晶圆进行调整，避免晶圆损伤。
参考图4，可选的，第一放置槽15和第二放置槽16内还包括通信模块155，通信模块155和检测电路153连接，通信模块155用于将晶圆的状态发送给监控设备。监控设备用于向用户展示晶圆的状态，便于用户及时了解晶圆的状态。
通信模块155与监控设备可以采用有线或者无线方式通信，例如，通信模块155和监控设备可以采用无线保证(Wireless Fidelity，简称WIFI)技术通信或者蓝牙技术(bluetooth)进行通信。
可选的，晶圆传送装置还包括显示屏，显示屏与检测电路153连接，各检测电路153得到晶圆的状态后，将晶圆的状态发送给显示屏，通过显示屏显示晶圆的状态。
可选的，晶圆传送装置还包括报警装置，报警装置与检测电路153连接，当晶圆的状态指示晶圆发生斜插或者叠片的情况下，输出报警信号。该报警装置可以包括发光二极管(Light Emitting Diode，简称LED)和/或蜂鸣器，LED灯通过闪烁通知工作人员晶圆状态发生异常，蜂鸣器通过发出特定的声音信号通知工作人员晶圆状态发生异常。
参考图4，可选的，电源154还连接有开关156，开关156用于控制电源154的开通和关闭。
目前，通常通过机械手臂将晶圆装载到晶圆传送装置的晶圆槽中，且通常情况下，按照从上到下的顺序依次装载。当机械手臂将晶圆20放置到晶圆槽上时，第一放置槽15和 第二放置槽16的极板由于形变使得两个极板之间的距离减小，极板之间的距离减小导致第一放置槽15对应的电容值和第二放置槽16对应的电容值增大。检测电路153在检测到第一放置槽15对应的电容值增大时，确定第一放置槽15内放置有晶圆，检测电路153检测到第二放置槽16对应的电容值增大时，确定第二放置槽16内放置有晶圆。通过该方式，可以检测到各个晶圆槽内是否放置有晶圆。
同样，当晶圆槽内的晶圆被取走时，第一放置槽15和第二放置槽16的极板恢复形变，两个极板之间的距离增大，极板之间的距离增大导致第一放置槽15对应的电容值和第二放置槽16对应的电容值减小。检测电路153检测到第一放置槽15对应的电容值减小时，确定第一放置槽15内放置的晶圆被取走，检测电路153检测到第二放置槽16对应的电容值减小时，确定第二放置槽16内放置的晶圆被取走。
正常情况下，晶圆应该放置到同一晶圆槽的第一放置槽15和第二放置槽16内，该晶圆槽的第一放置槽15和第二放置槽16对应的电容值都会增大，可以理解，由于晶圆放置位置14的偏差，第一放置槽15和第二放置槽16对应的电容值的增大量可能会发生较小的偏差。如果晶圆发生斜插，例如，晶圆的一端放置在第一晶圆槽的第一放置槽15中，晶圆的另一端放置在第二晶圆槽的第二放置槽16内，第一晶圆槽和第二晶圆槽为两个相邻的晶圆槽。此时，可以根据第一晶圆槽的两个放置槽对应的电容值的变化情况，确定晶圆是否发生了斜插，也可以根据第二晶圆槽中的两个放置槽对应的电容值的变化情况，确定晶圆是否发生斜插。
以第一晶圆槽为例，当第一晶圆槽中的第一放置槽15或者第二放置槽16对应的电容值增大，另一个放置槽对应的电容值没有变化的情况下，确定第一晶圆槽中的晶圆发生了斜插。当第一晶圆槽中的第一放置槽15和第二放置槽16对应的电容值均增大时，确定第一晶圆槽中的晶圆没有发生斜插。
叠片是指一个晶圆槽中放置了两片或者更多的晶圆，正常情况下，一个晶圆槽中只能放置一片晶圆，叠片是指相对设置的第一放置槽15和第二放置槽16上放置了两个或者更多的晶圆。当晶圆槽中放置的晶圆数量增多时，晶圆槽的第一放置槽15和第二放置槽16发生的形变增大，第一放置槽15和第二放置槽16的两个极板之间的距离更小，相应的，第一放置槽15和第二放置槽16对应的电容值的也增大。例如，晶圆槽中放置一片晶圆时，第一放置槽15的形变为1毫米，即两个极板之间的距离缩小了1毫米，第一放置槽15对应的电容值增大了1法拉(F)；当晶圆槽中放置两片晶圆时，第一放置槽15的形变为1.5毫米，即两个极板之间的距离缩小了1.5毫米，第一放置槽15对应的电容值增大了1.3法拉。所以，可以根据晶圆槽中的第一放置槽15和第二放置槽16对应的电容值的增大量确 定晶圆槽中放置的晶圆是否发生了叠片。
具体的，当检测电路153检测到晶圆槽中的第一放置槽15和第二放置槽16对应的电容值均增大，且电容值的增大量大于第一阈值时，确定晶圆槽中放置的晶圆发生了叠片。
上述方式中，检测电路153根据晶圆槽中的第一放置槽15和第二放置槽16对应的电容值的变化量确定晶圆是否发生叠片。可选的，检测电路153还可以根据晶圆槽中的第一放置槽15和第二放置槽16对应的电容值确定晶圆是否发生叠片，当检测电路153检测到晶圆槽中的第一放置槽15和第二放置槽16对应的电容值均增大，且第一放置槽15和第二放置槽16对应的电容值均大于第二阈值时，确定晶圆槽中放置的晶圆发生了叠片。
本申请实施例提供的晶圆传送装置，通过将晶圆槽的第一放置槽和第二放置槽采用两个导电极板形成电容，并且将放置晶圆的第一极板采用形变材料，当晶圆放置到第一极板上时，第一极板和第二极板之间的距离减小，并在极板之间连接有检测电路和电源，电源用于为极板提供电压，检测电路用于检测第一放置槽对应的电容值以及第二放置槽对应的电容值，两个极板之间的距离变化，会导致电容的电容值发生变化，所以能够根据第一放置槽对应的电容值和第二放置槽对应的电容值的变化情况，确定第一放置槽和第二放置槽上放置的晶圆的状态，该晶圆传送装置能够在晶圆装载至晶圆传送装置中及时发现晶圆的异常状态，及时采取对应的措施。
本领域技术人员在考虑说明书及实践这里公开的申请后，将容易想到本申请的其它实施方案。本申请旨在涵盖本申请的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本申请的一般性原理并包括本申请未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本申请的真正范围和精神由下面的权利要求书指出。
应当理解的是，本申请并不局限于上面已经描述并在附图中示出的精确结构，并且可以在不脱离其范围进行各种修改和改变。本申请的范围仅由所附的权利要求书来限制。

Claims (10)

  1. 一种晶圆传送装置，其特征在于，包括：顶板以及与所述顶板相对设置的底板，位于所述顶板与所述底板之间且相对设置的第一侧板和第二侧板，所述顶板和所述底板之间设置有多个晶圆槽，每个晶圆槽包括第一放置槽和第二放置槽，所述第一放置槽设置在所述第一侧板朝向所述第二侧板的表面，所述第二放置槽设置在所述第二侧板朝向所述第一侧板的表面；
    所述第一放置槽和所述第二放置槽均包括两个相对设置的第一极板和第二极板，所述第一极板和所述第二极板形成电容器，所述第一极板采用形变极板，当晶圆放置到所述第一极板上时，所述第一极板和所述第二极板之间的距离减小；
    所述第一极板和所述第二极板之间连接有检测电路和电源，所述电源用于为所述第一极板和所述第二极板提供电压；
    所述检测电路用于检测所述第一放置槽对应的电容值以及所述第二放置槽对应的电容值，根据所述第一放置槽对应的电容值和所述第二放置槽对应的电容值的变化情况，确定所述第一放置槽和所述第二放置槽上放置的晶圆的状态。
  2. 根据权利要求1所述的装置，其特征在于，所述检测电路具体用于：
    当所述第一放置槽对应的电容值增大时，确定所述第一放置槽内放置有晶圆；
    或者，当所述第二放置槽对应的电容值增大时，确定所述第二放置槽内放置有晶圆。
  3. 根据权利要求1所述的装置，其特征在于，所述检测电路具体用于：
    当所述第一放置槽对应的电容值减小时，确定所述第一放置槽内放置的晶圆被取走；
    或者，当所述第二放置槽对应的电容值减小时，确定所述第二放置槽内放置的晶圆被取走。
  4. 根据权利要求1所述的装置，其特征在于，所述检测电路具体用于：
    当所述晶圆槽中的第一放置槽或者第二放置槽对应的电容值增大，另一个放置槽对应的电容值没有变化时，确定所述晶圆槽中的晶圆发生了斜插。
  5. 根据权利要求1所述的装置，其特征在于，所述检测电路具体用于：
    当所述晶圆槽中的第一放置槽和第二放置槽对应的电容值均增大，且电容值的增大量大于第一阈值时，确定所述晶圆槽中放置的晶圆发生了叠片。
  6. 根据权利要求1-5任一项所述的装置，其特征在于，所述第二极板采用形变极板。
  7. 根据权利要求1-5任一项所述的装置，其特征在于，所述检测电路还连接有通信模块；
    所述通信模块，用于将所述晶圆的状态发送给监控设备。
  8. 根据权利要求7所述的装置，其特征在于，所述电源还连接有开关，所述开关用于控制所述电源的开通和关闭。
  9. 根据权利要求1-5任一项所述的装置，其特征在于，所述装置还包括：
    显示屏，与所述检测电路连接，用于显示所述晶圆的状态。
  10. 根据权利要求1-5任一项所述的装置，其特征在于，所述装置还包括：
    报警装置，与所述检测电路连接，用于当所述晶圆的状态指示所述晶圆发生叠片或者斜插时，输出报警信号。
PCT/CN2021/100186 2020-09-16 2021-06-15 晶圆传送装置 WO2022057340A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US17/451,528 US20220084854A1 (en) 2020-09-16 2021-10-20 Wafer transferring device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202010973763.X 2020-09-16
CN202010973763.XA CN114267617A (zh) 2020-09-16 2020-09-16 晶圆传送装置

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US17/451,528 Continuation US20220084854A1 (en) 2020-09-16 2021-10-20 Wafer transferring device

Publications (1)

Publication Number Publication Date
WO2022057340A1 true WO2022057340A1 (zh) 2022-03-24

Family

ID=80776439

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2021/100186 WO2022057340A1 (zh) 2020-09-16 2021-06-15 晶圆传送装置

Country Status (2)

Country Link
CN (1) CN114267617A (zh)
WO (1) WO2022057340A1 (zh)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6745901B2 (en) * 2001-10-12 2004-06-08 Taiwan Semiconductor Manufacturing Co., Ltd. Wafer cassette equipped with piezoelectric sensors
CN103264674A (zh) * 2013-05-23 2013-08-28 廊坊市金色时光科技发展有限公司 一种座椅乘员占用传感器
CN203344881U (zh) * 2013-05-23 2013-12-18 廊坊市金色时光科技发展有限公司 一种重物占用传感单元
CN104063992A (zh) * 2014-06-28 2014-09-24 浙江吉利控股集团有限公司 一种副驾驶侧仪表台表面物品检测报警装置
CN104697680A (zh) * 2015-03-17 2015-06-10 浙江传媒学院 一种电容式压力传感器及其制备方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6745901B2 (en) * 2001-10-12 2004-06-08 Taiwan Semiconductor Manufacturing Co., Ltd. Wafer cassette equipped with piezoelectric sensors
CN103264674A (zh) * 2013-05-23 2013-08-28 廊坊市金色时光科技发展有限公司 一种座椅乘员占用传感器
CN203344881U (zh) * 2013-05-23 2013-12-18 廊坊市金色时光科技发展有限公司 一种重物占用传感单元
CN104063992A (zh) * 2014-06-28 2014-09-24 浙江吉利控股集团有限公司 一种副驾驶侧仪表台表面物品检测报警装置
CN104697680A (zh) * 2015-03-17 2015-06-10 浙江传媒学院 一种电容式压力传感器及其制备方法

Also Published As

Publication number Publication date
CN114267617A (zh) 2022-04-01

Similar Documents

Publication Publication Date Title
CN109972083B (zh) 静电吸盘、成膜装置、基板吸附/剥离方法、成膜方法以及电子设备的制造方法
US11163121B2 (en) Detection method for electronic devices
US11616043B2 (en) Chip transfer method, display device, chip and target substrate
TWI597793B (zh) Workpiece holding device and work piece using the same
WO2022057340A1 (zh) 晶圆传送装置
JP2018078111A (ja) 二次電池移送装置及び二次電池の装着不良検出方法
US20170275083A1 (en) Substrate Cassette
US10304714B2 (en) Device comprising film for electrostatic coupling of a substrate to a substrate carrier
KR20170103061A (ko) 카메라 모듈 검사 장치
KR101761971B1 (ko) 쇼트 측정장치
WO2019056624A1 (zh) 一种探针装置
WO2019027801A1 (en) ACTIVE MONITORING SYSTEM FOR PREVENTING SUBSTRATE BREAKAGE
US11652231B2 (en) Secondary battery cell supply apparatus for process of folding secondary battery cell
US20220084854A1 (en) Wafer transferring device
CN113008126A (zh) 电池安全检测装置及电池管理系统
CN210487872U (zh) 一种用于电容器电容量的检测装置
WO2023022547A1 (ko) 배터리를 포함하는 전자 장치
CN110957240A (zh) 感应器、装载端及水平方法
US11307441B2 (en) Manufacturing for display panel
US8777286B2 (en) Unpacking device for glass substrate
US20220115556A1 (en) Device, method, and display device for transferring micro light-emitting diodes
CN215159013U (zh) 一种机械手浮动取放料夹爪
KR20150002120A (ko) 정전척 시스템
JP5744160B2 (ja) 部品実装機およびその実装ヘッド装置
KR20230026206A (ko) 픽앤 플레이스 장치 및 그 제어 방법

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 21868171

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 21868171

Country of ref document: EP

Kind code of ref document: A1