WO2022052681A1 - 显示基板及其制造方法和显示装置 - Google Patents

显示基板及其制造方法和显示装置 Download PDF

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Publication number
WO2022052681A1
WO2022052681A1 PCT/CN2021/110548 CN2021110548W WO2022052681A1 WO 2022052681 A1 WO2022052681 A1 WO 2022052681A1 CN 2021110548 W CN2021110548 W CN 2021110548W WO 2022052681 A1 WO2022052681 A1 WO 2022052681A1
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WIPO (PCT)
Prior art keywords
contact pads
layer
insulating layer
display
base substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2021/110548
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English (en)
French (fr)
Inventor
程博
苟结
都蒙蒙
颜俊
张波
杨益祥
张振华
马宏伟
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BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
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Application filed by BOE Technology Group Co Ltd, Chengdu BOE Optoelectronics Technology Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to US17/787,986 priority Critical patent/US12426459B2/en
Publication of WO2022052681A1 publication Critical patent/WO2022052681A1/zh
Anticipated expiration legal-status Critical
Priority to US19/285,537 priority patent/US20250359447A1/en
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/70—Testing, e.g. accelerated lifetime tests
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K77/00—Constructional details of devices covered by this subclass and not covered by groups H10K10/80, H10K30/80, H10K50/80 or H10K59/80
    • H10K77/10—Substrates, e.g. flexible substrates
    • H10K77/111—Flexible substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W46/00—Marks applied to devices, e.g. for alignment or identification
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/481—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a display substrate, a manufacturing method thereof, and a display device.
  • the pins used for connecting with the driver chip in the display substrate are designed in a multi-layer structure, so that the pins are elevated and the bonding force with the corresponding pins on the driver chip is increased.
  • the lead is covered with an organic layer, and then the organic layer on the surface of the lead is removed to expose the lead.
  • the driver chip IC is easy to fall off.
  • Embodiments of the present disclosure provide a display substrate, including:
  • a base substrate comprising a display area, a bonding area on at least one side of the display area, and a side area on at least the other side of the display area;
  • a gate driving circuit located in the side region, the gate driving circuit is connected to the plurality of sub-pixels, and is configured to provide gate driving signals to the plurality of sub-pixels;
  • a plurality of output contact pads located in the bonding area and between the plurality of input contact pads and the display area, the plurality of output contact pads and the plurality of sub-pixels and the gate driving circuit electrical connection;
  • a contact pad insulating layer located in the bonding area, and located in the gap between adjacent input contact pads among the plurality of input contact pads, the gap between adjacent output contact pads among the plurality of output contact pads, and the area between the plurality of input contact pads and the plurality of output contact pads, the surfaces of the plurality of input contact pads and the plurality of output contact pads facing away from the base substrate from the contact pads
  • the insulating layer is exposed, wherein the contact pad insulating layer includes a first portion having a first thickness and a second portion having a second thickness, the second thickness being less than the first thickness, the plurality of input contact pads and all the Edges of the plurality of output contact pads are covered by a first portion of the contact pad insulating layer, and a second portion of the contact pad insulating layer is located in an area between the plurality of input contact pads and the plurality of output contact pads middle.
  • the display substrate further includes: a plurality of first dummy contact pads located in the bonding region and in the region between the plurality of input contact pads and the plurality of output contact pads, wherein,
  • edges of the plurality of first dummy contact pads are covered by the first portion of the contact pad insulating layer, and the surfaces of the plurality of first dummy contact pads facing away from the base substrate extend from the first portion of the contact pad insulating layer. a portion is exposed;
  • the second portion of the contact pad insulating layer includes a first sub-portion and a second sub-portion, the first sub-portion is located in an area between the plurality of first dummy contact pads and the plurality of input contact pads, The second subsection is located in an area between the plurality of first dummy contact pads and the plurality of output contact pads.
  • the display substrate further includes: a plurality of array test contact pads located in the bonding area and in the area between the plurality of first dummy contact pads and the plurality of input contact pads, the A plurality of array test contact pads are electrically connected to the plurality of sub-pixels and the gate driving circuit, wherein,
  • the first portion of the contact pad insulating layer includes a first sub-portion and a second sub-portion, edges of the plurality of input contact pads, edges of the plurality of output contact pads, and edges of the first dummy contact pads are a first sub-portion of the first portion of the contact pad insulating layer is covered with edges of the plurality of array test contact pads covered by a second sub-portion of the first portion of the contact pad insulating layer, the plurality of array test contact pads a surface of the pad facing away from the base substrate is exposed from the first portion of the contact pad insulating layer; and
  • the projection of the second sub-portion of the first portion of the contact pad insulating layer on the base substrate is within the projection of the first sub-portion of the second portion of the contact pad insulating layer on the base substrate.
  • the projection of each of the plurality of input contact pads and the plurality of output contact pads on the base substrate is different from the projection of the second portion of the contact pad insulating layer on the base substrate
  • the spacing between them is in the range of 3 micrometers to 100 micrometers.
  • the second thickness is zero.
  • the plurality of input contact pads are arranged in at least a first row along a first direction, the first direction being an extension direction of a side of the display area facing the bonding area;
  • the plurality of output contact pads are arranged in at least a second row along the first direction;
  • the plurality of first virtual contact pads are arranged in at least a third row along the first direction;
  • the plurality of array test contact pads are arranged in at least a fourth row along the first direction.
  • the display substrate further includes: a plurality of second dummy contact pads, located in the bonding area, arranged in at least a first column and a second column along a second direction perpendicular to the first direction, wherein the first The column and the second column are respectively located on both sides of the plurality of first virtual contact pads in the first direction, wherein,
  • edges of the plurality of second dummy contact pads are covered by the first portion of the contact pad insulating layer, and the surfaces of the plurality of second dummy contact pads facing away from the base substrate extend from the first portion of the contact pad insulating layer. a portion is exposed;
  • the distance between the projection of each of the plurality of second dummy contact pads on the base substrate and the projection of the second portion of the contact pad insulating layer on the base substrate is 3 microns to 100 ⁇ in the micrometer range.
  • At least one of the plurality of input contact pads and the plurality of output contact pads includes:
  • first lead connection part located on the base substrate, wherein the first lead connection part of the input contact pad is electrically connected to the connection contact pad for connecting to an external circuit through the first lead wire arranged in the bonding area,
  • the first lead connection part of the output contact pad is electrically connected to the gate driving circuit or to at least one of the plurality of sub-pixels through a second lead disposed in the bonding region;
  • a first conductor portion located on the side of the first lead connecting portion away from the base substrate, and electrically connected to the first lead connecting portion;
  • a second conductor portion located on the side of the first conductor portion away from the base substrate, is electrically connected to the first conductor portion, and the edge of the second conductor portion is covered by the first portion of the contact pad insulating layer cover.
  • the display substrate further includes:
  • a first gate insulating layer in the bonding area is located in the bonding area and covers the base substrate, and the first lead connection part is located on the side of the first gate insulating layer in the bonding area away from the base substrate ;
  • a second gate insulating layer in the bonding region located in the bonding region, on the side of the bonding region facing away from the base substrate and covering the first lead connection portion;
  • the interlayer insulating layer in the bonding area is located in the bonding area, and is located on the side of the bonding area that is away from the base substrate, and the first conductor portion is disposed on the bonding area.
  • the via hole in the second gate insulating layer of the region and the via hole arranged in the interlayer insulating layer of the bonding region are electrically connected with the first lead connection part;
  • the passivation layer in the bonding area is located in the bonding area, is located on the side of the interlayer insulating layer in the bonding area away from the base substrate and covers the first conductor part, and the second conductor part is disposed on the The via hole in the passivation layer of the bonding area is electrically connected with the first conductor part.
  • the thickness of the portion of the passivation layer in the bonding region between the second portion of the contact pad insulating layer and the second gate insulating layer in the bonding region is greater than or equal to zero.
  • the display substrate also includes:
  • a first gate insulating layer in the bonding area is located in the bonding area and covers the base substrate, and the first lead connection part is located on the side of the first gate insulating layer in the bonding area away from the base substrate ;
  • a second gate insulating layer in the bonding region located in the bonding region, on the side of the bonding region facing away from the base substrate and covering the first lead connection portion;
  • the interlayer insulating layer in the bonding area is located in the bonding area, and is located on the side of the bonding area that is away from the base substrate, and the first conductor portion is disposed on the bonding area.
  • the via hole in the second gate insulating layer and the via hole provided in the interlayer insulating layer of the bonding region are electrically connected to the first lead connection portion, and the second conductor portion is located in the first conductor portion A side facing away from the base substrate and covering the first conductor portion.
  • the at least one of the plurality of input contact pads and the plurality of output contact pads further includes:
  • the third conductor portion is located on the side of the second conductor portion away from the base substrate, and is electrically connected to the second conductor portion.
  • the display substrate further includes:
  • a bonding area barrier layer located in the bonding area, covering the second conductor layer and the first part of the contact pad insulating layer
  • the bonding area inorganic layer is located in the bonding area and covers the bonding area barrier layer, and the third conductor part is arranged in the bonding area through a via hole provided in the bonding area barrier layer The via hole in the inorganic layer is electrically connected to the second conductor portion.
  • At least one of the plurality of first dummy contact pads includes a fourth conductor portion, and the fourth conductor portion is located on the base substrate facing the plurality of input contact pads and the plurality of output contact pads On one side, the edge of the fourth conductor portion is covered by the first portion of the contact pad insulating layer,
  • At least one of the plurality of input contact pads and the plurality of output contact pads includes a first lead connection portion, a first conductor portion and a second conductor portion, the fourth conductor portion and the second conductor portion Same layer settings.
  • At least one of the plurality of first dummy contact pads further includes a fifth conductor portion located between the fourth conductor portion and the base substrate and connected to the fourth conductor
  • the fifth conductor portion is electrically connected to the first conductor portion, and the fifth conductor portion is disposed on the same layer as the first conductor portion.
  • At least one of the plurality of array test contact pads includes:
  • a second lead connection part located on a side of the base substrate facing the plurality of input contact pads and the plurality of output contact pads;
  • a sixth conductor portion located on the side of the second lead connecting portion away from the base substrate, and electrically connected to the second lead connecting portion;
  • a seventh conductor part located on the side of the sixth conductor part away from the base substrate, and electrically connected to the sixth conductor part, and the edge of the seventh conductor part is covered by the first part of the contact pad insulating layer cover,
  • At least one of the plurality of input contact pads and the plurality of output contact pads includes a first lead connection part, a first conductor part and a second conductor part, the second lead connection part, the sixth conductor
  • the first lead connecting part, the first conductor part and the second conductor part are respectively provided in the same layer.
  • At least one of the plurality of second dummy contact pads includes an eighth conductor portion, and the eighth conductor portion is located at a portion of the base substrate facing the plurality of input contact pads and the plurality of output contact pads On one side, the edge of the eighth conductor portion is covered by the first portion of the contact pad insulating layer,
  • At least one of the plurality of input contact pads and the plurality of output contact pads includes a first lead connection portion, a first conductor portion and a second conductor portion, the eighth conductor portion and the second conductor portion Same layer settings.
  • At least one of the plurality of second dummy contact pads further includes a ninth conductor portion located between the eighth conductor portion and the base substrate and connected to the eighth conductor
  • the ninth conductor portion is electrically connected to the first conductor portion, and the ninth conductor portion and the first conductor portion are arranged in the same layer.
  • At least one of the plurality of sub-pixels includes a pixel driving circuit, a first planarization layer, a first transfer electrode, a second planarization layer, and a light-emitting element,
  • the first planarization layer is provided on a side of the pixel driving circuit away from the base substrate to provide a first planarized surface
  • the first transfer electrode is on the first planarized surface, and is electrically connected to the pixel driving circuit through a via hole provided in the first planarized layer;
  • the second planarization layer is provided on a side of the first via electrode away from the base substrate to provide a second planarized surface
  • the light-emitting element is electrically connected to the first transfer electrode on the second planarized surface and through a via hole provided in the second planarized layer;
  • the contact pad insulating layer and the second planarization layer are provided in the same layer.
  • the pixel driving circuit includes a thin film transistor including a gate electrode, a source electrode and a drain electrode, and at least one of the plurality of input contact pads and the plurality of output contact pads includes a first lead connection portion , a first conductor portion and a second conductor portion, wherein,
  • the first lead connection part is arranged in the same layer as the gate
  • the first conductor part is provided in the same layer as the source and drain electrodes,
  • the second conductor portion is disposed on the same layer as the first transfer electrode.
  • the display substrate further includes a display area passivation layer, the display area passivation layer is located between the pixel driving circuit and the first planarization layer, and the pixel driving circuit and the first transition layer
  • the electrodes are also electrically connected through via holes arranged in the passivation layer of the display area;
  • the display substrate further includes a bonding area passivation layer, and the bonding area passivation layer and the display area passivation layer are disposed in the same layer.
  • the display substrate further includes an encapsulation layer in the display area, a barrier layer in the display area, a first touch electrode layer, a second touch electrode layer, and a touch insulating layer, and the encapsulation layer is located far from the light-emitting element.
  • the display area barrier layer is located on the side of the encapsulation layer away from the base substrate
  • the first touch electrode layer is located on the display area barrier layer away from the substrate one side of the base substrate
  • the touch insulating layer is located on the side of the first touch electrode layer away from the base substrate and covers the first touch electrode layer
  • the second touch electrode layer is located on the side of the first touch electrode layer away from the base substrate a side of the touch insulating layer away from the base substrate;
  • the display substrate further includes a bonding area barrier layer and a bonding area inorganic layer located in the bonding area, and at least one of the plurality of input contact pads and the plurality of output contact pads further includes a third conductor portion, so The bonding area barrier layer, the bonding area inorganic layer and the third conductor portion are respectively located on the same layer as the display area barrier layer, the touch insulating layer and the second touch electrode layer.
  • At least one of the plurality of sub-pixels further includes an interlayer insulating layer in the display area, a first gate insulating layer in the display area, and a second gate insulating layer in the display area, and the interlayer insulating layer in the display area is located between the gate and the gate.
  • the first gate insulating layer in the display area is located on the side of the interlayer insulating layer in the display area facing the base substrate
  • the second gate insulating layer in the display area is located on the side of the interlayer insulating layer in the display area facing the base substrate.
  • the display substrate further includes an interlayer insulating layer in the bonding area, a first gate insulating layer in the bonding area, and a second gate insulating layer in the bonding area.
  • a gate insulating layer and the second gate insulating layer of the bonding region are respectively provided in the same layer as the interlayer insulating layer of the display region, the first gate insulating layer of the display region and the second gate insulating layer of the display region.
  • At least one of the plurality of sub-pixels further includes a storage capacitor, the first electrode of the storage capacitor is disposed in the same layer as the gate electrode, and the second electrode of the storage capacitor is disposed in the interlayer insulating layer in the display region and the second gate insulating layer in the display area.
  • the base substrate includes:
  • a second flexible layer located on a side of the first flexible layer facing the plurality of input contact pads and the plurality of output contact pads;
  • a second substrate barrier layer located on the side of the second flexible layer away from the first flexible layer
  • a buffer layer located on the side of the second substrate barrier layer away from the first flexible layer.
  • Embodiments of the present disclosure also provide a display device including the above-mentioned display substrate.
  • Embodiments of the present disclosure also provide a method for manufacturing the above-mentioned display substrate, including:
  • the base substrate comprising a display area, a bonding area on at least one side of the display area, and a side area on at least the other side of the display area;
  • the gate driving circuit is connected to the plurality of sub-pixels, and is configured to provide gate driving signals to the plurality of sub-pixels;
  • a plurality of output contact pads are formed in the bonding area, the plurality of output contact pads are located between the plurality of input contact pads and the display area, the plurality of output contact pads and the plurality of sub-pixels electrically connected to the gate drive circuit;
  • a contact pad insulating layer is formed in the bonding area, the contact pad insulating layer is located in the gap between adjacent input contact pads among the plurality of input contact pads, and adjacent output contact pads among the plurality of output contact pads gaps therebetween, and areas between the plurality of input contact pads and the plurality of output contact pads, the surfaces of the plurality of input contact pads and the plurality of output contact pads facing away from the base substrate Exposed from the contact pad insulating layer, wherein the contact pad insulating layer includes a first portion having a first thickness and a second portion having a second thickness, the second thickness being less than the first thickness, the plurality of The edges of the input contact pads and the plurality of output contact pads are covered by a first portion of the contact pad insulating layer, and a second portion of the contact pad insulating layer is located between the plurality of input contact pads and the plurality of output contact pads in the area between the pads.
  • FIG. 1A shows a schematic diagram of a display substrate according to an embodiment of the present disclosure.
  • FIG. 1B shows a schematic diagram of a display area of the display substrate of FIG. 1A .
  • FIG. 2 illustrates a partial plan view of a bonding area of a display substrate according to an embodiment of the present disclosure.
  • FIG. 3 shows a schematic diagram of a cross section of the display substrate of FIG. 2 along A1-B1.
  • FIG. 4A shows a cross-sectional view along A2-B2 of an example of the display substrate of FIG. 2 .
  • FIG. 4B shows a cross-sectional view along A3-B3 of an example of the display substrate of FIG. 2 .
  • FIG. 4C shows a cross-sectional view along A4-B4 of an example of the display substrate of FIG. 2 .
  • FIG 5 illustrates a cross-sectional view of a display area of a display substrate according to an embodiment of the present disclosure.
  • 6A and 6B respectively illustrate cross-sectional views along A2-B2 and A3-B3 of another example of the display substrate of FIG. 2 .
  • FIGS. 7A and 7B respectively show cross-sectional views along A2-B2 and along A3-B3 of a bonding region of yet another example of the display substrate of FIG. 2 .
  • 8A and 8B respectively illustrate cross-sectional views along A2-B2 and A3-B3 of a bonding region of yet another example of the display substrate of FIG. 2 .
  • FIG 9 illustrates a cross-sectional view of a display area of a display substrate according to another embodiment of the present disclosure.
  • FIG. 10 illustrates a partial plan view of a bonding area of a display substrate according to another embodiment of the present disclosure.
  • FIG. 11 shows a schematic diagram of a cross section of the display substrate of FIG. 10 along C1-D1.
  • FIG. 12A shows a cross-sectional view along C2-D2 of an example of the display substrate of FIG. 11 .
  • FIG. 12B shows a cross-sectional view along C2-D2 of another example of the display substrate of FIG. 11 .
  • FIG. 12C shows a cross-sectional view along C2-D2 of yet another example of the display substrate of FIG. 11 .
  • FIG. 13 illustrates a partial plan view of a bonding area of a display substrate according to yet another embodiment of the present disclosure.
  • FIG. 14 shows a schematic diagram of a cross section of the display substrate of FIG. 13 along E1-F1.
  • FIG. 15A shows a cross-sectional view along E2-F2 of one example of the display substrate of FIG. 13 .
  • FIG. 15B shows a cross-sectional view along E3-F3 of an example of the display substrate of FIG. 13 .
  • FIG. 15C shows a cross-sectional view along E3-F3 of another example of the display substrate of FIG. 13 .
  • FIG. 15D shows a cross-sectional view along E3-F3 of yet another example of the display substrate of FIG. 13 .
  • 16A illustrates a cross-sectional view of a display area of a display substrate according to another embodiment of the present disclosure.
  • FIG. 16B shows a cross-sectional view of a bonding region of the display substrate of FIG. 16A .
  • 17A to 17G illustrate schematic diagrams of a manufacturing process of a display substrate according to an embodiment of the present disclosure.
  • FIG. 1A shows a schematic diagram of a display substrate according to an embodiment of the present disclosure.
  • FIG. 1B shows a schematic diagram of a display area of the display substrate of FIG. 1A .
  • the display substrate includes a base substrate 10
  • the base substrate 10 includes a display area 11 , a bonding area 12 on at least one side of the display area 11 , and a side area on at least the other side of the display area 13.
  • the bonding area 12 is located on one side of the display area 11 along the y direction
  • the side area 13 is located on both sides of the display area 11 along the x direction.
  • a plurality of sub-pixels Pix are provided in the display area 11 .
  • a plurality of sub-pixels Pix may be arranged in an array.
  • x represents the row direction of the sub-pixel array
  • y represents the column direction of the sub-pixel array.
  • the display area 11 is further provided with a plurality of gate lines G1 to GN and a plurality of data lines D1 to DM, and each of the gate lines G1 to GN is connected to at least one row of sub-pixels Pix to provide gate driving to the row of sub-pixels Pix.
  • Each of the data lines D1 to DM is connected to at least one column of sub-pixels Pix to provide data signals to the column of sub-pixels Pix.
  • Each sub-pixel Pix can be turned on under the control of the gate driving signal on the gate line connected thereto, and the turned-on sub-pixel Pix can emit light under the driving of the data signal on the data line connected with it.
  • the gate driving circuits 130 are located in the side region 13 .
  • FIG. 1A there are two gate driving circuits 130 , which are respectively located in the side regions 13 on both sides of the display area 11 .
  • the gate driving circuit 130 is connected to the plurality of sub-pixels Pix.
  • FIGS. 1A and 1B the gate driving circuit 130 is connected to a plurality of rows of sub-pixels Pix through a plurality of gate lines G1 to GN to provide gate driving signals to the respective rows of sub-pixels Pix, respectively. As shown in FIG.
  • the gate driving circuit 130 is also connected to various driving control signal lines, such as a first clock signal line CK1 for providing a first clock signal and a second clock signal line CK2 for providing a second clock signal and a start signal line STV for providing a start signal.
  • the gate driving circuit 130 may include multi-stage cascaded shift registers GOA0 to GOAN, and the shift registers GOA0 to GOAN of each stage are connected to corresponding driving control signal lines, so as to generate gate driving signals and provide the gate driving signals under the control of the driving control signals. to the sub-pixel Pix of the display area 11 .
  • a plurality of input contact pads P1 and a plurality of output contact pads P2 are located in the bonding area 12 , and the plurality of output contact pads P2 are located between the plurality of input contact pads P1 and the display area 11 .
  • the plurality of input contact pads P1 are arranged in at least a first row along a first direction, and the first direction is an extension direction of the side of the display area 11 facing the bonding area 12 , i.e. the x direction.
  • the plurality of output contact pads P2 are arranged in at least a second row along the first direction.
  • the plurality of input contact pads P1 are used for electrical connection with external circuits, and the plurality of output contact pads P2 are electrically connected to the sub-pixels Pix in the display area 11 and the gate driving circuit 130 .
  • the plurality of input contact pads P1 may be respectively connected to the plurality of connection contact pads in the area 1220 for connecting the flexible circuit board through the plurality of first wires W1.
  • the plurality of output contact pads P2 may be connected to the sub-pixels Pix and the gate driving circuit 13 in the display area 11 through a plurality of second wires W2, respectively.
  • the plurality of output contact pads P2 located in the middle in FIG. 1A are respectively connected to the data lines D1 to DM in the display area 11 through a plurality of second leads W2 , and thus are connected to the sub-pixels Pix in the display area 11 .
  • structures such as a cell test (CT, Cell Test) circuit, an electrostatic protection (ESD, Electro-Static Discharge) circuit, and a multiplexing circuit may be arranged in the bonding area 12 .
  • a unit test circuit may be disposed in an area between a plurality of output contact pads P2 and the display area 11, and the unit test circuit may be connected to a plurality of test signal lines and a plurality of sub-pixels in the display area.
  • a multiplexing circuit may be provided in the area between the unit test circuit and the plurality of output contact pads P2, and the multiplexing circuit may be linked with at least one output contact pad P2 and a data line of the display area to connect the output
  • the data signals provided by the contact pads P2 are multiplexed and provided to the data lines of the display area.
  • the embodiments of the present disclosure are not limited thereto.
  • At least one of a unit test circuit, an ESD protection circuit, a multiplexer circuit, and other auxiliary circuits may be disposed in the area between the input contact pad P1 and the output contact pad P2, in other implementations The example may be located in the area between the output contact pad P2 and the first dummy contact pad P3 described below.
  • the input contact pad P1 is connected to the input pin of the control chip
  • the output contact pad P2 is connected to the output pin of the control chip.
  • the signals provided by the flexible circuit board (such as but not limited to power supply signals, control signals, etc.) are provided to the control chip through the input contact pad P1, so that the control chip generates driving signals (such as but not limited to clock signals, start signals, data signals, etc.) .
  • the driving signal generated by the control chip is provided to the sub-pixel Pix and/or the gate driving circuit of the display area 11 through the output contact pad P2.
  • the data signal generated by the control chip is provided to the data line D1 through the output contact pad P2 located in the middle part.
  • the first clock signal, the second clock signal and the start-up signal STV generated by the control chip are respectively provided to the first clock signal line CK1, the first clock signal line CK1, the first clock signal line CK1 and the first clock signal line CK1 through the output contact pads P2 located on both sides.
  • Two clock signal lines CK2 and start signal lines STV are supplied to the gate driving circuit 130 .
  • the contact pad insulating layer in the region 1210 between the plurality of input contact pads P1 and the plurality of output contact pads P2 is at least partially removed, thereby alleviating the Poor contact with the control chip caused by the contact pad insulating layer. This will be described in detail below with reference to FIGS. 2 to 15C .
  • FIG. 2 shows a partial plan view of a bonding area of a display substrate according to an embodiment of the present disclosure
  • FIG. 3 shows a schematic diagram of a cross section of the bonding area of FIG. 2 along A1 - B1 .
  • FIG. 2 only shows one side part of the bonding area in FIG. 1A (the left part in FIG. 2 ), and the other side part of the bonding area may have a similar structure, for example, relative to Symmetrical structure on the left side.
  • the cross-sectional view of FIG. 3 is only to illustrate the positional relationship and the difference in thickness between the first part and the second part of the contact pad insulating layer, and more details of the layer structure of the bonding area will be described in further detail below. .
  • the contact pad insulating layer 1230 is located in the gap between the adjacent input contact pads P1 among the plurality of input contact pads P1, the plurality of output contact pads P2 gaps between adjacent output contact pads P2, and areas between the plurality of input contact pads P1 and the plurality of output contact pads P2. Surfaces of the input contact pad P1 and the output contact pad P2 facing away from the base substrate 10 are exposed from the contact pad insulating layer 1230 .
  • the contact pad insulating layer 1230 includes a first portion 1230A having a first thickness and a second portion 1230B having a second thickness that is smaller than the first thickness.
  • the edges of the input contact pad P1 and the output contact pad P2 are covered by the first portion 1230A of the contact pad insulating layer 1230, and the second portion 1230B of the contact pad insulating layer 1230 is located between the plurality of input contact pads P1 and the plurality of output contact pads in the area between P1. As shown in FIG.
  • d1 there is a distance d1 between the projection of the input contact pad P1 on the base substrate 10 and the projection of the second portion 1230B of the contact pad insulating layer 1230 on the base substrate 10, and the output contact pad P2 is on the base substrate
  • d2 there is a distance d2 between the projection on 10 and the projection of the second portion 1230B of the contact pad insulating layer 1230 on the base substrate 10, and d1 and d2 may be in the range of 3 micrometers to 100 micrometers. In some embodiments, d1 may be equal to d2.
  • FIG. 4A shows a cross-sectional view along A2-B2 of an example of the display substrate of FIG. 2 at the bonding region.
  • the output contact pad P2 includes a first lead connection part 1241 , a first conductor part 1242 and a second conductor part 1243 .
  • the first lead connection portion 1241 is located on the base substrate 10 .
  • the first lead connection portion 1241 of the output contact pad P2 may be connected to the second lead W2 of the bonding area, thereby being electrically connected to the gate driving circuit 130 or to at least one of the plurality of sub-pixels in the display area 11 .
  • the first conductor portion 1242 is located on the side of the first lead connecting portion 1241 away from the base substrate 10 and is electrically connected to the first lead connecting portion 1241 .
  • the second conductor portion 1243 is located on the side of the first conductor portion 1242 away from the base substrate 10 , and is electrically connected to the first conductor portion 1242 .
  • the bonding area of the display substrate is further provided with a first gate insulating layer 1251 in the bonding area, a second gate insulating layer 1252 in the bonding area, an interlayer insulating layer 1253 in the bonding area, and a passivation layer 1254 in the bonding area.
  • the first gate insulating layer 1251 in the bonding area covers the base substrate 10
  • the first lead connection portion 1241 is located on the side of the first gate insulating layer 1251 in the bonding area away from the base substrate 10
  • the second gate insulating layer 1252 of the bonding region is located on the side of the first gate insulating layer 1251 of the bonding region facing away from the base substrate 10 and covers the first lead connection portion 1241 .
  • the interlayer insulating layer 1253 in the bonding region is located on the side of the second gate insulating layer 1252 in the bonding region facing away from the base substrate 10 .
  • the bonding region passivation layer 1254 is located on the side of the bonding region interlayer insulating layer 1253 away from the base substrate 10 and covers the first conductor portion 1242 .
  • the first conductor portion 1242 is connected to the first lead through the via hole provided in the second gate insulating layer 1252 in the bonding region and the via hole provided in the interlayer insulating layer 1253 in the bonding region.
  • the connection portion 1241 is electrically connected
  • the second conductor portion 1243 is electrically connected to the first conductor portion 1242 through a via hole provided in the passivation layer 1254 of the bonding region.
  • the second gate insulating layer 1252 of the bonding region, the interlayer insulating layer 1253 of the bonding region, and the passivation layer 1254 of the bonding region are all provided with a plurality of via holes, for example, three via holes.
  • the embodiments of the present disclosure are not limited thereto, and in other examples of the present disclosure, the number of vias may also be set as required, for example, 2 or 4.
  • the edge of the second conductor portion 1243 of the output contact pad P2 is covered by the first portion 1230A of the contact pad insulating layer 1230 with a thickness H1 , and the second portion 1230B of the contact pad insulating layer 1230 with a thickness H2 is located at the input In the area between the contact pad P1 and the output contact pad P1, where H2 is smaller than H1.
  • the so-called thickness may refer to the distance from the surface of the contact pad insulating layer 1230 on the side facing the base substrate 10 to the surface on the side facing away from the base substrate 10 .
  • the surface of the second portion 1230B of the contact pad insulating layer 1230 on the side facing away from the base substrate 10 can be lower than the surface of the first portion 1230A of the contact pad insulating layer 1230 on the side facing away from the base substrate 10,
  • the influence of the contact pad insulating layer 1230 on the connection reliability between the output contact pad P2 and the pins of the control chip can be alleviated, and the first part 1230A with a larger thickness can encapsulate the edge of the output contact pad P2, thereby improving the reliability of the connection. to protection.
  • FIG. 4B shows a cross-sectional view along A3-B3 of an example of the display substrate of FIG. 2 at the bonding region.
  • the structure of the input contact pad P1 and the output contact pad P2 may be basically the same, and the output contact pad P2 also includes a first lead connection part 1241 , a first conductor part 1242 and a second conductor part 1243 .
  • the first conductor part 1242 is electrically connected to the first lead connecting portion 1241 through the via hole in the second gate insulating layer 1252 in the bonding region and the via hole in the interlayer insulating layer 1253 in the bonding region, and the second conductor portion 1243 passes through the bonding region passivation layer
  • the vias in 1254 are electrically connected to the first conductor portion 1242 .
  • the first lead connection portion 1241 of the input contact pad P1 may be connected to the first lead W1 in the bonding area 12 to be electrically connected with the connection contact pad in the area 1220 for connecting to an external circuit.
  • the material of the contact pad insulating layer 1230 may include inorganic insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride, or may include polyimide, polyphthalimide, polyphthalamide, acrylic resin, Organic insulating materials such as benzocyclobutene or phenolic resin.
  • the embodiment of the present disclosure does not specifically limit the material of the contact pad insulating layer.
  • the materials of the first conductor part 1242 and the second conductor part 1243 may include metal materials or alloy materials, such as metal single-layer or multi-layer structures formed of molybdenum, aluminum, and titanium.
  • FIG. 4C shows a cross-sectional view along A4-B4 of an example of the display substrate of FIG. 2 at the bonding area.
  • the base substrate 10 of the embodiment of the present disclosure may include organic materials such as polyimide, polycarbonate, polyacrylate, polyetherimide, polyethersulfone, polyethylene terephthalate, and polyethylene naphthalene
  • the base substrate 10 may be a flexible substrate or a non-flexible substrate.
  • the base substrate 10 is a flexible substrate, and the base substrate 10 may include a first flexible layer 1010 , a second flexible layer 1020 , a first substrate barrier layer 1030 , a second substrate barrier layer 1040 and a buffer layer 1050 .
  • the second flexible layer 1020 is located on the side of the first flexible layer 1010 facing the plurality of input contact pads P1 and the plurality of output contact pads P2.
  • the first substrate barrier layer 1030 is located between the first flexible layer 1020 and the second flexible layer 1020 .
  • the second substrate barrier layer 1040 is located on the side of the second flexible layer 1020 away from the first flexible layer 1010 .
  • the buffer layer 1050 is located on the side of the second substrate barrier layer 1040 away from the first flexible layer 1010 .
  • the material of the buffer layer 1050 may include insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride.
  • the buffer layer 1050 can not only prevent harmful substances in the base substrate 10 from invading the interior of the display substrate, but also increase the adhesion of the film layer in the display substrate on the base substrate 10 .
  • the first gate insulating layer 1251 in the bonding area, the second gate insulating layer 1252 in the bonding area, the interlayer insulating layer 1253 in the bonding area, and the passivation in the bonding area are sequentially stacked on the surface of the buffer layer 1050 away from the first flexible layer 1010 layer 1254 and contact pad insulating layer 1230.
  • the contact pad insulating layer 1230 includes a first portion 1230A having a first thickness and a second portion 1230B having a second thickness, the second thickness being smaller than the first thickness.
  • the edges of the input contact pad P1 and the output contact pad P2 are covered by the first portion 1230A of the contact pad insulating layer 1230, and the second portion 1230B of the contact pad insulating layer 1230 is located between the plurality of input contact pads P1 and the plurality of output contact pads in the area between P1.
  • FIG 5 illustrates a cross-sectional view of a display area of a display substrate according to an embodiment of the present disclosure.
  • the sub-pixels in the display area may include a pixel driving circuit 1120 , a first planarization layer 1130 , a first transfer electrode 1180 , a second planarization layer 1190 and a light emitting element 1140 .
  • the pixel driving circuit 1120 includes an active layer 1122 located on the base substrate 10, a first gate insulating layer 1128 of the display area located on the side of the active layer 1122 away from the base substrate 1000, and a first gate insulating layer 1128 located on the first gate insulating layer 1128 of the display area.
  • the gate electrode 11211 may be disposed in the same layer as the first lead connection portion 1241 in the bonding region 12 .
  • the source electrode 1125 and the drain electrode 1126 may be disposed in the same layer as the first conductor portion 1242 in the bonding region 12 . Therefore, the gate electrode 11211 and the first lead connection portion 1241 can be formed in the same layer in the manufacturing process, for example, formed by using the same material layer through a patterning process.
  • the source electrode 1125 and the drain electrode 1126 and the first conductor portion 1242 in the bonding region 12 can be formed in the same layer in the manufacturing process, for example, formed by using the same material layer through a patterning process.
  • the display area first gate insulating layer 1128 in the display area is disposed in the same layer as the bonding area first gate insulating layer 1251 in the bonding area, and the display area second gate insulating layer 1129 in the display area and the bonding area in the bonding area.
  • the second gate insulating layer 1252 in the fixed area is disposed in the same layer, and the interlayer insulating layer 11211 in the display area and the interlayer insulating layer 1253 in the bonding area in the display area are disposed in the same layer.
  • the active layer 1122 may include a source region 1123 and a drain region 1124 , and a channel region between the source region 1123 and the drain region 1124 .
  • the display region interlayer insulating layer 11210 , the display region second gate insulating layer 1129 and the display region first gate insulating layer 1128 have via holes to expose the source region 1123 and the drain region 1124 .
  • the source electrode 1125 and the drain electrode 1126 are respectively electrically connected to the source electrode region 1123 and the drain electrode region 1124 through via holes.
  • the gate electrode 11211 overlaps the channel region between the source region 1123 and the drain region 1124 in the active layer 1122 in a direction perpendicular to the base substrate 1000 .
  • the first planarization layer 1130 is located above the source electrode 1125 and the drain electrode 1126 for planarizing the surface of the pixel driving circuit 1120 on the side away from the base substrate.
  • a via hole 1131 is formed in the first planarization layer 1130 to expose the source electrode 1125 or the drain electrode 1126 (the case shown in the figure).
  • a display area passivation layer 11110 is formed between the pixel driving circuit 1120 and the first planarization layer 1130 and the display area passivation layer 11110 includes a via hole 11111 .
  • the passivation layer 11110 in the display area can protect the source electrode and the drain electrode of the pixel driving circuit from being corroded by water vapor.
  • the bonding area passivation layer 1254 in the display area may be disposed in the same layer as the display area passivation layer 11110 . Therefore, the bonding area passivation layer 1254 of the display area and the display area passivation layer 11110 can be formed in the same layer in the manufacturing process, for example, formed by using the same material layer through a patterning process.
  • a first via electrode 1180 is formed on the first planarization layer 1130 .
  • the first transfer electrode 1180 is electrically connected to the drain electrode 1126 through the via hole 1131 and the via hole 11111 , and the first transfer electrode 1180 can avoid directly forming an excessively large aperture in the first planarization layer 1130 and the second planarization layer 1190 Therefore, the quality of the electrical connection of the via holes can be improved.
  • the first transfer electrode 1180 can also be formed in the same layer as other signal lines (eg, power lines, etc.), thereby not increasing the number of process steps.
  • the first transfer electrode 1180 and the second conductor portion 1243 of the contact pad 1210 are disposed in the same layer. Therefore, the first transfer electrode 1180 and the second conductor portion 1243 can be formed in the same layer in the manufacturing process, for example, the same material layer is used by patterning process, thereby simplifying the manufacturing process.
  • the material of the first transition electrode 1180 may include a metal material or an alloy material, such as a metal single-layer or multi-layer structure formed by molybdenum, aluminum, and titanium.
  • the material of the active layer 1122 may include polysilicon or an oxide semiconductor (eg, indium gallium zinc oxide).
  • the material of the gate electrode 11211 can include metal materials or alloy materials, such as a metal single-layer or multi-layer structure formed by molybdenum, aluminum and titanium, for example, the multi-layer structure is a multi-metal stack layer (such as titanium, aluminum and titanium three layers). Metal stack (Ti/Al/Ti).
  • the material of the source electrode 1125 and the drain electrode 1126 may include metal material or alloy material, such as a metal single-layer or multi-layer structure formed of molybdenum, aluminum and titanium, for example, the multiple
  • the layer structure is a multi-metal laminate layer (eg, titanium, aluminum, and titanium three-layer metal laminate (Ti/Al/Ti).
  • the embodiments of the present disclosure do not specifically limit the materials of each functional layer.
  • the material of the passivation layer 11110 in the display area may include organic insulating material or inorganic insulating material, for example, silicon nitride material, because of its high dielectric constant and good hydrophobic function, it can well protect the pixels The drive circuit is not corroded by water vapor.
  • the pixel driving circuit 1120 may further include a first display metal layer 1127 , and the first display region metal layer 1127 and the first conductor portion 1242 are disposed in the same layer.
  • the first display metal layer 1127 includes the source electrode 1125 and the drain electrode 1126 of the above-mentioned thin film transistor in the pixel driving circuit.
  • the source electrode 1125 and the drain electrode 1126 are provided in the same layer as the first conductor portion 1242 .
  • the second planarization layer 1190 is disposed on the side of the first via electrode 1180 away from the base substrate 10 , so as to be used when the first via electrode 1180 is away from the base substrate 10
  • One side provides a flattened surface.
  • Via holes 1191 are formed in the second planarization layer 1190 .
  • the second planarization layer 1190 and the contact pad insulating layer 1230 in the bonding region 1200 are formed in the same layer, so the second planarization layer 1190 and the contact pad insulating layer 1230 can be formed in the same layer in the manufacturing process, for example, using the same material layer through A patterning process is formed, thereby simplifying the manufacturing process.
  • the light-emitting element 1140 is formed on the second planarization layer, that is, the light-emitting element 1140 is disposed on the side of the second planarization layer 1190 away from the base substrate.
  • the light-emitting element 1140 includes a first electrode 1141 , a light-emitting layer 1142 and a second electrode 1143 .
  • the first electrode 1141 of the light emitting element is electrically connected to the first via electrode 1180 through the second via hole 1191 in the second planarization layer 1140 .
  • a pixel defining layer 1144 is formed on the first electrode 1141, and the pixel defining layer 1144 includes a plurality of openings to define a plurality of pixel units.
  • Each of the plurality of openings exposes the corresponding first electrode 1141; after that, the light-emitting layer 1142 is disposed in the plurality of openings of the pixel-defining layer 1144, and the second electrode 1143 is disposed on the pixel-defining layer 1144 and the light-emitting layer 1142, for example, the first
  • the second electrode 1143 may be disposed in part or the entire display area, so that the entire surface may be formed during the fabrication process.
  • the material of the second planarization layer 1190 may include inorganic insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride, and may also include polyimide, polyimide, polyamine, acrylic resin, benzoin Organic insulating materials such as cyclobutene or phenolic resin, which are not limited in the embodiments of the present disclosure.
  • the first electrode 1141 may include a reflective layer
  • the second electrode 1143 may include a transparent layer or a semitransparent layer.
  • the first electrode 1141 can reflect the light emitted from the light emitting layer 1142, and the part of the light is emitted into the external environment through the second electrode 1143, so that the light extraction rate can be improved.
  • the second electrode 1143 includes a semi-transmissive layer, some light reflected by the first electrode 1141 is reflected again by the second electrode 1143, so the first electrode 1141 and the second electrode 1143 form a resonance structure, which can improve light extraction efficiency.
  • the material of the first electrode 1141 may include at least one transparent conductive oxide material including indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), and the like.
  • the first electrode 1141 may include a metal having high reflectivity, such as silver (Ag), as a reflective layer.
  • the light-emitting layer 1142 may include a small molecular organic material or a polymer molecular organic material, may be a fluorescent light-emitting material or a phosphorescent light-emitting material, may emit red, green, blue, or white light; and, as required
  • the light-emitting layer may further include functional layers such as an electron injection layer, an electron transport layer, a hole injection layer, and a hole transport layer.
  • the light emitting layer may include quantum dot materials, eg, silicon quantum dots, germanium quantum dots, cadmium sulfide quantum dots, cadmium selenide quantum dots, cadmium telluride quantum dots, zinc selenide quantum dots, lead sulfide quantum dots, selenium Lead hydride quantum dots, indium phosphide quantum dots and indium arsenide quantum dots, etc., the particle size of the quantum dots is 2-20nm.
  • quantum dot materials eg, silicon quantum dots, germanium quantum dots, cadmium sulfide quantum dots, cadmium selenide quantum dots, cadmium telluride quantum dots, zinc selenide quantum dots, lead sulfide quantum dots, selenium Lead hydride quantum dots, indium phosphide quantum dots and indium arsenide quantum dots, etc.
  • the particle size of the quantum dots is 2-20nm.
  • the second electrode 1143 may include various conductive materials.
  • the second electrode 1143 may include metal materials such as lithium (Li), aluminum (Al), magnesium (Mg), silver (Ag).
  • the material of the pixel defining layer 1144 may include organic insulating materials such as polyimide, polyphthalimide, polyphthalamide, acrylic resin, benzocyclobutene, or phenolic resin, or include inorganic materials such as silicon oxide and silicon nitride. Insulation material, which is not limited in the embodiments of the present disclosure.
  • the display substrate further includes a storage capacitor 1160
  • the storage capacitor 1160 may include a first electrode 1161 and a second electrode 1162 .
  • the first electrode 1161 of the storage capacitor 1160 is disposed between the first gate insulating layer 1128 in the display area and the second gate insulating layer 1129 in the display area
  • the second electrode 1162 of the storage capacitor 1160 is disposed between the second gate insulating layer 1129 in the display area and the display area. between the interlayer insulating layers 11210.
  • the first pole 1161 and the second pole 1162 are overlapped, and at least partially overlap in a direction perpendicular to the base substrate 10 .
  • the first electrode 1161 and the second electrode 1162 use the display region second gate insulating layer 1129 as a dielectric material to form a storage capacitor.
  • the first electrode 1161 is disposed in the same layer as the gate electrode 11211 in the pixel driving circuit 1120 and the lead 1220 in the bonding area 1200 .
  • the first and second poles of the storage capacitor 1160 may also be located in other layers, thereby resulting in sub-pixels of different structures.
  • the first electrode of the storage capacitor is still arranged in the same layer as the gate electrode 11211
  • the second electrode of the storage capacitor is the same as the source electrode 1125 and the drain electrode 1126 in the thin film transistor.
  • layer arrangement ie also in the first display metal layer 1127
  • the first and second poles of the storage capacitor use the stack of the second gate insulating layer 1129 in the display area and the interlayer insulating layer 11210 in the display area as an intermediary. electrical materials to form storage capacitors.
  • the first electrode of the storage capacitor is no longer disposed in the same layer as the gate electrode 11211 , but is located between the second gate insulating layer 1129 in the display area and the interlayer insulating layer in the display area. 11210, and the second electrode of the storage capacitor is arranged in the same layer as the source electrode 1125 and the drain electrode 1126 in the thin film transistor (that is, also in the first display metal layer 1127), so that the first electrode and the second electrode of the storage capacitor A storage capacitor is formed using the display region interlayer insulating layer 11210 as a dielectric material.
  • the display substrate may further include an encapsulation layer 1150 disposed on the light emitting element 1140 .
  • the encapsulation layer 1150 seals the light emitting element 1140, so that deterioration of the light emitting element 1140 caused by moisture and/or oxygen included in the environment can be reduced or prevented.
  • the encapsulation layer 1150 may be a single-layer structure or a composite layer structure, and the composite layer structure includes an inorganic layer and an organic layer stacked structure.
  • the encapsulation layer 1150 may include a first inorganic encapsulation layer 1151, a first organic The encapsulation layer 1152 and the second inorganic encapsulation layer 1153 .
  • the encapsulation layer 1150 may extend to the bonding area, which in the above example does not cover the contact pads.
  • the material of the encapsulation layer may include insulating materials such as silicon nitride, silicon oxide, silicon oxynitride, and polymer resin.
  • insulating materials such as silicon nitride, silicon oxide, silicon oxynitride, and polymer resin.
  • Inorganic materials such as silicon nitride, silicon oxide, and silicon oxynitride have high compactness and can prevent the intrusion of water and oxygen;
  • the material of the organic encapsulation layer can be a polymer material containing a desiccant or a polymer material that can block water vapor, etc. , such as polymer resin, etc.
  • the display substrate to planarize the surface of the display substrate, and can relieve the stress of the first inorganic encapsulation layer and the second inorganic encapsulation layer, and can also include water-absorbing materials such as desiccants to absorb the water intruding inside, substances such as oxygen.
  • water-absorbing materials such as desiccants to absorb the water intruding inside, substances such as oxygen.
  • 6A and 6B respectively illustrate cross-sectional views along A2-B2 and A3-B3 of another example of the display substrate of FIG. 2 .
  • 6A and FIG. 6B are different from FIG. 4A and FIG. 4B at least in that the input contact pad P1 and the output contact pad P2 further include a third conductor portion.
  • the difference will be mainly described below in detail.
  • the output contact pad P2 includes a third conductor portion 1244 in addition to the above-described first wire connection portion 1241 , first conductor portion 1242 , and second conductor portion 1243 .
  • the display substrate further includes a bonding area barrier layer 1255 and a bonding area inorganic layer 1256 .
  • the third conductor portion 1244 is located on the side of the second conductor portion 1243 away from the base substrate 10 , and the bonding region barrier layer 1255 and the bonding region inorganic layer 1256 are located between the third conductor portion 1244 and the second conductor portion 1243 .
  • the bonding area barrier layer 1255 covers the second conductor layer 1243 and the first portion 1230A of the contact pad insulating layer 1230 , and the bonding area inorganic layer 1256 covers the bonding area barrier layer 1255 .
  • the third conductor portion 1244 is electrically connected to the second conductor portion 1243 through via holes provided in the bonding region barrier layer 1255 and via holes provided in the bonding region inorganic layer 1256 (as shown by the dotted frame in FIG. 6A ) .
  • the input contact pad P1 has substantially the same structure as the output contact pad P2 , and details are not repeated here.
  • FIGS. 7A and 7B respectively illustrate cross-sectional views along A2-B2 and A3-B3 of yet another example of the display substrate of FIG. 2 .
  • the bonding area of FIGS. 7A and 7B is different from that of FIGS. 6A and 6B .
  • At least a second portion of the contact pad insulating layer is removed, ie, the second thickness is zero.
  • the thickness of the second portion 1230B of the contact pad insulating layer 1230' is 0, that is, the second portion 1230B of the contact pad insulating layer 1230' is removed while the first portion 1230A remains.
  • the thickness of the portion of the passivation layer 1254 in the bonding region between the second portion 1230B and the second gate insulating layer 1254 in the bonding region is greater than 0, that is, at least partially retained.
  • FIGS. 8A and 8B respectively illustrate cross-sectional views along A2-B2 and A3-B3 of yet another example of the display substrate of FIG. 2 .
  • the bonding area of FIGS. 8A and 8B is different from that of FIGS. 7A and 7B , at least the passivation layer is also partially removed. As shown in FIGS.
  • the second portion 1230B of the contact pad insulating layer 1230 ′ and the portion of the bonding region passivation layer 1254 thereunder are removed, so that the thickness of the second portion 1230B is 0, and the bonding region is passivated
  • the thickness of the portion of the layer 1254 between the second portion 1230B of the contact pad insulating layer 1230' and the second gate insulating layer 1254 in the bonding region is also zero.
  • FIG. 9 illustrates a cross-sectional view of a display area of a display substrate according to another embodiment of the present disclosure.
  • the difference between the display area structure in FIG. 9 and FIG. 5 is at least that the display substrate further includes a display area barrier layer, a first touch electrode layer, a second touch electrode layer, and a touch insulating layer.
  • the display substrate further includes a display area barrier layer, a first touch electrode layer, a second touch electrode layer, and a touch insulating layer.
  • the encapsulation layer 1150 is located on the side of the light-emitting element 1140 away from the base substrate 10
  • the display area barrier layer 1171 is located on the side of the encapsulation layer 1150 away from the base substrate 10
  • the first touch electrode layer 1172 is located on the side of the encapsulation layer 1150 away from the base substrate 10
  • the display area barrier layer 1171 is located on the side away from the base substrate 10
  • the touch insulating layer 1174 is located on the side of the first touch electrode layer 1172 away from the base substrate 10 and covers the first touch electrode layer 1172 and the second touch electrode
  • the layer 1173 is located on the side of the touch insulating layer 1174 away from the base substrate 10 .
  • the second touch electrode layer 1173 is electrically connected to the first touch electrode layer 1172 through via holes in the touch insulating layer 1174 .
  • the first touch electrode layer 1172 and The second touch electrode layer 1173 can be provided in other patterns as required.
  • the first touch electrode layer 1172 and the second touch electrode layer 1173 can be used to realize a capacitive touch structure, and the capacitive touch structure is a self-capacitance type or a mutual capacitance type.
  • the third conductor portion 1244 located in the bonding area may be disposed in the same layer as the second touch electrode layer 1173 in the display area, and the bonding area barrier layer 1255 located in the bonding area may be the same as the display area barrier layer 1171 in the display area.
  • Layer arrangement, the above-mentioned inorganic layer 1256 in the bonding region and the touch insulating layer 1174 in the display region can be arranged in the same layer.
  • FIG. 10 illustrates a partial plan view of a bonding area of a display substrate according to another embodiment of the present disclosure.
  • FIG. 11 shows a schematic diagram of a cross section of the bonding region of FIG. 10 along C1-D1.
  • the difference between the display substrate of FIGS. 10 and 11 and the display substrate of FIGS. 2 and 3 is at least that the bonding area 12 is further provided with a plurality of first dummy contact pads P3.
  • the difference will be mainly described below in detail. illustrate.
  • the display substrate further includes a plurality of first dummy contact pads P3, which are located in the bonding area 12, and located in a plurality of input contact pads P1 and a plurality of output contact pads in the area between the contact pads P2.
  • the first dummy contact pads P3 may not be connected to leads, and when the control chip is bonded to the bonding area of the display substrate, the first dummy contact pads P3 are docked with corresponding pins on the control chip to play a supporting role.
  • the edge of the first dummy contact pad P3 is covered by the first portion 1230A of the contact pad insulating layer 1230 , and the surface of the first dummy contact pad P3 facing away from the base substrate 10 is exposed from the first portion 1230A of the contact pad insulating layer 1230 .
  • the second portion 1230B of the contact pad insulating layer 1230 includes a first sub-portion 1230B1 and a second sub-portion 1230B2, and the first sub-portion 1230B1 is located between the plurality of first dummy contact pads P3 and the plurality of input contact pads P1. area, the second sub-portion 1230B2 is located in the area between the plurality of first dummy contact pads P3 and the plurality of output contact pads P2.
  • FIG. 12A shows a cross-sectional view along C2-D2 of an example of the display substrate of FIG. 10 .
  • the first dummy contact pad P3 includes a fourth conductor portion 1245 .
  • the first gate insulating layer 1251 of the bonding area, the second gate insulating layer 1252 of the bonding area, the interlayer insulating layer 1253 of the bonding area and the passivation layer 1254 of the bonding area are stacked on the base substrate 10 in sequence.
  • the fourth conductor portion 1245 is located on the side of the bonding region passivation layer 1254 facing away from the base substrate 10 , that is, on the side of the base substrate 10 facing the plurality of input contact pads P1 and the plurality of output contact pads P2 .
  • the first portion 1230A of the contact pad insulating layer 1230 covers the edge of the fourth conductor portion 1245, and the second portion 1230B of the contact pad insulating layer 1230 includes a first sub-portion 1230B1 and a second sub-portion 1230B2 with a thickness smaller than that of the first portion 1230A.
  • the fourth conductor portion 1245 may be disposed in the same layer as the above-mentioned second conductor portion 1243, for example, the fourth conductor portion 1245 and the second conductor portion 1243 may be disposed in the same layer as the first transition electrode 1180 in the display area.
  • FIG. 12B shows a cross-sectional view along C2-D2 of another example of the display substrate of FIG. 11 .
  • the display substrate of FIG. 12B is different from the display substrate of FIG. 12A at least in that a second portion of the contact pad insulating layer and a portion of the bonding region passivation layer are removed.
  • the second portion 1230B of the contact pad insulating layer 1230' and a portion of the first gate insulating layer 1251 in the bonding region below it are removed, that is, both have a thickness of zero.
  • FIG. 12C shows a cross-sectional view along C2-D2 of the bonding area of yet another example of the bonding area of FIG. 11 .
  • the difference between the display substrate of FIG. 12C and the display substrate of FIG. 12A is at least that the first dummy contact pad P3 includes a fifth conductor part 1246 in addition to the fourth conductor part 1245 ′, and the fifth conductor part 1246 is located in the fourth conductor part 1245 and the base substrate 10.
  • the first gate insulating layer 1251 in the bonding area, the second gate insulating layer 1252 in the bonding area, and the interlayer insulating layer 1253 in the bonding area are sequentially stacked on the base substrate 10 .
  • the fifth conductor portion 1246 is located on the side of the bonding region interlayer insulating layer 1253 away from the base substrate 10 .
  • the bonding region passivation layer 1254 is located on the side of the bonding region interlayer insulating layer 1253 away from the base substrate 10 and covers the edge of the fifth conductor portion 1246 .
  • the fourth conductor portion 1245' is located on the side of the fifth conductor portion 1246 away from the substrate 10, and the edge of the fourth conductor portion is covered by the first portion of the contact pad insulating layer.
  • the fifth conductor portion 1246 is electrically connected to the fourth conductor portion 1245 through via holes in the bonding region passivation layer 1254 .
  • the fourth conductor portion 1245' may be provided in the same layer as the second conductor portion 1243 described above, and the fifth conductor portion 1246 may be provided in the same layer as the first conductor portion 1242 described above.
  • the fourth conductor part 1245 ′ can be provided in the same layer as the second conductor part 1243 and the first transfer electrode 1180 in the display area, and the fifth conductor part 1246 can be arranged with the first conductor part 1242 and the first display metal in the display area.
  • Layer 1127 is set on the same layer.
  • FIG. 13 shows a partial plan view of a bonding area of a display substrate according to yet another embodiment of the present disclosure
  • FIG. 14 shows a schematic diagram of a cross section of the display substrate of FIG. 13 along E1-F1.
  • the plan view of FIG. 13 shows the left and right side portions of the bonding area of the display substrate along the x-direction.
  • the difference between the display substrates of FIGS. 13 and 14 and the display substrates of FIGS. 10 and 11 is at least that the bonding area 12 is further provided with a plurality of array test contact pads P4 and a plurality of second dummy contact pads P5.
  • the different parts will be mainly described in detail below.
  • the bonding area of the display substrate is further provided with a plurality of array test contact pads P4, and the plurality of array test contact pads P4 are located between the plurality of first dummy contact pads P1 and the plurality of array test contact pads P4. input in the area between the contact pads P2.
  • the plurality of array test contact pads P4 are used for the array test during the manufacturing process of the display substrate.
  • the array test contact pad P4 may be associated with the plurality of sub-pixels.
  • At least one of the array test contact pads P4 may be connected to the sub-pixels of the display area through wires of the bonding area, such as to a multiplexing circuit through wires, so as to be connected to a plurality of strips of the display area via the multiplexing circuit data signal lines to achieve electrical connection with the sub-pixels.
  • the first portion 1230A of the contact pad insulating layer 1230 includes a first sub-portion 1230A1 and a second sub-portion 1230A2.
  • the edges of the plurality of input contact pads P1, the edges of the plurality of output contact pads P2, and the edge of the first dummy contact pad P3 are protected by the first sub-portion 1230A1 of the first portion 1230A of the contact pad insulating layer 1230 cover.
  • the edges of the plurality of array test contact pads P4 whose surfaces facing away from the base substrate 10 from the contact pad insulation layer 1230 are covered by the second sub-portion 1230A2 of the first portion 1230A of the contact pad insulating layer 1230 .
  • the second sub-portion 1230A1 of the first portion 1230A of the pad insulating layer 1230 is exposed.
  • the projection of the second sub-portion 1230A2 of the first portion 1230A of the contact pad insulating layer 1230 on the base substrate 10 is located at the second sub-portion 1230B of the second portion 1230B of the contact pad insulating layer 1230 .
  • a sub-portion 1230B1 is within the projection of the base substrate 10 .
  • This arrangement of the contact pad insulating layer 1230 makes it possible to protect the edges of the input contact pad P1, the output contact pad P2, the first dummy contact pad P3 and the array test contact pad P4 while improving the connection stability of the contact pads, The etchant in the subsequent patterning process is prevented from etching the edges of the exposed contact pads, thereby improving the product yield and reliability of the display substrate.
  • the plurality of input contact pads P1 are arranged in a first row along the first direction, the first direction being the extension direction (x direction) of the side of the display area facing the bonding area; the plurality of output contact pads The pads P2 are arranged in a second row along the first direction; the plurality of first dummy contact pads are arranged in a third row along the first direction; the plurality of array test contact pads are arranged in a fourth row along the first direction.
  • the embodiments of the present disclosure are not limited thereto, and any one of the input contact pads P1, the output contact pads P2, the first dummy contact pads P3 and the array test contact pads P4 may be arranged in multiple rows or in other forms as required.
  • a plurality of second dummy contact pads P5 may also be provided in the bonding area of the display substrate.
  • the second dummy contact pad P5 may have a structure similar to that of the first dummy contact pad P4, and may also play a supporting role.
  • a plurality of second dummy contact pads P5 are arranged in a first column and a second column along a second direction (y direction) perpendicular to the first direction, wherein the first column and the second column are respectively located in the plurality of first Both sides of the dummy contact pads P1 in the first direction.
  • the embodiments of the present disclosure are not limited thereto, and the plurality of second dummy contact pads P5 may be arranged in multiple columns or in other forms as required, or may be located on one side (eg, the left side or the left side) of the plurality of first dummy contact pads P1. Right).
  • the first portion 1230A of the insulating layer 1230 is exposed.
  • the second portion 1230B of the insulating layer 1230 and the contact pad each have a certain distance between the projections of the base substrate 10 , and the distance may be in the range of 3 micrometers to 100 micrometers.
  • the input contact pad P1 , the output contact pad P2 , the first dummy contact pad P3 , the array test contact pad P4 and the second dummy contact pad P5 may each have the same or different pitches from the second portion 1230B of the contact pad insulating layer 1230 .
  • the input contact pad P1, the output contact pad P2, and the second dummy contact pad P5 may be equal to the second portion 1230B of the contact pad insulating layer 1230, but larger than the first dummy contact pad P3 and the array test contact pad P4 and the contact pad.
  • the pitch of the second portion 1230B of the insulating layer 1230 may be equal to the first dummy contact pad P3 and the array test contact pad P4 and the contact pad.
  • the respective projections of the input contact pads P1, the output contact pads P2, the first dummy contact pads P3, the array test contact pads P4, and the second dummy contact pads P5 on the base substrate 10 are shown as having a specific
  • the projection of the input contact pad P1 and the output contact pad P2 on the base substrate 10 is a parallelogram
  • the projection of the array test contact pad P4 and the second virtual contact pad P5 on the base substrate 10 is a rectangle
  • the first The projection of the dummy contact pad P3 on the base substrate 10 is substantially square.
  • the input contact pads P1, the output contact pads P2, the first dummy contact pads P3, the array test contact pads P4, and the second dummy contact pads P5 are each symmetric along the symmetry axis Y of the display substrate in the y-direction set up.
  • the embodiments of the present disclosure are not limited thereto, and the shape and arrangement of each contact pad can be set as required.
  • FIG. 15A shows a cross-sectional view along E2-F2 of one example of the display substrate of FIG. 13 .
  • the array test contact pad P5 has a structure similar to the output contact pad of FIG. 4A and the input contact pad of FIG. 4B.
  • the array test contact pad P5 includes a second lead connection part 1247 , a sixth conductor part 1248 and a seventh conductor part 1249 .
  • the second lead connecting part 1247 , the sixth conductor part 1248 and the seventh conductor part 1249 may be the same as the first lead connecting part 1241 , the first conductor part 1242 and the second conductor part 1243 , respectively Layer settings.
  • the second lead connecting portion 1247 is located on the side of the base substrate 10 facing the plurality of input contact pads P1 and the plurality of output contact pads P2, and is used for connecting with lead wires connected to the data lines, thereby realizing the first The electrical connection between the two-wire connection portion 1247 and the sub-pixels in the display area.
  • the sixth conductor portion 1248 is located on the side of the second lead connecting portion 1247 away from the base substrate 10 , and is electrically connected to the second lead connecting portion 1247 .
  • the seventh conductor portion 1249 is located on the side of the sixth conductor portion 1247 away from the base substrate 10 and is electrically connected to the sixth conductor portion 1248 .
  • the second dummy contact pad P5 may have a structure similar to that of the first dummy contact pad P4 described above, which will be described below with reference to FIGS. 15B to 15D .
  • FIG. 15B shows a cross-sectional view along E3-F3 of an example of the display substrate of FIG. 13 .
  • the second dummy contact pad P5 has a structure similar to that of the first dummy contact pad P4 in FIG. 12A
  • the second dummy contact pad P5 includes an eighth conductor portion 12410
  • the eighth conductor portion 12410 is located on the substrate surface 10 to one side of the plurality of input contact pads P1 and the plurality of output contact pads P2.
  • the eighth conductor portion 12410 may be provided in the same layer as the second conductor portion 1243 described above.
  • the edge of the eighth conductor portion 12410' is covered by the first portion 1230A of the contact pad insulating layer 1230, which is covered by the first sub-portion 1230A1 of the first portion 1230A of the contact pad insulating layer 1230 in FIG. 15D.
  • FIG. 15C shows a cross-sectional view along E3-F3 of another example of the display substrate of FIG. 13 .
  • the display substrate of FIG. 15C is different from the display substrate of FIG. 15B at least in that the second portion 1230B of the contact pad insulating layer 1230 and a portion of the bonding region passivation layer 1241 are removed.
  • the thicknesses of the second portion 1230B of the contact pad insulating layer 1230' and the first gate insulating layer 1251 of the bonding region below it are both zero.
  • FIG. 15D shows a cross-sectional view along E3-F3 of another example of the display substrate of FIG. 13 .
  • the second dummy contact pad P5 has a structure similar to that of the first dummy contact pad P4 of FIG. 12C , and the second dummy contact pad P5 includes a ninth conductor part 12411 in addition to the eighth conductor part 12410 ′ , the ninth conductor portion 12411 is located between the eighth conductor portion 12410 ′ and the base substrate 10 and is electrically connected to the eighth conductor portion 12410 ′.
  • the eighth conductor portion 12410' may be provided in the same layer as the second conductor portion 1243, and the ninth conductor portion may be provided in the same layer as the first conductor portion 1242.
  • the edge of the eighth conductor portion 12410' is covered by the first portion 1230A of the contact pad insulating layer 1230, which is covered by the first sub-portion 1230A1 of the first portion 1230A of the contact pad insulating layer 1230 in FIG. 15D.
  • the embodiments of the present disclosure are not limited thereto.
  • the thinning or removal of the second portion of the layer and its underlying bonding region passivation layer is applicable to other contact pad structures, such as in some embodiments, at least The second portion of one of the contact pad insulating layers and/or the bonding region passivation layer thereunder may be thinned or removed as desired.
  • FIG. 16A illustrates a cross-sectional view of a display area of a display substrate according to another embodiment of the present disclosure.
  • FIG. 16B illustrates a cross-sectional view of a bonding area of the display substrate of FIG. 16A .
  • the display substrates of FIGS. 16A and 16B differ from the display substrates of the foregoing embodiments at least not having a passivation layer.
  • the display area of the display substrate has a structure similar to that of the display area in FIG. 9 , except that the display area passivation layer 11110 is not provided.
  • the bonding area of the display substrate has a structure similar to that of the bonding area in FIGS.
  • the bonding area passivation layers 1245 and 1245 ′ are not provided, and the second conductor portion 1243 is located on the first conductor
  • the part 1242 faces away from the base substrate 10 and covers the first conductor part 1242
  • the contact pad insulating layer 1230 ′ is provided on the side of the bonding area interlayer insulating layer 1253 away from the base substrate 10 and covers the second conductor part 1243 edge.
  • FIG. 16B For the sake of simplicity, only the bonding area structure of the output contact pad P2 and its surrounding area is shown in FIG. 16B , and other parts of the bonding area may be the same as those shown in FIGS. 4A to 4C , 6A to 8B and 12A to 12C Similar to the structures described in Figures 15A-15D except that the bonding region passivation layer is removed from these structures.
  • At least one embodiment of the present disclosure provides a display device, and the display device may include the display substrate of any of the foregoing embodiments.
  • the display device may further include a flexible circuit board and a control chip.
  • the flexible circuit board is bonded to the bonding area of the display substrate, and the control chip is mounted on the flexible circuit board, thereby being electrically connected to the display area; or, the control chip is directly bonded to the bonding area, thereby being connected to the display area. electrical connection.
  • control chip may be a central processing unit, a digital signal processor, a system-on-chip (SoC), or the like.
  • the control chip may further include a memory, a power supply module, etc., and implement power supply and signal input and output functions through additionally provided wires, signal wires, and the like.
  • the control chip may also include hardware circuits, computer executable codes, and the like.
  • Hardware circuits may include conventional very large scale integration (VLSI) circuits or gate arrays as well as off-the-shelf semiconductors such as logic chips, transistors, or other discrete components; hardware circuits may also include field programmable gate arrays, programmable array logic, Programmable logic devices, etc.
  • VLSI very large scale integration
  • the display device provided by at least one embodiment of the present disclosure may be any product or component with a display function, such as a mobile phone, a tablet computer, a TV, a monitor, a notebook computer, a digital photo frame, and a navigator.
  • a display function such as a mobile phone, a tablet computer, a TV, a monitor, a notebook computer, a digital photo frame, and a navigator.
  • At least one embodiment of the present disclosure further provides a method for fabricating a display substrate, the method comprising: providing a base substrate, the base substrate including a display area, a bonding area located on at least one side of the display area, and a bonding area located on at least one side of the display area.
  • FIGS. 17A to 17G The manufacturing process of the display substrate according to the embodiment of the present disclosure will be described below with reference to FIGS. 17A to 17G in conjunction with the display substrate of FIGS. 8A and 9 .
  • a base substrate 10 is provided, the base substrate 10 includes a display area and a peripheral area located around the display area, the peripheral area includes at least one bonding area located on at least one side of the display area and a peripheral area located on the display area. The side area on at least the other side of the area.
  • the pixel driving circuit 1120 , the storage capacitor 1160 , the first planarization layer 1130 and the first transfer electrode 1180 are formed in the display area of the base substrate 10 , and the first gate insulating layer 1251 of the bonding area is formed in the bonding area of the display substrate 10 .
  • first lead connection portion 1231 a first lead connection portion 1231 , a second gate insulating layer 1252 , a bonding region interlayer insulating layer 1253 , a first conductor portion 1242 , a bonding region passivation layer 1254 ′ and a second conductor portion 1243 .
  • the second conductor portion 1243 covers the edge of the first conductor portion 1242 to prevent the first conductor portion 1242 from being corroded.
  • the first conductor portion 1242 and the second conductor portion 1243 are stacked.
  • an insulating material layer 1710 is deposited on the base substrate, and a photoresist 1720 is deposited on the insulating material layer 1710 .
  • the insulating material layer 1710 may include insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride.
  • a mask 1610 is provided to expose the photoresist 1720, and the mask 1610 includes a fully transparent area, a partially transparent area and an opaque area.
  • the mask 1610 includes a first light-transmitting pattern 1611 overlapping with a region where the second portion 1230B of the contact pad insulating layer 1230 is to be formed and a second light-transmitting pattern 1612 overlapping with the output contact pad P2 in the bonding area.
  • the mask 1610 includes a second light-transmitting pattern 1612 and a non-light-transmitting pattern 1613 in the display area.
  • the first transparent pattern 1611 is located in the partially transparent area
  • the second transparent pattern 1612 is located in the fully transparent area
  • the non-transparent pattern 1613 is located in the opaque area. That is, the reticle 1610 is a gray reticle or a halftone reticle.
  • the photoresist is a positive photoresist.
  • the light transmittance of the first light-transmitting pattern 1611 is lower than that of the second light-transmitting pattern 1612 .
  • a portion of the photoresist 1720 corresponding to the first light-transmitting pattern 1611 may be partially exposed under the condition that the portion of the photoresist 1720 corresponding to the second light-transmitting pattern 1612 is completely exposed.
  • the portion of the photoresist 1720 corresponding to the non-transmissive pattern 1613 in the display area is not exposed.
  • negative photoresist can also be used, then the mask used is, for example, a mask complementary to the above mask 1610, so that the above photoresist pattern 1721 is obtained after exposure and development. and photoresist pattern 1722.
  • the photoresist 1720 is developed, and the fully exposed portion of the photoresist 1720 is removed, that is, in the bonding area, the contact pad P2 and the second portion where the contact pad insulating layer is to be provided
  • the photoresist 1720 that overlaps the area of 1230B is removed, the partially exposed portion of the photoresist 1720 is thinned, and the thickness of the unexposed portion of the photoresist 1720 is, for example, substantially unchanged.
  • the photoresist 1720 is formed into a photoresist pattern 1721 in the bonding area.
  • the photoresist 1720 overlapping the drain electrode 1126 is removed.
  • the photoresist 1720 is formed into a photoresist pattern 1722 in the display area.
  • the insulating material layer 1710 in the bonding area and the display area is etched to remove the insulation overlapping the output contact pad P2 and the area where the second portion 1230B of the insulating layer of the contact pad is to be provided in the bonding area material layer, and a second via hole 1191 is formed in the display area.
  • an ashing process is performed to remove the photoresist pattern 1721 in the bonding area and thin the photoresist pattern 1722 in the display area, where the photoresist pattern 1722 in the display area is retained. Then, using the current photoresist pattern, the remaining insulating material layer 1710 in the bonding area is etched and the etching thickness is controlled to form the contact pad insulating layer 1230, and the contact pad insulating layer 1230 formed after etching has The first portion 1230A and the second portion 1230B having a thickness smaller than the first portion 1230A, the thickness of the second portion 1230B in FIG. 17F is 0, that is, the insulating material of this portion is removed.
  • the photoresist pattern 1722 of the display area is removed.
  • a second planarization layer 1190 is formed in the display area to provide a planarized surface.
  • the light emitting element 1140 is formed on the second planarization 1190 of the display area.
  • An encapsulation layer 1150 is formed on the light emitting elements 1140 in the display area. The encapsulation layer 1150 seals the light emitting element 1140, so that deterioration of the light emitting element 1140 caused by moisture and/or oxygen included in the environment can be reduced or prevented.
  • a display area barrier layer 1171 is formed on the encapsulation layer 1150 in the display area, and a bonding area barrier layer 1255 is formed in the bonding area.
  • a first touch electrode layer 1172 is formed on the display area barrier layer 1171 in the display area.
  • a touch insulating layer 1174 is formed on the first touch electrode layer 1172 in the display area, and a bonding area inorganic layer 1256 is formed on the bonding area barrier layer 1255 in the bonding area.
  • a second touch electrode layer 1173 is formed on the touch insulating layer 1174 in the display area, and a third conductor portion 1244 is formed on the bonding area inorganic layer 1256 in the bonding area.

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Abstract

本公开提供了一种显示基板及其制造方法和显示装置。所述显示基板包括：衬底基板、多个子像素、栅极驱动电路、多个输入接触垫、多个输出接触垫和接触垫绝缘层，所述多个输入接触垫和所述多个输出接触垫的背离所述衬底基板的表面从所述接触垫绝缘层外露，其中所述接触垫绝缘层包括具有第一厚度的第一部分和具有第二厚度的第二部分，所述第二厚度小于所述第一厚度，所述多个输入接触垫和所述多个输出接触垫的边缘被所述接触垫绝缘层的第一部分覆盖，所述接触垫绝缘层的第二部分位于所述多个输入接触垫与所述多个输出接触垫之间的区域中。

Description

显示基板及其制造方法和显示装置
本申请要求于2020年9月10日提交的、申请号为202010950350.X的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开涉及显示技术领域，具体涉及一种显示基板及其制造方法和显示装置。
背景技术
通常，显示基板中用于与驱动芯片连接的引脚被设计为多层结构，以使引脚垫高，增大与驱动芯片上对应引脚的粘结力。在制作过程中会在引脚上覆盖有机层，然后去除引脚表面的有机层以使引脚外露。但是传统显示基板在进行高温高湿信赖性测试时，驱动芯片IC容易脱落。
发明内容
本公开实施例提供了一种显示基板，包括：
衬底基板，包括显示区、位于所述显示区至少一侧的邦定区和位于所述显示区至少另一侧的侧边区；
多个子像素，位于所述显示区中；
栅极驱动电路，位于所述侧边区，所述栅极驱动电路与所述多个子像素连接，并且被配置为向所述多个子像素提供栅极驱动信号；
多个输入接触垫，位于所述邦定区，用于与外部电路电连接；
多个输出接触垫，位于所述邦定区，且位于所述多个输入接触垫与所述显示区之间，所述多个输出接触垫与所述多个子像素和所述栅极驱动电路电连接；
接触垫绝缘层，位于所述邦定区，且位于所述多个输入接触垫中相邻输入接触垫之间的间隙、所述多个输出接触垫中相邻输出接触垫之间的间隙、以及所述多个输入接触垫与所述多个输出接触垫之间的区域，所述多个输入接触垫和所述多个输出接触垫的背离所述衬底基板的表面从所述接触垫绝缘层外露，其中所述接触垫绝缘层包括具有第一厚度的第一部分和具有第二厚度的第二部分，所述第二厚度小于所述第一厚度，所述多 个输入接触垫和所述多个输出接触垫的边缘被所述接触垫绝缘层的第一部分覆盖，所述接触垫绝缘层的第二部分位于所述多个输入接触垫与所述多个输出接触垫之间的区域中。
例如，所述显示基板还包括：多个第一虚拟接触垫，位于所述邦定区，且位于所述多个输入接触垫与所述多个输出接触垫之间的区域中，其中，
所述多个第一虚拟接触垫的边缘被所述接触垫绝缘层的第一部分覆盖，所述多个第一虚拟接触垫的背离所述衬底基板的表面从所述接触垫绝缘层的第一部分外露；并且
所述接触垫绝缘层的第二部分包括第一子部分和第二子部分，所述第一子部分位于所述多个第一虚拟接触垫与所述多个输入接触垫之间的区域，所述第二子部分位于所述多个第一虚拟接触垫与所述多个输出接触垫之间的区域。
例如，所述显示基板还包括：多个阵列测试接触垫，位于所述邦定区，且位于所述多个第一虚拟接触垫与所述多个输入接触垫之间的区域中，所述多个阵列测试接触垫与所述多个子像素和所述栅极驱动电路电连接，其中，
所述接触垫绝缘层的第一部分包括第一子部分和第二子部分，所述多个输入接触垫的边缘、所述多个输出接触垫的边缘和所述第一虚拟接触垫的边缘被所述接触垫绝缘层的第一部分的第一子部分覆盖，所述多个阵列测试接触垫的边缘被所述接触垫绝缘层的第一部分的第二子部分覆盖，所述多个阵列测试接触垫的背离所述衬底基板的表面从所述接触垫绝缘层的第一部分外露；并且
所述接触垫绝缘层的第一部分的第二子部分在所述衬底基板上的投影位于所述接触垫绝缘层的第二部分的第一子部分在所述衬底基板的投影之内。
例如，所述多个输入接触垫和所述多个输出接触垫中的每一个在所述衬底基板上的投影与所述接触垫绝缘层的第二部分在所述衬底基板的投影之间的间距在3微米至100微米的范围内。
例如，所述第二厚度为0。
例如，所述多个输入接触垫沿第一方向排列成至少第一行，所述第一方向为所述显示区的面向所述邦定区的侧边的延伸方向；
所述多个输出接触垫沿第一方向排列成至少第二行；
所述多个第一虚拟接触垫沿第一方向排列成至少第三行；
所述多个阵列测试接触垫沿第一方向排列成至少第四行。
例如，所述显示基板还包括：多个第二虚拟接触垫，位于所述邦定区，沿垂直于所 述第一方向的第二方向排列成至少第一列和第二列，其中第一列和第二列分别位于所述多个第一虚拟接触垫在第一方向上的两侧，其中，
所述多个第二虚拟接触垫的边缘被所述接触垫绝缘层的第一部分覆盖，所述多个第二虚拟接触垫的背离所述衬底基板的表面从所述接触垫绝缘层的第一部分外露；并且
所述多个第二虚拟接触垫中的每一个在所述衬底基板上的投影与所述接触垫绝缘层的第二部分在所述衬底基板的投影之间的间距在3微米至100微米的范围内。
例如，所述多个输入接触垫和所述多个输出接触垫中的至少一个包括：
第一引线连接部，位于所述衬底基板上，其中输入接触垫的第一引线连接部通过设置在所述邦定区的第一引线与用于连接到外部电路的连接接触垫电连接，输出接触垫的第一引线连接部通过设置在所述邦定区的第二引线与所述栅极驱动电路或者与所述多个子像素中的至少一个电连接；
第一导体部，位于所述第一引线连接部背离所述衬底基板的一侧，与所述第一引线连接部电连接；
第二导体部，位于所述第一导体部背离所述衬底基板的一侧，与所述第一导体部电连接，所述第二导体部的边缘被所述接触垫绝缘层的第一部分覆盖。
例如，所述显示基板还包括：
邦定区第一栅绝缘层，位于所述邦定区，覆盖所述衬底基板，所述第一引线连接部位于所述邦定区第一栅绝缘层背离所述衬底基板的一侧；
邦定区第二栅绝缘层，位于所述邦定区，位于所述邦定区第一栅绝缘层背离所述衬底基板的一侧并且覆盖所述第一引线连接部；
邦定区层间绝缘层，位于所述邦定区，且位于所述邦定区第二栅绝缘层背离所述衬底基板的一侧，所述第一导体部通过设置在所述邦定区第二栅绝缘层中的过孔和设置在所述邦定区层间绝缘层中的过孔与所述第一引线连接部电连接；
邦定区钝化层，位于邦定区，位于所述邦定区层间绝缘层背离所述衬底基板的一侧并且覆盖所述第一导体部，所述第二导体部通过设置在所述邦定区钝化层中的过孔与所述第一导体部电连接。
例如，所述邦定区钝化层位于所述接触垫绝缘层的第二部分与所述邦定区第二栅绝缘层之间的部分厚度大于或等于0。
例如，显示基板还包括：
邦定区第一栅绝缘层，位于所述邦定区，覆盖所述衬底基板，所述第一引线连接部 位于所述邦定区第一栅绝缘层背离所述衬底基板的一侧；
邦定区第二栅绝缘层，位于所述邦定区，位于所述邦定区第一栅绝缘层背离所述衬底基板的一侧并且覆盖所述第一引线连接部；
邦定区层间绝缘层，位于所述邦定区，且位于所述邦定区第二栅绝缘层背离所述衬底基板的一侧，所述第一导体部通过设置在所述邦定区第二栅绝缘层中的过孔和设置在所述邦定区层间绝缘层中的过孔与所述第一引线连接部电连接，所述第二导体部位于所述第一导体部背离所述衬底基板的一侧并且覆盖所述第一导体部。
例如，所述多个输入接触垫和所述多个输出接触垫中的所述至少一个还包括：
第三导体部，位于所述第二导体部背离所述衬底基板的一侧，与所述第二导体部电连接。
例如，所述显示基板还包括：
邦定区阻挡层，位于所述邦定区，覆盖所述第二导体层和所述接触垫绝缘层的第一部分，
邦定区无机层，位于所述邦定区，覆盖所述邦定区阻挡层，所述第三导体部通过设置在所述邦定区阻挡层中的过孔和设置在所述邦定区无机层中的过孔与所述第二导体部电连接。
例如，所述多个第一虚拟接触垫中的至少一个包括第四导体部，所述第四导体部位于所述衬底基板面向所述多个输入接触垫和所述多个输出接触垫的一侧，所述第四导体部的边缘被所述接触垫绝缘层的第一部分覆盖，
其中所述多个输入接触垫和所述多个输出接触垫中的至少一个包括第一引线连接部、第一导体部和第二导体部，所述第四导体部与所述第二导体部同层设置。
例如，所述多个第一虚拟接触垫中的至少一个还包括第五导体部，所述第五导体部位于所述第四导体部与所述衬底基板之间并且与所述第四导体部电连接，所述第五导体部与所述第一导体部同层设置。
例如，所述多个阵列测试接触垫中的至少一个包括：
第二引线连接部，位于所述衬底基板面向所述多个输入接触垫和所述多个输出接触垫的一侧；
第六导体部，位于所述第二引线连接部背离所述衬底基板的一侧，与所述第二引线连接部电连接；
第七导体部，位于所述第六导体部背离所述衬底基板的一侧，与所述第六导体部电 连接，所述第七导体部的边缘被所述接触垫绝缘层的第一部分覆盖，
其中所述多个输入接触垫和所述多个输出接触垫中的至少一个包括第一引线连接部、第一导体部和第二导体部，所述第二引线连接部、所述第六导体部和所述第七导体部分别与所述第一引线连接部、所述第一导体部和所述第二导体部同层设置。
例如，所述多个第二虚拟接触垫中的至少一个包括第八导体部，所述第八导体部位于所述衬底基板面向所述多个输入接触垫和所述多个输出接触垫的一侧，所述第八导体部的边缘被所述接触垫绝缘层的第一部分覆盖，
其中所述多个输入接触垫和所述多个输出接触垫中的至少一个包括第一引线连接部、第一导体部和第二导体部，所述第八导体部与所述第二导体部同层设置。
例如，所述多个第二虚拟接触垫中的至少一个还包括第九导体部，所述第九导体部位于所述第八导体部与所述衬底基板之间并且与所述第八导体部电连接，所述第九导体部与所述第一导体部同层设置。
例如，所述多个子像素中至少一个包括像素驱动电路、第一平坦化层、第一转接电极、第二平坦化层以及发光元件，
所述第一平坦化层在所述像素驱动电路远离所述衬底基板的一侧以提供第一平坦化表面；
所述第一转接电极在所述第一平坦化表面上，且通过设置在所述第一平坦化层中的过孔与所述像素驱动电路电连接；
所述第二平坦化层在所述第一转接电极远离所述衬底基板的一侧以提供第二平坦化表面；
所述发光元件在所述第二平坦化表面上且通过设置在所述第二平坦化层中的过孔与所述第一转接电极电连接；
其中，所述接触垫绝缘层与所述第二平坦化层同层设置。
例如，所述像素驱动电路包括薄膜晶体管，所述薄膜晶体管包括栅极、源极和漏极，所述多个输入接触垫和所述多个输出接触垫中的至少一个包括第一引线连接部、第一导体部和第二导体部，其中，
所述第一引线连接部与所述栅极同层设置；
所述第一导体部与所述源极和漏极同层设置，
所述第二导体部与所述第一转接电极同层设置。
例如，所述显示基板还包括显示区钝化层，所述显示区钝化层位于所述像素驱动电 路和所述第一平坦化层之间，所述像素驱动电路和所述第一转接电极还通过设置在所述显示区钝化层中的过孔电连接；
所述显示基板还包括邦定区钝化层，所述邦定区钝化层和所述显示区钝化层同层设置。
例如，所述显示基板还包括位于显示区的封装层、显示区阻挡层、第一触控电极层、第二触控电极层和触控绝缘层，所述封装层位于所述发光元件的远离所述衬底基板的一侧，所述显示区阻挡层位于所述封装层的远离所述衬底基板的一侧，所述第一触控电极层位于所述显示区阻挡层背离所述衬底基板的一侧，所述触控绝缘层位于所述第一触控电极层背离所述衬底基板的一侧并且覆盖所述第一触控电极层，所述第二触控电极层位于所述触控绝缘层背离所述衬底基板的一侧；
所述显示基板还包括位于邦定区的邦定区阻挡层和邦定区无机层，所述多个输入接触垫和所述多个输出接触垫中的至少一个还包括第三导体部，所述邦定区阻挡层、所述邦定区无机层和所述第三导体部分别与所述显示区阻挡层、所述触控绝缘层和所述第二触控电极层位于同层。
例如，所述多个子像素中至少一个还包括显示区层间绝缘层、显示区第一栅绝缘层以及显示区第二栅绝缘层，所述显示区层间绝缘层位于所述栅极与所述源极和所述漏极之间，所述显示区第一栅绝缘层位于所述显示区层间绝缘层面向所述衬底基板的一侧，所述显示区第二栅绝缘层位于所述显示区层间绝缘层与所述显示区第一栅绝缘层之间；
所述显示基板还包括邦定区层间绝缘层、邦定区第一栅绝缘层和所述邦定区第二栅绝缘层，所述邦定区层间绝缘层、所述邦定区第一栅绝缘层和所述邦定区第二栅绝缘层分别与所述显示区层间绝缘层、所述显示区第一栅绝缘层和所述显示区第二栅绝缘层同层设置。
例如，所述多个子像素中至少一个还包括存储电容器，所述存储电容器的第一极与所述栅极同层设置，所述存储电容器的第二极设置在所述显示区层间绝缘层与所述显示区第二栅绝缘层之间。
例如，所述衬底基板包括：
第一柔性层，
第二柔性层，位于所述第一柔性层面向所述多个输入接触垫和所述多个输出接触垫的一侧；
第一衬底阻挡层，位于所述第一柔性层和所述第二柔性层之间；
第二衬底阻挡层，位于所述第二柔性层背离所述第一柔性层的一侧；
缓冲层，位于所述第二衬底阻挡层背离所述第一柔性层的一侧。
本公开的实施例还提供了一种显示装置，包括上述显示基板。
本公开的实施例还提供了一种制造上述显示基板的方法，包括：
提供衬底基板，所述衬底基板包括显示区、位于所述显示区至少一侧的邦定区和位于所述显示区至少另一侧的侧边区；
在所述显示区中形成多个子像素；
在所述侧边区形成栅极驱动电路，所述栅极驱动电路与所述多个子像素连接，并且被配置为向所述多个子像素提供栅极驱动信号；
在所述邦定区形成用于与外部电路电连接的多个输入接触垫；
在所述邦定区中形成多个输出接触垫，所述多个输出接触垫位于所述多个输入接触垫与所述显示区之间，所述多个输出接触垫与所述多个子像素和所述栅极驱动电路电连接；
在所述邦定区形成接触垫绝缘层，所述接触垫绝缘层位于所述多个输入接触垫中相邻输入接触垫之间的间隙、所述多个输出接触垫中相邻输出接触垫之间的间隙、以及所述多个输入接触垫与所述多个输出接触垫之间的区域，所述多个输入接触垫和所述多个输出接触垫的背离所述衬底基板的表面从所述接触垫绝缘层外露，其中所述接触垫绝缘层包括具有第一厚度的第一部分和具有第二厚度的第二部分，所述第二厚度小于所述第一厚度，所述多个输入接触垫和所述多个输出接触垫的边缘被所述接触垫绝缘层的第一部分覆盖，所述接触垫绝缘层的第二部分位于所述多个输入接触垫与所述多个输出接触垫之间的区域中。
附图说明
图1A示出了根据本公开实施例的显示基板的示意图。
图1B示出了图1A的显示基板的显示区的示意图。
图2示出了根据本公开实施例的显示基板的邦定区的局部平面图。
图3示出了图2的显示基板沿A1-B1的截面的示意图。
图4A示出了图2的显示基板的一个示例沿A2-B2的截面图。
图4B示出了图2的显示基板的一个示例沿A3-B3的截面图。
图4C示出了图2的显示基板的一个示例沿A4-B4的截面图。
图5示出了根据本公开一实施例的显示基板的显示区的截面图。
图6A和图6B分别示出了图2的显示基板的另一个示例沿A2-B2和沿A3-B3的截面图。
图7A和图7B分别示出了图2的显示基板的又一个示例在邦定区沿A2-B2和沿A3-B3的截面图。
图8A和图8B分别示出了图2的显示基板的再一个示例在邦定区沿A2-B2和沿A3-B3的截面图。
图9示出了根据本公开另一实施例的显示基板的显示区的截面图。
图10示出了根据本公开另一实施例的显示基板的邦定区的局部平面图。
图11示出了图10的显示基板沿C1-D1的截面的示意图。
图12A示出了图11的显示基板的一个示例沿C2-D2的截面图。
图12B示出了图11的显示基板的另一个示例沿C2-D2的截面图。
图12C示出了图11的显示基板的又一个示例沿C2-D2的截面图。
图13示出了根据本公开又一实施例的显示基板的邦定区的局部平面图。
图14示出了图13的显示基板沿E1-F1的截面的示意图。
图15A示出了图13的显示基板的一个示例沿E2-F2的截面图。
图15B示出了图13的显示基板的一个示例沿E3-F3的截面图。
图15C示出了图13的显示基板的另一个示例沿E3-F3的截面图。
图15D示出了图13的显示基板的又一个示例沿E3-F3的截面图。
图16A示出了根据本公开另一实施例的显示基板的显示区的截面图。
图16B示出了图16A的显示基板的邦定区的截面图。
图17A至图17G示出了根据本公开实施例的显示基板的制造过程的示意图。
具体实施方式
虽然将参照含有本公开的较佳实施例的附图充分描述本公开，但在此描述之前应了解本领域的普通技术人员可修改本文中所描述的公开，同时获得本公开的技术效果。因此，须了解以上的描述对本领域的普通技术人员而言为一广泛的揭示，且其内容不在于限制本公开所描述的示例性实施例。
另外，在下面的详细描述中，为便于解释，阐述了许多具体的细节以提供对本披露实施例的全面理解。然而明显地，一个或多个实施例在没有这些具体细节的情况下也可 以被实施。在其他情况下，公知的结构和装置以图示的方式体现以简化附图。
图1A示出了根据本公开实施例的显示基板的示意图。图1B示出了图1A的显示基板的显示区的示意图。
如图1A和图1B所示，显示基板包括衬底基板10，衬底基板10包括显示区11、位于显示区11至少一侧的邦定区12和位于显示区至少另一侧的侧边区13。在图1A中，邦定区12沿y方向位于显示区11的一侧，侧边区13沿x方向位于显示区11的两侧。显示区11中设有多个子像素Pix。多个子像素Pix可以布置成阵列的形式。在图1B中，x表示子像素阵列的行方向，y表示子像素阵列的列方向。显示区11还设有多条栅极线G1至GN以及多条数据线D1至DM，每条栅极线G1至GN与至少一行子像素Pix连接，以向该行子像素Pix提供栅极驱动信号，每条数据线D1至DM与至少一列子像素Pix连接以向该列子像素Pix提供数据信号。每个子像素Pix可以在与之连接的栅极线上的栅极驱动信号的控制下开启，开启的子像素Pix可以在与之连接的数据线上的数据信号的驱动下发光。
栅极驱动电路130位于侧边区13，在图1A中栅极驱动电路130有两个，分别位于显示区11两侧的侧边区13。栅极驱动电路130与所述多个子像素Pix连接。在图1A和图1B中，栅极驱动电路130通过多条栅极线G1至GN连接至多行子像素Pix，以分别向各行子像素Pix提供栅极驱动信号。如图1A所示，栅极驱动电路130还连接各种驱动控制信号线，例如用于提供第一时钟信号的第一时钟信号线CK1、用于提供第二时钟信号的第二时钟信号线CK2以及用于提供启动信号的启动信号线STV。栅极驱动电路130可以包括多级级联的移位寄存器GOA0至GOAN，各级移位寄存器GOA0至GOAN连接相应的驱动控制信号线，以在驱动控制信号的控制下产生栅极驱动信号并提供至显示区11的子像素Pix。
多个输入接触垫P1和多个输出接触垫P2位于邦定区12，所述多个输出接触垫P2位于所述多个输入接触垫P1与显示区11之间。在图1A中，所述多个输入接触垫P1沿第一方向排列成至少第一行，所述第一方向为所述显示区11的面向所述邦定区12的侧边的延伸方向，即x方向。所述多个输出接触垫P2沿第一方向排列成至少第二行。
所述多个输入接触垫P1用于与外部电路电连接，所述多个输出接触垫P2与显示区11中的子像素Pix和栅极驱动电路130电连接。例如多个输入接触垫P1可以通过多条第一引线W1分别连接至区域1220中用于连接柔性电路板的多个连接接触垫。多个输出接触垫P2可以通过多条第二引线W2分别连接至显示区11中的子像素Pix和栅极驱动 电路13。例如图1A中左右两侧的多个输出接触垫P2分别通过多条第二引线W2连接至第一时钟信号线CK1、第二时钟信号线CK2和启动信号线STV，从而连接至栅极驱动电路13；图1A中位于中间的多个输出接触垫P2分别通过多条第二引线W2连接至显示区11中的数据线D1至DM，从而连接至显示区11中的子像素Pix。在一些实施例中，邦定区12中可以设置例如单元测试(CT，Cell Test)电路、静电防护(ESD，Electro-Static Discharge)电路、多路复用电路等结构。例如单元测试电路可以设置在多个输出接触垫P2与显示区11之间的区域中，单元测试电路可以连接至多条测试信号线和显示区中的多个子像素。例如多路复用电路可以设置在单元测试电路与所述多个输出接触垫P2之间的区域，多路复用电路可以与至少一个输出接触垫P2以及显示区的数据线链接，以将输出接触垫P2提供的数据信号进行多路复用之后提供至显示区的数据线。当然本公开的实施例不限于此。在一些实施例中，单元测试电路、静电防护电路、多路复用电路以及其他辅助电路中的至少之一可以设置在输入接触垫P1与输出接触垫P2之间的区域中，在另一些实施例中可以位于输出接触垫P2与以下描述的第一虚拟接触垫P3之间的区域中。
在将控制芯片连接到显示基板时，输入接触垫P1与控制芯片的输入引脚连接，输出接触垫P2与控制芯片的输出引脚连接。柔性电路板提供的信号(例如但不限于电源信号、控制信号等)通过输入接触垫P1提供给控制芯片，使得控制芯片产生驱动信号(例如但不限于时钟信号、启动信号、数据信号等等)。控制芯片产生的驱动信号通过输出接触垫P2提供至显示区11的子像素Pix和/或栅极驱动电路，例如控制芯片产生的数据信号通过位于中间部分的输出接触垫P2提供至数据线D1至DM，从而提供给显示区11中的子像素；控制芯片产生的第一时钟信号、第二时钟信号和启动信号STV分别通过位于两侧的输出接触垫P2提供给第一时钟信号线CK1、第二时钟信号线CK2和启动信号线STV，从而提供给栅极驱动电路130。
在邦定区12中，位于所述多个输入接触垫P1与所述多个输出接触垫P2之间的区域1210中的接触垫绝缘层被至少部分地去除，从而缓解由于该区域1210中的接触垫绝缘层而导致的与控制芯片接触不良。下面将参考图2至图15C来对此进行详细说明。
图2示出了根据本公开实施例的显示基板的邦定区的局部平面图，图3示出了图2的邦定区沿A1-B1的截面的示意图。需要说明的是，图2为了便于描述仅示出了图1A的邦定区的一侧部分(图2中为左侧部分)，邦定区的另一侧部分可以具有类似结构，例如相对于左侧部分而对称的结构。另外需要说明的是，图3的截面图仅仅是为了说明 接触垫绝缘层的第一部分和第二部分的位置关系以及厚度的区别，邦定区的层结构的更多细节将在下文进一步详细说明。
如图2和图3所示，在邦定区12中，接触垫绝缘层1230位于所述多个输入接触垫P1中相邻输入接触垫P1之间的间隙、所述多个输出接触垫P2中相邻输出接触垫P2之间的间隙、以及所述多个输入接触垫P1与所述多个输出接触垫P2之间的区域。输入接触垫P1和输出接触垫P2的背离衬底基板10的表面从接触垫绝缘层1230外露。根据本公开的实施例，接触垫绝缘层1230包括具有第一厚度的第一部分1230A和具有第二厚度的第二部分1230B，第二厚度小于第一厚度。输入接触垫P1和输出接触垫P2的边缘被接触垫绝缘层1230的第一部分1230A覆盖，接触垫绝缘层1230的第二部分1230B位于所述多个输入接触垫P1与所述多个输出接触垫P1之间的区域中。如图2所示，输入接触垫P1在衬底基板10上的投影与接触垫绝缘层1230的第二部分1230B在衬底基板10的投影之间存在间距d1，输出接触垫P2在衬底基板10上的投影与接触垫绝缘层1230的第二部分1230B在衬底基板10的投影之间存在间距d2，d1和d2可以在3微米至100微米的范围内。在一些实施例中，d1可以等于d2。
图4A示出了图2的显示基板的一个示例在邦定区沿A2-B2的截面图。
如图4A所示，输出接触垫P2包括第一引线连接部1241、第一导体部1242和第二导体部1243。第一引线连接部1241位于衬底基板10上。参考图1A，输出接触垫P2的第一引线连接部1241可以连接至邦定区的第二引线W2，从而与栅极驱动电路130或者与显示区11中的多个子像素中的至少一个电连接。
第一导体部1242位于所述第一引线连接部1241背离衬底基板10的一侧，并且与第一引线连接部1241电连接。第二导体部1243位于第一导体部1242背离衬底基板10的一侧，并且与第一导体部1242电连接。
显示基板的邦定区还设置有邦定区第一栅绝缘层1251、邦定区第二栅绝缘层1252、邦定区层间绝缘层1253和邦定区钝化层1254。邦定区第一栅绝缘层1251覆盖衬底基板10，第一引线连接部1241位于邦定区第一栅绝缘层1251背离衬底基板10的一侧。邦定区第二栅绝缘层1252位于邦定区第一栅绝缘层1251背离衬底基板10的一侧并且覆盖第一引线连接部1241。邦定区层间绝缘层1253位于邦定区第二栅绝缘层1252背离衬底基板10的一侧。邦定区钝化层1254位于邦定区层间绝缘层1253背离衬底基板10的一侧并且覆盖第一导体部1242。
如图4A中的虚线框所示，第一导体部1242通过设置在邦定区第二栅绝缘层1252 中的过孔和设置在邦定区层间绝缘层1253中的过孔与第一引线连接部1241电连接，第二导体部1243通过设置在邦定区钝化层1254中的过孔与第一导体部1242电连接。在图4A中，邦定区第二栅绝缘层1252、邦定区层间绝缘层1253和邦定区钝化层1254中均设置有多个过孔，例如3个。然而本公开的实施例不限于此，在本公开的其它示例中，过孔的数量也可以根据需要来设置，例如，2个或4个。
如图4A所示，输出接触垫P2的第二导体部1243的边缘被接触垫绝缘层1230的厚度为H1的第一部分1230A覆盖，接触垫绝缘层1230的厚度为H2的第二部分1230B位于输入接触垫P1与输出接触垫P1之间的区域中，其中H2小于H1。这里所谓厚度可以指的是接触垫绝缘层1230面相衬底基板10一侧的表面到背离衬底基板10一侧表面的距离。通过使厚度H2小于厚度H1，可以使接触垫绝缘层1230的第二部分1230B背离衬底基板10一侧的表面低于接触垫绝缘层1230的第一部分1230A背离衬底基板10一侧的表面，从而缓解接触垫绝缘层1230对于输出接触垫P2与控制芯片的引脚之间的连接可靠性的影响，同时厚度较大的第一部分1230A能够实现对输出接触垫P2的边缘进行包封，从而起到保护作用。
图4B示出了图2的显示基板的一个示例在邦定区沿A3-B3的截面图。
如图4B所示，输入接触垫P1的结构与输出接触垫P2可以基本相同，输出接触垫P2同样包括第一引线连接部1241、第一导体部1242和第二导体部1243，第一导体部1242通过邦定区第二栅绝缘层1252中的过孔和邦定区层间绝缘层1253中的过孔与第一引线连接部1241电连接，第二导体部1243通过邦定区钝化层1254中的过孔与第一导体部1242电连接。参考图1A，输入接触垫P1的第一引线连接部1241可以连接至邦定区12中的第一引线W1，从而与区域1220中用于连接到外部电路的连接接触垫电连接。
在一些实施例中，接触垫绝缘层1230的材料可以包括氧化硅、氮化硅、氮氧化硅等无机绝缘材料，或者可以包括聚酰亚胺、聚酞亚胺、聚酞胺、丙烯酸树脂、苯并环丁烯或酚醛树脂等有机绝缘材料。本公开的实施例对接触垫绝缘层的材料不做具体限定。第一导体部1242和第二导体部1243的材料可以包括金属材料或者合金材料，例如由钼、铝及钛等形成的金属单层或多层结构。
图4C示出了图2的显示基板的一个示例在邦定区沿A4-B4的截面图。
本公开实施例的衬底基板10可以包括有机材料，例如聚酰亚胺、聚碳酸酯、聚丙烯酸酯、聚醚酰亚胺、聚醚砜、聚对苯二甲酸乙二醇酯和聚萘二甲酸乙二醇酯等树脂类材料中的一种或多种，衬底基板10可以为柔性基板或非柔性基板。在图4C中衬底基板 10为柔性基板，衬底基板10可以包括第一柔性层1010、第二柔性层1020、第一衬底阻挡层1030、第二衬底阻挡层1040和缓冲层1050。第二柔性层1020位于第一柔性层1010面向所述多个输入接触垫P1和所述多个输出接触垫P2的一侧。第一衬底阻挡层1030位于所述第一柔性层1020和第二柔性层1020之间。第二衬底阻挡层1040，位于第二柔性层1020背离第一柔性层1010的一侧。缓冲层1050，位于第二衬底阻挡层1040背离第一柔性层1010的一侧。例如，缓冲层1050的材料可以包括氧化硅、氮化硅、氮氧化硅等绝缘材料。缓冲层1050即可以防止衬底基板10中的有害物质侵入显示基板的内部，又可以增加显示基板中的膜层在衬底基板10上的附着力。
缓冲层1050背离第一柔性层1010一侧的表面上依次堆叠邦定区第一栅绝缘层1251、邦定区第二栅绝缘层1252、邦定区层间绝缘层1253、邦定区钝化层1254和接触垫绝缘层1230。接触垫绝缘层1230包括具有第一厚度的第一部分1230A和具有第二厚度的第二部分1230B，第二厚度小于第一厚度。输入接触垫P1和输出接触垫P2的边缘被接触垫绝缘层1230的第一部分1230A覆盖，接触垫绝缘层1230的第二部分1230B位于所述多个输入接触垫P1与所述多个输出接触垫P1之间的区域中。
图5示出了根据本公开一实施例的显示基板的显示区的截面图。
如图5所示，显示区中的子像素可以包括像素驱动电路1120、第一平坦化层1130、第一转接电极1180、第二平坦化层1190以及发光元件1140。
像素驱动电路1120包括位于衬底基板10上的有源层1122、位于有源层1122远离衬底基板1000一侧的显示区第一栅绝缘层1128、位于显示区第一栅绝缘层1128上的栅极11211，位于栅极11211远离衬底基板10一侧的显示区第二栅绝缘层1129，位于显示区第二栅绝缘层1129上的显示区层间绝缘层11210以及位于显示区层间绝缘层11210上的源极1125及漏极1126。栅极11211可以与邦定区12中的第一引线连接部1241同层设置。源极1125及漏极1126可以与邦定区12中的第一导体部1242同层设置。因此，栅极11211和第一引线连接部1241可以在制备工艺中同层形成，例如采用同一材料层通过构图工艺形成。源极1125及漏极1126与邦定区12中的第一导体部1242可以在制备工艺中同层形成，例如采用同一材料层通过构图工艺形成。显示区中的显示区第一栅绝缘层1128与邦定区中的邦定区第一栅绝缘层1251同层设置，显示区中的显示区第二栅绝缘层1129与邦定区中的邦定区第二栅绝缘层1252同层设置，显示区中的显示区层间绝缘层11211与邦定区层间绝缘层1253同层设置。
在本公开上述实施例一些示例中，有源层1122可以包括源极区1123和漏极区1124， 以及包括位于源极区1123和漏极区1124之间的沟道区。显示区层间绝缘层11210、显示区第二栅绝缘层1129及显示区第一栅绝缘层1128具有过孔，以暴露源极区1123和漏极区1124。源极1125及漏极1126分别通过过孔与源极区1123和漏极区1124电连接。栅极11211在垂直于衬底基板1000的方向上与有源层1122中位于源极区1123和漏极区1124之间的沟道区重叠。第一平坦化层1130位于源极1125及漏极1126的上方，用于平坦化像素驱动电路1120远离衬底基板一侧的表面。第一平坦化层1130中形成过孔1131，以暴露源极1125或漏极1126(图中示出的情况)。在像素驱动电路1120和第一平坦化层1130之间形成显示区钝化层11110且显示区钝化层11110包括过孔11111。显示区钝化层11110可以保护像素驱动电路的源极和漏极不被水汽腐蚀。显示区的邦定区钝化层1254可以与显示区钝化层11110同层设置。因此显示区的邦定区钝化层1254与显示区钝化层11110可以在制备工艺中同层形成，例如采用同一材料层通过构图工艺形成。
第一平坦化层1130上形成第一转接电极1180。第一转接电极1180通过过孔1131以及过孔11111与漏极1126电连接，该第一转接电极1180可以避免直接在第一平坦化层1130和第二平坦化层1190中形成孔径过大的直通过孔，从而改善过孔电连接的质量，同时第一转接电极1180还可以与其他信号线(例如电源线等)等同层形成，由此不会导致工艺步骤增加。第一转接电极1180与接触垫1210的第二导体部1243同层设置，因此，第一转接电极1180与第二导体部1243可以在制备工艺中同层形成，例如采用同一材料层通过构图工艺形成，从而简化制备工艺。
例如，第一转接电极1180的材料可以包括金属材料或者合金材料，例如钼、铝及钛等形成的金属单层或多层结构。
例如，有源层1122的材料可以包括多晶硅或氧化物半导体(例如，氧化铟镓锌)。栅极11211的材料可以包括金属材料或者合金材料，例如钼、铝及钛等形成的金属单层或多层结构，例如，该多层结构为多金属层叠层(如钛、铝及钛三层金属叠层(Ti/Al/Ti)。源极1125及漏极1126的材料可以包括金属材料或者合金材料，例如由钼、铝及钛等形成的金属单层或多层结构，例如，该多层结构为多金属层叠层(如钛、铝及钛三层金属叠层(Ti/Al/Ti)。本公开的实施例对各功能层的材料不做具体限定。
例如，显示区钝化层11110的材料可以包括有机绝缘材料或无机绝缘材料，例如，氮化硅材料，由于其具有较高的介电常数且具有很好的疏水功能，能够很好的保护像素驱动电路不被水汽腐蚀。
在本公开的一些示例中，如图5所示，像素驱动电路1120还可以包括第一显示金 属层1127，第一显示区金属层1127与第一导体部1242同层设置。第一显示金属层1127包括像素驱动电路中上述薄膜晶体管的源极1125和漏极1126。源极1125和漏极1126与第一导体部1242同层设置。
在本公开的一些示例中，如图5所示，第二平坦化层1190设置在第一转接电极1180远离衬底基板10的一侧，用以在第一转接电极1180远离衬底基板10一侧提供平坦化表面。在第二平坦化层1190中形成过孔1191。第二平坦化层1190与邦定区1200中的接触垫绝缘层1230同层形成，因此第二平坦化层1190与接触垫绝缘层1230可以在制备工艺中同层形成，例如采用同一材料层通过构图工艺形成，从而简化制备工艺。
例如，在第二平坦化层上形成发光元件1140，即发光元件1140设置在第二平坦化层1190远离衬底基板一侧。发光元件1140包括第一电极1141、发光层1142及第二电极1143。发光元件的第一电极1141通过第二平坦化层1140中的第二过孔1191与第一转接电极1180电连接。第一电极1141上形成像素限定层1144，像素限定层1144包括多个开口，以限定多个像素单元。多个开口的每个暴露对应的第一电极1141；之后，发光层1142设置在像素限定层1144的多个开口中，第二电极1143设置在像素限定层1144以及发光层1142上，例如该第二电极1143可以设置在部分或整个显示区域中，从而在制备工艺中可以整面形成。
例如，第二平坦化层1190的材料可以包括括氧化硅、氮化硅、氮氧化硅等无机绝缘材料，也可以包括聚酰亚胺、聚酞亚胺、聚酞胺、丙烯酸树脂、苯并环丁烯或酚醛树脂等有机绝缘材料，本公开的实施例对此不做限定。
例如，第一电极1141可以包括反射层，第二电极1143可以包括透明层或半透明层。由此，第一电极1141可以反射从发光层1142发射的光，该部分光通过第二电极1143发射到外界环境中，从而可以提供光出射率。当第二电极1143包括半透射层时，由第一电极1141反射的一些光通过第二电极1143再次反射，因此第一电极1141和第二电极1143形成共振结构，从而可以改善光出射效率。
例如，第一电极1141的材料可以包括至少一种透明导电氧化物材料，包括氧化铟锡(ITO)、氧化铟锌(IZO)、氧化锌(ZnO)等。此外，第一电极1141可以包括具有高反射率的金属作为反射层，诸如银(Ag)。
例如，对于OLED，发光层1142可以包括小分子有机材料或聚合物分子有机材料，可以为荧光发光材料或磷光发光材料，可以发红光、绿光、蓝光，或可以发白光；并且，根据需要发光层还可以进一步包括电子注入层、电子传输层、空穴注入层、空穴传输层 等功能层。对于QLED，发光层可以包括量子点材料，例如，硅量子点、锗量子点、硫化镉量子点、硒化镉量子点、碲化镉量子点、硒化锌量子点、硫化铅量子点、硒化铅量子点、磷化铟量子点和砷化铟量子点等，量子点的粒径为2-20nm。
例如，第二电极1143可以包括各种导电材料。例如，第二电极1143可以包括锂(Li)、铝(Al)、镁(Mg)、银(Ag)等金属材料。
例如，像素限定层1144的材料可以包括聚酰亚胺、聚酞亚胺、聚酞胺、丙烯酸树脂、苯并环丁烯或酚醛树脂等有机绝缘材料，或者包括氧化硅、氮化硅等无机绝缘材料，本公开的实施例对此不做限定。
此外，显示基板还包括存储电容器1160，存储电容器1160可以包括第一极1161和第二极1162。存储电容器1160的第一极1161设置在显示区第一栅绝缘层1128与显示区第二栅绝缘层1129之间，存储电容器1160的第二极1162设置在显示区第二栅绝缘层1129与显示区层间绝缘层11210之间。第一极1161和第二极1162叠置，在垂直于衬底基板10的方向上至少部分重叠。第一极1161和第二极1162使用显示区第二栅绝缘层1129作为介电材料来形成存储电容器。第一极1161与像素驱动电路1120中的栅极11211、邦定区1200中的引线1220同层设置。同样地，如上所述，在上述示例的变型中，存储电容器1160的第一极和第二极还可以位于其他层中，从而得到不同结构的子像素。
在另一示例中，作为图5所示示例的变型，存储电容器的第一极仍然与栅极11211同层设置，而存储电容器的第二极与薄膜晶体管中的源极1125和漏极1126同层设置(即也位于第一显示金属层1127中)，由此存储电容器的第一极和第二极使用显示区第二栅绝缘层1129以及显示区层间绝缘层11210的叠层来作为介电材料来形成存储电容器。
在再一示例中，作为图5所示示例的变型，存储电容器的第一极不再与栅极11211同层设置，而是位于在显示区第二栅绝缘层1129与显示区层间绝缘层11210之间，而存储电容器的第二极与薄膜晶体管中的源极1125和漏极1126同层设置(即也位于第一显示金属层1127中)，由此存储电容器的第一极和第二极使用显示区层间绝缘层11210来作为介电材料来形成存储电容器。
在本公开的一些示例中，如图5所示，显示基板还可以包括设置在发光元件1140上的封装层1150。封装层1150将发光元件1140密封，从而可以减少或防止由环境中包括的湿气和/或氧引起的发光元件1140的劣化。封装层1150可以为单层结构，也可以为复合层结构，该复合层结构包括无机层和有机层堆叠的结构，例如，封装层1150可以包括依次设置的第一无机封装层1151、第一有机封装层1152、第二无机封装层1153。 封装层1150可以延伸至邦定区，在上述示例中，该封装层未覆盖接触垫。
例如，该封装层的材料可以包括氮化硅、氧化硅、氮氧化硅、高分子树脂等绝缘材料。氮化硅、氧化硅、氮氧化硅等无机材料的致密性高，可以防止水、氧等的侵入；有机封装层的材料可以为含有干燥剂的高分子材料或可阻挡水汽的高分子材料等，例如高分子树脂等以对显示基板的表面进行平坦化处理，并且可以缓解第一无机封装层和第二无机封装层的应力，还可以包括干燥剂等吸水性材料以吸收侵入内部的水、氧等物质。
图6A和图6B分别示出了图2的显示基板的另一个示例沿A2-B2和沿A3-B3的截面图。图6A和图6B的邦定区域图4A和图4B相比区别至少在于输入接触垫P1和输出接触垫P2还包括第三导体部，为了简明起见，下面将主要对区别部分进行详细说明。
如图6A所示，输出接触垫P2除了包括上述第一引线连接部1241、第一导体部1242和第二导体部1243之外还包括第三导体部1244。显示基板还包括邦定区阻挡层1255和邦定区无机层1256。第三导体部1244位于所述第二导体部1243背离衬底基板10的一侧，邦定区阻挡层1255和邦定区无机层1256位于第三导体部1244与第二导体部1243之间。邦定区阻挡层1255覆盖第二导体层1243和接触垫绝缘层1230的第一部分1230A，邦定区无机层1256覆盖邦定区阻挡层1255。第三导体部1244通过设置在邦定区阻挡层1255中的过孔和设置在邦定区无机层1256中的过孔(如图6A中的虚线框所示)与第二导体部1243电连接。
如图6B所示，输入接触垫P1具有与输出接触垫P2基本相同的结构，这里不再赘述。
图7A和图7B分别示出了图2的显示基板的又一个示例沿A2-B2和沿A3-B3的截面图。图7A和图7B的邦定区域图6A和图6B相比区别至少接触垫绝缘层的第二部分被去除，即，第二厚度为0。如图7A和7B所示，接触垫绝缘层1230’的第二部分1230B的厚度为0，即接触垫绝缘层1230’的第二部分1230B被去除，而保留第一部分1230A。邦定区钝化层1254位于第二部分1230B与邦定区第二栅绝缘层1254之间的部分厚度大于0，即被至少部分保留。
图8A和图8B分别示出了图2的显示基板的再一个示例沿A2-B2和沿A3-B3的截面图。图8A和图8B的邦定区域图7A和图7B相比区别至少钝化层也被部分地去除。如图8A和8B所示，接触垫绝缘层1230’的第二部分1230B及其下方的邦定区钝化层1254部分均被去除，使得第二部分1230B厚度为0，且邦定区钝化层1254位于接触垫绝缘层1230’的第二部分1230B与邦定区第二栅绝缘层1254之间的部分厚度也为0。
图9示出了根据本公开另一实施例的显示基板的显示区的截面图。图9的显示区结构与图5相比区别至少在于显示基板还包括显示区阻挡层、第一触控电极层、第二触控电极层和触控绝缘层，为了简明起见，下面将主要对区别部分进行详细说明。
如图9所示，封装层1150位于发光元件1140的远离衬底基板10的一侧，显示区阻挡层1171位于封装层1150的远离衬底基板10的一侧，第一触控电极层1172位于显示区阻挡层1171背离衬底基板10的一侧，触控绝缘层1174位于第一触控电极层1172背离衬底基板10的一侧并且覆盖第一触控电极层1172，第二触控电极层1173位于触控绝缘层1174背离衬底基板10的一侧。在图9中，第二触控电极层1173通过触控绝缘层1174中的过孔与第一触控电极层1172电连接，当然本公开实施例不限于此，第一触控电极层1172和第二触控电极层1173可以根据需要而设置成其他图案。第一触控电极层1172和第二触控电极层1173可以用于实现电容型触控结构，该电容型触控结构为自电容型或互电容型。
上述位于邦定区的第三导体部1244可以与显示区的第二触控电极层1173同层设置，上述位于邦定区的邦定区阻挡层1255可以与显示区的显示区阻挡层1171同层设置，上述位于邦定区的邦定区无机层1256可以与显示区的触控绝缘层1174同层设置。
图10示出了根据本公开另一实施例的显示基板的邦定区的局部平面图。图11示出了图10的邦定区沿C1-D1的截面的示意图。图10和图11的显示基板与图2和图3的显示基板相比区别至少在于邦定区12还设置有多个第一虚拟接触垫P3，为了简明起见，下面将主要对区别部分进行详细说明。
如图10和图11所示，显示基板还包括多个第一虚拟接触垫P3，所述多个第一虚拟接触垫P3位于邦定区12，且位于多个输入接触垫P1与多个输出接触垫P2之间的区域中。第一虚拟接触垫P3可以不连接引线，其可以在控制芯片邦定到显示基板的邦定区时，第一虚拟接触垫P3与控制芯片上的对应引脚对接，从而起到支撑作用。第一虚拟接触垫P3的边缘被所述接触垫绝缘层1230的第一部分1230A覆盖，第一虚拟接触垫P3的背离衬底基板10的表面从接触垫绝缘层1230的第一部分1230A外露。接触垫绝缘层1230第二部分1230B包括第一子部分1230B1和第二子部分1230B2，第一子部分1230B1位于所述多个第一虚拟接触垫P3与所述多个输入接触垫P1之间的区域，所述第二子部分1230B2位于所述多个第一虚拟接触垫P3与所述多个输出接触垫P2之间的区域。
图12A示出了图10的显示基板的一个示例沿C2-D2的截面图。
如图12A所示，第一虚拟接触垫P3包括第四导体部1245。衬底基板10上依次叠置 邦定区第一栅绝缘层1251、邦定区第二栅绝缘层1252、邦定区层间绝缘层1253和邦定区钝化层1254。第四导体部1245位于邦定区钝化层1254背离衬底基板10的一侧，即位于衬底基板10面向所述多个输入接触垫P1和所述多个输出接触垫P2的一侧。接触垫绝缘层1230的第一部分1230A覆盖第四导体部1245的边缘，接触垫绝缘层1230的第二部分1230B包括第一子部分1230B1和第二子部分1230B2，其厚度小于第一部分1230A的厚度。第四导体部1245可以与上述的第二导体部1243同层设置，例如第四导体部1245和第二导体部1243可以均与显示区的第一转接电极1180同层设置。
图12B示出了图11的显示基板的另一个示例沿C2-D2的截面图。图12B的显示基板与图12A的显示基板相比区别至少在于接触垫绝缘层的第二部分和邦定区钝化层的一部分被去除。如图12B所示，接触垫绝缘层1230’的第二部分1230B及其下方的邦定区第一栅绝缘层1251的一部分被去除，即，二者厚度均为0。
图12C示出了图11的邦定区的又一个示例在邦定区沿C2-D2的截面图。图12C的显示基板与图12A的显示基板相比区别至少在于第一虚拟接触垫P3除了包括第四导体部1245’之外还包括第五导体部1246，第五导体部1246位于第四导体部1245与衬底基板10之间。
在图12C中，衬底基板10上依次叠置邦定区第一栅绝缘层1251、邦定区第二栅绝缘层1252和邦定区层间绝缘层1253。第五导体部1246位于邦定区层间绝缘层1253背离衬底基板10的一侧。邦定区钝化层1254位于邦定区层间绝缘层1253背离衬底基板10的一侧并且覆盖第五导体部1246的边缘。第四导体部1245’位于第五导体部1246背离衬基板10的一侧，第四导体部的边缘被所述接触垫绝缘层的第一部分覆盖。第五导体部1246通过邦定区钝化层1254中的过孔与第四导体部1245电连接。第四导体部1245’可以与上述第二导体部1243同层设置，第五导体部1246可以与上述的第一导体部1242同层设置。例如第四导体部1245’可以与上述第二导体部1243和显示区的第一转接电极1180同层设置，第五导体部1246可以与上述第一导体部1242和显示区的第一显示金属层1127同层设置。
图13示出了根据本公开又一实施例的显示基板的邦定区的局部平面图，图14示出了图13的显示基板沿E1-F1的截面的示意图。与图2和图10的单侧示意不同，图13的平面图示出了显示基板的邦定区沿x方向的左右两侧部分。图13和图14的显示基板与图10和图11的显示基板相比区别至少在于邦定区12还设置有多个阵列测试接触垫P4和多个第二虚拟接触垫P5，为了简明起见，下面将主要对区别部分进行详细说明。
如图13和图14所示，显示基板的邦定区还设置有还多个阵列测试接触垫P4，多个阵列测试接触垫P4位于所述多个第一虚拟接触垫P1与所述多个输入接触垫P2之间的区域中。多个阵列测试接触垫P4用于在显示基板制作过程中的阵列测试。阵列测试接触垫P4可以与所述多个子像素。例如阵列测试接触垫P4中的至少一个可以通过邦定区的引线连接到显示区的子像素，例如通过引线连接到多路复用电路，以经由多路复用电路连接到显示区的多条数据信号线，从而实现与子像素的电连接。
如图13和图14所示，接触垫绝缘层1230的第一部分1230A包括第一子部分1230A1和第二子部分1230A2。所述多个输入接触垫P1的边缘、所述多个输出接触垫P2的边缘和所述第一虚拟接触垫P3的边缘被所述接触垫绝缘层1230的第一部分1230A的第一子部分1230A1覆盖。多个阵列测试接触垫P4的边缘被所述接触垫绝缘层1230的第一部分1230A的第二子部分1230A2覆盖，所述多个阵列测试接触垫P4的背离衬底基板10的表面从所述接触垫绝缘层1230的第一部分1230A的第二子部分1230A1外露。在一些实施例中，如图13所示，接触垫绝缘层1230的第一部分1230A的第二子部分1230A2在衬底基板10上的投影位于所述接触垫绝缘层1230的第二部分1230B的第一子部分1230B1在衬底基板10的投影之内。接触垫绝缘层1230的这种设置使得可以在提高接触垫连接稳固性的同时，实现对输入接触垫P1、输出接触垫P2、第一虚拟接触垫P3和阵列测试接触垫P4的边缘的保护，避免后续的构图工艺中的刻蚀液刻蚀裸露的接触垫的边缘，进而提高显示基板的产品良率和可靠性。
在上述实施例中，多个输入接触垫P1沿第一方向排列成第一行，所述第一方向为显示区的面向邦定区的侧边的延伸方向(x方向)；多个输出接触垫P2沿第一方向排列成第二行；多个第一虚拟接触垫沿第一方向排列成第三行；所述多个阵列测试接触垫沿第一方向排列成第四行。当然本公开的实施例不限于此，输入接触垫P1、输出接触垫P2、第一虚拟接触垫P3和阵列测试接触垫P4中的任意一者可以根据需要呈多行排列或者以其他形式排列。
在一些实施例中，如图13所示，显示基板的邦定区还可以设置有多个第二虚拟接触垫P5。第二虚拟接触垫P5可以具有与第一虚拟接触垫P4相似的结构，可以同样起到支撑作用。多个第二虚拟接触垫P5沿垂直于所述第一方向的第二方向(y方向)排列成第一列和第二列，其中第一列和第二列分别位于所述多个第一虚拟接触垫P1在第一方向上的两侧。当然本公开的实施例不限于此，多个第二虚拟接触垫P5可以根据需要呈多列排列或者以其他形式排列，也可以位于多个第一虚拟接触垫P1的一侧(例如左 侧或右侧)。
在图13中，多个第二虚拟接触垫P5的边缘被接触垫绝缘层1230的第一部分1230A覆盖，所述多个第二虚拟接触垫P5的背离衬底基板10的表面从所述接触垫绝缘层1230的第一部分1230A外露。在一些实施例中，如图13所示，输入接触垫P1、输出接触垫P2、第一虚拟接触垫P3、阵列测试接触垫P4和第二虚拟接触垫P5各自在衬底基板10上的投影与接触垫绝缘层1230的第二部分1230B在衬底基板10的投影之间均具有一定的间距，该间距可以在3微米至100微米的范围内。输入接触垫P1、输出接触垫P2、第一虚拟接触垫P3、阵列测试接触垫P4和第二虚拟接触垫P5各自与接触垫绝缘层1230的第二部分1230B的间距可以相同或不同。例如输入接触垫P1、输出接触垫P2和第二虚拟接触垫P5与接触垫绝缘层1230的第二部分1230B的间距可以相等，但是大于第一虚拟接触垫P3和阵列测试接触垫P4与接触垫绝缘层1230的第二部分1230B的间距。
在上述实施例中，输入接触垫P1、输出接触垫P2、第一虚拟接触垫P3、阵列测试接触垫P4和第二虚拟接触垫P5各自在衬底基板10上的投影被示出为具有特定的形状，例如输入接触垫P1和输出接触垫P2在衬底基板10上的投影为平行四边形，阵列测试接触垫P4和第二虚拟接触垫P5在衬底基板10上的投影为矩形，第一虚拟接触垫P3在衬底基板10上的投影基本上为正方形。在图13中，输入接触垫P1、输出接触垫P2、第一虚拟接触垫P3、阵列测试接触垫P4和第二虚拟接触垫P5各自均沿着显示基板在y方向上的对称轴Y而对称设置。然而本公开的实施例不限于此，各个接触垫的形状和排列方式可以根据需要来设置。
图15A示出了图13的显示基板的一个示例沿E2-F2的截面图。
如图15A所示，阵列测试接触垫P5具有类似于图4A的输出接触垫和图4B的输入接触垫的结构。阵列测试接触垫P5包括第二引线连接部1247、第六导体部1248和第七导体部1249。第二引线连接部1247、所述第六导体部1248和所述第七导体部1249可以分别与所述第一引线连接部1241、所述第一导体部1242和所述第二导体部1243同层设置。
第二引线连接部1247位于衬底基板10面向所述多个输入接触垫P1和所述多个输出接触垫P2的一侧，用于与引线连接，所述引线连接到数据线，从而实现第二引线连接部1247与显示区的子像素的电连接。第六导体部1248位于第二引线连接部1247背离所述衬底基板10的一侧，与第二引线连接部1247电连接。第七导体部1249位于第六导体部1247背离所述衬底基板10的一侧，与所述第六导体部1248电连接。
第二虚拟接触垫P5可以具有与上述第一虚拟接触垫P4相似的结构，下面将参考图15B至图15D来进行说明。
图15B示出了图13的显示基板的一个示例沿E3-F3的截面图。如图15B所示，第二虚拟接触垫P5具有与图12A的第一虚拟接触垫P4类似的结构，第二虚拟接触垫P5包括第八导体部12410，第八导体部12410位于衬底基板面10向所述多个输入接触垫P1和所述多个输出接触垫P2的一侧。第八导体部12410可以与上述第二导体部1243同层设置。第八导体部12410’的边缘被接触垫绝缘层1230的第一部分1230A覆盖，在图15D中接触垫绝缘层1230的第一部分1230A的第一子部分1230A1覆盖。
图15C示出了图13的显示基板的另一个示例沿E3-F3的截面图。图15C的显示基板与图15B的显示基板相比区别至少在于接触垫绝缘层1230的第二部分1230B和邦定区钝化层1241的一部分被去除。如图15C所示，接触垫绝缘层1230’的第二部分1230B及其下方的邦定区第一栅绝缘层1251的厚度均为0。
图15D示出了图13的显示基板的另一个示例沿E3-F3的截面图。如图15D所示，第二虚拟接触垫P5具有类似于图12C的第一虚拟接触垫P4的结构，第二虚拟接触垫P5除了包括第八导体部12410’之外还包括第九导体部12411，第九导体部12411位于第八导体部12410’与衬底基板10之间并且与第八导体部12410’电连接。第八导体部12410’可以与上述第二导体部1243同层设置，第九导体部可以与上述第一导体部1242同层设置。第八导体部12410’的边缘被接触垫绝缘层1230的第一部分1230A覆盖，在图15D中接触垫绝缘层1230的第一部分1230A的第一子部分1230A1覆盖。
虽然以上结合特定的接触垫结构说明了接触垫绝缘层的第二部分及其下方的邦定区钝化层被减薄或去除的实施例，然而本公开的实施例不限于此，接触垫绝缘层的第二部分及其下方的邦定区钝化层的减薄或去除适用于其他接触垫结构，例如在一些实施例中，图4A至图4C、图12C以及图15A和图15D中至少一个的接触垫绝缘层的第二部分和/或其下方的邦定区钝化层可以根据需要被减薄或去除。
图16A示出了根据本公开另一实施例的显示基板的显示区的截面图图16B示出了图16A的显示基板的邦定区的截面图。图16A和图16B的显示基板与前述实施例的显示基板区别至少不具有钝化层。
如图16A所示，显示基板的显示区具有类似于图9的显示区的结构，区别在于不具有显示区钝化层11110。如图16B所示，显示基板的邦定区具有类似于图7A和8A的邦定区的结构，区别在于不具有邦定区钝化层1245、1245’，第二导体部1243位于第一 导体部1242背离衬底基板10的一侧并且覆盖第一导体部1242，接触垫绝缘层1230’设置在邦定区层间绝缘层1253背离衬底基板10的一侧且覆盖第二导体部1243的边缘。
为了简明起见在图16B中仅示出了输出接触垫P2及其周围区域的邦定区结构，邦定区的其他部分可以与图4A至图4C、图6A至图8B、图12A至图12C以及图15A至图15D描述的结构类似，区别在于从这些结构中去除了邦定区钝化层。
本公开至少一个实施例提供一种显示装置，该显示装置可以包括上述任一实施例的显示基板。
例如，在一些示例中，显示装置还可以包括柔性电路板及控制芯片。例如，柔性电路板邦定到显示基板的邦定区，而控制芯片安装在柔性电路板上，由此与显示区电连接；或者，控制芯片直接邦定到邦定区，由此与显示区电连接。
例如，控制芯片可以为中央处理器、数字信号处理器、系统芯片(SoC)等。例如，控制芯片还可以包括存储器，还可以包括电源模块等，且通过另外设置的导线、信号线等实现供电以及信号输入输出功能。例如，控制芯片还可以包括硬件电路以及计算机可执行代码等。硬件电路可以包括常规的超大规模集成(VLSI)电路或者门阵列以及诸如逻辑芯片、晶体管之类的现有半导体或者其它分立的元件；硬件电路还可以包括现场可编程门阵列、可编程阵列逻辑、可编程逻辑设备等。
例如，本公开至少一个实施例提供的显示装置可以为手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
本公开至少一个实施例还提供一种显示基板的制备方法，该方法包括：提供衬底基板，所述衬底基板包括显示区、位于所述显示区至少一侧的邦定区和位于所述显示区至少另一侧的侧边区；在所述显示区中形成多个子像素；在所述侧边区形成栅极驱动电路，所述栅极驱动电路与所述多个子像素连接，并且被配置为向所述多个子像素提供栅极驱动信号；在所述邦定区形成用于与外部电路电连接的多个输入接触垫；在所述邦定区中形成多个输出接触垫，所述多个输出接触垫位于所述多个输入接触垫与所述显示区之间，所述多个输出接触垫与所述多个子像素和所述栅极驱动电路电连接；在所述邦定区形成接触垫绝缘层，所述接触垫绝缘层位于所述多个输入接触垫中相邻输入接触垫之间的间隙、所述多个输出接触垫中相邻输出接触垫之间的间隙、以及所述多个输入接触垫与所述多个输出接触垫之间的区域，所述多个输入接触垫和所述多个输出接触垫的背离所述衬底基板的表面从所述接触垫绝缘层外露，其中所述接触垫绝缘层包括具有第一厚度的第一部分和具有第二厚度的第二部分，所述第二厚度小于所述第一厚度，所述多个 输入接触垫和所述多个输出接触垫的边缘被所述接触垫绝缘层的第一部分覆盖，所述接触垫绝缘层的第二部分位于所述多个输入接触垫与所述多个输出接触垫之间的区域中。
下面结合图8A和图9的显示基板，参考图17A至图17G来说明本公开实施例的显示基板的制造过程。
如图17A所示，提供衬底基板10，该衬底基板10包括显示区和位于显示区周边的周边区，该周边区包括位于显示区至少一侧的至少一个邦定区和位于所述显示区至少另一侧的侧边区。在衬底基板10的显示区形成像素驱动电路1120、存储电容器1160、第一平坦化层1130和第一转接电极1180，在显示基板10的邦定区形成邦定区第一栅绝缘层1251、第一引线连接部1231、第二栅绝缘层1252、邦定区层间绝缘层1253、第一导体部1242、邦定区钝化层1254’和第二导体部1243。第二导体部1243覆盖第一导体部1242的边缘，以避免第一导体部1242被腐蚀。在该实施例中，第一导体部1242和第二导体部1243层叠。
如图17B所示，在衬底基板上沉积绝缘材料层1710，在绝缘材料层1710上沉积光刻胶1720。绝缘材料层1710可以包括氧化硅、氮化硅、氮氧化硅等绝缘材料。
如图17C所示，提供掩膜版1610对光刻胶1720进行曝光，掩膜版1610包括完全透光区、部分透光区及不透光区。掩膜版1610在邦定区包括与要形成接触垫绝缘层1230的第二部分1230B的区域重叠的第一透光图案1611及与输出接触垫P2重叠的第二透光图案1612。掩膜版1610在显示区包括与第二透光图案1612及非透光图案1613。第一透光图案1611位于部分透光区，第二透光图案1612位于完全透光区，非透光图案1613位于不透光区。即，掩膜版1610为灰色掩膜版或半色调掩膜版。光刻胶为正性光刻胶，对应地，第一透光图案1611的透光率小于第二透光图案1612的透光率。在曝光过程中，可以在使得光刻胶1720中与第二透光图案1612对应的部分被完全曝光的情况下，光刻胶1720中与第一透光图案1611对应的部分被部分曝光。光刻胶1720在显示区与非透光图案1613对应的部分未被曝光。
又例如，在上述构图工艺中，也可以采用负性光刻胶，那么所采用的掩模板例如是与上述掩模板1610互补的掩模板，由此在曝光、显影后得到上述光刻胶图案1721及光刻胶图案1722。
如图17D所示，对光刻胶1720进行显影，光刻胶1720的被完全曝光的部分去除，即，在邦定区中，与输出接触垫P2以及要设置接触垫绝缘层的第二部分1230B的区域重叠的光刻胶1720被去除，光刻胶1720的被部分曝光的部分被减薄，而光刻胶1720的 未被曝光的部分的厚度例如基本未改变。显影后，光刻胶1720在邦定区形成为光刻胶图案1721。同样地，在显示区中，与漏极1126重叠的光刻胶1720被去除。显影后，光刻胶1720在显示区形成为光刻胶图案1722。
如图17E所示，对邦定区及显示区中的绝缘材料层1710进行刻蚀以去除在邦定区域与输出接触垫P2和要设置接触垫绝缘层的第二部分1230B的区域重叠的绝缘材料层，以及在显示区形成第二过孔1191。
如图17F所示，进行灰化工艺去除邦定区的光刻胶图案1721和减薄显示区的光刻胶图案1722，这里显示区的光刻胶图案1722被保留。然后，利用当前的光刻胶图案，对邦定区中剩余的绝缘材料层1710进行刻蚀并控制刻蚀厚度以形成接触垫绝缘层1230，并且使得刻蚀后形成的接触垫绝缘层1230具有第一部分1230A以及厚度小于第一部分1230A的第二部分1230B，在图17F中第二部分1230B厚度为0，即该部分的绝缘材料被去除。这使得接触垫绝缘层的第二部分1230B相对于衬底基板10的表面的高度低于第一部分1230B相对于衬底基板1000的表面的高度。去除显示区的光刻胶图案1722。在显示区形成第二平坦化层1190以提供平坦化表面。在显示区的第二平坦化1190上形成发光元件1140。在显示区的发光元件1140上形成封装层1150。封装层1150将发光元件1140密封，从而可以减少或防止由环境中包括的湿气和/或氧引起的发光元件1140的劣化。
如图17G所示，在显示区的封装层1150上形成显示区阻挡层1171，在邦定区形成邦定区阻挡层1255。然后，在显示区的显示区阻挡层1171上形成第一触控电极层1172。在显示区的第一触控电极层1172上形成触控绝缘层1174，在邦定区的邦定区阻挡层1255上形成邦定区无机层1256。然后在显示区的触控绝缘层1174上形成第二触控电极层1173，在邦定区的邦定区无机层1256上形成第三导体部1244。
本领域的技术人员可以理解，上面所描述的实施例都是示例性的，并且本领域的技术人员可以对其进行改进，各种实施例中所描述的结构在不发生结构或者原理方面的冲突的情况下可以进行自由组合。
在详细说明本公开的较佳实施例之后，熟悉本领域的技术人员可清楚的了解，在不脱离随附权利要求的保护范围与精神下可进行各种变化与改变，且本公开亦不受限于说明书中所举示例性实施例的实施方式。

Claims (27)

  1. 一种显示基板，包括：
    衬底基板，包括显示区、位于所述显示区至少一侧的邦定区和位于所述显示区至少另一侧的侧边区；
    多个子像素，位于所述显示区中；
    栅极驱动电路，位于所述侧边区，所述栅极驱动电路与所述多个子像素连接，并且被配置为向所述多个子像素提供栅极驱动信号；
    多个输入接触垫，位于所述邦定区，用于与外部电路电连接；
    多个输出接触垫，位于所述邦定区，且位于所述多个输入接触垫与所述显示区之间，所述多个输出接触垫与所述多个子像素和所述栅极驱动电路电连接；
    接触垫绝缘层，位于所述邦定区，且位于所述多个输入接触垫中相邻输入接触垫之间的间隙、所述多个输出接触垫中相邻输出接触垫之间的间隙、以及所述多个输入接触垫与所述多个输出接触垫之间的区域，所述多个输入接触垫和所述多个输出接触垫的背离所述衬底基板的表面从所述接触垫绝缘层外露，其中所述接触垫绝缘层包括具有第一厚度的第一部分和具有第二厚度的第二部分，所述第二厚度小于所述第一厚度，所述多个输入接触垫和所述多个输出接触垫的边缘被所述接触垫绝缘层的第一部分覆盖，所述接触垫绝缘层的第二部分位于所述多个输入接触垫与所述多个输出接触垫之间的区域中。
  2. 根据权利要求书1所述的显示基板，还包括：多个第一虚拟接触垫，位于所述邦定区，且位于所述多个输入接触垫与所述多个输出接触垫之间的区域中，其中，
    所述多个第一虚拟接触垫的边缘被所述接触垫绝缘层的第一部分覆盖，所述多个第一虚拟接触垫的背离所述衬底基板的表面从所述接触垫绝缘层的第一部分外露；并且
    所述接触垫绝缘层的第二部分包括第一子部分和第二子部分，所述第一子部分位于所述多个第一虚拟接触垫与所述多个输入接触垫之间的区域，所述第二子部分位于所述多个第一虚拟接触垫与所述多个输出接触垫之间的区域。
  3. 根据权利要求书2所述的显示基板，还包括：多个阵列测试接触垫，位于所述邦定区，且位于所述多个第一虚拟接触垫与所述多个输入接触垫之间的区域中，所述多个阵列测试接触垫与所述多个子像素电连接，其中，
    所述接触垫绝缘层的第一部分包括第一子部分和第二子部分，所述多个输入接触 垫的边缘、所述多个输出接触垫的边缘和所述第一虚拟接触垫的边缘被所述接触垫绝缘层的第一部分的第一子部分覆盖，所述多个阵列测试接触垫的边缘被所述接触垫绝缘层的第一部分的第二子部分覆盖，所述多个阵列测试接触垫的背离所述衬底基板的表面从所述接触垫绝缘层的第一部分外露；并且
    所述接触垫绝缘层的第一部分的第二子部分在所述衬底基板上的投影位于所述接触垫绝缘层的第二部分的第一子部分在所述衬底基板的投影之内。
  4. 根据权利要求书1所述的显示基板，其中，所述多个输入接触垫和所述多个输出接触垫中的每一个在所述衬底基板上的投影与所述接触垫绝缘层的第二部分在所述衬底基板的投影之间的间距在3微米至100微米的范围内。
  5. 根据权利要求书1所述的显示基板，其中，所述第二厚度为0。
  6. 根据权利要求书3所述的显示基板，其中，
    所述多个输入接触垫沿第一方向排列成至少第一行，所述第一方向为所述显示区的面向所述邦定区的侧边的延伸方向；
    所述多个输出接触垫沿第一方向排列成至少第二行；
    所述多个第一虚拟接触垫沿第一方向排列成至少第三行；
    所述多个阵列测试接触垫沿第一方向排列成至少第四行。
  7. 根据权利要求书6所述的显示基板，还包括：多个第二虚拟接触垫，位于所述邦定区，沿垂直于所述第一方向的第二方向排列成至少第一列和第二列，其中第一列和第二列分别位于所述多个第一虚拟接触垫在第一方向上的两侧，其中，
    所述多个第二虚拟接触垫的边缘被所述接触垫绝缘层的第一部分覆盖，所述多个第二虚拟接触垫的背离所述衬底基板的表面从所述接触垫绝缘层的第一部分外露；并且
    所述多个第二虚拟接触垫中的每一个在所述衬底基板上的投影与所述接触垫绝缘层的第二部分在所述衬底基板的投影之间的间距在3微米至100微米的范围内。
  8. 根据权利要求书1所述的显示基板，其中，所述多个输入接触垫和所述多个输出接触垫中的至少一个包括：
    第一引线连接部，位于所述衬底基板上，其中输入接触垫的第一引线连接部通过设置在所述邦定区的第一引线与用于连接到外部电路的连接接触垫电连接，输出接触垫的第一引线连接部通过设置在所述邦定区的第二引线与所述栅极驱动电路或者与所述多个子像素中的至少一个电连接；
    第一导体部，位于所述第一引线连接部背离所述衬底基板的一侧，与所述第一引线连接部电连接；
    第二导体部，位于所述第一导体部背离所述衬底基板的一侧，与所述第一导体部电连接，所述第二导体部的边缘被所述接触垫绝缘层的第一部分覆盖。
  9. 根据权利要求书8所述的显示基板，还包括：
    邦定区第一栅绝缘层，位于所述邦定区，覆盖所述衬底基板，所述第一引线连接部位于所述邦定区第一栅绝缘层背离所述衬底基板的一侧；
    邦定区第二栅绝缘层，位于所述邦定区，位于所述邦定区第一栅绝缘层背离所述衬底基板的一侧并且覆盖所述第一引线连接部；
    邦定区层间绝缘层，位于所述邦定区，且位于所述邦定区第二栅绝缘层背离所述衬底基板的一侧，所述第一导体部通过设置在所述邦定区第二栅绝缘层中的过孔和设置在所述邦定区层间绝缘层中的过孔与所述第一引线连接部电连接；
    邦定区钝化层，位于邦定区，位于所述邦定区层间绝缘层背离所述衬底基板的一侧并且覆盖所述第一导体部，所述第二导体部通过设置在所述邦定区钝化层中的过孔与所述第一导体部电连接。
  10. 根据权利要求书9所述的显示基板，其中，所述邦定区钝化层位于所述接触垫绝缘层的第二部分与所述邦定区第二栅绝缘层之间的部分厚度大于或等于0。
  11. 根据权利要求书8所述的显示基板，还包括：
    邦定区第一栅绝缘层，位于所述邦定区，覆盖所述衬底基板，所述第一引线连接部位于所述邦定区第一栅绝缘层背离所述衬底基板的一侧；
    邦定区第二栅绝缘层，位于所述邦定区，位于所述邦定区第一栅绝缘层背离所述衬底基板的一侧并且覆盖所述第一引线连接部；
    邦定区层间绝缘层，位于所述邦定区，且位于所述邦定区第二栅绝缘层背离所述衬底基板的一侧，所述第一导体部通过设置在所述邦定区第二栅绝缘层中的过孔和设置在所述邦定区层间绝缘层中的过孔与所述第一引线连接部电连接，所述第二导体部位于所述第一导体部背离所述衬底基板的一侧并且覆盖所述第一导体部。
  12. 根据权利要求书8所述的显示基板，其中，所述多个输入接触垫和所述多个输出接触垫中的所述至少一个还包括：
    第三导体部，位于所述第二导体部背离所述衬底基板的一侧，与所述第二导体部电连接。
  13. 根据权利要求书12所述的显示基板，还包括：
    邦定区阻挡层，位于所述邦定区，覆盖所述第二导体层和所述接触垫绝缘层的第一部分，
    邦定区无机层，位于所述邦定区，覆盖所述邦定区阻挡层，所述第三导体部通过设置在所述邦定区阻挡层中的过孔和设置在所述邦定区无机层中的过孔与所述第二导体部电连接。
  14. 根据权利要求书2所述的显示基板，其中，所述多个第一虚拟接触垫中的至少一个包括第四导体部，所述第四导体部位于所述衬底基板面向所述多个输入接触垫和所述多个输出接触垫的一侧，所述第四导体部的边缘被所述接触垫绝缘层的第一部分覆盖，
    其中所述多个输入接触垫和所述多个输出接触垫中的至少一个包括第一引线连接部、第一导体部和第二导体部，所述第四导体部与所述第二导体部同层设置。
  15. 根据权利要求书14所述的显示基板，其中，所述多个第一虚拟接触垫中的至少一个还包括第五导体部，所述第五导体部位于所述第四导体部与所述衬底基板之间并且与所述第四导体部电连接，所述第五导体部与所述第一导体部同层设置。
  16. 根据权利要求书3所述的显示基板，其中，所述多个阵列测试接触垫中的至少一个包括：
    第二引线连接部，位于所述衬底基板面向所述多个输入接触垫和所述多个输出接触垫的一侧；
    第六导体部，位于所述第二引线连接部背离所述衬底基板的一侧，与所述第二引线连接部电连接；
    第七导体部，位于所述第六导体部背离所述衬底基板的一侧，与所述第六导体部电连接，所述第七导体部的边缘被所述接触垫绝缘层的第一部分覆盖，
    其中所述多个输入接触垫和所述多个输出接触垫中的至少一个包括第一引线连接部、第一导体部和第二导体部，所述第二引线连接部、所述第六导体部和所述第七导体部分别与所述第一引线连接部、所述第一导体部和所述第二导体部同层设置。
  17. 根据权利要求书7所述的显示基板，其中，所述多个第二虚拟接触垫中的至少一个包括第八导体部，所述第八导体部位于所述衬底基板面向所述多个输入接触垫和所述多个输出接触垫的一侧，所述第八导体部的边缘被所述接触垫绝缘层的第一部分覆盖，
    其中所述多个输入接触垫和所述多个输出接触垫中的至少一个包括第一引线连接部、第一导体部和第二导体部，所述第八导体部与所述第二导体部同层设置。
  18. 根据权利要求书17所述的显示基板，其中，所述多个第二虚拟接触垫中的至少一个还包括第九导体部，所述第九导体部位于所述第八导体部与所述衬底基板之间并且与所述第八导体部电连接，所述第九导体部与所述第一导体部同层设置。
  19. 根据权利要求书1至18中任一项权利要求所述的显示基板，其中，所述多个子像素中至少一个包括像素驱动电路、第一平坦化层、第一转接电极、第二平坦化层以及发光元件，
    所述第一平坦化层在所述像素驱动电路远离所述衬底基板的一侧以提供第一平坦化表面；
    所述第一转接电极在所述第一平坦化表面上，且通过设置在所述第一平坦化层中的过孔与所述像素驱动电路电连接；
    所述第二平坦化层在所述第一转接电极远离所述衬底基板的一侧以提供第二平坦化表面；
    所述发光元件在所述第二平坦化表面上且通过设置在所述第二平坦化层中的过孔与所述第一转接电极电连接；
    其中，所述接触垫绝缘层与所述第二平坦化层同层设置。
  20. 根据权利要求19所述的显示基板，其中，所述像素驱动电路包括薄膜晶体管，所述薄膜晶体管包括栅极、源极和漏极，所述多个输入接触垫和所述多个输出接触垫中的至少一个包括第一引线连接部、第一导体部和第二导体部，其中，
    所述第一引线连接部与所述栅极同层设置；
    所述第一导体部与所述源极和漏极同层设置，
    所述第二导体部与所述第一转接电极同层设置。
  21. 根据权利要求19所述的显示基板，还包括显示区钝化层，所述显示区钝化层位于所述像素驱动电路和所述第一平坦化层之间，所述像素驱动电路和所述第一转接电极还通过设置在所述显示区钝化层中的过孔电连接；
    所述显示基板还包括邦定区钝化层，所述邦定区钝化层和所述显示区钝化层同层设置。
  22. 根据权利要求19所述的显示基板，还包括位于显示区的封装层、显示区阻挡层、第一触控电极层、第二触控电极层和触控绝缘层，所述封装层位于所述发光元件 的远离所述衬底基板的一侧，所述显示区阻挡层位于所述封装层的远离所述衬底基板的一侧，所述第一触控电极层位于所述显示区阻挡层背离所述衬底基板的一侧，所述触控绝缘层位于所述第一触控电极层背离所述衬底基板的一侧并且覆盖所述第一触控电极层，所述第二触控电极层位于所述触控绝缘层背离所述衬底基板的一侧；
    所述显示基板还包括位于邦定区的邦定区阻挡层和邦定区无机层，所述多个输入接触垫和所述多个输出接触垫中的至少一个还包括第三导体部，所述邦定区阻挡层、所述邦定区无机层和所述第三导体部分别与所述显示区阻挡层、所述触控绝缘层和所述第二触控电极层位于同层。
  23. 根据权利要求20所述的显示基板，其中，所述多个子像素中至少一个还包括显示区层间绝缘层、显示区第一栅绝缘层以及显示区第二栅绝缘层，所述显示区层间绝缘层位于所述栅极与所述源极和所述漏极之间，所述显示区第一栅绝缘层位于所述显示区层间绝缘层面向所述衬底基板的一侧，所述显示区第二栅绝缘层位于所述显示区层间绝缘层与所述显示区第一栅绝缘层之间；
    所述显示基板还包括邦定区层间绝缘层、邦定区第一栅绝缘层和所述邦定区第二栅绝缘层，所述邦定区层间绝缘层、所述邦定区第一栅绝缘层和所述邦定区第二栅绝缘层分别与所述显示区层间绝缘层、所述显示区第一栅绝缘层和所述显示区第二栅绝缘层同层设置。
  24. 根据权利要求20所述的显示基板，其中，所述多个子像素中至少一个还包括存储电容器，所述存储电容器的第一极与所述栅极同层设置，所述存储电容器的第二极设置在所述显示区层间绝缘层与所述显示区第二栅绝缘层之间。
  25. 根据权利要求1至18中任一项权利要求所述的显示基板，其中，所述衬底基板包括：
    第一柔性层，
    第二柔性层，位于所述第一柔性层面向所述多个输入接触垫和所述多个输出接触垫的一侧；
    第一衬底阻挡层，位于所述第一柔性层和所述第二柔性层之间；
    第二衬底阻挡层，位于所述第二柔性层背离所述第一柔性层的一侧；
    缓冲层，位于所述第二衬底阻挡层背离所述第一柔性层的一侧。
  26. 一种显示装置，包括如权利要求1-25中任一项所述的显示基板。
  27. 一种制造根据权利要求书1至25中任一项所述的显示基板的方法，包括：
    提供衬底基板，所述衬底基板包括显示区、位于所述显示区至少一侧的邦定区和位于所述显示区至少另一侧的侧边区；
    在所述显示区中形成多个子像素；
    在所述侧边区形成栅极驱动电路，所述栅极驱动电路与所述多个子像素连接，并且被配置为向所述多个子像素提供栅极驱动信号；
    在所述邦定区形成用于与外部电路电连接的多个输入接触垫；
    在所述邦定区中形成多个输出接触垫，所述多个输出接触垫位于所述多个输入接触垫与所述显示区之间，所述多个输出接触垫与所述多个子像素和所述栅极驱动电路电连接；
    在所述邦定区形成接触垫绝缘层，所述接触垫绝缘层位于所述多个输入接触垫中相邻输入接触垫之间的间隙、所述多个输出接触垫中相邻输出接触垫之间的间隙、以及所述多个输入接触垫与所述多个输出接触垫之间的区域，所述多个输入接触垫和所述多个输出接触垫的背离所述衬底基板的表面从所述接触垫绝缘层外露，其中所述接触垫绝缘层包括具有第一厚度的第一部分和具有第二厚度的第二部分，所述第二厚度小于所述第一厚度，所述多个输入接触垫和所述多个输出接触垫的边缘被所述接触垫绝缘层的第一部分覆盖，所述接触垫绝缘层的第二部分位于所述多个输入接触垫与所述多个输出接触垫之间的区域中。
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Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117479684A (zh) * 2022-07-19 2024-01-30 群创光电股份有限公司 电子装置
KR20240133813A (ko) * 2023-02-27 2024-09-05 삼성디스플레이 주식회사 표시 장치
CN118693057B (zh) * 2023-03-24 2026-01-30 京东方科技集团股份有限公司 显示面板及显示装置
EP4598324A4 (en) * 2023-03-28 2025-12-31 Boe Technology Group Co Ltd DISPLAY PANEL, RELATED PREPARATION METHOD AND DISPLAY DEVICE
KR20250047513A (ko) * 2023-09-27 2025-04-04 삼성디스플레이 주식회사 표시 장치

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102253507A (zh) * 2011-04-08 2011-11-23 深圳市华星光电技术有限公司 芯片扇出设计、其形成方法及使用所述设计的液晶显示器
CN109459895A (zh) * 2018-12-13 2019-03-12 厦门天马微电子有限公司 显示面板和显示装置
CN109860224A (zh) * 2017-11-30 2019-06-07 京东方科技集团股份有限公司 显示基板及其制作方法、显示面板、显示装置
WO2020074869A1 (en) * 2018-10-08 2020-04-16 Zytronic Displays Limited Button supply
CN111223899A (zh) * 2019-11-25 2020-06-02 昆山国显光电有限公司 显示面板、显示装置及显示面板的制备方法

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101948173B1 (ko) 2012-11-29 2019-02-14 엘지디스플레이 주식회사 유기전계발광 표시소자
KR20150080825A (ko) * 2014-01-02 2015-07-10 삼성디스플레이 주식회사 표시 패널, 이를 포함하는 표시 장치 및 이의 제조 방법
KR102515033B1 (ko) 2015-05-29 2023-03-28 엘지디스플레이 주식회사 유기 발광 표시 장치 및 그 제조 방법
CN105096780B (zh) * 2015-07-29 2018-07-03 武汉华星光电技术有限公司 基板电路及显示面板的信号测试电路
KR102349281B1 (ko) * 2015-10-28 2022-01-11 삼성디스플레이 주식회사 디스플레이 장치
KR102558922B1 (ko) * 2016-08-29 2023-07-25 삼성디스플레이 주식회사 플렉시블 전자 회로 및 표시 장치
KR102743728B1 (ko) * 2016-11-08 2024-12-19 삼성디스플레이 주식회사 표시 장치
KR102787595B1 (ko) * 2017-01-10 2025-04-01 삼성디스플레이 주식회사 표시 장치
US12004392B2 (en) * 2017-04-28 2024-06-04 Chengdu Boe Optoelectronics Technology Co., Ltd. Display panel and display device
US10692411B2 (en) 2017-12-21 2020-06-23 Lg Display Co., Ltd. Display device, test circuit, and test method thereof
KR102552266B1 (ko) * 2018-01-31 2023-07-07 삼성디스플레이 주식회사 표시 장치
KR102662722B1 (ko) * 2018-09-17 2024-05-02 삼성디스플레이 주식회사 표시장치
KR102661283B1 (ko) 2018-11-26 2024-05-02 삼성디스플레이 주식회사 표시 기판, 이의 제조 방법, 및 이를 포함하는 표시 장치
CN109616480B (zh) * 2018-12-27 2020-11-10 厦门天马微电子有限公司 一种显示面板及显示装置
KR102960446B1 (ko) * 2019-06-28 2026-05-04 삼성디스플레이 주식회사 표시장치 및 그 제조방법
KR102795318B1 (ko) * 2019-09-16 2025-04-16 삼성디스플레이 주식회사 표시 장치
KR102936323B1 (ko) * 2020-02-18 2026-03-09 삼성디스플레이 주식회사 표시 장치
KR102851627B1 (ko) * 2020-02-25 2025-08-28 삼성디스플레이 주식회사 표시 장치
KR102892879B1 (ko) * 2020-06-22 2025-11-28 삼성디스플레이 주식회사 디스플레이 장치
CN212625587U (zh) * 2020-09-10 2021-02-26 京东方科技集团股份有限公司 显示基板和显示装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102253507A (zh) * 2011-04-08 2011-11-23 深圳市华星光电技术有限公司 芯片扇出设计、其形成方法及使用所述设计的液晶显示器
CN109860224A (zh) * 2017-11-30 2019-06-07 京东方科技集团股份有限公司 显示基板及其制作方法、显示面板、显示装置
WO2020074869A1 (en) * 2018-10-08 2020-04-16 Zytronic Displays Limited Button supply
CN109459895A (zh) * 2018-12-13 2019-03-12 厦门天马微电子有限公司 显示面板和显示装置
CN111223899A (zh) * 2019-11-25 2020-06-02 昆山国显光电有限公司 显示面板、显示装置及显示面板的制备方法

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