WO2022048286A1 - 一种测试治具转接板及记忆体测试装置 - Google Patents

一种测试治具转接板及记忆体测试装置 Download PDF

Info

Publication number
WO2022048286A1
WO2022048286A1 PCT/CN2021/103409 CN2021103409W WO2022048286A1 WO 2022048286 A1 WO2022048286 A1 WO 2022048286A1 CN 2021103409 W CN2021103409 W CN 2021103409W WO 2022048286 A1 WO2022048286 A1 WO 2022048286A1
Authority
WO
WIPO (PCT)
Prior art keywords
capacitor
memory
power supply
capacitors
circuit board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2021/103409
Other languages
English (en)
French (fr)
Inventor
陈律言
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Suzhou Wave Intelligent Technology Co Ltd
Original Assignee
Suzhou Wave Intelligent Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Suzhou Wave Intelligent Technology Co Ltd filed Critical Suzhou Wave Intelligent Technology Co Ltd
Publication of WO2022048286A1 publication Critical patent/WO2022048286A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01R—ELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS
    • H01R13/00—Details of coupling devices of the kinds covered by groups H01R12/70 or H01R24/00 - H01R33/00
    • H01R13/66—Structural association with built-in electrical component
    • H01R13/6608—Structural association with built-in electrical component with built-in single component
    • H01R13/6625—Structural association with built-in electrical component with built-in single component with capacitive component
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01R—ELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS
    • H01R13/00—Details of coupling devices of the kinds covered by groups H01R12/70 or H01R24/00 - H01R33/00
    • H01R13/66—Structural association with built-in electrical component
    • H01R13/665—Structural association with built-in electrical component with built-in electronic circuit
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01R—ELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS
    • H01R31/00—Coupling parts supported only by co-operation with counterpart
    • H01R31/06—Intermediate parts for linking two coupling parts, e.g. adapter
    • H01R31/065—Intermediate parts for linking two coupling parts, e.g. adapter with built-in electric apparatus
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01R—ELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS
    • H01R2201/00—Connectors or connections adapted for particular applications
    • H01R2201/20—Connectors or connections adapted for particular applications for testing or measuring purposes

Definitions

  • the invention relates to the field of server testing, in particular to a test fixture adapter board and a memory testing device.
  • the server is usually equipped with more stringent test conditions. For example, for the central processing unit and memory on the server, the pre-defined power test specifications must be followed when the power supply test is performed on them to ensure that the central processing unit and memory on the server are tested. Reliability of processors and memory in server operation.
  • memory is divided into many types according to the application and performance, such as UDIMM (Unbuffered Dual In-Line Memory Modules, unbuffered dual-channel memory modules), RDIMM (Registered Dual In-line Memory Modules, dual-channel memory modules with registers) ), LRDIMM (Load-Reduced Dual In-line Memory Module, low-load dual-channel memory module), etc.
  • UDIMM Unbuffered Dual In-Line Memory Modules, unbuffered dual-channel memory modules
  • RDIMM Registered Dual In-line Memory Modules, dual-channel memory modules with registers
  • LRDIMM Load-Reduced Dual In-line Memory Module, low-load dual-channel memory module
  • the power test conditions corresponding to different types of memory are different, such as different types of memory need to be matched with different power test number and capacity of capacitors.
  • the purpose of the present invention is to provide a test fixture adapter board and a memory test device, which can set capacitors on a low-cost test fixture adapter board, thereby reducing the cost of capacitor rework damage; Capacitors connected to the power supply of the memory to be tested do not need to be re-soldered to replace the number and capacity of the capacitors, thereby improving the service life of the test fixture adapter plate and the test efficiency of the memory.
  • test fixture adapter board including:
  • a capacitor switching circuit arranged on the circuit board and connected to a plurality of capacitors is used to connect the capacitors that meet the needs of the power supply to be connected to the capacitors according to the needs of the capacitors to be connected to the power supply of the memory to be tested.
  • the power supply of the memory to be tested so that the memory test fixture can perform a power supply test on the memory to be tested through the connection line of the circuit board under the condition of satisfying the power test conditions.
  • the plurality of capacitors include:
  • the capacitance switching circuit includes:
  • Multiple capacitor selection circuits connected with multiple sets of capacitors one by one;
  • the capacitance switching circuit is specifically configured to determine a target capacitance group to be connected to the power supply according to the demand of the capacitance to be connected to the power supply of the memory to be tested, so as to connect the target capacitance group to all the capacitors through the capacitance selection circuit. power supply.
  • the multiple groups of capacitors include:
  • the plurality of capacitor selection circuits include:
  • a first capacitor selection circuit arranged on the front side of the circuit board and connected to the first capacitor group
  • a second capacitor selection circuit arranged on the reverse side of the circuit board and connected to the second capacitor group.
  • each of the capacitance selection circuits includes a first pin, a second pin, a jumper cap for connecting the first pin and the second pin, a first resistor, a second resistor, The first switch tube and the second switch tube; wherein:
  • the first end of the first resistor is connected to the power circuit on the circuit board connected to the power end of the memory to be tested, and the second end of the first resistor is connected to the first pin and the The control end of the first switch tube is connected, the first end of the first switch tube is respectively connected to the first end of the second resistor and the control end of the second switch tube, and the first end of the second resistor is connected to the control end of the second switch tube.
  • the two ends are connected to the DC power supply, the first end of the second switch tube is connected to the first end of the corresponding capacitor bank, the second end of the capacitor bank is connected to the power supply line, the second pin, The second end of the first switch tube and the second end of the second switch tube are both grounded; wherein, the first switch tube and the second switch tube are both turned on at a high level and a low level cut-off switch.
  • the first switch transistor and the second switch transistor are both NMOS transistors; wherein:
  • the gate of the NMOS transistor is used as the control terminal of the first switch transistor and the second switch transistor, and the drain of the NMOS transistor is used as the first terminal of the first switch transistor and the second switch transistor , the source of the NMOS transistor is used as the second end of the first switch transistor and the second switch transistor.
  • test fixture adapter plate further includes:
  • a plurality of capacitor clamping devices corresponding to multiple groups of capacitors one-to-one and each including a plurality of capacitor card slots; each capacitor clamping device is used to connect a capacitor to a capacitor when it is placed in a capacitor card slot. On the circuit board, it is used as a capacitor pre-connected to the power supply.
  • each of the capacitor clamping devices includes:
  • the first probe of the housing where the capacitor slot is located is in contact with the first pin pin where the capacitor is placed, and the second probe of the housing where the capacitor slot is situated Make a pin contact connection with the second pin where the capacitor is placed.
  • the present invention also provides a memory testing device, which includes a memory testing fixture and any of the above-mentioned test fixture adapter boards.
  • the invention provides a test fixture adapter board, which includes a circuit board, a first connecting part, a second connecting part, a plurality of capacitors and a capacitor switching circuit arranged on the circuit board.
  • the first connection part is inserted into the gold finger of the memory test fixture, and the second connection part is inserted into the slot of the memory to be tested, so that the memory test fixture is connected to the memory to be tested through the connection line of the circuit board.
  • the capacitor switching circuit connects the capacitor that meets the demand of the capacitor to be connected to the power supply of the memory to be tested to the power supply of the memory to be tested according to the demand of the power to be connected to the capacitor of the memory to be tested.
  • the capacitor is arranged on the low-cost test jig adapter board, thereby reducing the cost of rework damage to the capacitor; moreover, the present application can flexibly select the capacitor connected to the power supply of the memory to be tested through the capacitor switching circuit, and it is not necessary to rework the capacitor. Soldering to replace the number and capacity of capacitors, thus improving the service life of the test fixture adapter board and the test efficiency of the memory.
  • the present invention also provides a memory test device, which has the same beneficial effects as the above-mentioned test fixture adapter board.
  • FIG. 1 is a schematic structural diagram of a test fixture adapter plate according to an embodiment of the present invention
  • FIG. 2 is a circuit diagram of a capacitor selection circuit provided by an embodiment of the present invention.
  • FIG. 3 is a circuit diagram of a capacitance switching circuit provided by an embodiment of the present invention.
  • FIG. 4 is a schematic diagram of a front structure of a test fixture adapter plate according to an embodiment of the present invention.
  • FIG. 5 is a schematic diagram of a reverse side structure of a test fixture adapter plate according to an embodiment of the present invention.
  • FIG. 6 is a timing diagram of a capacitance switching circuit according to an embodiment of the present invention.
  • the core of the present invention is to provide a test jig adapter board and a memory test device.
  • Capacitors are arranged on the low-cost test jig adapter board, thereby reducing the cost of rework damage to the capacitor; moreover, the capacitance switching circuit is used to flexibly select Capacitors connected to the power supply of the memory to be tested do not need to be re-soldered to replace the number and capacity of the capacitors, thereby improving the service life of the test fixture adapter plate and the test efficiency of the memory.
  • FIG. 1 is a schematic structural diagram of a test fixture adapter board according to an embodiment of the present invention.
  • the test fixture adapter board includes:
  • a first connection part 2 arranged on the circuit board 1 and connected with the gold fingers of the memory test fixture;
  • the capacitor switching circuit 4 which is arranged on the circuit board 1 and connected with a plurality of capacitors, is used to connect the capacitors that meet the requirements of the capacitors to be connected to the power supply to the memory to be tested according to the requirements of the capacitors to be connected to the power supply of the memory to be tested. power supply, so that the memory test fixture can perform power supply test on the memory to be tested through the connection line of the circuit board 1 under the condition that the power supply test conditions are met.
  • test fixture adapter board of the present application includes a circuit board 1, a first connection part 2, a second connection part 3, a plurality of capacitors and a capacitance switching circuit 4 arranged on the circuit board 1, and its working principle is:
  • the circuit board 1 of the test fixture adapter board is provided with a first connection part 2 (such as a slot structure), which is used for plugging with the gold fingers of the memory test fixture; the circuit board 1 is also provided with a second connection Part 3 (such as a gold finger structure) is used to connect with the socket of the memory to be tested. That is to say, the test fixture adapter board is used as a connection bridge between the memory test fixture and the memory to be tested, instead of the gold finger of the original memory test fixture and the socket of the memory to be tested.
  • the connection method is adopted, so that the memory test fixture can perform power test on the memory to be tested through the connection line of the circuit board 1, and will not affect the power test of the memory to be tested.
  • the capacitor required for the memory power test is arranged on the circuit board 1 of the low-cost test fixture adapter board.
  • the present application sets a plurality of capacitors that meet the power supply test conditions of different types of memory on the circuit board 1, and is a plurality of capacitors.
  • the capacitor is provided with a capacitor switching circuit 4, and the capacitor switching circuit 4 can connect the capacitor that meets the power supply to be connected to the capacitor demand of the to-be-tested memory to the power of the to-be-tested memory, so that the to-be-tested memory In other words, the capacitor switching circuit 4 can flexibly select the capacitor connected to the power supply of the memory to be tested, which improves the service life of the test fixture adapter board and the test efficiency of the memory.
  • the invention provides a test fixture adapter board, which includes a circuit board, a first connecting part, a second connecting part, a plurality of capacitors and a capacitor switching circuit arranged on the circuit board.
  • the first connection part is inserted into the gold finger of the memory test fixture, and the second connection part is inserted into the slot of the memory to be tested, so that the memory test fixture is connected to the memory to be tested through the connection line of the circuit board.
  • the capacitor switching circuit connects the capacitor that meets the demand of the capacitor to be connected to the power supply of the memory to be tested to the power supply of the memory to be tested according to the demand of the power to be connected to the capacitor of the memory to be tested.
  • the capacitor is arranged on the low-cost test fixture adapter board, thereby reducing the cost of rework damage to the capacitor; moreover, the present application can flexibly select the capacitor connected to the power supply of the memory to be tested through the capacitor switching circuit, without having to rework Soldering to replace the number and capacity of capacitors, thus improving the service life of the test fixture adapter board and the test efficiency of the memory.
  • the plurality of capacitors include:
  • the capacitance switching circuit 4 includes:
  • Multiple capacitor selection circuits connected with multiple sets of capacitors one by one;
  • the capacitor switching circuit 4 is specifically configured to determine the target capacitor bank to be connected to the power supply according to the requirement of the capacitor to be connected to the power supply of the memory to be tested, so as to connect the target capacitor bank to the power supply through the capacitor selection circuit.
  • the present application divides the multiple capacitors on the circuit board 1 that meet the needs of the capacitors to be connected to the power supply of different types of memory into multiple sets of capacitors, each set of capacitors includes multiple capacitors connected in parallel, and each set of capacitors includes multiple capacitors. Capacitors have the same value. It should be noted that some memory power needs to be connected to the capacitors need only one set of capacitors, such as LRDIMM power needs to be connected to 22uF x 16 capacitors; some memory power needs to be connected to the capacitor needs to be more The combination of group capacitors can be satisfied.
  • the capacitor switching circuit 4 on the circuit board 1 includes a plurality of capacitor selection circuits corresponding to multiple groups of capacitors one-to-one. Through the capacitor selection circuits, the capacitor groups corresponding to the capacitor selection circuits can be connected to the power supply of the memory to be tested. Then the working principle of the capacitor switching circuit 4 is: firstly determine the target capacitor bank to be connected to the power supply according to the demand of the capacitor to be connected to the power supply of the memory to be tested, and then connect the target capacitor bank to the target capacitor bank through the capacitor selection circuit corresponding to the target capacitor bank. The power supply of the memory to be tested meets the needs of the capacitor to be connected to the power supply of the memory to be tested.
  • the multiple groups of capacitors include:
  • the plurality of capacitor selection circuits include:
  • a first capacitor selection circuit arranged on the front of the circuit board 1 and connected to the first capacitor group;
  • the second capacitor selection circuit is arranged on the reverse side of the circuit board 1 and connected to the second capacitor group.
  • the present application can divide the multiple groups of capacitors on the circuit board 1 into two groups, namely the first capacitor group and the second capacitor group.
  • the first capacitor group is arranged on the front of the circuit board 1
  • the second capacitance group is arranged On the reverse side of the circuit board 1 , thereby saving the area of the circuit board 1 .
  • a capacitor selection circuit (referred to as the first capacitor selection circuit) for managing the access of the first capacitor group to the power supply of the memory to be tested is provided on the front side of the circuit board 1 to manage the access of the second capacitor group to the under-test.
  • the capacitor selection circuit of the power supply of the memory (referred to as the second capacitor selection circuit) is arranged on the reverse side of the circuit board 1 , so as to facilitate the circuit connection of the circuit board 1 .
  • FIG. 2 is a circuit diagram of a capacitor selection circuit according to an embodiment of the present invention.
  • each capacitor selection circuit includes a first pin Z1, a second pin Z2, a jumper cap for connecting the first pin Z1 and the second pin Z2, and a first resistor R1 , the second resistor R2, the first switch tube Q1 and the second switch tube Q2;
  • the first end of the first resistor R1 is connected to the power circuit on the circuit board 1 connected to the power end of the memory to be tested, and the second end of the first resistor R1 is connected to the control of the first pin Z1 and the first switch tube Q1 respectively.
  • the first end of the first switch tube Q1 is connected to the first end of the second resistor R2 and the control end of the second switch tube Q2 respectively, the second end of the second resistor R2 is connected to the DC power supply, and the second switch tube
  • the first end of Q2 is connected to the first end of the corresponding capacitor group, the second end of the capacitor group is connected to the power supply line, the second pin Z2, the second end of the first switch tube Q1 and the second end of the second switch tube Q2 Both ends are grounded; wherein, the first switch tube Q1 and the second switch tube Q2 are both switch tubes that are turned on at a high level and cut off at a low level.
  • each capacitor selection circuit of the present application includes a first pin Z1, a second pin Z2, a jumper cap, a first resistor R1, a second resistor R2, a first switch tube Q1 and a second switch tube Q2, Its working principle is:
  • the control terminal of the first switch tube Q1 inputs the power signal (high level) of the memory to be tested, The first switch tube Q1 is turned on, the control end of the first switch tube Q1 is grounded (low level), the second switch tube Q2 is disconnected, and the capacitor bank corresponding to the capacitor selection circuit is not connected to the power supply of the memory to be tested; if The jumper cap is connected to the first pin Z1 and the second pin Z2, and the first pin Z1 is grounded, then the control terminal of the first switch tube Q1 inputs a low level signal, the first switch tube Q1 is disconnected, and the first switch tube Q1 is disconnected.
  • the control terminal of Q1 inputs a DC power supply (high level), the second switch tube Q2 is turned on, and the capacitor group corresponding to the capacitor selection circuit is connected to the power supply of the memory to be tested. It can be seen that, in the present application, the jumper cap can be used to select whether the capacitor bank corresponding to the capacitor selection circuit is connected to the power supply of the memory to be tested.
  • the working principle of the capacitor switching circuit 4 is described by taking the multiple capacitors including two groups of capacitors and the capacitor switching circuit 4 including two capacitor selection circuits as an example:
  • one set of capacitors and the capacitor selection circuit corresponding to this capacitor group are arranged on the front of the circuit board 1, and another group of capacitors and the capacitor selection circuit corresponding to this capacitor group (except the jumper cap) are arranged in the circuit
  • the reverse side of the board 1, and for the convenience of user operation, the jumper caps of the two capacitor selection circuits are set on the front side of the circuit board 1.
  • the capacitor bank is connected in parallel to the memory to be tested; similarly, when the jumper cap corresponding to the capacitor selection circuit on the reverse side of the circuit board 1 is connected, the capacitor bank on the reverse side of the circuit board 1 can also be connected in parallel to the memory to be tested , to meet the power test specifications compatible with different types of memory.
  • the first switch transistor Q1 and the second switch transistor Q2 are both NMOS transistors; wherein:
  • the gate of the NMOS transistor is used as the control terminal of the first switch transistor Q1 and the second switch transistor Q2,
  • the drain of the NMOS transistor serves as the first end of the first switch transistor Q1 and the second switch transistor Q2, and the source of the NMOS transistor serves as the second end of the first switch transistor Q1 and the second switch transistor Q2.
  • the first switch transistor Q1 and the second switch transistor Q2 of the present application can be selected but are not limited to NMOS (N-Metal-Oxide-Semiconductor, N-type metal-oxide-semiconductor) transistors, which are not described in this application. Special restrictions.
  • NMOS N-Metal-Oxide-Semiconductor, N-type metal-oxide-semiconductor
  • test fixture adapter board further includes:
  • a plurality of capacitor clamping devices corresponding to a plurality of groups of capacitors and each including a plurality of capacitor card slots; each capacitor clamping device is used to connect a capacitor to a circuit when the capacitor is placed in a capacitor card slot On board 1, it is used as a capacitor that is pre-connected to the power supply.
  • test fixture adapter plate of the present application also includes a plurality of capacitor clamping devices, and its working principle is as follows:
  • the capacitors used for the memory power test are welded on the memory test fixture, and the number and capacity of the capacitors on the memory test fixture are replaced by re-soldering. If the capacitors are also soldered on the circuit board 1, there will be the following problems: in order to save the area of the circuit board 1, usually the number of capacitors soldered on the circuit board 1 is not many, so the capacitors on the circuit board 1 are compatible with the type of memory. Limited, if the capacitors on the circuit board 1 are not compatible with the memory to be tested next, it is also necessary to replace the number and capacity of the capacitors on the circuit board 1 by re-soldering to be compatible with the memory to be tested next, but the capacitors are easy to rework cause damage to the circuit board 1.
  • a capacitor clamping device for each group of capacitors on the circuit board 1, and the capacitor clamping device includes a plurality of capacitor clamping slots.
  • the capacitor is connected to the It is used as a capacitor pre-connected to the power supply of the memory to be tested. It can be seen that the capacitor is detachably connected to the circuit board 1 through the capacitor clamping device, that is, the number and capacity of the capacitors on the circuit board 1 are replaced by taking out the capacitor from the capacitor card slot and placing a new capacitor, so as to avoid the capacitor rework. Circuit board 1 is damaged.
  • each capacitor clamping device includes:
  • the first probe of the housing where the capacitor slot is located is in contact with the first pin pin where the capacitor is placed, and the second probe of the housing where the capacitor slot is situated Make a pin contact connection with the second pin where the capacitor is placed.
  • the capacitor clamping device of the present application includes a housing including a plurality of capacitor card slots, a plurality of first probes and a plurality of second probes, and its working principle is as follows:
  • the first probe penetrating through the casing where the target capacitor slot is located is in contact with the first pin of the target capacitor connection, the first probe is connected to the capacitor selection circuit used to select whether the target capacitor is connected to the power supply of the memory to be tested, which is equivalent to the first pin pin of the target capacitor is connected to the corresponding capacitor selection circuit; runs through the target capacitor card slot
  • the second probe of the housing is in contact with the second pin of the target capacitor, and the second probe is connected to the power line on the circuit board 1 connected to the power supply terminal of the memory to be tested, which is equivalent to the second pin of the target capacitor.
  • the pins are connected to the power supply line on the circuit board 1 that is connected to the power supply terminal of the memory to be tested, so that the target capacitor is connected to the circuit board 1 .
  • the present application also provides a memory test device, including a memory test fixture and any of the above-mentioned test fixture adapter boards.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Tests Of Electronic Circuits (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)

Abstract

一种测试治具转接板及记忆体测试装置，包括电路板和设于电路板上的第一连接部、第二连接部、多个电容及电容切换电路。第一连接部与记忆体测试治具的金手指进行插接，第二连接部与待测试记忆体的插槽进行插接，以使记忆体测试治具通过电路板的连接线路对待测试记忆体进行电源测试。此外，电容切换电路在待测试记忆体进行电源测试之前，将满足待测试记忆体的电源待接入电容需求的电容接入其电源，以满足待测试记忆体的电源测试条件。可见，本申请将电容设在低成本的转接板上，从而降低电容重工损坏成本；而且，本申请可通过电容切换电路灵活选择接入待测试记忆体的电源的电容，从而提升了测试治具转接板的使用寿命及记忆体的测试效率。

Description

一种测试治具转接板及记忆体测试装置
本申请要求于2020年09月04日提交至中国专利局、申请号为202010921832.2、发明名称为“一种测试治具转接板及记忆体测试装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及服务器测试领域，特别是涉及一种测试治具转接板及记忆体测试装置。
背景技术
随着云计算应用的发展，信息化逐渐覆盖到社会的各个领域。对于信息服务的不断增加，对服务器的稳定性提出更高要求。为了提高服务器的稳定性，通常为服务器搭配较为严格的测试条件，比如，对于服务器上的中央处理器及记忆体，在对其进行电源测试时必须遵守预定义好的电源测试规范，以确保中央处理器及记忆体在服务器运行中的可靠性。
但是，记忆体根据应用场合及性能分为很多种类，如UDIMM(Unbuffered Dual In-Line Memory Modules，无缓冲双通道内存模块)、RDIMM(Registered Dual In-line Memory Module，带寄存器的双通道内存模块)、LRDIMM(Load-Reduced Dual In-line Memory Module，低负载双通道内存模块)等，不同种类的记忆体对应的电源测试条件并不相同，如不同种类的记忆体在电源测试时需搭配不同数量及容量的电容。
现有技术中，为了适应不同种类记忆体的电源测试条件，通常在记忆体测试治具中与记忆体电源连接的路径上预留供电容接入的脚位，测试人员可根据待测试记忆体的种类在记忆体测试治具上焊接对应数量及容量的电容，以满足待测试记忆体的电源测试条件。但是，一服务器大都搭配不同种类的记忆体，这就需要在测试不同种类的记忆体时，更换记忆体治具上电容的数量及容量，即重新焊接对应数量及容量的电容，这种电容重工方式不仅容易造成极为昂贵的测试治具的损坏，而且测试效率较低。
因此，如何提供一种解决上述技术问题的方案是本领域的技术人员目 前需要解决的问题。
发明内容
本发明的目的是提供一种测试治具转接板及记忆体测试装置，将电容设置在低成本的测试治具转接板上，从而降低电容重工损坏成本；而且，通过电容切换电路灵活选择接入待测试记忆体的电源的电容，不必重新焊接来更换电容的数量及容量，从而提升了测试治具转接板的使用寿命及记忆体的测试效率。
为解决上述技术问题，本发明提供了一种测试治具转接板，包括：
电路板；
设于所述电路板上、与记忆体测试治具的金手指进行插接的第一连接部；
设于所述电路板上、与待测试记忆体的插槽进行插接的第二连接部；
设于所述电路板上的多个电容；
设于所述电路板上、与多个电容连接的电容切换电路，用于根据所述待测试记忆体的电源待接入电容需求，将满足所述电源待接入电容需求的电容接入所述待测试记忆体的电源，以使所述记忆体测试治具在满足电源测试条件的情况下，通过所述电路板的连接线路对所述待测试记忆体进行电源测试。
优选地，所述多个电容包括：
用于满足不同种类记忆体的电源待接入电容需求的多组电容；
相应的，所述电容切换电路包括：
与多组电容一一连接的多个电容选择电路；
所述电容切换电路具体用于根据所述待测试记忆体的电源待接入电容需求确定待接入所述电源的目标电容组，以通过所述电容选择电路将所述目标电容组接入所述电源。
优选地，所述多组电容包括：
设于所述电路板的正面的第一电容组；
设于所述电路板的反面的第二电容组；
相应的，所述多个电容选择电路包括：
设于所述电路板的正面、与所述第一电容组连接的第一电容选择电路；
设于所述电路板的反面、与所述第二电容组连接的第二电容选择电路。
优选地，每个所述电容选择电路均包括第一插针、第二插针、用于连接所述第一插针和所述第二插针的跳帽、第一电阻、第二电阻、第一开关管及第二开关管；其中：
所述第一电阻的第一端接入所述电路板上与所述待测试记忆体的电源端连接的电源线路，所述第一电阻的第二端分别与所述第一插针和所述第一开关管的控制端连接，所述第一开关管的第一端分别与所述第二电阻的第一端和所述第二开关管的控制端连接，所述第二电阻的第二端接入直流电源，所述第二开关管的第一端与对应的电容组的第一端连接，所述电容组的第二端接入所述电源线路，所述第二插针、所述第一开关管的第二端及所述第二开关管的第二端均接地；其中，所述第一开关管和所述第二开关管均为高电平导通、低电平截止的开关管。
优选地，所述第一开关管和所述第二开关管均为NMOS管；其中：
所述NMOS管的栅极作为所述第一开关管和所述第二开关管的控制端，所述NMOS管的漏极作为所述第一开关管和所述第二开关管的第一端，所述NMOS管的源极作为所述第一开关管和所述第二开关管的第二端。
优选地，所述测试治具转接板还包括：
与多组电容一一对应、均包含多个电容卡槽的多个电容卡接装置；每个电容卡接装置均用于在一电容放置于一电容卡槽内时，将此电容接入所述电路板上，作为预接入所述电源的电容使用。
优选地，每个所述电容卡接装置包括：
包含多个电容卡槽的壳体；
一一贯穿于多个电容卡槽所在的壳体上、均与对应的电容选择电路连接的多个第一探针；
一一贯穿于多个电容卡槽所在的壳体上、均接入所述电路板上与所述待测试记忆体的电源端连接的电源线路的多个第二探针；
其中，在一电容放置于一电容卡槽内时，此电容卡槽所在壳体的第一探针与放置电容的第一引脚针接触连接，此电容卡槽所在壳体的第二探针与放置电容的第二引脚针接触连接。
为解决上述技术问题，本发明还提供了一种记忆体测试装置，包括记忆体测试治具和上述任一种测试治具转接板。
本发明提供了一种测试治具转接板，包括电路板和设于电路板上的第一连接部、第二连接部、多个电容及电容切换电路。第一连接部与记忆体测试治具的金手指进行插接，第二连接部与待测试记忆体的插槽进行插接，以使记忆体测试治具通过电路板的连接线路对待测试记忆体进行电源测试。此外，电容切换电路在待测试记忆体进行电源测试之前，根据待测试记忆体的电源待接入电容需求，将满足电源待接入电容需求的电容接入待测试记忆体的电源，以满足待测试记忆体的电源测试条件。可见，本申请将电容设置在低成本的测试治具转接板上，从而降低电容重工损坏成本；而且，本申请可通过电容切换电路灵活选择接入待测试记忆体的电源的电容，不必重新焊接来更换电容的数量及容量，从而提升了测试治具转接板的使用寿命及记忆体的测试效率。
本发明还提供了一种记忆体测试装置，与上述测试治具转接板具有相同的有益效果。
附图说明
为了更清楚地说明本发明实施例中的技术方案，下面将对现有技术和实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本发明实施例提供的一种测试治具转接板的结构示意图；
图2为本发明实施例提供的一种电容选择电路的电路图；
图3为本发明实施例提供的一种电容切换电路的电路图；
图4为本发明实施例提供的一种测试治具转接板的正面结构示意图；
图5为本发明实施例提供的一种测试治具转接板的反面结构示意图；
图6为本发明实施例提供的一种电容切换电路的时序图。
具体实施方式
本发明的核心是提供一种测试治具转接板及记忆体测试装置，将电容设置在低成本的测试治具转接板上，从而降低电容重工损坏成本；而且，通过电容切换电路灵活选择接入待测试记忆体的电源的电容，不必重新焊接来更换电容的数量及容量，从而提升了测试治具转接板的使用寿命及记忆体的测试效率。
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
请参照图1，图1为本发明实施例提供的一种测试治具转接板的结构示意图。
该测试治具转接板包括：
电路板1；
设于电路板1上、与记忆体测试治具的金手指进行插接的第一连接部2；
设于电路板1上、与待测试记忆体的插槽进行插接的第二连接部3；
设于电路板1上的多个电容；
设于电路板1上、与多个电容连接的电容切换电路4，用于根据待测试记忆体的电源待接入电容需求，将满足电源待接入电容需求的电容接入待测试记忆体的电源，以使记忆体测试治具在满足电源测试条件的情况下，通过电路板1的连接线路对待测试记忆体进行电源测试。
具体地，本申请的测试治具转接板包括电路板1和设于电路板1上的第一连接部2、第二连接部3、多个电容及电容切换电路4，其工作原理为：
测试治具转接板的电路板1上设有第一连接部2(如插槽结构)，用于与记忆体测试治具的金手指进行插接；电路板1上还设有第二连接部3(如金手指结构)，用于与待测试记忆体的插槽进行插接。也就是说，测试治具转接板作为记忆体测试治具与待测试记忆体之间的连接桥梁，代替原来记忆体测试治具的金手指与待测试记忆体的插槽直接进行插接的连接方式，从而使记忆体测试治具通过电路板1的连接线路对待测试记忆体进行电源测试，不会对待测试记忆体的电源测试造成影响。
考虑到记忆体测试治具比较昂贵，电容重工容易造成记忆体测试治具的损坏，本申请将记忆体电源测试所需的电容设于低成本的测试治具转接板的电路板1上，以降低电容重工损坏成本；且为了避免通过重新焊接来更换电容的数量及容量，本申请将满足于不同种类记忆体的电源测试条件的多个电容均设于电路板1上，并为多个电容设置电容切换电路4，电容切换电路4可根据待测试记忆体的电源待接入电容需求，将满足电源待接入电容需求的电容接入待测试记忆体的电源，以使待测试记忆体的电源测试条件达标，也就是说，通过电容切换电路4可灵活选择接入待测试记忆体的电源的电容，提升了测试治具转接板的使用寿命及记忆体的测试效率。
本发明提供了一种测试治具转接板，包括电路板和设于电路板上的第一连接部、第二连接部、多个电容及电容切换电路。第一连接部与记忆体测试治具的金手指进行插接，第二连接部与待测试记忆体的插槽进行插接，以使记忆体测试治具通过电路板的连接线路对待测试记忆体进行电源测试。此外，电容切换电路在待测试记忆体进行电源测试之前，根据待测试记忆体的电源待接入电容需求，将满足电源待接入电容需求的电容接入待测试记忆体的电源，以满足待测试记忆体的电源测试条件。可见，本申请将电容设置在低成本的测试治具转接板上，从而降低电容重工损坏成本；而且，本申请可通过电容切换电路灵活选择接入待测试记忆体的电源的电容，不必重新焊接来更换电容的数量及容量，从而提升了测试治具转接板的使用寿命及记忆体的测试效率。
在上述实施例的基础上：
作为一种可选的实施例，多个电容包括：
用于满足不同种类记忆体的电源待接入电容需求的多组电容；
相应的，电容切换电路4包括：
与多组电容一一连接的多个电容选择电路；
电容切换电路4具体用于根据待测试记忆体的电源待接入电容需求确定待接入电源的目标电容组，以通过电容选择电路将目标电容组接入电源。
具体地，本申请将电路板1上满足不同种类记忆体的电源待接入电容需求的多个电容分为多组电容，每组电容均包含多个并联的电容，且每组电容包含的多个电容的容值相同。需要说明的是，有些记忆体的电源待接入电容需求只需要一组电容便可满足，比如LRDIMM的电源需要接入22uF x 16个电容；有些记忆体的电源待接入电容需求则需要多组电容组合才可满足。
基于此，电路板1上的电容切换电路4包括与多组电容一一对应的多个电容选择电路，通过电容选择电路可将与电容选择电路对应的电容组接入待测试记忆体的电源，则电容切换电路4的工作原理为：首先根据待测试记忆体的电源待接入电容需求确定待接入电源的目标电容组，然后通过与目标电容组对应的电容选择电路将目标电容组接入待测试记忆体的电源，以满足待测试记忆体的电源待接入电容需求。
作为一种可选的实施例，多组电容包括：
设于电路板1的正面的第一电容组；
设于电路板1的反面的第二电容组；
相应的，多个电容选择电路包括：
设于电路板1的正面、与第一电容组连接的第一电容选择电路；
设于电路板1的反面、与第二电容组连接的第二电容选择电路。
具体地，本申请可将电路板1上的多组电容划分为两大组，分别是第一电容组和第二电容组，第一电容组设于电路板1的正面，第二电容组设于电路板1的反面，从而节约电路板1的面积。基于此，用于管理第一电容组接入待测试记忆体的电源的电容选择电路(称为第一电容选择电路)设于电路板1的正面，用于管理第二电容组接入待测试记忆体的电源的电 容选择电路(称为第二电容选择电路)设于电路板1的反面，从而便于电路板1线路连接。
请参照图2，图2为本发明实施例提供的一种电容选择电路的电路图。
作为一种可选的实施例，每个电容选择电路均包括第一插针Z1、第二插针Z2、用于连接第一插针Z1和第二插针Z2的跳帽、第一电阻R1、第二电阻R2、第一开关管Q1及第二开关管Q2；其中：
第一电阻R1的第一端接入电路板1上与待测试记忆体的电源端连接的电源线路，第一电阻R1的第二端分别与第一插针Z1和第一开关管Q1的控制端连接，第一开关管Q1的第一端分别与第二电阻R2的第一端和第二开关管Q2的控制端连接，第二电阻R2的第二端接入直流电源，第二开关管Q2的第一端与对应的电容组的第一端连接，电容组的第二端接入电源线路，第二插针Z2、第一开关管Q1的第二端及第二开关管Q2的第二端均接地；其中，第一开关管Q1和第二开关管Q2均为高电平导通、低电平截止的开关管。
具体地，本申请的每个电容选择电路均包括第一插针Z1、第二插针Z2、跳帽、第一电阻R1、第二电阻R2、第一开关管Q1及第二开关管Q2，其工作原理为：
在待测试记忆体上电后，若跳帽未接入第一插针Z1和第二插针Z2，则第一开关管Q1的控制端输入待测试记忆体的电源信号(高电平)，第一开关管Q1导通，第一开关管Q1的控制端接地(低电平)，第二开关管Q2断开，此电容选择电路对应的电容组未接入待测试记忆体的电源；若跳帽接入第一插针Z1和第二插针Z2，第一插针Z1接地，则第一开关管Q1的控制端输入低电平信号，第一开关管Q1断开，第一开关管Q1的控制端输入直流电源(高电平)，第二开关管Q2导通，此电容选择电路对应的电容组接入待测试记忆体的电源。可见，本申请可通过跳帽来选择所在电容选择电路对应的电容组是否接入待测试记忆体的电源。
比如，请参照图3，以多个电容包含两组电容、电容切换电路4包括两个电容选择电路为例，对电容切换电路4的工作原理进行说明：
如图4和图5所示，一组电容及此电容组对应的电容选择电路设于电路板1的正面，另一组电容及此电容组对应的电容选择电路(除了跳帽)设于电路板1的反面，且为了方便用户操作，两个电容选择电路的跳帽都设于电路板1的正面。
以设于电路板1的正面的电容选择电路为例，并搭配图6的时序进行工作原理说明：在A区间时为初始状态；当待测试记忆体上电后进入B区间，Va会爬升并导通第一开关管Q1，Vb因第一开关管Q1导通而接地，第二开关管Q2断开，因此Vc会维持高准位；将设于电路板1的正面的电容选择电路对应的跳帽接上后则进入C区间，Va会变成低准位关闭第一开关管Q1，Vb则变成高准位并开启第二开关管Q2，Vc顺势接地将设于电路板1正面的电容组并联入待测试记忆体中；同理，当设于电路板1的反面的电容选择电路对应的跳帽接上后也可将设于电路板1反面的电容组并联入待测试记忆体中，达到兼容不同种类的记忆体的电源测试规范。
作为一种可选的实施例，第一开关管Q1和第二开关管Q2均为NMOS管；其中：
NMOS管的栅极作为第一开关管Q1和第二开关管Q2的控制端，
NMOS管的漏极作为第一开关管Q1和第二开关管Q2的第一端，NMOS管的源极作为第一开关管Q1和第二开关管Q2的第二端。
具体地，本申请的第一开关管Q1和第二开关管Q2均可选用但不仅限于NMOS(N-Metal-Oxide-Semiconductor，N型金属-氧化物-半导体)管，本申请在此不做特别的限定。
作为一种可选的实施例，测试治具转接板还包括：
与多组电容一一对应、均包含多个电容卡槽的多个电容卡接装置；每个电容卡接装置均用于在一电容放置于一电容卡槽内时，将此电容接入电路板1上，作为预接入电源的电容使用。
进一步地，本申请的测试治具转接板还包括多个电容卡接装置，其工作原理为：
现有技术中，供记忆体电源测试使用的电容焊接于记忆体测试治具上，通过重新焊接来更换记忆体测试治具上电容的数量及容量，若本申请中供 记忆体电源测试使用的电容同样焊接于电路板1上，则会存在如下问题：为了节约电路板1的面积，通常情况下电路板1上焊接的电容数量并不多，则电路板1上的电容兼容记忆体的种类有限，若电路板1上的电容不能兼容接下来待测试的记忆体，同样需要通过重新焊接来更换电路板1上电容的数量及容量，以兼容接下来待测试的记忆体，但电容重工容易造成电路板1的损坏。
基于此，本申请为电路板1上的每组电容均设置一个电容卡接装置，电容卡接装置上包含多个电容卡槽，在一电容放置于一电容卡槽内时，此电容便接入电路板1上，作为预接入待测试记忆体的电源的电容使用。可见，电容通过电容卡接装置与电路板1可拆卸式连接，即通过从电容卡槽内取出电容并重新放置新电容来更换电路板1上电容的数量及容量，从而避免因电容重工造成的电路板1损坏。
作为一种可选的实施例，每个电容卡接装置包括：
包含多个电容卡槽的壳体；
一一贯穿于多个电容卡槽所在的壳体上、均与对应的电容选择电路连接的多个第一探针；
一一贯穿于多个电容卡槽所在的壳体上、均接入电路板1上与待测试记忆体的电源端连接的电源线路的多个第二探针；
其中，在一电容放置于一电容卡槽内时，此电容卡槽所在壳体的第一探针与放置电容的第一引脚针接触连接，此电容卡槽所在壳体的第二探针与放置电容的第二引脚针接触连接。
具体地，本申请的电容卡接装置包括包含多个电容卡槽的壳体、多个第一探针及多个第二探针，其工作原理为：
在一电容(称为目标电容)放置于一电容卡槽(称为目标电容卡槽)内时，贯穿于目标电容卡槽所在壳体的第一探针与目标电容的第一引脚针接触连接，第一探针与用于选择目标电容是否接入待测试记忆体电源的电容选择电路连接，相当于目标电容的第一引脚针与对应的电容选择电路连接；贯穿于目标电容卡槽所在壳体的第二探针与目标电容的第二引脚针接触连接，第二探针接入电路板1上与待测试记忆体的电源端连接的电源线 路，相当于目标电容的第二引脚针接入电路板1上与待测试记忆体的电源端连接的电源线路，从而实现目标电容接入电路板1上。
本申请还提供了一种记忆体测试装置，包括记忆体测试治具和上述任一种测试治具转接板。
本申请提供的记忆体测试装置的介绍请参考上述测试治具转接板的实施例，本申请在此不再赘述。
还需要说明的是，在本说明书中，诸如第一和第二等之类的关系术语仅仅用来将一个实体或者操作与另一个实体或操作区分开来，而不一定要求或者暗示这些实体或操作之间存在任何这种实际的关系或者顺序。而且，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者设备不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者设备所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括所述要素的过程、方法、物品或者设备中还存在另外的相同要素。
对所公开的实施例的上述说明，使本领域专业技术人员能够实现或使用本发明。对这些实施例的多种修改对本领域的专业技术人员来说将是显而易见的，本文中所定义的一般原理可以在不脱离本发明的精神或范围的情况下，在其他实施例中实现。因此，本发明将不会被限制于本文所示的这些实施例，而是要符合与本文所公开的原理和新颖特点相一致的最宽的范围。

Claims (8)

  1. 一种测试治具转接板，其特征在于，包括：
    电路板；
    设于所述电路板上、与记忆体测试治具的金手指进行插接的第一连接部；
    设于所述电路板上、与待测试记忆体的插槽进行插接的第二连接部；
    设于所述电路板上的多个电容；
    设于所述电路板上、与多个电容连接的电容切换电路，用于根据所述待测试记忆体的电源待接入电容需求，将满足所述电源待接入电容需求的电容接入所述待测试记忆体的电源，以使所述记忆体测试治具在满足电源测试条件的情况下，通过所述电路板的连接线路对所述待测试记忆体进行电源测试。
  2. 如权利要求1所述的测试治具转接板，其特征在于，所述多个电容包括：
    用于满足不同种类记忆体的电源待接入电容需求的多组电容；
    相应的，所述电容切换电路包括：
    与多组电容一一连接的多个电容选择电路；
    所述电容切换电路具体用于根据所述待测试记忆体的电源待接入电容需求确定待接入所述电源的目标电容组，以通过所述电容选择电路将所述目标电容组接入所述电源。
  3. 如权利要求2所述的测试治具转接板，其特征在于，所述多组电容包括：
    设于所述电路板的正面的第一电容组；
    设于所述电路板的反面的第二电容组；
    相应的，所述多个电容选择电路包括：
    设于所述电路板的正面、与所述第一电容组连接的第一电容选择电路；
    设于所述电路板的反面、与所述第二电容组连接的第二电容选择电路。
  4. 如权利要求2所述的测试治具转接板，其特征在于，每个所述电容选择电路均包括第一插针、第二插针、用于连接所述第一插针和所述第二插针的跳帽、第一电阻、第二电阻、第一开关管及第二开关管；其中：
    所述第一电阻的第一端接入所述电路板上与所述待测试记忆体的电源端连接的电源线路，所述第一电阻的第二端分别与所述第一插针和所述第一开关管的控制端连接，所述第一开关管的第一端分别与所述第二电阻的第一端和所述第二开关管的控制端连接，所述第二电阻的第二端接入直流电源，所述第二开关管的第一端与对应的电容组的第一端连接，所述电容组的第二端接入所述电源线路，所述第二插针、所述第一开关管的第二端及所述第二开关管的第二端均接地；其中，所述第一开关管和所述第二开关管均为高电平导通、低电平截止的开关管。
  5. 如权利要求4所述的测试治具转接板，其特征在于，所述第一开关管和所述第二开关管均为NMOS管；其中：
    所述NMOS管的栅极作为所述第一开关管和所述第二开关管的控制端，所述NMOS管的漏极作为所述第一开关管和所述第二开关管的第一端，所述NMOS管的源极作为所述第一开关管和所述第二开关管的第二端。
  6. 如权利要求2-5任一项所述的测试治具转接板，其特征在于，所述测试治具转接板还包括：
    与多组电容一一对应、均包含多个电容卡槽的多个电容卡接装置；每个电容卡接装置均用于在一电容放置于一电容卡槽内时，将此电容接入所述电路板上，作为预接入所述电源的电容使用。
  7. 如权利要求6所述的测试治具转接板，其特征在于，每个所述电容卡接装置包括：
    包含多个电容卡槽的壳体；
    一一贯穿于多个电容卡槽所在的壳体上、均与对应的电容选择电路连接的多个第一探针；
    一一贯穿于多个电容卡槽所在的壳体上、均接入所述电路板上与所述待测试记忆体的电源端连接的电源线路的多个第二探针；
    其中，在一电容放置于一电容卡槽内时，此电容卡槽所在壳体的第一探针与放置电容的第一引脚针接触连接，此电容卡槽所在壳体的第二探针与放置电容的第二引脚针接触连接。
  8. 一种记忆体测试装置，其特征在于，包括记忆体测试治具和如权利要求1-7任一项所述的测试治具转接板。
PCT/CN2021/103409 2020-09-04 2021-06-30 一种测试治具转接板及记忆体测试装置 Ceased WO2022048286A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202010921832.2A CN111816242B (zh) 2020-09-04 2020-09-04 一种测试治具转接板及记忆体测试装置
CN202010921832.2 2020-09-04

Publications (1)

Publication Number Publication Date
WO2022048286A1 true WO2022048286A1 (zh) 2022-03-10

Family

ID=72859974

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2021/103409 Ceased WO2022048286A1 (zh) 2020-09-04 2021-06-30 一种测试治具转接板及记忆体测试装置

Country Status (2)

Country Link
CN (1) CN111816242B (zh)
WO (1) WO2022048286A1 (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115243479A (zh) * 2022-07-25 2022-10-25 联宝(合肥)电子科技有限公司 多功能半成品测试治具
CN120849204A (zh) * 2025-09-23 2025-10-28 浪潮电子信息产业股份有限公司 一种重定时器测试装置、方法及电子设备

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111816242B (zh) * 2020-09-04 2021-02-19 苏州浪潮智能科技有限公司 一种测试治具转接板及记忆体测试装置
CN112630678B (zh) * 2020-12-11 2022-04-29 浪潮电子信息产业股份有限公司 一种主板核心电源的测试系统

Citations (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200722766A (en) * 2005-12-01 2007-06-16 Inventec Corp Memory test tool
TW200739338A (en) * 2006-04-06 2007-10-16 Mitac Int Corp Test card
TW201003085A (en) * 2008-07-11 2010-01-16 Hon Hai Prec Ind Co Ltd Power testing apparatus for universal serial bus interface
CN102255208A (zh) * 2010-05-21 2011-11-23 鸿富锦精密工业（深圳）有限公司 转接卡
CN102455966A (zh) * 2010-10-29 2012-05-16 鸿富锦精密工业（深圳）有限公司 内存负载转接板
CN102608525A (zh) * 2011-01-25 2012-07-25 鸿富锦精密工业（深圳）有限公司 电压极限测试系统及辅助测试治具
CN103364740A (zh) * 2012-04-10 2013-10-23 鸿富锦精密工业（深圳）有限公司 转接板及具有该转接板的直流电源测试系统
CN103383437A (zh) * 2012-05-02 2013-11-06 鸿富锦精密工业(武汉)有限公司 电源测试装置
TW201435891A (zh) * 2013-03-04 2014-09-16 Winbond Electronics Corp 快閃記憶體的驗證裝置
US8908407B1 (en) * 2011-07-30 2014-12-09 Rambus Inc. Content addressable memory (“CAM”)
CN207074249U (zh) * 2017-08-03 2018-03-06 郑州云海信息技术有限公司 一种电路板测试用辅助治具
CN207624550U (zh) * 2017-11-08 2018-07-17 阳光电源股份有限公司 用于插件式电容器的固定装置、机箱以及电机控制器
CN109946590A (zh) * 2019-04-11 2019-06-28 苏州浪潮智能科技有限公司 一种板卡转接设备和测试系统
CN111816242A (zh) * 2020-09-04 2020-10-23 苏州浪潮智能科技有限公司 一种测试治具转接板及记忆体测试装置

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6956387B2 (en) * 2003-08-15 2005-10-18 Intel Corporation Socket connection test modules and methods of using the same
CN106291399A (zh) * 2016-09-21 2017-01-04 郑州云海信息技术有限公司 一种电源模块pmbus专业的测试治具
TWI668566B (zh) * 2018-06-05 2019-08-11 和碩聯合科技股份有限公司 記憶體檢測系統、記憶體檢測方法以及用於記憶體檢測的錯誤映射表建立方法

Patent Citations (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200722766A (en) * 2005-12-01 2007-06-16 Inventec Corp Memory test tool
TW200739338A (en) * 2006-04-06 2007-10-16 Mitac Int Corp Test card
TW201003085A (en) * 2008-07-11 2010-01-16 Hon Hai Prec Ind Co Ltd Power testing apparatus for universal serial bus interface
CN102255208A (zh) * 2010-05-21 2011-11-23 鸿富锦精密工业（深圳）有限公司 转接卡
CN102455966A (zh) * 2010-10-29 2012-05-16 鸿富锦精密工业（深圳）有限公司 内存负载转接板
CN102608525A (zh) * 2011-01-25 2012-07-25 鸿富锦精密工业（深圳）有限公司 电压极限测试系统及辅助测试治具
US8908407B1 (en) * 2011-07-30 2014-12-09 Rambus Inc. Content addressable memory (“CAM”)
CN103364740A (zh) * 2012-04-10 2013-10-23 鸿富锦精密工业（深圳）有限公司 转接板及具有该转接板的直流电源测试系统
CN103383437A (zh) * 2012-05-02 2013-11-06 鸿富锦精密工业(武汉)有限公司 电源测试装置
TW201435891A (zh) * 2013-03-04 2014-09-16 Winbond Electronics Corp 快閃記憶體的驗證裝置
CN207074249U (zh) * 2017-08-03 2018-03-06 郑州云海信息技术有限公司 一种电路板测试用辅助治具
CN207624550U (zh) * 2017-11-08 2018-07-17 阳光电源股份有限公司 用于插件式电容器的固定装置、机箱以及电机控制器
CN109946590A (zh) * 2019-04-11 2019-06-28 苏州浪潮智能科技有限公司 一种板卡转接设备和测试系统
CN111816242A (zh) * 2020-09-04 2020-10-23 苏州浪潮智能科技有限公司 一种测试治具转接板及记忆体测试装置

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115243479A (zh) * 2022-07-25 2022-10-25 联宝(合肥)电子科技有限公司 多功能半成品测试治具
CN120849204A (zh) * 2025-09-23 2025-10-28 浪潮电子信息产业股份有限公司 一种重定时器测试装置、方法及电子设备

Also Published As

Publication number Publication date
CN111816242A (zh) 2020-10-23
CN111816242B (zh) 2021-02-19

Similar Documents

Publication Publication Date Title
WO2022048286A1 (zh) 一种测试治具转接板及记忆体测试装置
US7491066B1 (en) Patch panel
JP2014516474A (ja) 周辺回路と共に用いられるマザーボード上方インターポーザー
CN103092737A (zh) 具有固态硬盘速率指示功能的电脑系统
CN201413379Y (zh) 测试板
CN102999096B (zh) 计算机
CN206602524U (zh) 一种用于光模块测试的转换板
CN111929620B (zh) 一种支持edsff-1c标准的接口的测试装置
CN108169663A (zh) 一种具有防呆调试接口的pcb板
CN107870834B (zh) 一种硬盘背板的测试治具
CN108897653A (zh) 一种服务器及其板卡
CN219285243U (zh) 一种测试平台
CN210182075U (zh) 一种内存条电源电路的短路测试装置
CN115509984A (zh) 一种pcie端口顺序识别系统及方法
CN107515317A (zh) 一种电源测试治具及测试方法
CN100573158C (zh) 一种先进夹层子卡测试通用载板及制作方法
CN219248153U (zh) 一种多功能转接印刷线路板
CN201436662U (zh) 存储器测试制具
CN223941362U (zh) 一种PCIe信号槽位拓展设备
CN219224997U (zh) 子卡在位检测电路、电子设备和子卡在位检测系统
CN115691645A (zh) 一种硬盘浪涌电流测试治具及测试方法
CN101881897B (zh) 测试治具及背光逆变器模块的测试方法
CN212009552U (zh) 可插拔的板卡调试装置
CN100517514C (zh) 存储器测试卡具
CN116301224B (zh) 连接器、电子保险装置以及板卡

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 21863354

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 21863354

Country of ref document: EP

Kind code of ref document: A1