WO2022048276A1 - 失调电压校正电路及失调电压校正方法 - Google Patents

失调电压校正电路及失调电压校正方法 Download PDF

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WO2022048276A1
WO2022048276A1 PCT/CN2021/103166 CN2021103166W WO2022048276A1 WO 2022048276 A1 WO2022048276 A1 WO 2022048276A1 CN 2021103166 W CN2021103166 W CN 2021103166W WO 2022048276 A1 WO2022048276 A1 WO 2022048276A1
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signal
data
offset
mos transistor
enable
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PCT/CN2021/103166
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English (en)
French (fr)
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张志强
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长鑫存储技术有限公司
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Priority to EP21863344.4A priority Critical patent/EP4181399A4/en
Priority to US17/647,901 priority patent/US11349467B2/en
Publication of WO2022048276A1 publication Critical patent/WO2022048276A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
    • H03M1/0617—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
    • H03K5/24—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
    • H03K5/2472—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors
    • H03K5/2481—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors with at least one differential stage
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/022—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in I/O circuitry
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/028—Detection or location of defective auxiliary circuits, e.g. defective refresh counters with adaption or trimming of parameters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/12005—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details comprising voltage or current generators
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/1201—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details comprising I/O circuitry
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1048—Data bus control circuits, e.g. precharging, presetting, equalising
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
    • H03F3/45183—Long tailed pairs
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/45475—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using IC blocks as the active amplifying circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45479—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection
    • H03F3/45928—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection using IC blocks as the active amplifying circuit
    • H03F3/45968—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection using IC blocks as the active amplifying circuit by offset reduction
    • H03F3/45991—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection using IC blocks as the active amplifying circuit by offset reduction by using balancing means
    • H03F3/45995—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection using IC blocks as the active amplifying circuit by offset reduction by using balancing means using switching means
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/10—Calibration or testing
    • H03M1/1009—Calibration
    • H03M1/1014—Calibration at one point of the transfer characteristic, i.e. by adjusting a single reference value, e.g. bias or gain error
    • H03M1/1023—Offset correction
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45291—Indexing scheme relating to differential amplifiers the active amplifying circuit [AAC] comprising balancing means
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45368—Indexing scheme relating to differential amplifiers the AAC comprising multiple transistors parallel coupled at their sources only, e.g. in a cascode dif amp, only those forming the composite common source transistor

Definitions

  • the present disclosure relates to, but is not limited to, an offset voltage correction circuit and an offset voltage correction method.
  • the operational amplifier is a basic analog circuit function module and is widely used. However, the input stage of the operational amplifier will introduce offset voltage.
  • the trim enable module is turned on by an enable signal, and the trim enable module generates an enable identification signal based on the comparison result between the theoretical indication signal and the data indication signal, and the offset The correction module cancels the offset signal generated in the data acquisition module based on the enable identification signal, thereby ensuring that the data indicating signal is consistent with the theoretical indicating signal, thereby avoiding errors in the acquired data indicating signal caused by the offset signal.
  • the offset voltage correction method is turned on by an enable signal, an enable identification signal is generated based on the comparison result of the theoretical indication signal and the data indication signal, and an enable identification signal is generated based on the enable identification signal.
  • the generated offset signal is offset, so as to ensure that the data indicating signal is consistent with the theoretical indicating signal, thereby avoiding the error of the acquired data indicating signal caused by the offset signal.
  • FIG. 2 is a schematic diagram of a specific structure of a data acquisition module provided by the first embodiment of the present disclosure
  • FIG. 3 is a schematic diagram of a specific structure of a data receiving unit provided by the first embodiment of the present disclosure
  • FIG. 4 is a schematic structural diagram of the calibration MOS transistor array provided by the first embodiment of the present disclosure.
  • FIG. 5 is a schematic structural diagram of a calibration sequence provided by the first embodiment of the present disclosure.
  • FIG. 6 is a schematic flowchart of an offset voltage correction method provided by the second embodiment of the present disclosure.
  • a data acquisition module 111, a data receiving unit; 121, a data comparison unit;
  • the first embodiment of the present disclosure provides an offset voltage correction circuit, including: a data acquisition module, configured to receive a data signal and a reference signal, and obtain a data indication according to a comparison result between the reference signal and the offset data signal Signal, the offset data signal is the data signal after superimposing the offset signal; the trim enable module is used to receive the data signal, the reference signal, the data indication signal and the enable signal; if the enable signal is high level, according to the data signal The theoretical indication signal is obtained by comparing the result with the reference signal, and based on the comparison result between the theoretical indication signal and the data indication signal, an enable identification signal is generated; the offset correction module is used to cancel the offset signal based on the enable identification signal.
  • a data acquisition module configured to receive a data signal and a reference signal, and obtain a data indication according to a comparison result between the reference signal and the offset data signal Signal, the offset data signal is the data signal after superimposing the offset signal
  • the trim enable module is used to receive the data signal, the reference signal, the data indication signal and the enable
  • the offset voltage correction circuit 100 includes: a data acquisition module 101 , a trim enable module 102 and an offset correction module 103 .
  • the data acquisition module 101 is configured to receive a data signal and a reference signal, and obtain a data indication signal according to a comparison result between the reference signal and the offset data signal, where the offset data signal is a data signal after superimposing the offset signal.
  • the trim enable module 102 is used to receive the data signal, the reference signal, the data indication signal and the enable signal; if the enable signal is at a high level, obtain the theoretical indication signal according to the comparison result between the data signal and the reference signal, and Based on the comparison result of the theoretical indication signal and the data indication signal, the enable identification signal is generated.
  • the offset correction module 103 is configured to cancel the offset signal generated in the data acquisition module 101 based on the enable identification signal.
  • the data acquisition module 101 includes a data receiving unit 111 and a data comparing unit 121 .
  • the data receiving unit 111 has a first input terminal and a second input terminal, the first input terminal is used for receiving the data signal, and the second input terminal is used for receiving the reference signal.
  • the data comparing unit 121 has an input end connected to the output end of the data receiving unit 111, and is used for comparing the reference signal and the data signal after superimposing the offset signal to obtain a data indication signal.
  • the data receiving unit 111 is an amplifier, and the data receiving unit 121 is a comparator; the first input terminal of the data receiving unit 111 is used to receive the data signal, that is, the positive input terminal is used to receive the data signal, and the data signal is the DQ signal, and the DQ signal is a continuous analog signal; the second input terminal of the data receiving unit 121 is used to receive the reference signal, that is, the negative input terminal is used to receive the reference signal, the reference signal is the VREFDQ signal, and the VREFDQ signal is a continuous analog signal .
  • the data receiving unit 111 amplifies the received DQ signal and the VREFDQ signal and inputs them to the data comparing unit 121 , and the data receiving unit 121 compares the received signals to obtain a data indication signal.
  • the data indication signal obtained by the data comparison unit 121 is at a low level, that is, the DQ_int signal is at a low level; if the DQ signal is greater than the VREFDQ signal, the data indication signal obtained by the data comparison unit 121 is at a high level, That is, the DQ_int signal is high.
  • an offset signal will be introduced and superimposed on the data signal, and the data signal after the offset signal will be superimposed will cause the result of the data signal to be larger or smaller, resulting in a larger or smaller signal than the reference signal.
  • the data signal becomes smaller, or the data signal originally smaller than the reference signal becomes larger, thereby causing the acquired data to indicate an error in the signal.
  • the above-mentioned data receiving unit 111 as an amplifier and data comparison unit 121 as a comparator is an implementation manner of the data receiving unit 111 and the data comparison unit 121 provided in this embodiment, and does not constitute a limitation to this embodiment.
  • the data receiving unit 111 at least includes a receiving differential amplifying circuit for amplifying the received data signal and the reference signal.
  • the data signal and the reference signal are received through the differential amplifier circuit, so that the application range of the offset voltage correction circuit is wide.
  • the receiving differential amplifier circuit includes a first differential MOS transistor 305 and a second differential MOS transistor 304, the gate of the first differential MOS transistor 305 is used for receiving data signals, and the source of the first differential MOS transistor 305 is used for connection
  • the first load 302 the gate of the second differential MOS transistor 304 is used to receive the reference signal, the source of the second differential MOS transistor is used to connect the second load 301; the drain of the first differential MOS transistor 305 and the second differential MOS transistor
  • the drain of the transistor 304 is connected to the same current source 303, so that the first differential MOS transistor 305 and the second differential MOS transistor 304 form a differential pair.
  • the first load 302 and the second load 301 may adopt the same load circuit.
  • the receiving unit 112 is configured to receive a data signal, a reference signal, a data indication signal and an enable signal.
  • the trim enable module 102 works based on the enable signal.
  • the enable signal is at a high level
  • the first comparison unit 132 and the second comparison unit 142 are turned on, and the trim enable module 102 starts to work;
  • the signal is at a low level
  • the first comparison unit 132 and the second comparison unit 142 are turned off, and the trim enabling module 102 stops working.
  • the first comparison unit 132 is configured to compare the data signal and the reference signal, and obtain the theoretical indication signal based on the comparison result between the data signal and the reference signal.
  • the second comparison unit 142 is configured to compare the theoretical indication signal and the data indication signal, and generate an enable identification signal based on the comparison result of the theoretical indication signal and the data indication signal.
  • the offset correction module 103 includes: a control unit 113 and a correction unit 123 .
  • the calibration MOS tube array includes the calibration MOS tubes of N branches in parallel.
  • the width-length ratio of the calibration MOS tubes of the N branches is doubled according to the exponential relationship of 2, and the equivalent width-length ratio of the MOS tubes of the N branches is doubled. After that, it is smaller than the second differential MOS transistor 304, and N is a natural number greater than or equal to 1.
  • the calibration MOS tube array further includes: a switch MOS tube connected in series with the calibration MOS tube on each branch; the drain of the calibration MOS tube is connected to the drain of the second differential MOS tube, and the calibration MOS tube
  • the source of the switch MOS tube is connected to the source of the switch MOS tube, and the source of the switch MOS tube is connected to the source of the second differential MOS tube.
  • the calibration MOS tube 407 on the first branch of the calibration MOS tube array is connected to the first switch MOS tube 406 ; the calibration MOS tube on the second branch of the calibration MOS tube array is connected 417 is connected to the second switch MOS tube 416; the calibration MOS tube 427 on the third branch of the calibration MOS tube array is connected to the third switch MOS tube 426; the calibration MOS tube 437 on the Nth branch of the calibration MOS tube array is connected to the Nth Switch MOS transistor 436 .
  • the switch MOS transistor is used for judging whether the branch is turned on according to the control signal, so as to change the equivalent width to length ratio of the second differential MOS transistor 304 , thereby correspondingly amplifying the received reference signal to offset the offset signal.
  • the control signal is Code ⁇ N:0> shown in Figure 2 and Figure 3, Code ⁇ N:0> is an N-bit binary number, 1 represents high level, 0 represents low level, and high level is used for The corresponding branch of the correction MOS tube array is turned on, and the low level is used to turn off the corresponding branch of the correction MOS tube array.
  • the signal Code ⁇ 4:0> of four branches is used for description.
  • the DQ_BF enable signal and the enable signal enabled by the ZQCL command jump from low level to high level, and the enable signal is used to control the trim enable module 102 Work
  • the DQ_BF enable signal is used to control the work of the offset correction module 103, until the DQ_BF enable signal and the enable signal jump from high level to low level, the correction stops; the period from receiving the ZQCL command until the correction stops is ZQCL Command-controlled correction time TZQoper.
  • the trim enable module is turned on by the enable signal, the trim enable module generates an enable identification signal based on the comparison result of the theoretical indication signal and the data indication signal, and the offset correction module is based on the enable identification signal
  • the offset signal generated in the data acquisition module is offset, so as to ensure that the data indicating signal is consistent with the theoretical indicating signal, thereby avoiding the error of the acquired data indicating signal caused by the offset signal.
  • a logical unit may be a physical unit, a part of a physical unit, or a combination of multiple physical units.
  • this embodiment does not introduce units that are not closely related to solving the technical problems raised by the present disclosure, but this does not mean that there are no other units in this embodiment.
  • the second embodiment of the present disclosure relates to an offset voltage correction method.
  • FIG. 6 is a schematic flowchart corresponding to the offset voltage correction method provided by the present embodiment. The following will describe the offset voltage correction method provided by the present embodiment in detail with reference to FIG. 6. The same or corresponding parts as the first embodiment will not be described below Describe in detail.
  • the offset voltage correction method includes the following steps:
  • the data signal is the actual DQ signal received by the data acquisition module, and the actual DQ signal is a continuous analog signal.
  • the reference signal is the VREFDQ signal, and the reference signal is used to compare with the actual DQ signal, so as to obtain a signal used to characterize the high and low levels, so as to control the corresponding function of the memory.
  • Step 502 acquiring a data indication signal.
  • a data indication signal is obtained, and the offset data signal is a data signal after superimposing the offset signal. If the reference signal is greater than the data signal after superimposing the offset signal, the acquired data indication signal is low level, that is, the DQ_int signal is low level; if the reference signal is smaller than the data signal after superimposing the offset signal, the acquired data indication signal is High level, that is, the DQ_int signal is high level.
  • Step 503 Obtain an enable signal, and determine whether the enable signal is at a high level.
  • the enable signal is obtained. If the enable signal is high, the correction of the offset signal is started, that is, step 504 is entered; if the enable signal is low, the correction of the offset signal is not performed, and the end step is entered.
  • the enable signal is generated based on the ZQCL (ZQ Calibration Long) command
  • the ZQCL command is an internal memory command used for system power-on initialization and device reset in ZQ calibration, that is, the offset voltage correction circuit in this embodiment works based on internal commands, with Stable work environment and safety.
  • Step 504 obtaining a theoretical indication signal.
  • Step 505 generating an enable identification signal.
  • the enable identification signal is generated.
  • the theoretical indication signal and the data indication signal are the same, that is, the introduction of the offset voltage has little effect on the acquired data indication signal, and the enable identification signal generated at this time is low level; when the theoretical indication signal and the data indication signal are not At the same time, that is, the introduction of the offset voltage has a great influence on the acquired data indication signal, and the enable identification signal generated at this time is a high level.
  • Step 506 compensating the offset signal superimposed in the data signal.
  • the offset signal superimposed in the data signal is compensated.
  • a method for adjusting an offset correction module includes: acquiring, based on a control signal, a target on-off state of each MOS transistor in the MOS transistor array for correcting; acquiring an actual on-off state of each MOS transistor in the correcting MOS transistor array; The actual on-off state is adjusted based on the target on-off state shown; the offset signal superimposed on the data signal is compensated by changing the reference signal.
  • this embodiment can be implemented in cooperation with the first embodiment.
  • the relevant technical details mentioned in the first embodiment are still valid in this embodiment, and the technical effects that can be achieved in the first embodiment can also be achieved in this embodiment. In order to reduce repetition, details are not repeated here. Correspondingly, the relevant technical details mentioned in this embodiment can also be applied in the first embodiment.
  • the offset voltage correction method is turned on by an enable signal, an enable identification signal is generated based on the comparison result of the theoretical indication signal and the data indication signal, and the generated offset is offset based on the enable identification signal. signal, so as to ensure that the data indication signal is consistent with the theoretical indication signal, thereby avoiding the error of the acquired data indication signal caused by the offset signal.

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Abstract

本公开提供一种失调电压校正电路及失调电压校正方法，其中，失调电压校正电路包括：数据获取模块，用于接收数据信号和基准信号，并根据基准信号和失调数据信号的比较结果获取数据指示信号，失调数据信号为叠加失调信号后的数据信号；修调使能模块，用于接收数据信号、基准信号、数据指示信号以及使能信号；若使能信号为高电平，则根据数据信号和基准信号的比较结果，获取理论指示信号，并基于理论指示信号与数据指示信号的比较结果，生成使能标识信号；失调校正模块，用于基于使能标识信号抵消失调信号。

Description

失调电压校正电路及失调电压校正方法
本公开要求在2020年09月02日提交中国专利局、申请号为202010910741.9、发明名称为“失调电压校正电路及失调电压校正方法”的中国专利申请的优先权，其全部内容通过引用结合在本公开中。
技术领域
本公开涉及但不限于一种失调电压校正电路及失调电压校正方法。
背景技术
存储器在信号的传输过程中，广泛应用了各种运算放大器，运算放大器是一个基本的模拟电路功能模块，被非常广泛的应用，然而，运算放大器的输入级会引入失调电压。
由输入的模拟信号通过运算放大器进行信号转换得到数字信号的过程中，由于运算放大器的输入失调电压，可能存在对模拟信号进行误转换的过程，这一过程严重影响了信号传输的准确性，从而严重影响了存储器的使用。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本公开的一些实施例提供了一种失调电压校正电路，包括：数据获取模块，设置为接收数据信号和基准信号，并根据基准信号和失调数据信号的比较结果获取数据指示信号，失调数据信号为叠加失调信号后的数据信号；修调使能模块，设置为接收数据信号、基准信号、数据指示信号以及使能信号；若使能信号为高电平，则根据数据信号和基准信号的比较结果，获取理论指示信号，并基于理论指示信号与数据指示信号的比较结果，生成使能标识信号；失调校正模块，设置为基于使能标识信号抵消失调信号。
与现有技术相比，本公开提供的失调电压校正电路，通过使能信号开启修调使能模块，修调使能模块基于理论指示信号和数据指示信号的比较结果生成 使能标识信号，失调校正模块基于使能标识信号抵消数据获取模块中产生的失调信号，从而保证数据指示信号与理论指示信号一致，从而避免了由于失调信号造成的获取的数据指示信号的误差。
本公开实施例还提供了一种失调电压校正方法，应用于存储器，包括：接收数据信号和基准信号；基于基准信号和失调数据信号的比较结果，获取数据指示信号，失调数据信号为叠加失调信号后的数据信号；获取使能信号，当使能信号为高电平，基于数据信号和基准信号的比较结果，获取理论指示信号；基于数据指示信号和理论指示信号的比较结果，生成使能标识信号；基于使能标识信号，抵消失调信号。
相比于现有技术而言，本公开提供的失调电压校正方法，通过使能信号开启失调电压校正方法，基于理论指示信号和数据指示信号的比较结果生成使能标识信号，基于使能标识信号抵消产生的失调信号，从而保证数据指示信号与理论指示信号一致，从而避免了由于失调信号造成的获取的数据指示信号的误差。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
并入到说明书中并且构成说明书的一部分的附图示出了本公开的实施例，并且与描述一起用于解释本公开实施例的原理。在这些附图中，类似的附图标记用于表示类似的要素。下面描述中的附图是本公开的一些实施例，而不是全部实施例。对于本领域技术人员来讲，在不付出创造性劳动的前提下，可以根据这些附图获得其他的附图。
图1为本公开第一实施例提供的失调电压校正电路的模拟结构示意图；
图2为本公开第一实施例提供的数据获取模块的具体结构示意图；
图3为本公开第一实施例提供的数据接收单元的具体结构示意图；
图4为本公开第一实施例提供的校正MOS管阵列的结构示意图；
图5为本公开第一实施例提供的校正时序的结构示意图；
图6为本公开第二实施例提供的失调电压校正方法的流程示意图。
附图标记：
100、失调电压校正电路；
101、数据获取模块；111、数据接收单元；121、数据比较单元；
102、修调使能模块；112、接收单元；122、判断单元；132、第一比较单元；142、第二比较单元；
103、失调校正模块；113、控制单元；123、校正单元；
305、第一差分MOS管；304、第二差分MOS管；302、第一负载；301、第二负载；303、电流源；306、校正开关MOS管；307、407、417、427、437、校正MOS管；406、一开关MOS管；416、第二开关MOS管；436、第三开关MOS管。
具体实施方式
目前，由输入的模拟信号通过运算放大器进行信号转换得到数字信号的过程中，由于运算放大器的输入失调电压，可能存在对模拟信号进行误转换的过程，这一过程严重影响了信号传输的准确性，从而严重影响了存储器的使用。
为解决上述问题，本公开的第一实施例提供了一种失调电压校正电路，包括：数据获取模块，用于接收数据信号和基准信号，并根据基准信号和失调数据信号的比较结果获取数据指示信号，失调数据信号为叠加失调信号后的数据信号；修调使能模块，用于接收数据信号、基准信号、数据指示信号以及使能信号；若使能信号为高电平，则根据数据信号和基准信号的比较结果，获取理论指示信号，并基于理论指示信号与数据指示信号的比较结果，生成使能标识信号；失调校正模块，用于基于使能标识信号抵消失调信号。
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合附图对本公开的各实施例进行详细的阐述。然而，本领域的技术人员可以理解，在本公开各实施例中，为了使读者更好地理解本申请而提出了许多技术细节。但是，即使没有这些技术细节和基于以下各实施例的种种变化和修改，也可以实现本申请所要求保护的技术方案。以下各个实施例的划分是为了描述方便，不应对本公开的具体实现方式构成任何限定，各个实施例在不矛盾的前提下可以相互 结合，相互引用。
图1为本实施例提供的失调电压校正电路对应的模拟结构示意图，下面结合图1对本实施例提供的失调电压校正电路进行具体说明。
参考图1，失调电压校正电路100，包括：数据获取模块101、修调使能模块102和失调校正模块103。
数据获取模块101，用于接收数据信号和基准信号，并根据基准信号和失调数据信号的比较结果，获取数据指示信号，所述失调数据信号为叠加失调信号后的数据信号。
修调使能模块102，用于接收数据信号、基准信号、数据指示信号以及使能信号；若使能信号为高电平，则根据数据信号和基准信号的比较结果，获取理论指示信号，并基于理论指示信号与数据指示信号的比较结果，生成使能标识信号。
失调校正模块103，用于基于使能标识信号抵消数据获取模块101中产生的失调信号。
数据获取模块101包括数据接收单元111和数据比较单元121。
数据接收单元111，具有第一输入端和第二输入端，第一输入端用于接收数据信号，第二输入端用于接收基准信号。
数据比较单元121，输入端连接数据接收单元111的输出端，用于比较基准信号和叠加失调信号后的数据信号，获取数据指示信号。
参考图2，数据接收单元111为一放大器，数据接收单元121为一比较器；数据接收单元111的第一输入端用于接收数据信号，即正输入端用于接收数据信号，数据信号即DQ信号，且DQ信号为连续的模拟信号；数据接收单元121的第二输入端用于接收基准信号，即负输入端用于接收基准信号，基准信号即VREFDQ信号，且VREFDQ信号为连续的模拟信号。数据接收单元111对接收到的DQ信号和VREFDQ信号进行放大后输入到数据比较单元121中，数据接收单元121对接收到的信号进行比较获取数据指示信号。
若DQ信号小于VREFDQ信号，数据比较单元121获取的数据指示信号为低电平，即DQ_int信号为低电平；若DQ信号大于VREFDQ信号，数据比较 单元121获取的数据指示信号为高电平，即DQ_int信号为高电平。
在数据接收单元111接收数据信号和基准信号的过程中，会引入失调信号叠加在数据信号上，叠加失调信号后的数据信号会导致数据信号的结果偏大或者偏小，导致原本大于基准信号的数据信号变小，或原本小于基准信号的数据信号变大，从而导致获取的数据指示信号错误。
上述以数据接收单元111为放大器和数据比较单元121为比较器，是本实施例提供的一种数据接收单元111和数据比较单元121的实现方式，并不构成对本实施例的限定。
在本公开的一些实施例中，数据接收单元111至少包括接收差分放大电路，用于对接收的数据信号和基准信号进行放大。通过差分放大电路来接收数据信号和基准信号，使得失调电压校正电路的应用范围广。
参考图3，接收差分放大电路包括第一差分MOS管305和第二差分MOS管304，第一差分MOS管305的栅极用于接收数据信号，第一差分MOS管305的源极用于连接第一负载302，第二差分MOS管304的栅极用于接收基准信号，第二差分MOS管的源极用于连接第二负载301；第一差分MOS管305的漏极和第二差分MOS管304的漏极连接同一电流源303，使得第一差分MOS管305和第二差分MOS管304构成差分对。
在本公开的一个实施例中，第一负载302和第二负载301可以采用同一负载电路。
第二差分MOS管304并联有校正MOS管校正电路，校正电路包括校正开关MOS管306和校正MOS管307，校正MOS管307的宽长比小于第二差分MOS管304的宽长比，用于改变第二差分MOS管304的等效宽长比，从而改变对基准信号的放大效果，以抵消失调信号。
继续参考图1，修调使能模块102包括：接收单元112、判断单元122、第一比较单元132和第二比较单元142。
接收单元112，用于接收数据信号、基准信号、数据指示信号和使能信号。
使能信号基于ZQCL(ZQ Calibration Long)命令产生，ZQCL命令为ZQ校准中用于系统上电初始化和器件复位的存储器内部命令，即本实施例中失调 电压校正电路是基于内部命令工作，具有稳定的工作环境和安全性。
判断单元122，用于判断使能信号是否为高电平，当使能信号为高电平时，导通第一比较单元132和第二比较单元142。
即修调使能模块102是基于使能信号工作的，当使能信号为高电平时，导通第一比较单元132和第二比较单元142，修调使能模块102开始工作；当使能信号为低电平时，关断第一比较单元132和第二比较单元142，修调使能模块102停止工作。
第一比较单元132，用于比较数据信号和基准信号，并基于数据信号和基准信号的比较结果，获取理论指示信号。
第二比较单元142，用于比较理论指示信号和数据指示信号，并基于理论指示信号和数据指示信号的比较结果，生成使能标识信号。
当理论指示信号和数据指示信号相同时，即引入失调电压后对获取的数据指示信号并无太大影响，此时产生的使能标识信号为低电平；当理论指示信号和数据指示信号不同时，即引入失调电压后对获取的数据指示信号产生了较大影响，此时产生的使能标识信号为高电平。
继续参考图1，失调校正模块103包括：控制单元113和校正单元123。
控制单元113，用于接收使能标识信号，并基于使能标识信号生成相应的控制信号。
校正单元123，基于控制信号，改变内部晶体管阵列的导通情况，以补偿数据获取模块101中产生的失调信号。
在本公开的一些实施例中，参考图4，校正单元123包括：与第二差分MOS管并联的校正MOS管阵列。
校正MOS管阵列包括并列的N个支路的校正MOS管，N个支路的校正MOS管的宽长比按照2的指数关系成倍增加，N个支路的MOS管的等效宽长比之后小于第二差分MOS管304，N为大于等于1的自然数。
若第1个支路的校正MOS管407宽长比为m，第2个支路的校正MOS管417的宽长比为2m，第3个支路的校正MOS管427的宽长比为4m，第N个支路的校正MOS管子437的宽长比为2 N-1m。此时N个支路的校正MOS管的等 效宽长比之和为(2 N-1)m小于第二差分MOS管304的宽长比，从而基于设置的阵列支路数N以确定m的数值大小。
在本公开的一些实施例中，校正MOS管阵列还包括：每个支路上与校正MOS管串联的开关MOS管；校正MOS管的漏极与第二差分MOS管的漏极相连，校正MOS管的源极与开关MOS管的源极相连，开关MOS管的源极与第二差分MOS管的源极相连。
在本公开的一个实施例中，参考图4，校正MOS管阵列的第1个支路上的校正MOS管407连接第一开关MOS管406；校正MOS管阵列的第2个支路上的校正MOS管417连接第二开关MOS管416；校正MOS管阵列的第3个支路上的校正MOS管427连接第三开关MOS管426；校正MOS管阵列的第N个支路上的校正MOS管437连接第N开关MOS管436。开关MOS管用于根据控制信号，判断是否导通所在支路，从而改变第二差分MOS管304的等效宽长比，从而相应放大接收的基准信号，以抵消失调信号。
控制信号即图2和图3中所示的Code<N:0>，Code<N:0>是一个N位的二进制数，1代表高电平，0代表低电平，高电平用于导通相应的校正MOS管阵列的支路，低电平用于关断相应的校正MOS管阵列的支路。在本公开的一个实施例中，以4条支路的信号Code<4:0>进行说明，例如Code<4:0>为1110，即Code<0>＝0、Code<1>＝1、Code<2>＝1、Code<3>＝1；相应导通校正MOS管的第2支路、第3支路和第4支路，并关断校正MOS管阵列的第1支路。
参考图5，当接收到ZQCL命令后，经过一个时钟延时，基于ZQCL命令开启的DQ_BF enable信号和enable信号由低电平跳变到高电平，enable信号用于控制修调使能模块102工作，DQ_BF enable信号用于控制失调校正模块103工作，直到DQ_BF enable信号和enable信号由高电平跳变为低电平，校正停止；从接收到ZQCL命令，直到校正停止的这一段时间为ZQCL命令控制的校正时间TZQoper。
本公开提出的失调电压校正电路，通过使能信号开启修调使能模块，修调使能模块基于理论指示信号和数据指示信号的比较结果生成使能标识信号，失调校正模块基于使能标识信号抵消数据获取模块中产生的失调信号，从而保证数据指示信号与理论指示信号一致，从而避免了由于失调信号造成的获取的数 据指示信号的误差。
本实施例中所涉及到的各模块均为逻辑模块，在实际应用中，一个逻辑单元可以是一个物理单元，也可以是一个物理单元的一部分，还可以以多个物理单元的组合实现。此外，为了突出本公开的创新部分，本实施例中并没有将与解决本公开所提出的技术问题关系不太密切的单元引入，但这并不表明本实施例中不存在其它的单元。
本公开第二实施例涉及一种失调电压校正方法。
图6为本实施例提供的失调电压校正方法对应的流程示意图，以下将结合图6对本实施例提供的失调电压校正方法进行详细说明，与第一实施例相同或相应的部分，以下将不做详细赘述。
参考图6，失调电压校正方法，包括以下步骤：
步骤501，接收数据信号和基准信号。
数据信号即数据获取模块接收的实际DQ信号，实际DQ信号为连续的模拟信号。基准信号即VREFDQ信号，基准信号用于与实际DQ信号进行对比，从而获取一个用于表征高低电平的信号，从而控制存储器的相应功能。
步骤502，获取数据指示信号。
基于基准信号和失调数据信号的比较结果，获取数据指示信号，失调数据信号为叠加失调信号后的数据信号。若基准信号大于叠加失调信号后的数据信号，则获取的数据指示信号为低电平，即DQ_int信号为低电平；若基准信号小于叠加失调信号后的数据信号，则获取的数据指示信号为高电平，即DQ_int信号为高电平。
步骤503，获取使能信号，并判断使能信号是否为高电平。
获取使能信号，若使能信号为高电平，则开启执行失调信号的校正，即进入步骤504；若使能信号为低电平，则不执行失调信号的校正，即进入结束步骤。
使能信号基于ZQCL(ZQ Calibration Long)命令产生，ZQCL命令为ZQ校准中用于系统上电初始化和器件复位的存储器内部命令，即本实施例中失调电压校正电路是基于内部命令工作的，具有稳定的工作环境和安全性。
步骤504，获取理论指示信号。
基于数据信号和基准信号的比较结果，获取理论指示信号。若基准信号大于数据信号，则获取的理论指示信号为低电平；若基准信号小于数据信号，则获取的理论指示信号为高电平。
步骤505，生成使能标识信号。
基于数据指示信号和理论指示信号的比较结果，生成使能标识信号。当理论指示信号和数据指示信号相同时，即引入失调电压后对获取的数据指示信号并无太大影响，此时产生的使能标识信号为低电平；当理论指示信号和数据指示信号不同时，即引入失调电压后对获取的数据指示信号产生了较大影响，此时产生的使能标识信号为高电平。
步骤506，补偿数据信号中叠加的失调信号。
基于使能标识信号，补偿数据信号中叠加的失调信号。
判断使能标识信号的状态，若使能标识信号为高电平，则根据使能标识信号生成相应的控制信号；若使能标识信号低电平，则不生成控制信号。根据控制信号，调整失调校正模块，以抵消失调信号。
在本公开的一个实施例中，调整失调校正模块的方法包括：基于控制信号，获取校正MOS管阵列中每个MOS管的目标通断状态；获取校正MOS管阵列中每个MOS管的实际通断状态；基于所示目标通断状态，调整实际通断状态；通过改变基准信号，以补偿数据信号中叠加的失调信号。
相比于现有技术而言，通过使能信号开启失调电压校正方法，基于理论指示信号和数据指示信号的比较结果生成使能标识信号，基于使能标识信号抵消产生的失调信号，从而保证数据指示信号与理论指示信号一致，从而避免了由于失调信号造成的获取的数据指示信号的误差。
上面各种步骤划分，只是为了描述清楚，实现时可以合并为一个步骤或者对某些步骤进行拆分，分解为多个步骤，只要包括相同的逻辑关系，都在本专利的保护范围内；对流程中添加无关紧要的修改或者引入无关紧要的设计，但不改变其流程的核心设计都在该专利的保护范围内。
由于第一实施例与本实施例相互对应，因此本实施例可与第一实施例互相 配合实施。第一实施例中提到的相关技术细节在本实施例中依然有效，在第一实施例中所能达到的技术效果在本实施例中也同样可以实现，为了减少重复，这里不再赘述。相应地，本实施例中提到的相关技术细节也可应用在第一实施例中。
本领域技术人员在考虑说明书及实践的公开后，将容易想到本公开的其它实施方案。本公开旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由下面的权利要求指出。
应当理解的是，本公开并不局限于上面已经描述并在附图中示出的精确结构，并且可以在不脱离其范围进行各种修改和改变。本公开的范围仅由所附的权利要求来限制。公开公开
工业实用性
本公开提出的失调电压校正电路及失调电压校正方法，通过使能信号开启失调电压校正方法，基于理论指示信号和数据指示信号的比较结果生成使能标识信号，基于使能标识信号抵消产生的失调信号，从而保证数据指示信号与理论指示信号一致，从而避免了由于失调信号造成的获取的数据指示信号的误差。

Claims (13)

  1. 一种失调电压校正电路，其中，所述失调电压校正电路包括：
    数据获取模块，设置为接收数据信号和基准信号，并根据所述基准信号和失调数据信号的比较结果获取数据指示信号，所述失调数据信号为叠加失调信号后的数据信号；
    修调使能模块，设置为接收所述数据信号、所述基准信号、所述数据指示信号以及使能信号；若所述使能信号为高电平，则根据所述数据信号和所述基准信号的比较结果，获取理论指示信号，并基于所述理论指示信号与所述数据指示信号的比较结果，生成使能标识信号；
    失调校正模块，设置为基于所述使能标识信号抵消所述失调信号。
  2. 根据权利要求1所述的失调电压校正电路，其中，所述数据获取模块包括：
    数据接收单元，具有第一输入端和第二输入端，所述第一输入端设置为接收所述数据信号，所述第二输入端设置为接收所述基准信号；
    数据比较单元，输入端连接所述数据接收单元的输出端，设置为比较所述基准信号和叠加失调信号后的所述数据信号，获取所述数据指示信号。
  3. 根据权利要求2所述的失调电压校正电路，其中，所述数据接收单元至少包括接收差分放大电路，设置为对接收的所述数据信号和所述基准信号进行放大。
  4. 根据权利要求3所述的失调电压校正电路，其中，所述接收差分放大电路包括：第一差分MOS管和第二差分MOS管；
    所述第一差分MOS管的栅极设置为接收所述数据信号，所述第一差分MOS管的源极设置为连接第一负载；所述第二差分MOS管的栅极设置为接收所述基准信号，所述第二差分MOS管的源极设置为连接第二负载；
    所述第一差分MOS管的漏极与所述第二差分MOS管的漏极连接同一电流源，使得所述第一差分MOS管与所述第二差分MOS管构成差分对。
  5. 根据权利要求4所述的失调电压校正电路，其中，所述第一负载和所述第二负载采用同一负载电路。
  6. 根据权利要求2所述的失调电压校正电路，其中，所述数据比较单元包括比较器。
  7. 根据权利要求1所述的失调电压校正电路，其中，所述修调使能模块包括：
    接收单元，设置为接收所述数据信号、所述基准信号、所述数据指示信号和所述使能信号；
    判断单元，设置为判断所述使能信号是否为高电平，当所述使能信号为高电平，导通第一比较单元和第二比较单元；
    所述第一比较单元，设置为比较所述数据信号和所述基准信号，并基于所述数据信号和所述基准信号的比较结果，获取所述理论指示信号；
    所述第二比较单元，设置为比较所述理论指示信号和所述数据指示信号，并基于所述理论指示信号和所述数据指示信号的比较结果，生成所述使能标识信号。
  8. 根据权利要求4所述的失调电压校正电路，其中，所述失调校正模块包括：
    控制单元，设置为接收所述使能标识信号，并基于所述使能标识信号生成相应的控制信号；
    校正单元，基于所述控制信号，改变内部晶体管阵列的导通情况，以抵消所述失调信号。
  9. 根据权利要求8所述的失调电压校正电路，其中，所述校正单元包括：
    与所述第二差分MOS管并联的校正MOS管阵列；
    所述校正MOS管阵列包括：并列的N个支路的校正MOS管；
    所述N个支路的校正MOS管的宽长比按照2的指数关系成倍增加，且所述N个支路的MOS管的等效宽长比之和小于所述第二差分MOS管；
    所述N为大于等于1的自然数。
  10. 根据权利要求9所述的失调电压校正电路，其中，所述校正MOS管阵 列还包括：每个支路上与所述校正MOS管串联的开关MOS管；
    所述校正MOS管的漏极与所述第二差分MOS管的漏极相连，所述校正MOS管的源极与所述开关MOS管的漏极相连，所述开关MOS管的源极与所述第二差分MOS管的源极相连；
    所述开关MOS管设置为根据所述控制信号，判断是否导通所在支路。
  11. 一种失调电压校正方法，应用于存储器，其中，所述失调电压校正方法包括：
    接收数据信号和基准信号；
    基于所述基准信号和失调数据信号的比较结果，获取数据指示信号，所述失调数据信号为叠加失调信号后的数据信号；
    获取使能信号，当所述使能信号为高电平，基于所述数据信号和所述基准信号的比较结果，获取理论指示信号；
    基于所述数据指示信号和所述理论指示信号的比较结果，生成使能标识信号；
    基于所述使能标识信号，抵消所述失调信号。
  12. 根据权利要求11所述的失调电压校正方法，其中，所述基于所述使能标识信号，抵消所述失调信号，包括：
    判断所述使能标识信号的状态；
    若所述使能标识信号为高电平，则根据所述使能标识信号，生成相应的控制信号；若所述使能标识信号为低电平，则不生成控制信号；
    根据所述控制信号，调整失调校正模块，以抵消所述失调信号。
  13. 根据权利要求12所述的失调电压校正方法，其中，所述根据所述控制信号，调整失调校正模块，以抵消所述失调信号，包括：
    基于所述控制信号，获取校正MOS管阵列中每个MOS管的目标通断状态；
    获取所述校正MOS管阵列中每个MOS管的实际通断状态；
    基于所述目标通断状态，调整所述实际通断状态。
PCT/CN2021/103166 2020-09-02 2021-06-29 失调电压校正电路及失调电压校正方法 WO2022048276A1 (zh)

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