WO2022048274A1 - 测试系统以及测试方法 - Google Patents

测试系统以及测试方法 Download PDF

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Publication number
WO2022048274A1
WO2022048274A1 PCT/CN2021/103029 CN2021103029W WO2022048274A1 WO 2022048274 A1 WO2022048274 A1 WO 2022048274A1 CN 2021103029 W CN2021103029 W CN 2021103029W WO 2022048274 A1 WO2022048274 A1 WO 2022048274A1
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Prior art keywords
clock signal
memory
tested
duty cycle
signal
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English (en)
French (fr)
Inventor
潘宜飞
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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Priority to US17/504,836 priority Critical patent/US11380413B2/en
Publication of WO2022048274A1 publication Critical patent/WO2022048274A1/zh
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/023—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in clock generator or timing circuitry
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/10—Test algorithms, e.g. memory scan [MScan] algorithms; Test patterns, e.g. checkerboard patterns 
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the present disclosure relates to, but is not limited to, a testing system and testing method.
  • the work of the memory is realized based on the clock signal, but there is no clock source inside the memory to provide the clock signal, that is, the work of the memory requires an externally input clock signal, so the clock signal tolerance test of the memory is required.
  • the clock signal tolerance test is to obtain the minimum duty cycle that makes the memory work normally; if the memory works on the falling edge, the clock signal tolerance test is to obtain the maximum duty cycle that makes the memory work normally. Compare.
  • An embodiment of the present disclosure provides a test system, including: a signal providing module configured to provide a first clock signal and a second clock signal for a memory to be tested; the memory to be tested executes a write command based on the first clock signal, so that the memory to be tested The memory stores preset data, and the memory to be tested executes a read command based on the second clock signal to read the stored data stored in the memory to be tested; one of the first clock signal and the second clock signal is a symmetric clock signal, and the other is an asymmetric clock signal with a preset duty cycle; the processing module is configured to obtain stored data, and obtain the clock signal tolerance of the memory to be tested according to the comparison result between the stored data and the preset data.
  • the memory to be tested executes the read command and the write command based on the symmetric clock signal and the asymmetric clock signal provided by the signal providing module respectively, and the memory to be tested executes the read command based on the symmetric clock signal.
  • the command or write command can completely read the stored data in the memory under test, or completely store the data to be stored in the memory under test. It can be seen that the error caused by the symmetric clock signal is small; the memory under test is based on the asymmetric clock.
  • the read command or write command executed by the signal because the interval time between each rising edge and falling edge of the asymmetric clock signal is different, the memory may not be able to read data/write data normally.
  • the processing module can accurately obtain the error caused by the operation of the memory under the asymmetric clock through the comparative test of the symmetric clock signal and the asymmetric clock signal, so as to accurately judge the clock signal tolerance of the memory.
  • the embodiment of the present disclosure also provides a test method, which is applied to a test machine, including: acquiring preset data; when it is detected that the test machine sends a write command for the memory to be tested, providing a first clock signal to the memory to be tested to Make the memory to be tested store preset data; when it is detected that the test machine sends a read command for the memory to be tested, a second clock signal is provided for the memory to be tested to read the stored data stored in the memory to be tested; the first clock signal and the first clock signal One of the two clock signals is a symmetric clock signal, and the other is an asymmetric clock signal with a preset duty cycle; acquiring stored data; comparing the stored data with the preset data, and comparing the stored data with the preset data As a result, the clock signal tolerance of the memory under test is obtained.
  • the memory under test executes the read command and the write command based on the symmetric clock signal and the asymmetric clock signal respectively, and the memory under test executes the read command or write command based on the symmetric clock signal.
  • the command can completely read out the stored data in the memory to be tested, or completely store the data to be stored in the memory to be tested. It can be seen that the error caused by the symmetric clock signal is small; the memory to be tested is executed based on the asymmetric clock signal. For a read command or a write command, since the interval between each rising edge and falling edge of the asymmetric clock signal is different, the memory may not be able to read/write data normally.
  • the error caused by the asymmetric clock signal is large.
  • the error caused by the memory operating under the asymmetric clock can be accurately obtained, so as to accurately judge the clock signal tolerance of the memory.
  • FIG. 1 is a schematic structural diagram of a test system provided by a first embodiment of the present disclosure
  • FIG. 2 is a schematic flowchart of a testing method provided by a second embodiment of the present disclosure.
  • 100 testing system; 101, signal providing module; 121, processing unit; 103, judging subunit; 104, calling subunit; 111, command providing unit; 201, first signal providing unit; 202, second signal providing unit; 102 , a processing module; 112, an acquisition unit; 122, a first adjustment unit; 132, a second adjustment unit.
  • the first embodiment of the present disclosure provides a test system, including: a signal providing module for providing a first clock signal and a second clock signal for the memory to be tested; the memory to be tested executes the test based on the first clock signal write command, so that the memory to be tested stores preset data, and the memory to be tested executes a read command based on the second clock signal to read the stored data stored in the memory to be tested; one of the first clock signal and the second clock signal is a symmetric clock signal, and the other is an asymmetric clock signal with a preset duty cycle; the processing module is used to obtain the stored data, and obtain the clock signal tolerance of the memory to be tested according to the comparison result between the stored data and the preset data Spend.
  • FIG. 1 is a schematic flowchart of a test system provided by an embodiment of the present disclosure. The test method provided by the present embodiment will be described in detail below with reference to the accompanying drawings.
  • a testing system 100 includes: a signal providing module 101 and a processing module 102 .
  • the signal providing module 101 is used to provide a first clock signal and a second clock signal for the memory to be tested.
  • the memory to be tested executes a write command based on the first clock signal, so that the memory to be tested stores preset data; the memory to be tested executes a read command based on the second clock signal to read the stored data stored in the memory to be tested.
  • the stored data is the preset data stored by the aforementioned write command.
  • One of the first clock signal and the second clock signal is a symmetrical clock signal, and the other is an asymmetrical clock signal with a preset duty cycle, wherein the symmetrical clock signal is a clock signal with a duty cycle of 50%, and the non-symmetrical clock signal is a clock signal with a duty cycle of 50%.
  • a symmetric clock signal is a clock signal whose duty cycle is not 50%.
  • the signal providing module 101 includes: a command providing unit 111 and a processing unit 121 .
  • the command providing unit 111 is configured to provide control commands for the memory to be tested, and the control commands at least include write commands and read commands.
  • the processing unit 121 is used to detect the control command provided by the command providing unit 111 for the memory to be tested. When a write command is detected, the signal providing module 101 provides a first clock signal to the memory to be tested, and when a read command is detected, the signal providing module 101 provides a second clock signal to the memory to be tested.
  • the processing unit 121 includes: a judging subunit 103 and a calling subunit 104 .
  • the judging subunit 103 is configured to send a first control signal to the calling subunit 104 when a write command is detected.
  • the subunit 104 is invoked, for the control signal providing module 101 to provide a first clock signal to the memory under test based on the first control signal.
  • the judging subunit 103 is further configured to send a second control signal to the calling subunit 104 when a read command is detected.
  • the calling subunit 104 is also used for, based on the second control signal, the control signal providing module 101 to provide the second clock signal to the memory under test.
  • the signal providing module 101 further includes: a first signal providing unit 201 and a second signal providing unit 202 .
  • the endurance test of the memory if the execution of the read command and the write command is based on the symmetric clock signal, the endurance test of the memory cannot be realized; if the execution of the read command and the write command is based on the asymmetric clock signal , due to the large error in the reading process and the writing process, a single read/write process based on the asymmetric clock signal will obtain a tolerance result, and two read/write processes based on the asymmetric clock signal will result in a The signal tolerance test results are inaccurate.
  • the first signal providing unit 201 is configured to provide a first clock signal, and the first clock signal is an asymmetric clock signal with a preset duty cycle.
  • the second signal providing unit 202 is configured to provide a second clock signal, which is a symmetric clock signal, that is, the memory under test uses an asymmetric clock signal to execute a write command, and a symmetric clock signal to execute a read command.
  • the memory to be tested uses an asymmetrical clock signal to execute the write command.
  • the interval between each rising edge and falling edge of the asymmetrical clock signal is different. There may be a time sequence in which data cannot be written normally, thus causing the memory to fail to work normally.
  • the data signal stored in the memory to be tested by the clock signal is 101.
  • the memory to be tested uses a symmetrical clock signal to execute the read command. The interval between each rising edge and falling edge of the symmetrical clock signal is the same, and the stored data in the memory to be tested can be read out. That is, the read command executed by the symmetrical clock signal can be read out. Correctly obtain the stored data in the memory to be tested, and the stored data read out at this time is 101. If the stored data is different from the preset stored data, it means that the asymmetric clock signal of the memory to be tested cannot work normally under the current duty cycle.
  • the first signal providing unit 201 is configured to provide a first clock signal, and the first clock signal is a symmetric clock signal.
  • the second signal providing unit 202 is configured to provide a second clock signal, and the second clock signal is an asymmetric clock signal with a preset duty cycle, that is, the memory to be tested uses a symmetric clock signal to execute a write command, and an asymmetric clock signal is used to execute a read command Order.
  • This embodiment takes the test of three storage units in the memory to be tested as an example and describes the performance in detail, assuming that the default data is 111.
  • the memory to be tested uses a symmetric clock signal to execute the write command.
  • the interval between each rising edge and the falling edge of the symmetric clock signal is the same, and the preset storage data can be completely stored in the memory to be tested, that is, the write command executed by the symmetric clock signal , the preset data can be correctly written into the memory to be tested, and the data signal written to the memory to be tested is 111 at this time.
  • the memory to be tested uses an asymmetric clock signal to execute the read command. The interval between each rising edge and falling edge of the asymmetric clock signal is different.
  • the clock signal reads the data signal stored in the memory under test as 101, and the stored data is different from the preset stored data, which means that the asymmetric clock signal of the memory under test cannot work normally under the current duty cycle.
  • the processing module 102 is configured to acquire the stored data, and acquire the clock signal tolerance of the memory to be tested according to the comparison result between the stored data and the preset data.
  • the processing module 102 includes: an acquisition unit 112 for acquiring stored data, and generating a clock adjustment signal according to a comparison result between the stored data and the preset data; the signal providing module 101 adjusts the preset duty cycle based on the clock adjustment signal until the acquisition Clock signal tolerance of the memory under test.
  • the clock signal tolerance is used to characterize, and when the error between the stored data and the preset data is within a preset range, the minimum duty cycle of the asymmetric clock signal Compare.
  • the error between the stored data and the preset data that is, the ratio of the different data between the stored data and the preset data to the total data of the stored data. Since the memory to be tested works on the rising edge, that is, the high level is active, the smaller the duty cycle of the asymmetric clock signal, the shorter the normal working time of the memory to be tested, thereby obtaining the clock signal tolerance of the memory to be tested.
  • the processing module 102 further includes: a first adjustment unit 112 and a second adjustment unit 122 .
  • the first adjustment unit 112 is configured to reduce the preset duty cycle if the clock signal tolerance of the memory to be tested under the preset duty cycle indicates that the memory to be tested is operating normally.
  • the second adjustment unit 122 is configured to increase the preset duty cycle if the clock signal tolerance of the memory to be tested under the preset duty cycle indicates that the memory to be tested cannot operate normally.
  • the adjustment method of the preset duty cycle is obtained, and the preset duty cycle is adjusted by feedback, so as to obtain the clock signal tolerance of the memory to be tested.
  • the clock signal tolerance is used to characterize, and when the error between the stored data and the preset data is within a preset range, the maximum duty cycle of the asymmetric clock signal Compare.
  • the error between the stored data and the preset data that is, the ratio of the different data between the stored data and the preset data to the total data of the stored data. Since the memory to be tested works on the falling edge, that is, the low level is active, the larger the duty cycle of the asymmetric clock signal, the shorter the normal working time of the memory to be tested, thereby obtaining the clock signal tolerance of the memory to be tested.
  • the processing module 102 further includes: a first adjustment unit 112 and a second adjustment unit 122 .
  • the first adjustment unit 112 is used to increase the preset duty cycle if the clock signal tolerance of the memory to be tested under the preset duty cycle indicates that the memory to be tested is running normally.
  • the second adjustment unit 122 is configured to reduce the preset duty cycle if the clock signal tolerance of the memory to be tested under the preset duty cycle indicates that the memory to be tested cannot operate normally.
  • the adjustment method of the preset duty cycle is obtained, and the preset duty cycle is adjusted by feedback, so as to obtain the clock signal tolerance of the memory to be tested.
  • the memory to be tested executes the read command and executes the write command
  • the conversion of the first clock signal and the second clock signal is executed.
  • the switching of the first clock signal and the second clock signal is performed in timing.
  • the memory to be tested executes the read command and the write command based on the symmetric clock signal and the asymmetric clock signal provided by the signal providing module, respectively.
  • the stored data in the memory to be tested is completely read, or the data to be stored is completely stored in the memory to be tested. It can be seen that the error caused by the symmetric clock signal is small; the read command or write executed by the memory to be tested based on the asymmetric clock signal Command, because the interval time between each rising edge and falling edge of the asymmetric clock signal is different, the memory may not be able to read data/write data normally. It can be seen that the error caused by the asymmetric clock signal is large.
  • the processing module can accurately obtain the error caused by the memory operating under the asymmetric clock through the comparative test of the symmetric clock signal and the asymmetric clock signal, so as to accurately judge the clock signal tolerance of the memory.
  • a logical unit may be a physical unit, a part of a physical unit, or a combination of multiple physical units.
  • this embodiment does not introduce units that are not closely related to solving the technical problems raised by the present disclosure, but this does not mean that there are no other units in this embodiment.
  • the second embodiment of the present disclosure relates to a testing method.
  • FIG. 2 is a schematic flowchart of the test method provided by the embodiment of the present disclosure.
  • the test method provided by the present embodiment will be described in detail below with reference to the accompanying drawings. The same or corresponding parts as the first embodiment will not be described in detail below.
  • test method applied to the test machine, includes the following steps:
  • Step 301 Acquire preset data.
  • the preset data is the data signal that needs to be stored when the memory to be tested executes the write command.
  • three storage cells in the memory to be tested are taken as an example for detailed description, and it is assumed that the preset data is 111.
  • Step 302 based on the first clock signal, for the memory to be tested to store preset data.
  • Step 303 based on the second clock signal, read the stored data of the memory to be tested.
  • test machine When it is detected that the test machine issues a write command for the memory to be tested, it provides a first clock signal for the memory to be tested, so that the memory to be tested stores preset data; when it is detected that the test machine issues a read command to the memory to be tested, The test memory provides a second clock signal to read the memory data stored in the test memory.
  • One of the first clock signal and the second clock signal is a symmetric clock signal, and the other is an asymmetric clock signal.
  • Step 304 acquiring stored data.
  • the memory to be tested uses an asymmetric clock signal to execute a write command, and the interval time between each rising edge and falling edge of the asymmetric clock signal is different, and there may be a time sequence in which data cannot be written normally, resulting in The memory cannot work normally, that is, the data signal stored in the memory to be tested using an asymmetric clock signal is 101.
  • the memory to be tested uses a symmetrical clock signal to execute the read command. The interval between each rising edge and falling edge of the symmetrical clock signal is the same, and the stored data in the memory to be tested can be read out. That is, the read command executed by the symmetrical clock signal can be read out. Correctly obtain the stored data in the memory to be tested, and the stored data read out at this time is 101.
  • the memory to be tested uses a symmetric clock signal to execute the write command, and the interval time between each rising edge and the falling edge of the symmetric clock signal is the same, and the preset storage data can be completely stored in the memory to be tested, That is, the write command executed by the symmetrical clock signal can correctly write the preset data into the memory to be tested, and the data signal written to the memory to be tested is 111 at this time.
  • the memory to be tested uses an asymmetric clock signal to execute the read command.
  • the interval between each rising edge and falling edge of the asymmetric clock signal is different. There may be a timing that cannot read data normally, which will cause the memory to fail to work normally.
  • the clock signal reads out the data signal stored in the memory to be tested as 101.
  • the error caused by the memory under the asymmetric clock can be accurately obtained, so as to accurately judge the clock signal tolerance of the memory.
  • Step 305 Obtain the clock signal tolerance of the memory to be tested.
  • the clock signal tolerance of the memory to be tested is obtained.
  • the clock signal tolerance is used to characterize, and when the error between the stored data and the preset data is within a preset range, the minimum duty cycle of the asymmetric clock signal Compare.
  • the error between the stored data and the preset data that is, the ratio of the different data between the stored data and the preset data to the total data of the stored data. Since the memory to be tested works on the rising edge, that is, the high level is active, the smaller the duty cycle of the first clock signal and the second clock signal, the shorter the normal working time of the memory to be tested, so as to obtain the clock signal resistance of the memory to be tested. Acceptance.
  • the clock signal tolerance is used to characterize, and when the error between the stored data and the preset data is within a preset range, the maximum duty cycle of the asymmetric clock signal Compare.
  • the error between the stored data and the preset data that is, the ratio of the different data between the stored data and the preset data to the total data of the stored data. Since the memory to be tested works on the falling edge, that is, the low level is active, the larger the duty ratio of the first clock signal and the second clock signal, the shorter the normal working time of the memory to be tested, so as to obtain the clock signal resistance of the memory to be tested. Acceptance.
  • Step 306 adjusting the preset duty cycle.
  • the preset duty cycle is adjusted in the following manner:
  • the preset duty cycle is reduced; if the clock signal tolerance of the memory to be tested under the preset duty cycle indicates that the memory to be tested If the memory is not functioning properly, increase the preset duty cycle.
  • the preset duty cycle is adjusted in the following manner:
  • the preset duty cycle is increased; if the clock signal tolerance of the memory to be tested under the preset duty cycle indicates that the memory to be tested If the memory is not functioning properly, reduce the preset duty cycle.
  • the adjustment method of the preset duty cycle is obtained, and the preset duty cycle is adjusted by feedback. After the feedback adjustment, go to step 302 and repeat the above steps , so as to obtain the clock signal tolerance of the memory under test.
  • the memory to be tested executes the read command and executes the write command
  • the conversion of the first clock signal and the second clock signal is executed.
  • the switching of the first clock signal and the second clock signal is performed in timing.
  • the memory under test executes the read command and the write command based on the symmetric clock signal and the asymmetric clock signal, respectively.
  • the memory under test executes the read command or write command based on the symmetric clock signal. It can be seen that the error caused by the symmetric clock signal is small; the read command or write command executed by the memory to be tested based on the asymmetric clock signal, because the The interval time between each rising edge and falling edge of the asymmetric clock signal is different, and the memory may not be able to read/write data normally. It can be seen that the error caused by the asymmetric clock signal is large. Through the comparative test of the symmetric clock signal and the asymmetric clock signal, the error caused by the memory working under the asymmetric clock can be accurately obtained, so as to accurately judge the clock signal tolerance of the memory.
  • this embodiment can be implemented in cooperation with the first embodiment.
  • the relevant technical details mentioned in the first embodiment are still valid in this embodiment, and the technical effects that can be achieved in the first embodiment can also be achieved in this embodiment. In order to reduce repetition, details are not repeated here. Correspondingly, the relevant technical details mentioned in this embodiment can also be applied in the first embodiment.
  • test system and test method provided by the present disclosure can accurately obtain the error caused by the memory operating under the asymmetric clock through the comparative test of the symmetric clock signal and the asymmetric clock signal, so as to accurately judge the clock signal tolerance of the memory.

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Abstract

一种测试系统以及测试方法，其中，测试系统包括：信号提供模块，用于为待测存储器提供第一时钟信号和第二时钟信号；待测存储器基于第一时钟信号执行写命令，以使待测存储器存储预设数据，待测存储器基于第二时钟信号执行读命令，以读取待测存储器存储的存储数据；第一时钟信号和第二时钟信号的其中一者为对称时钟信号，另一者为具有预设占空比的非对称时钟信号；处理模块，用于获取存储数据，并根据存储数据和预设数据的比较结果，获取待测存储器的时钟信号耐受度。

Description

测试系统以及测试方法
本公开要求在2020年09月07日提交中国专利局、申请号为202010929507.0、发明名称为“测试系统以及测试方法”的中国专利申请的优先权，其全部内容通过引用结合在本公开中。
技术领域
本公开涉及但不限于一种测试系统以及测试方法。
背景技术
存储器的工作是基于时钟信号实现的，但存储器的内部并没有时钟源来提供时钟信号，即存储器的工作需要通过外部输入的时钟信号，因此需要对存储器进行时钟信号耐受度测试。
若存储器工作在上升沿，时钟信号耐受度测试，即获取使得存储器正常工作的最小占空比；若存储器工作在下降沿，时钟信号耐受度测试，即获取使得存储器正常工作的最大占空比。
然而，目前对时钟信号耐受度测试存在较大误差，无法获取存储器的实际性能参数。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本公开的实施例提供了一种测试系统，包括：信号提供模块，设置成为待测存储器提供第一时钟信号和第二时钟信号；待测存储器基于第一时钟信号执行写命令，以使待测存储器存储预设数据，待测存储器基于第二时钟信号执行读命令，以读取待测存储器存储的存储数据；第一时钟信号和第二时钟信号的其中一者为对称时钟信号，另一者为具有预设占空比的非对称时钟信号；处理 模块，设置为获取存储数据，并根据存储数据和预设数据的比较结果，获取待测存储器的时钟信号耐受度。
与现有技术相比，本公开提供的测试系统，待测存储器执行读命令和写命令，分别基于信号提供模块提供的对称时钟信号和非对称时钟信号，待测存储器基于对称时钟信号执行的读命令或写命令，能将待测存储器中的存储数据完整读出，或将需要存储的数据完整存储进待测存储器，由此可见，对称时钟信号引起的误差小；待测存储器基于非对称时钟信号执行的读命令或写命令，由于非对称时钟信号每个上升沿和下降沿的间隔时间不相同，存储器可能无法正常读出数据/写入数据，由此可见，非对称时钟信号引起的误差大。处理模块通过对称时钟信号和非对称时钟信号的对照测试，可以准确的获取存储器工作在非对称时钟下造成的误差，从而准确的判断存储器的时钟信号耐受度。
本公开实施例还提供了一种测试方法，应用于测试机台，包括：获取预设数据；当检测到测试机台为待测存储器发出写命令，为待测存储器提供第一时钟信号，以使待测存储器存储预设数据；当检测到测试机台为待测存储器发出读命令，为待测存储器提供第二时钟信号，以读取待测存储器存储的存储数据；第一时钟信号和第二时钟信号的其中一者为对称时钟信号，另一者为具有预设占空比的非对称时钟信号；获取存储数据；比较存储数据和预设数据，并根据存储数据和预设数据的比较结果，获取待测存储器的时钟信号耐受度。
相比于现有技术而言，本公开提供的测试方法，待测存储器执行读命令和写命令，分别基于对称时钟信号和非对称时钟信号，待测存储器基于对称时钟信号执行的读命令或写命令，能将待测存储器中的存储数据完整读出，或将需要存储的数据完整存储进待测存储器，由此可见，对称时钟信号引起的误差小；待测存储器基于非对称时钟信号执行的读命令或写命令，由于非对称时钟信号每个上升沿和下降沿的间隔时间不相同，存储器可能无法正常读出数据/写入数据，由此可见，非对称时钟信号引起的误差大。通过对称时钟信号和非对称时钟信号的对照测试，可以准确的获取存储器工作在非对称时钟下造成的误差，从而准确的判断存储器的时钟信号耐受度。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
并入到说明书中并且构成说明书的一部分的附图示出了本公开的实施例，并且与描述一起用于解释本公开实施例的原理。在这些附图中，类似的附图标记用于表示类似的要素。下面描述中的附图是本公开的一些实施例，而不是全部实施例。对于本领域技术人员来讲，在不付出创造性劳动的前提下，可以根据这些附图获得其他的附图。
一个或多个实施例通过与之对应的附图中的图片进行示例性说明，除非有特别申明，附图中的图不构成比例限制。
图1为本公开第一实施例提供的测试系统的结构示意图；
图2为本公开第二实施例提供的测试方法的流程示意图。
附图标记：
100、测试系统；101、信号提供模块；121、处理单元；103、判断子单元；104、调用子单元；111、命令提供单元；201第一信号提供单元；202、第二信号提供单元；102、处理模块；112、获取单元；122、第一调整单元；132、第二调整单元。
具体实施方式
目前，目前对时钟信号耐受度测试存在较大误差，无法获取存储器的实际性能参数。
为解决上述问题，本公开第一实施例提供了一种测试系统，包括：信号提供模块，用于为待测存储器提供第一时钟信号和第二时钟信号；待测存储器基于第一时钟信号执行写命令，以使待测存储器存储预设数据，待测存储器基于第二时钟信号执行读命令，以读取待测存储器存储的存储数据；第一时钟信号和第二时钟信号的其中一者为对称时钟信号，另一者为具有预设占空比的非对称时钟信号；处理模块，用于获取存储数据，并根据存储数据和预设数据的比较结果，获取待测存储器的时钟信号耐受度。
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合附图对本公开的各实施例进行详细的阐述。然而，本领域的技术人员可以理解，在本 公开各实施例中，为了使读者更好地理解本申请而提出了许多技术细节。但是，即使没有这些技术细节和基于以下各实施例的种种变化和修改，也可以实现本申请所要求保护的技术方案。以下各个实施例的划分是为了描述方便，不应对本公开的具体实现方式构成任何限定，各个实施例在不矛盾的前提下可以相互结合，相互引用。
图1为本公开实施例提供的测试系统的流程示意图，以下将结合附图对本实施例提供的测试方法进行详细说明。
参考图1，测试系统100，包括：信号提供模块101和处理模块102。
信号提供模块101，用于为待测存储器提供第一时钟信号和第二时钟信号。
待测存储器基于第一时钟信号执行写命令，以使待测存储器存储预设数据；待测存储器基于第二时钟信号执行读命令，以读取所述待测存储器存储的存储数据，读取的存储数据即前述写命令存储的预设数据。
第一时钟信号和第二时钟信号的其中一者为对称时钟信号，另一者为具有预设占空比的非对称时钟信号，其中对称时钟信号即占空比为50％的时钟信号，非对称时钟信号即占空比不为50％的时钟信号。
信号提供模块101包括：命令提供单元111和处理单元121。
命令提供单元111，用于为待测存储器提供控制命令，控制命令至少包括写命令和读命令。
处理单元121用于检测命令提供单元111为待测存储器提供的控制命令。当检测到写命令，信号提供模块101向待测存储器提供第一时钟信号，当检测到读命令，信号提供模块101向待测存储器提供第二时钟信号。
处理单元121包括：判断子单元103和调用子单元104。
判断子单元103，用于当检测到写命令，向调用子单元104发送第一控制信号。调用子单元104，用于基于第一控制信号，控制信号提供模块101向待测存储器提供第一时钟信号。
判断子单元103还用于，当检测到读命令，向调用子单元104发送第二控制信号。调用子单元104还用于，基于第二控制信号，控制信号提供模块101 向待测存储器提供第二时钟信号。
在本实施例中，信号提供模块101还包括：第一信号提供单元201和第二信号提供单元202。
在对存储器进行耐受度的测试中，若读命令和写命令的执行都基于对称时钟信号，则无法实现对存储器的耐受度测试；若读命令和写命令的执行都基于非对称时钟信号，由于读取过程和写入过程都存在较大误差，单次基于非对称时钟信号的读/写过程会获取一个耐受度结果，两次基于非对称时钟信号的读/写过程会导致获取的信号耐受度的测试结果不准确。
在公开的一些实施例中，第一信号提供单元201用于提供第一时钟信号，第一时钟信号为具有预设占空比的非对称时钟信号。第二信号提供单元202用于提供第二时钟信号，第二时钟信号为对称时钟信号，即待测存储器采用非对称时钟信号执行写命令，采用对称时钟信号执行读命令。
本实施例以测试待测存储器中三个存储单元为例进行详细描述，假设预设数据为111。待测存储器采用非对称时钟信号执行写命令，非对称时钟信号每个上升沿和下降沿的间隔时间不相同，可能存在无法正常写入数据的时序，从而导致存储器无法正常工作，即采用非对称时钟信号存入待测存储器的数据信号为101。待测存储器采用对称时钟信号执行读命令，对称时钟信号每个上升沿和下降沿的间隔时间相同，可以将待测存储器中的存储数据完成读出，即采用对称时钟信号执行的读命令，可以正确的获取待测存储器中的存储数据，此时读出的存储数据为101，存储数据与预设存储数据不同，则表示待测存储器在当前占空比下的非对称时钟信号无法正常工作。
上述以三个存储单元对本实施例的测试原理进行详细描述，其目的在于使本领域技术人员理解本实施例的测试原理，并不构成对本实施例的限定，在具体使用过程中，可以根据实际需要测试的存储单元的数量执行上述测试流程。
在本公开的一些实施例中，第一信号提供单元201用于提供第一时钟信号，第一时钟信号为对称时钟信号。第二信号提供单元202用于提供第二时钟信号，第二时钟信号为具有预设占空比的非对称时钟信号，即待测存储器采用对称时钟信号执行写命令，采用非对称时钟信号执行读命令。
本实施例以测试待测存储器中三个存储单元为例及性能详细描述，假设预设数据为111。待测存储器采用对称时钟信号执行写命令，对称时钟信号每个上升沿和下降沿的间隔时间相同，可以将预设存储数据完整地存入待测存储器中，即采用对称时钟信号执行的写命令，可以正确的向待测存储器中写入预设数据，此时写入待测存储器的数据信号为111。待测存储器采用非对称时钟信号执行读命令，非对称时钟信号每个上升沿和下降沿的间隔时间不相同，可能存在无法正常读出数据的时序，从而导致存储器无法正常工作，即采用非对称时钟信号读出待测存储器存储的数据信号为101，存储数据与预设存储数据不同，则表示待测存储器在当前占空比下的非对称时钟信号无法正常工作。
上述以三个存储单元对本实施例的测试原理进行详细描述，其目的在于使本领域技术人员理解本实施例的测试原理，并不构成对本实施例的限定，在具体使用过程中，可以根据实际需要测试的存储单元的数量执行上述测试流程。
处理模块102，用于获取存储数据，并根据存储数据和预设数据的比较结果，获取待测存储器的时钟信号耐受度。
处理模块102包括：获取单元112，用于获取存储数据，并根据存储数据和预设数据的比较结果，生成时钟调整信号；信号提供模块101基于时钟调整信号，调整预设占空比，直至获取待测存储器的时钟信号耐受度。
在本公开的一些实施例中，若待测存储器工作在上升沿，时钟信号耐受度用于表征，存储数据和预设数据的误差在预设范围内时，非对称时钟信号的最小占空比。存储数据和预设数据的误差，即存储数据和预设数据的不同的数据占存储数据总数据的比例。由于待测存储器工作在上升沿，即高电平有效，非对称时钟信号的占空比越小，待测存储器正常工作的时间越短，从而获取待测存储器的时钟信号耐受度。
处理模块102还包括：第一调整单元112和第二调整单元122。
第一调整单元112，若预设占空比下待测存储器的时钟信号耐受度表征待测存储器正常运行，用于降低预设占空比。
第二调整单元122，若预设占空比下待测存储器的时钟信号耐受度表征待测存储器无法正常运行，用于提高预设占空比。
通过前一次测试中的预设占空比下存储器的耐受度测试结果，获取预设占空比的调整方式对预设占空比进行反馈调节，从而获取待测存储器的时钟信号耐受度。
在本公开的一些实施例中，若待测存储器工作在下降沿，时钟信号耐受度用于表征，存储数据和预设数据的误差在预设范围内时，非对称时钟信号的最大占空比。存储数据和预设数据的误差，即存储数据和预设数据的不同的数据占存储数据总数据的比例。由于待测存储器工作在下降沿，即低电平有效，非对称时钟信号的占空比越大，待测存储器正常工作的时间越短，从而获取待测存储器的时钟信号耐受度。
处理模块102还包括：第一调整单元112和第二调整单元122。
第一调整单元112，若预设占空比下待测存储器的时钟信号耐受度表征待测存储器正常运行，用于提高预设占空比。
第二调整单元122，若预设占空比下待测存储器的时钟信号耐受度表征待测存储器无法正常运行，用于降低预设占空比。
通过前一次测试中的预设占空比下存储器的耐受度测试结果，获取预设占空比的调整方式对预设占空比进行反馈调节，从而获取待测存储器的时钟信号耐受度。
在本实施例中，在待测存储器执行读命令和执行写命令时，执行第一时钟信号和第二时钟信号的转换，在其他实施例中，可以在执行读命令和写命令之间的其他时序中执行第一时钟信号和第二时钟信号的切换。
与现有技术相比，待测存储器执行读命令和写命令，分别基于信号提供模块提供的对称时钟信号和非对称时钟信号，待测存储器基于对称时钟信号执行的读命令或写命令，能将待测存储器中的存储数据完整读出，或将需要存储的数据完整存储进待测存储器，由此可见，对称时钟信号引起的误差小；待测存储器基于非对称时钟信号执行的读命令或写命令，由于非对称时钟信号每个上升沿和下降沿的间隔时间不相同，存储器可能无法正常读出数据/写入数据，由此可见，非对称时钟信号引起的误差大。处理模块通过对称时钟信号和非对称时钟信号的对照测试，可以准确的获取存储器工作在非对称时钟下造成的误差， 从而准确的判断存储器的时钟信号耐受度。
本实施例中所涉及到的各模块均为逻辑模块，在实际应用中，一个逻辑单元可以是一个物理单元，也可以是一个物理单元的一部分，还可以以多个物理单元的组合实现。此外，为了突出本公开的创新部分，本实施例中并没有将与解决本公开所提出的技术问题关系不太密切的单元引入，但这并不表明本实施例中不存在其它的单元。
本公开第二实施例涉及一种测试方法。
图2为本公开实施例提供的测试方法的流程示意图，以下将结合附图对本实施例提供的测试方法进行详细说明，与第一实施例相同或相应的部分，以下将不做详细赘述。
参考图2，测试方法，应用于测试机台，包括以下步骤：
步骤301，获取预设数据。
预设数据即待测存储器在执行写命令时需要存储的数据信号。
在本公开的一些实施例中，以测试待测存储器中三个存储单元为例进行详细描述，假设预设数据为111。
步骤302，基于第一时钟信号，供待测存储器存储预设数据。
步骤303，基于第二时钟信号，读取待测存储器的存储数据。
当检测到测试机台为待测存储器发出写命令，为待测存储器提供第一时钟信号，以使待测存储器存储预设数据；当检测到测试机台为待测存储器发出读命令，为待测存储器提供第二时钟信号，以读取待测存储器存储的存储器数据。
第一时钟信号和第二时钟信号的其中一者为对称时钟信号，另一者为非对称时钟信号。
步骤304，获取存储数据。
获取待测存储器基于读命令读取的存储器数据信号。
在本公开的一些实施例中，待测存储器采用非对称时钟信号执行写命令，非对称时钟信号每个上升沿和下降沿的间隔时间不相同，可能存在无法正常写入数据的时序，从而导致存储器无法正常工作，即采用非对称时钟信号存入待 测存储器的数据信号为101。待测存储器采用对称时钟信号执行读命令，对称时钟信号每个上升沿和下降沿的间隔时间相同，可以将待测存储器中的存储数据完成读出，即采用对称时钟信号执行的读命令，可以正确的获取待测存储器中的存储数据，此时读出的存储数据为101。
在本公开的一些实施例中，待测存储器采用对称时钟信号执行写命令，对称时钟信号每个上升沿和下降沿的间隔时间相同，可以将预设存储数据完整地存入待测存储器中，即采用对称时钟信号执行的写命令，可以正确的向待测存储器中写入预设数据，此时写入待测存储器的数据信号为111。待测存储器采用非对称时钟信号执行读命令，非对称时钟信号每个上升沿和下降沿的间隔时间不相同，可能存在无法正常读出数据的时序，从而导致存储器无法正常工作，即采用非对称时钟信号读出待测存储器存储的数据信号为101。
通过对称时钟信号和非对称时钟信号的对照测试，可以准确的获取存储器在非对称时钟下造成的误差，从而准确的判断存储器的时钟信号耐受度。
步骤305，获取待测存储器的时钟信号耐受度。
根据存储数据和预设数据的比较结果，获取待测存储器的时钟信号耐受度。
在本公开的一些实施例中，若待测存储器工作在上升沿，时钟信号耐受度用于表征，存储数据和预设数据的误差在预设范围内时，非对称时钟信号的最小占空比。存储数据和预设数据的误差，即存储数据和预设数据的不同的数据占存储数据总数据的比例。由于待测存储器工作在上升沿，即高电平有效，第一时钟信号和第二时钟信号的占空比越小，待测存储器正常工作的时间越短，从而获取待测存储器的时钟信号耐受度。
在本公开的一些实施例中，若待测存储器工作在下降沿，时钟信号耐受度用于表征，存储数据和预设数据的误差在预设范围内时，非对称时钟信号的最大占空比。存储数据和预设数据的误差，即存储数据和预设数据的不同的数据占存储数据总数据的比例。由于待测存储器工作在下降沿，即低电平有效，第一时钟信号和第二时钟信号的占空比越大，待测存储器正常工作的时间越短，从而获取待测存储器的时钟信号耐受度。
步骤306，调整预设占空比。
根据当前占空比下待测存储器的时钟信号耐受度，调整预设占空比。
在本公开的一些实施例中，若待测存储器工作在上升沿，通过以下方式进行调整预设占空比：
若预设占空比下待测存储器的时钟信号耐受度表征待测存储器正常运行，则降低预设占空比；若预设占空比下待测存储器的时钟信号耐受度表征待测存储器无法正常运行，则提高预设占空比。
在本公开的一些实施例中，若待测存储器工作在下降沿，通过以下方式进行调整预设占空比：
若预设占空比下待测存储器的时钟信号耐受度表征待测存储器正常运行，则提高预设占空比；若预设占空比下待测存储器的时钟信号耐受度表征待测存储器无法正常运行，则降低预设占空比。
通过前一次测试中的预设占空比下存储器的耐受度测试结果，获取预设占空比的调整方式对预设占空比进行反馈调节，反馈调节后继续执行步骤302，重复以上步骤，从而获取待测存储器的时钟信号耐受度。
上述以三个存储单元对本实施例的测试原理进行详细描述，其目的在于使本领域技术人员理解本实施例的测试原理，并不构成对本实施例的限定，在具体使用过程中，可以根据实际需要测试的存储单元的数量执行上述测试流程。
在本实施例中，在待测存储器执行读命令和执行写命令时，执行第一时钟信号和第二时钟信号的转换，在其他实施例中，可以在执行读命令和写命令之间的其他时序中执行第一时钟信号和第二时钟信号的切换。
相比于现有技术而言，待测存储器执行读命令和写命令，分别基于对称时钟信号和非对称时钟信号，待测存储器基于对称时钟信号执行的读命令或写命令，能将待测存储器中的存储数据完整读出，或将需要存储的数据完整存储进待测存储器，由此可见，对称时钟信号引起的误差小；待测存储器基于非对称时钟信号执行的读命令或写命令，由于非对称时钟信号每个上升沿和下降沿的间隔时间不相同，存储器可能无法正常读出数据/写入数据，由此可见，非对称时钟信号引起的误差大。通过对称时钟信号和非对称时钟信号的对照测试，可以准确的获取存储器工作在非对称时钟下造成的误差，从而准确的判断存储器 的时钟信号耐受度。
上面各种步骤划分，只是为了描述清楚，实现时可以合并为一个步骤或者对某些步骤进行拆分，分解为多个步骤，只要包括相同的逻辑关系，都在本专利的保护范围内；对流程中添加无关紧要的修改或者引入无关紧要的设计，但不改变其流程的核心设计都在该专利的保护范围内。
由于第一实施例与本实施例相互对应，因此本实施例可与第一实施例互相配合实施。第一实施例中提到的相关技术细节在本实施例中依然有效，在第一实施例中所能达到的技术效果在本实施例中也同样可以实现，为了减少重复，这里不再赘述。相应地，本实施例中提到的相关技术细节也可应用在第一实施例中。
本领域技术人员在考虑说明书及实践的公开后，将容易想到本公开的其它实施方案。本公开旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由下面的权利要求指出。
应当理解的是，本公开并不局限于上面已经描述并在附图中示出的精确结构，并且可以在不脱离其范围进行各种修改和改变。本公开的范围仅由所附的权利要求来限制。公开公开
工业实用性
本公开所提供的测试系统以及测试方法通过对称时钟信号和非对称时钟信号的对照测试，可以准确的获取存储器工作在非对称时钟下造成的误差，从而准确的判断存储器的时钟信号耐受度。

Claims (14)

  1. 一种测试系统，其中，所述测试系统包括：
    信号提供模块，设置成为待测存储器提供第一时钟信号和第二时钟信号；
    所述待测存储器基于第一时钟信号执行写命令，以使所述待测存储器存储预设数据，所述待测存储器基于第二时钟信号执行读命令，以读取所述待测存储器存储的存储数据；
    所述第一时钟信号和所述第二时钟信号的其中一者为对称时钟信号，另一者为具有预设占空比的非对称时钟信号；
    处理模块，设置为获取所述存储数据，并根据所述存储数据和所述预设数据的比较结果，获取所述待测存储器的时钟信号耐受度。
  2. 根据权利要求1所述的测试系统，其中，所述信号提供模块包括：
    命令提供单元，设置成为所述待测存储器提供控制命令，所述控制命令至少包括所述写命令和所述读命令；
    处理单元，设置为检测所述命令提供单元为所述待测存储器提供的控制命令；
    当检测到所述写命令，所述信号提供模块向所述待测存储器提供所述第一时钟信号，当检测到所述读命令，所述信号提供模块向所述待测存储器提供所述第二时钟信号。
  3. 根据权利要求2所述的测试系统，其中，所述处理单元包括：
    判断子单元，设置为当检测到所述写命令，向调用子单元发送第一控制信号，当检测到所述读命令，向所述调用子单元发送第二控制信号；
    所述调用子单元，设置为基于所述第一控制信号，控制所述信号提供模块向所述待测存储器提供第一时钟信号，基于所述第二控制信号，控制所述信号提供模块向所述待测存储器提供第二时钟信号。
  4. 根据权利要求1所述的测试系统，其中，所述信号提供模块包括：第一 信号提供单元和第二信号提供单元；
    所述第一信号提供单元设置为提供所述第一时钟信号，所述第一时钟信号为具有预设占空比的非对称时钟信号；
    所述第二信号提供单元设置为提供所述第二时钟信号，所述第二时钟信号为对称时钟信号。
  5. 根据权利要求1所述的测试系统，其中，所述信号提供模块包括：第一信号提供单元和第二信号提供单元；
    所述第一信号提供单元设置为提供所述第一时钟信号，所述第一时钟信号为对称时钟信号；
    所述第二信号提供单元设置为提供所述第二时钟信号，所述第二时钟信号为具有预设占空比的非对称时钟信号。
  6. 根据权利要求1所述的测试系统，其中，所述处理模块包括：
    获取单元，设置为获取所述存储数据，并根据所述存储数据和所述预设数据的比较结果，生成时钟调整信号；
    所述信号提供模块基于所述时钟调整信号，调整所述预设占空比，直至获取所述待测存储器的时钟信号耐受度。
  7. 根据权利要求6所述的测试系统，其中，若所述待测存储器工作在上升沿，所述时钟信号耐受度用于表征，所述存储数据和所述预设数据的误差在预设范围内时，所述非对称时钟信号的最小占空比。
  8. 根据权利要求7所述的测试系统，其中，所述处理模块包括：
    第一调整单元，若当前占空比下所述待测存储器的时钟信号耐受度表征所述待测存储器正常运行，设置为降低所述非对称时钟信号的预设占空比；
    第二调整单元，若当前占空比下所述待测存储器的时钟信号耐受度表征所述待测存储器无法正常运行，设置为提高所述非对称时钟信号的预设占空比。
  9. 根据权利要求6所述的测试系统，其中，若所述待测存储器工作在下降沿，所述时钟信号耐受度用于表征，所述存储数据和所述预设数据的误差在预设范围内时，所述非对称时钟信号的最大占空比。
  10. 根据权利要求9所述的测试系统，其中，所述处理模块包括：
    第一调整单元，若当前占空比下所述待测存储器的时钟信号耐受度表征所述待测存储器正常运行，单元设置为提高所述非对称时钟信号的预设占空比；
    第二调整单元，若当前占空比下所述待测存储器的时钟信号耐受度表征所述待测存储器无法正常运行，设置为降低非对称时钟信号的预设占空比。
  11. 一种测试方法，应用于测试机台，其中，所述测试方法包括：
    获取预设数据；
    当检测到所述测试机台为待测存储器发出写命令，为所述待测存储器提供第一时钟信号，以使所述待测存储器存储所述预设数据；
    当检测到所述测试机台为所述待测存储器发出读命令，为所述待测存储器提供第二时钟信号，以读取所述待测存储器存储的存储数据；
    所述第一时钟信号和所述第二时钟信号的其中一者为对称时钟信号，另一者为具有预设占空比的非对称时钟信号；
    获取所述存储数据；
    比较所述存储数据和所述预设数据，并根据所述存储数据和所述预设数据的比较结果，获取所述待测存储器的时钟信号耐受度。
  12. 根据权利要求11所述的测试方法，其中，所述测试方法还包括：根据所述预设占空比下所述待测存储器的时钟信号耐受度，调整所述预设占空比。
  13. 根据权利要求12所述的测试方法，其中，所述根据所述预设占空比下所述待测存储器的时钟信号耐受度，调整所述预设占空比，包括以下步骤：
    若所述待测存储器工作在上升沿，通过以下方式进行调整所述预设占空比：
    若基于所述预设占空比的非对称信号，所述待测存储器的时钟信号耐受度表征所述待测存储器正常运行，则降低所述预设占空比；
    若基于所属预设占空比的非对称信号，所述待测存储器的时钟信号耐受度表征所述待测存储器无法正常运行，则提高预设占空比。
  14. 根据权利要求12所述的测试方法，其中，所述根据所述预设占空比下 所述待测存储器的时钟信号耐受度，调整所述预设占空比，包括以下步骤：
    若所述待测存储器工作在下降沿，通过以下方式进行调整所述预设占空比：
    若基于所述预设占空比的非对称信号，所述待测存储器的时钟信号耐受度表征所述待测存储器正常运行，则提高所述预设占空比；
    若基于所述预设占空比的非对称信号，所述待测存储器的时钟信号耐受度表征所述待测存储器无法正常运行，则降低所述预设占空比。
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