WO2022048232A1 - 半导体器件及其制作方法 - Google Patents

半导体器件及其制作方法 Download PDF

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Publication number
WO2022048232A1
WO2022048232A1 PCT/CN2021/100228 CN2021100228W WO2022048232A1 WO 2022048232 A1 WO2022048232 A1 WO 2022048232A1 CN 2021100228 W CN2021100228 W CN 2021100228W WO 2022048232 A1 WO2022048232 A1 WO 2022048232A1
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Prior art keywords
semiconductor device
connection plug
connection
active regions
test
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English (en)
French (fr)
Inventor
黄晨
蔡孟峯
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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Priority to US17/446,956 priority Critical patent/US11961774B2/en
Publication of WO2022048232A1 publication Critical patent/WO2022048232A1/zh
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P74/00—Testing or measuring during manufacture or treatment of wafers, substrates or devices
    • H10P74/27—Structural arrangements therefor
    • H10P74/273—Interconnections for measuring or testing, e.g. probe pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P74/00—Testing or measuring during manufacture or treatment of wafers, substrates or devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P74/00—Testing or measuring during manufacture or treatment of wafers, substrates or devices
    • H10P74/20—Testing or measuring during manufacture or treatment of wafers, substrates or devices characterised by the properties tested or measured, e.g. structural or electrical properties
    • H10P74/207—Electrical properties, e.g. testing or measuring of resistance, deep levels or capacitance-voltage characteristics

Definitions

  • the present application relates to the technical field of semiconductor memory devices, and in particular, to a semiconductor device and a manufacturing method thereof.
  • DRAM Dynamic Random Access Memory
  • the testing of key parameters of semiconductor devices includes the testing of resistance of semiconductor devices. For example, by performing a bit line contact resistance test, it can be tested whether the contact between the bit line contact plug and the substrate is good. However, when the current bit line contact resistance test structure is tested, there is a shallow trench isolation structure between the active regions, so when the shallow trench isolation structure in the substrate in the middle of the active region is abnormal, it will also lead to BLC (Bit Line contact) The resistance is abnormally high, so the contact between the bit line plug and the substrate cannot be accurately reflected.
  • BLC Bit Line contact
  • a semiconductor device and a method of fabricating the same are provided.
  • a semiconductor device comprising:
  • a semiconductor substrate including a plurality of chip regions and scribe lines for separating the chip regions
  • test structure is formed in the scribe line, and the test structure is used for bit line contact resistance test, and the test structure includes:
  • connection structure is located at the end of the active region, and the plurality of active regions located in the same column are connected end to end in sequence through the connection structure.
  • a method of fabricating a semiconductor device comprising:
  • connection structures are located at the ends of the active regions, and the plurality of active regions located in the same column are connected end to end in sequence through the connection structures;
  • the active region and the connection structure together constitute a test structure for bit line contact resistance test.
  • 1 is a top view of a semiconductor device including a chip area and a scribe line
  • FIG. 2 is a top view of a semiconductor device provided by an embodiment of the present application.
  • FIG. 3 is a schematic diagram of the arrangement of active regions of an exemplary semiconductor device
  • FIG. 4 is a cross-sectional view of the semiconductor device along the dotted line L2 in FIG. 2;
  • FIG. 5 is a flowchart of a method for fabricating a semiconductor device according to an embodiment of the present application.
  • Chip area-10 scribe line-20, test structure-200, active area-210, connection structure-220, first connection plug-221, second connection plug-222, metal layer-223, metal barrier layer 224, insulating layer-230, filling layer-240, shallow trench isolation structure 250, semiconductor substrate-30.
  • first doping type becomes the second doping type
  • second doping type can be the first doping type
  • the first doping type and the second doping type are different doping types, for example,
  • the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.
  • Spatial relational terms such as “under”, “below”, “below”, “under”, “above”, “above”, etc., in This may be used to describe the relationship of one element or feature to other elements or features shown in the figures. It should be understood that in addition to the orientation shown in the figures, the spatially relative terms encompass different orientations of the device in use and operation. For example, if the device in the figures is turned over, elements or features described as “below” or “beneath” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the exemplary terms “below” and “under” can encompass both an orientation of above and below. In addition, the device may also be otherwise oriented (eg, rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
  • Embodiments of the present application provide a semiconductor device including a semiconductor substrate, please refer to FIG. 1 and FIG. 2 .
  • the semiconductor substrate 30 includes a plurality of chip regions 10 and a dicing line 20 for separating the chip regions 10 ; wherein, a test structure 200 is formed in the dicing line 20 , and the test structure 200 includes an active region 210 and a connection structure 220, the active region 210 is formed in the semiconductor substrate 30, the connection structure 220 is located at the end of the active region 210, and the connection structure 220 connects a plurality of all the The active regions 210 are connected end to end in sequence, and the test structure 200 is used for bit line contact resistance test.
  • test structure 200 of the semiconductor device is usually manufactured in the same process as the semiconductor device in the semiconductor substrate 30, and the test structure 200 of the semiconductor device and the semiconductor device have a corresponding relationship with each other.
  • each layer of interconnect lines in the semiconductor device corresponds to a test line located on the same layer in the test structure 200 of the semiconductor device
  • each bit line contact plug in the semiconductor device corresponds to a test line located on the same layer in the test structure 200 of the semiconductor device Connect the plug. Therefore, in this embodiment, when the bit line contact plugs and the bit line connection lines are formed, the test structure 200 is simultaneously formed in the scribe line 20 , and the test structure 200 includes the active region 210 and the connection structure 220 .
  • the active region 210 is formed in the semiconductor substrate 30
  • the connecting structure 220 is located at the end of the active region 210
  • the plurality of active regions 210 located in the same row are connected in sequence through the connecting structure 220 . connect.
  • the plurality of active regions 210 located in the same column are connected end to end in sequence through the connection structures 220 located at the ends of the active regions 210, as shown by the black dotted lines in FIG.
  • the line contact hole is connected in series with the active area, and the sum of the contact resistances of multiple bit lines and the resistance of the active area on the same column is finally obtained. Subtraction can be performed to accurately obtain the sum of the resistance values of the contact resistances of the bit lines.
  • Other test methods include connecting the active regions in series to obtain the sum of the resistances of the active regions by testing, which will not be repeated here, so this technical solution is effective. The problem of inaccurate measurement of the contact resistance of the bit line caused by the abnormal shallow trench isolation structure is solved, thereby improving the test accuracy and thus the product quality.
  • the connection structure 220 includes a first connection plug 221 , a second connection plug 222 and a metal layer 223 .
  • the first connection plug 221 is located at the head of the active region 210; the second connection plug 222 is located at the tail of the active region 210; the metal layer 223 is located at the first connection plug Above the plug 221 and the second connection plug 222 , the first connection plug 221 and the second connection plug 222 are connected through a metal layer 223 .
  • the semiconductor substrate 30 includes a base and a shallow trench structure (not shown) formed in the base, and a plurality of active regions 210 arranged in parallel and staggered are defined by the shallow trench structure, and The shallow trench structure is filled with insulating material to form the shallow trench isolation structure 250 , as shown in FIG. 3 , the strip-shaped region in the figure is the active region, and the rest is the shallow trench isolation structure.
  • the semiconductor substrate 30 further includes a word line structure (not shown) and a bit line structure (not shown), wherein the word line structure is a buried word line structure, and an extension method of the buried word line structure It intersects with the extending direction of the bit line structure.
  • the bit line structure includes a bit line contact plug, a bit line and an insulating layer that are stacked from bottom to top, and from bottom to top refers to the direction from the substrate to away from the substrate, and the bottom of the bit line contact plug is located on the substrate , which is in direct contact with the substrate; and after the bit line structure is formed, a plurality of bit lines are connected through the connection structure 220 .
  • the test structure 200 is formed in the scribe line 20 while the bit line structure is formed, as shown in FIG. 2 and FIG. 4 .
  • the test structure 200 includes an active region 210 and the connection structure 220 .
  • the first connection plug 221 is located at the head of the active area 210 ; the second connection plug 222 is located at the tail of the active area 210 .
  • the first connection plug 221 and the second connection plug 222 have the same structure, and both include a non-metallic conductive layer.
  • the metal layer 223 can be formed by laminating any one or any combination of titanium nitride, titanium, copper, tungsten silicide, and tungsten nitride with tungsten; the non-metal conductive layer is made of polysilicon, Semiconductor conductive materials, etc. are formed.
  • a plurality of the active regions 210 are alternately arranged, and the extending direction of the active regions 210 has a certain angle with the row direction, and is aligned in the column direction.
  • a plurality of active regions 210 located on the same column, each of the head and the tail closest to it are connected to the metal layer 223 through a first contact plug or a second contact plug, the metal layer 223 is the test line of the bit line contact resistance test structure.
  • connection structure in order to prevent metal atoms from diffusing into the polysilicon material layer, the connection structure further includes a metal barrier layer 224, and the metal barrier layer 224 is located between the first connection plug and the metal layer and between the second connection plug and the metal layer.
  • titanium nitride is used to form the metal barrier layer, and the metal barrier layer 224 can prevent the metal atoms in the metal layer 223 from diffusing into the polysilicon layer.
  • a plurality of the active regions 210 and a plurality of the connection structures 220 located on the same column together form a "Z"-shaped test structure 200 .
  • the included angle between the extending direction of the active region 210 and the row direction is in the range of 60° ⁇ 80°, so that the number and size of the active region 210 are not affected.
  • the plurality of active regions 210 can be aligned in the column direction, and the distance between the head and the tail of two adjacent active regions 210 in the column direction is the shortest, and the corresponding connection structures 220 are also arranged in the y direction, This simplifies the manufacturing process.
  • the contact resistances located on the same column are connected in series through the test structure 200 , thereby solving the problem of decreased test accuracy caused by abnormal shallow trench isolation structures.
  • every two adjacent active regions 210 are connected in a direction along the extending direction of the active regions 210 .
  • active regions with larger specifications (mainly referring to the length of the active regions) and arranged in parallel and staggered are first formed in the semiconductor substrate, and then two layers of cutting masks are used for the active regions with larger specifications.
  • the regions are divided to form a plurality of spaced small-sized active regions.
  • only one layer of dicing mask can be used, so it is impossible to completely separate the small-sized active regions to be formed. Therefore, every two adjacent active regions along the extending direction of the active regions active region connection.
  • the test structure 200 is one of a plurality of test structures 200 in the scribe line 20 . It can be understood that the test structure 200 of the semiconductor device and the semiconductor device in the semiconductor substrate are manufactured in the same process, and the test structure 200 of the semiconductor device and the semiconductor device have a corresponding relationship with each other, so the semiconductor device Each layer of interconnect lines corresponds to a test structure 200 .
  • the test of the key parameters of the semiconductor device includes the test of the resistance of the semiconductor device, the test of the thickness of the dielectric layer, and the test of the relative position between the semiconductor devices, etc. Therefore, the scribe line 20 has a plurality of test structures 200 for different purposes. The above includes: The test structure 200 of the source region 210 and the connection structure 220 is only one of a plurality of test structures 200 in the scribe line 20 .
  • the chip area 10 is a semiconductor memory chip, that is, the chip area 10 includes a semiconductor memory chip area.
  • the chip area 10 is an area where a semiconductor memory chip is formed, and the semiconductor device is a semiconductor memory.
  • the test structure 200 is used to test the bit line contact resistance in the semiconductor memory, and then according to the measured A bit line contact circuit detects the quality of the semiconductor memory.
  • the test structure 200 is used to connect the plurality of active regions 210 located on the same column end to end in sequence, and the obtained value is the sum of the resistance values of the contact resistances of the plurality of bit lines and the resistances of the active regions.
  • embodiments of the present application also provide a method for fabricating a semiconductor device.
  • the fabrication method of the semiconductor device includes:
  • Step S410 providing a semiconductor substrate 30
  • Step S420 forming a plurality of chip regions 10 and dicing lines on the semiconductor substrate 30 ; wherein, the dicing lines are used to separate the chip regions, and the dicing lines have a plurality of dicing lines formed synchronously with the chip regions 10 .
  • Step S430 forming a plurality of connection structures 220, the connection structures 220 are located at the ends of the active regions 210, and the connection structures 220 are used to connect the plurality of the active regions 210 in the same row end to end in sequence; Wherein, the active region and the connection structure together constitute a test structure for bit line contact resistance test.
  • test structure 200 of the semiconductor device is usually manufactured in the same process as the semiconductor device in the semiconductor substrate, and the test structure 200 of the semiconductor device and the semiconductor device have a mutual correspondence: semiconductor device
  • Each layer of interconnect lines in the semiconductor device corresponds to the test lines located on the same layer in the test structure 200 of the semiconductor device (ie, the metal layer 223 in the above-mentioned semiconductor structure), and each bit line contact plug in the semiconductor device corresponds to the test structure 200 of the semiconductor device.
  • a connection plug located in the same layer ie the first connection plug or the second connection plug in the above-mentioned semiconductor structure).
  • the test structure 200 when the bit line contact plugs and the bit line connection lines are formed, the test structure 200 is simultaneously formed in the scribe line 20 , and the test structure 200 includes the active region 210 and the connection structure 220 .
  • the active region 210 is formed in the semiconductor substrate 30
  • the connecting structure 220 is located at the end of the active region 210
  • the plurality of active regions 210 located in the same row are connected in sequence through the connecting structure 220 . connect.
  • a plurality of the active regions 210 located on the same column are connected end to end in sequence through the connection structures 220 located at the ends of the active regions 210, so as to obtain a plurality of bit line contact resistances located on the same column and
  • the sum of the resistance values of the active area can be accurately obtained by subtracting the resistance value test results of the active area obtained by other test methods, and the sum of the resistance values of the contact resistance of the bit line can be accurately obtained, thus effectively solving the problem of shallow trench isolation.
  • the inaccurate measurement of the contact resistance of the bit line caused by the structural abnormality improves the test accuracy, thereby improving the product quality.
  • the step of forming the connection structure 220 includes:
  • a first connection plug 221 and a second connection plug 222 are formed through the insulating layer 230 , wherein the first connection plug 221 is located at the head of the active region 210 , and the second connection plug 222 is located at the head of the active region 210 the tail of the active region 210;
  • a metal layer 223 is formed, the metal layer 223 covers the first connection plug 221 and the second connection plug 222, the first connection plug 221 and the second connection plug 222 pass through the metal Layer 223 is connected.
  • the semiconductor device described in this embodiment is a semiconductor memory.
  • the semiconductor substrate 30 includes a base and a shallow trench structure (not shown) formed in the base, and a plurality of active regions 210 arranged in parallel and staggered are defined by the shallow trench structure, and the The shallow trench structure is filled with insulating material to form the shallow trench isolation structure.
  • every two adjacent active regions are connected along the extending direction of the active regions.
  • a larger size (mainly referring to the length of the active region) is generally formed in the semiconductor substrate, and the active regions are arranged in parallel and staggered, and then a two-layer cutting mask is used for the larger size of the active region.
  • the regions are divided to form a plurality of spaced small-sized active regions.
  • only one layer of dicing mask can be used, which cannot completely separate the small-sized active regions to be formed, so every two adjacent dicing Active area connection.
  • the substrate further includes a word line structure (not shown) and a bit line structure (not shown), wherein the word line structure is a buried word line structure, and the method for extending the buried word line structure is the same as the above.
  • the extension directions of the bit line structures intersect.
  • the bit line structure includes a bit line structure including bit line contact plugs, bit lines and insulating layers 230 stacked from bottom to top. Bottom to top refers to the direction from the substrate to the direction away from the substrate.
  • the bottom of the plug is located on the semiconductor substrate and is in direct contact with the semiconductor substrate; and after the bit line structure is formed, a plurality of bit lines are connected through the connection structure 220 .
  • the test structure 200 is formed synchronously with the bit line structure and the connection structure 220, and the specific formation process includes:
  • Step 1 deposit insulating materials such as silicon nitride, silicon oxide and silicon oxynitride through a deposition process to form an insulating layer 230 covering the surface of the semiconductor substrate (including the active region 210 and the shallow trench isolation structure 250 ) .
  • the deposition process may include chemical vapor deposition (CVD), low pressure CVD (LPCVD), plasma enhanced CVD (PECVD), atomic layer deposition (ALD), plasma enhanced ALD (PEALD), and the like.
  • CVD chemical vapor deposition
  • LPCVD low pressure CVD
  • PECVD plasma enhanced CVD
  • ALD atomic layer deposition
  • PEALD plasma enhanced ALD
  • Step 2 When forming the bit line contact hole, an etching process is used to simultaneously form a through hole for forming the first connection plug 221 and the second connection plug 222 in the scribe line 20, and the through hole is exposed out the active region 210 .
  • polysilicon materials are sequentially deposited by a deposition process to form a polysilicon material layer, and the polysilicon material layer covers the insulating layer 230 and fills the through holes.
  • Step 3 the polysilicon material layer is etched, the polysilicon material layer located in the insulating layer 230 is removed, and the remaining polysilicon material layer forms a first connection plug and a second connection plug in the scribe line 20 .
  • the first connection plug and the second connection plug are both located in the through hole and fill the through hole.
  • Step 4 through the PC (Periphery Contact, peripheral area connection) process, a bit line connection structure is formed in the chip area 10, and the metal layers in the bit line structure are connected together through the connection structure 220; and, A metal layer 223 connecting the first connection plug and the second connection plug is simultaneously formed.
  • the fourth step specifically includes:
  • a bit line isolation structure covering the side surface of the bit line structure is formed through deposition and etching processes; this step specifically includes: first, forming a surface covering the bit line structure by depositing an insulating material and a layer of isolation material on the surface of the substrate.
  • silicon nitride is used to form the isolation material layer.
  • the isolation material layer is etched by an etching process, the isolation material layer located on the top of the bit line structure and the surface of the substrate is removed, and the isolation material layer located on the sidewall of the bit line structure is retained, And as the bit line isolation structure (not shown).
  • a filling layer 240 is formed using a deposition process and an etching/chemical mechanical polishing process.
  • the filling layer 240 is formed by depositing a silicon nitride material.
  • the metal layer 223 is formed through a PC process, the metal layer 223 covers the first connection plug 221 and the second connection plug 222, the first connection plug 221 and the second connection plug 221 The connection plugs 222 are connected through the metal layer 223 .
  • it before forming the metal layer, it further includes the step of forming a metal barrier layer, the metal barrier layer is located between the first connection plug and the metal layer and the second connection between the plug and the metal layer.
  • titanium nitride is used to form the metal barrier layer, and the metal barrier layer 224 can prevent the metal atoms in the metal layer 223 from diffusing into the polysilicon layer.
  • a plurality of the active regions 210 and a plurality of the connection structures 220 located on the same column together form a "Z"-shaped test structure 200 .
  • the included angle between the extending direction of the active region 210 and the row direction is in the range of 60° ⁇ 80°, so that while the number and size of the active region 210 are not affected, a plurality of active regions
  • the regions 210 can be aligned in the column direction, and the distance between the head and the tail of two adjacent active regions 210 in the column direction is the shortest, and the corresponding connection structures 220 are also arranged in the y direction, thereby simplifying the fabrication process.
  • the test structure 200 is used to connect the contact resistances and active regions in the same row in series, and then test to obtain the sum of the resistances of the contact resistances and the active regions of a plurality of bit lines in the same row, By subtracting the active area resistance test results obtained by other test methods, the sum of the bit line contact hole resistance values can be accurately obtained, thereby solving the bit line contact resistance value test caused by the abnormal shallow trench isolation structure. The problem of decreased accuracy.
  • the embodiments of the present application provide a semiconductor device and a manufacturing method thereof, wherein the semiconductor device includes a semiconductor substrate 30 , and the semiconductor substrate 30 includes a plurality of chip regions 10 and is used for separating the chip regions 10
  • the dicing road 20 wherein, a test structure 200 is formed in the dicing road, the test structure 200 includes an active region 210 and a connection structure 220, the active region 210 is formed in the semiconductor substrate 30, and the connection structure 220 is located at the end of the active region 210 , and the plurality of active regions 210 located in the same column are connected end to end in sequence through the connection structure 220 .
  • the semiconductor device is provided with a test structure 200 for testing the contact resistance of the bit line in the scribe line 20 .
  • the active regions 210 are connected end-to-end in sequence, that is, the bit line contact holes and the active region are connected in series, so as to obtain the sum of the contact resistances of a plurality of bit lines located in the same column.
  • the sum of the resistance values of the bit line contact holes can be accurately obtained, and the sum of the resistance values of the bit line contact holes can be accurately obtained, which solves the problem of inconsistency in the measurement of the contact resistance value of the bit line caused by the abnormal shallow trench isolation structure. Accurate questions, improve test accuracy, and then improve product quality.

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  • Manufacturing & Machinery (AREA)
  • Semiconductor Integrated Circuits (AREA)
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Abstract

本申请涉及一种半导体器件及其制作方法，其中半导体器件包括半导体衬底(30)，半导体衬底(30)包括多个芯片区域(10)以及用于分隔芯片区域(10)的切割道(20)；切割道(20)内形成有测试结构(200)，测试结构(200)用于位线接触电阻测试，测试结构(200)包括有源区(210)和连接结构(220)，有源区(210)形成于半导体衬底(30)内，连接结构(220)位于有源区(210)的端部，通过连接结构(220)将位于同一列上的多个有源区(210)依次首尾连接。

Description

半导体器件及其制作方法 技术领域
本申请涉及半导体存储器件技术领域，尤其涉及一种半导体器件及其制作方法。
相关申请的交叉引用
本申请要求于2020年09月04日提交中国专利局、申请号为2020109227232、发明名称为“半导体器件及其制作方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
背景技术
这里的陈述仅提供与本申请有关的背景信息，而不必然地构成现有技术。
随着半导体器件尺寸微缩，17nm的动态随机存取存储器(Dynamic Random Access Memory，DRAM)制程相对于19nm的DRAM而言，存储单元阵列区和周边电路区的晶体管的尺寸都越来越小，工艺复杂度越来越高，为了对半导体器件的制造工艺进行监控，以保证半导体器件的可靠性，通常的做法是在半导体器件中形成测试结构(test key)，用于半导体器件的一些关键参数的测试和模拟，以保证半导体器件出厂的质量。
对半导体器件关键参数的测试包括半导体器件电阻的测试等。例如，通过进行位线接触电阻测试，可测试位线接触插塞与衬底之间的是否接触良好。但是，由于当前的位线接触电阻测试结构测试时，有源区之间存在浅沟槽隔离结构，所以当有源区中间的衬底中的浅沟槽隔离结构出现异常时，同样会导致BLC(Bit Line contact)电阻异常高，因此无法准确反应出位线插塞与衬底之间的接触情况。
发明内容
根据本申请的各种实施例，提供了一种半导体器件及其制作方法。
一种半导体器件，包括：
半导体衬底，包括多个芯片区域以及用于分隔所述芯片区域的切割道；
其中，所述切割道内形成有测试结构，所述测试结构用于位线接触电阻测试，所述测试结构包括：
有源区，位于半导体衬底内；以及
连接结构，位于所述有源区的端部，通过所述连接结构将位于同一列上的多个所述有源区依次首尾连接。
一种半导体器件的制作方法，包括：
提供半导体衬底；
在所述半导体衬底上形成多个芯片区域及用于分隔所述芯片区域的切割道；其中，所述切割道内具有多个与所述芯片区域同步形成的有源区；以及
形成多个连接结构，所述连接结构位于所述有源区的端部，通过所述连接结构将位于同一列上的多个所述有源区依次首尾连接；
其中，所述有源区和所述连接结构共同构成用于位线接触电阻测试的测试结构。
本申请的一个或多个实施例的细节在下面的附图和描述中提出。本申请的其他特征、目的和优点将从说明书、附图以及权利要求书变得明显。
附图说明
为了更清楚地说明本申请实施例或示例性技术中的技术方案，下面将对实施例或示例性技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他实施例的 附图。
图1为包括芯片区域和切割道的半导体器件的俯视图；
图2为本申请实施例提供的一种半导体器件的俯视图；
图3为示例性的半导体器件的有源区的排布示意图；
图4为沿图2中虚线L2处的半导体器件的剖面图；
图5为本申请实施例提供的一种半导体器件的制作方法流程图。
附图标号说明：
芯片区域-10，切割道-20，测试结构-200，有源区-210，连接结构-220，第一连接插塞-221，第二连接插塞-222，金属层-223，金属阻挡层224，绝缘层-230，填充层-240，浅沟槽隔离结构250，半导体衬底-30。
具体实施方式
为使本申请的上述目的、特征和优点能够更加明显易懂，下面结合附图对本申请的具体实施方式做详细的说明。在下面的描述中阐述了很多具体细节以便于充分理解本申请。但是本申请能够以很多不同于在此描述的其它方式来实施，本领域技术人员可以在不违背本申请内涵的情况下做类似改进，因此本申请不受下面公开的具体实施的限制。
应当明白，当元件或层被称为“在...上”、“与...相邻”、“连接到”或“耦合到”其它元件或层时，其可以直接地在其它元件或层上、与之相邻、连接或耦合到其它元件或层，或者可以存在居间的元件或层。相反，当元件被称为“直接在...上”、“与...直接相邻”、“直接连接到”或“直接耦合到”其它元件或层时，则不存在居间的元件或层。应当明白，尽管可使用术语第一、第二、第三等描述各种元件、部件、区、层、掺杂类型和/或部分，这些元件、部件、区、层、掺杂类型和/或部分不应当被这些术语限制。这些术语仅仅用来区分一个元件、部件、区、层、掺杂类型或部分与另一个元件、部件、区、层、掺杂类型或部分。因此，在不脱离本申请教导之下，下面讨论的第一元件、部件、区、层、掺杂类型或部分可表示为第二元件、部件、区、 层或部分；举例来说，可以将第一掺杂类型成为第二掺杂类型，且类似地，可以将第二掺杂类型成为第一掺杂类型；第一掺杂类型与第二掺杂类型为不同的掺杂类型，譬如，第一掺杂类型可以为P型且第二掺杂类型可以为N型，或第一掺杂类型可以为N型且第二掺杂类型可以为P型。
空间关系术语例如“在...下”、“在...下面”、“下面的”、“在...之下”、“在...之上”、“上面的”等，在这里可以用于描述图中所示的一个元件或特征与其它元件或特征的关系。应当明白，除了图中所示的取向以外，空间关系术语还包括使用和操作中的器件的不同取向。例如，如果附图中的器件翻转，描述为“在其它元件下面”或“在其之下”或“在其下”元件或特征将取向为在其它元件或特征“上”。因此，示例性术语“在...下面”和“在...下”可包括上和下两个取向。此外，器件也可以包括另外地取向(譬如，旋转90度或其它取向)，并且在此使用的空间描述语相应地被解释。
在此使用时，单数形式的“一”、“一个”和“所述/该”也可以包括复数形式，除非上下文清楚指出另外的方式。还应当理解的是，术语“包括/包含”或“具有”等指定所陈述的特征、整体、步骤、操作、组件、部分或它们的组合的存在，但是不排除存在或添加一个或更多个其他特征、整体、步骤、操作、组件、部分或它们的组合的可能性。同时，在本说明书中，术语“和/或”包括相关所列项目的任何及所有组合。
本申请实施例提供了一种半导体器件，包括半导体衬底，请参见图1和图2。所述半导体衬底30包括多个芯片区域10以及用于分隔所述芯片区域10的切割道20；其中，所述切割道20内形成有测试结构200，所述测试结构200包括有源区210和连接结构220，所述有源区210形成于半导体衬底30内，所述连接结构220位于所述有源区210的端部，通过所述连接结构220将位于同一列上的多个所述有源区210依次首尾连接，所述测试结构200用于位线接触电阻测试。
可以理解，所述半导体器件的测试结构200通常与半导体衬底30中的半导体器件是在同样的工艺中制造获得的，且所述半导体器件的测试结构200 与所述半导体器件具有相互的对应关系：半导体器件中每一层互连线对应于半导体器件的测试结构200中位于同一层的测试线，半导体器件中每一个位线接触插塞对应于半导体器件的测试结构200中位于同一层的一个连接插塞。因此，本实施例中在形成位线接触插塞和位线连接线时，在切割道20内同步形成所述测试结构200，所述测试结构200包括有源区210和连接结构220，所述有源区210形成于半导体衬底30内，所述连接结构220位于所述有源区210的端部，通过所述连接结构220将位于同一列上的多个所述有源区210依次首尾连接。
由于本实施例是通过位于所述有源区210的端部的连接结构220将位于同一列上的多个所述有源区210依次首尾连接，如图2中的黑色虚线所示，即将位线接触孔与有源区进行串联，最终测试得到位于同一列上的多个位线接触电阻与有源区电阻的阻值之和，通过与采用其他测试方法获得的有源区阻值测试结果进行减法运算，可以准确得到位线接触电阻的阻值之和，其他测试方法包括通过将有源区进行串联，测试得到有源区的电阻之和，在此不做赘述，因此本技术方案有效解决了因浅沟槽隔离结构异常所导致的位线接触电阻测量不准确的问题，从而提高了测试准确度，进而提高了产品品质。
参见图4，在其中一个实施例中，所述连接结构220包括第一连接插塞221、第二连接插塞222和金属层223。其中，所述第一连接插塞221位于所述有源区210的首部；所述第二连接插塞222位于所述有源区210的尾部；所述金属层223位于所述第一连接插塞221和所述第二连接插塞222上方，通过金属层223将所述第一连接插塞221与所述第二连接插塞222连接。
可以理解，所述半导体衬底30包括基底和于基底内形成的浅沟槽结构(未图示)，通过所述浅沟槽结构定出多个平行交错设置的多个有源区210，且所述浅沟槽结构内填充有绝缘材料，以形成浅沟槽隔离结构250，如图3所示，图中条状区域为有源区，其余部分为浅槽隔离结构。所述半导体衬底30还包括字线结构(未图示)和位线结构(未图示)，其中所述字线结构为埋入式字线结构，该埋入式字线结构的延伸方法与所述位线结构的延伸方向 交叉。位线结构包括由下至上叠层设置的位线接触插塞、位线和绝缘层，由下至上指的是由基底至远离基底的方向，所述位线接触插塞底部位于所述基底上，与所述基底直接接触；并在形成位线结构后，通过连接结构220将多个位线连接。
为了便于测试位线接触电阻，在形成所述位线结构的同时，在切割道20内形成了所述测试结构200，如图2、图4所示。所述测试结构200包括有源区210和所述连接结构220。所述第一连接插塞221位于所述有源区210的首部；所述第二连接插塞222位于所述有源区210的尾部。所述第一连接插塞221和第二连接插塞222的结构相同，均包括非金属导电层。本实施例中，所述金属层223可以通过将氮化钛、钛、铜、硅化钨、氮化钨中的任一种或任意组合与钨层叠来形成；所述非金属导电层采用多晶硅、半导体导电材料等形成。本实施例中，多个所述有源区210交错排布，且所述有源区210的延伸方向与行方向具有一定夹角，在列方向上对齐。位于同一列上的多个有源区210，每一所述首部和与之最邻近的所述尾部通过第一接触插塞或第二接触插塞和所述金属层223连接，所述金属层223即为位线接触电阻的测试结构的测试线。
通常情况下，采用多晶硅形成所述第一连接插塞221和所述第二连接插塞222，采用金属钨形成所述金属层223。在其中一个实施例中，为了阻止金属原子向多晶硅材料层中扩散，所述连接结构还包括金属阻挡层224，所述金属阻挡层224位于所述第一连接插塞与所述金属层之间以及所述第二连接插塞与所述金属层之间。本实施例中采用氮化钛形成所述金属阻挡层，通过所述金属阻挡层224可以阻挡金属层223中的金属原子向多晶硅层中扩散。
在其中一个实施例中，位于同一列上的多个所述有源区210和多个所述连接结构220共同构成“Z”字型测试结构200。
请继续参见图2，本实施例中所述有源区210的延伸方向与行方向之间的夹角在60°～80°范围内，以使得在不影响有源区210划分数量和大小的同时，多个有源区210可以在列方向对齐，以及在列方向上相邻的两个有源 区210的首部与尾部之间的距离最短，且相应的连接结构220也沿y方向排列，进而简化制作工艺。本实施例中，通过所述测试结构200将位于同一列上的接触电阻串联，从而解决了因浅沟槽隔离结构异常所导致的测试准确度下降的问题。
在其中一个实施例中，在沿所述有源区210延伸的方向上每相邻两个所述有源区210连接。
可以理解，一般先在半导体衬底中形成规格(主要是指有源区的长度)较大的、平行交错设置的有源区，然后使用两层切割掩膜板对该规格较大的有源区进行分割，以形成多个间隔的小尺寸的有源区。但是在切割道内，仅能使用一层切割掩膜板，因此无法将即将形成的小尺寸的有源区完全分隔开，故在沿所述有源区延伸的方向上每相邻两个所述有源区连接。
在其中一个实施例中，所述测试结构200为所述切割道20内的多个测试结构200之一。可以理解，半导体器件的测试结构200与半导体衬底中的半导体器件是在同样的工艺中制造获得的，且所述半导体器件的测试结构200与所述半导体器件具有相互的对应关系，因此半导体器件中每一层互连线都会对应一个测试结构200。而对半导体器件关键参数的测试包括半导体器件电阻的测试、介质层厚度的测试和半导体器件间相对位置的测试等，因此所述切割道20内具有多个不同用途的测试结构200，上述包括有源区210和连接结构220的所述测试结构200仅为所述切割道20内的多个测试结构200中的一个。
在其中一个实施例中，所述芯片区域10为半导体存储芯片，即所述芯片区域10包括半导体存储芯片区域。本实施例中，所述芯片区域10为形成半导体存储芯片的区域，所述半导体器件为半导体存储器，所述测试结构200用于测试所述半导体存储器中的位线接触电阻，进而根据测得的位线接触电路检测所述半导体存储器的品质。由于本实施例中通过所述测试结构200将位于同一列上的多个所述有源区210依次首尾连接，得到的是多个位线接触电阻与有源区电阻的阻值之和，通过与采用其他测试方法获得的有源区阻值 测试结果进行减法运算，可以准确得到位线接触电阻的阻值之和，从而可避免出现因浅沟槽隔离结构异常所导致的测试准确度下降的问题，提高测试准确度，并提高器件品质。
基于同一发明构思，本申请实施例还提供了一种半导体器件的制作方法。请参见图5，所述半导体器件的制作方法包括：
步骤S410，提供半导体衬底30；
步骤S420，在所述半导体衬底30上形成多个芯片区域10和切割道；其中，切割道用于分隔所述芯片区域，所述切割道内具有多个与所述芯片区域10同步形成的有源区210；以及
步骤S430，形成多个连接结构220，所述连接结构220位于所述有源区210的端部，通过所述连接结构220将位于同一列上的多个所述有源区210依次首尾连接；其中，所述有源区和所述连接结构共同构成用于位线接触电阻测试的测试结构。
由于所述半导体器件的测试结构200通常与半导体衬底中的半导体器件是在同样的工艺中制造获得的，且所述半导体器件的测试结构200与所述半导体器件具有相互的对应关系：半导体器件中每一层互连线对应半导体器件的测试结构200中位于同一层的测试线(即上述半导体结构中的金属层223)，半导体器件中每一个位线接触插塞对应半导体器件的测试结构200中位于同一层的一个连接插塞(即上述半导体结构中的第一连接插塞或第二连接插塞)。因此，本实施例中在形成位线接触插塞和位线连接线时，在切割道20内同步形成所述测试结构200，所述测试结构200包括有源区210和连接结构220，所述有源区210形成于半导体衬底30内，所述连接结构220位于所述有源区210的端部，通过所述连接结构220将位于同一列上的多个所述有源区210依次首尾连接。
本实施例通过位于所述有源区210的端部的连接结构220将位于同一列上的多个所述有源区210依次首尾连接，进而得到位于同一列上的多个位线接触电阻与有源区的阻值之和，通过与采用其他测试方法获得的有源区阻值 测试结果进行减法运算，可以准确得到位线接触电阻的阻值之和，因此有效解决了因浅沟槽隔离结构异常所导致的位线接触电阻测量不准确问题，从而提高了测试准确度，进而提高了产品品质。
在其中一个实施例中，形成所述连接结构220的步骤包括：
在所述有源区上方形成绝缘层230；
形成贯穿所述绝缘层230的第一连接插塞221和第二连接插塞222，其中所述第一连接插塞221位于所述有源区210的首部，所述第二连接插塞222位于所述有源区210的尾部；
形成金属层223，所述金属层223覆盖所述第一连接插塞221和所述第二连接插塞222，所述第一连接插塞221与所述第二连接插塞222通过所述金属层223连接。
本实施例中所述半导体器件为半导体存储器。所述半导体衬底30包括基底和形成于基底内形成的浅沟槽结构(未图示)，通过所述浅沟槽结构定出多个平行交错设置的多个有源区210，且所述浅沟槽结构内填充有绝缘材料以形成浅沟槽隔离结构。在其中一个实施例中，在沿所述有源区延伸的方向上每相邻两个所述有源区连接。可以理解，一般先在半导体衬底中形成规格(主要是指有源区的长度)较大的、平行交错设置待有源区，然后使用两层切割掩膜板对该规格较大的有源区进行分割，以形成多个间隔的小尺寸的有源区。但是在切割道内，仅能使用一层切割掩膜板，无法将即将形成的小尺寸的有源区完全分隔开，故在沿所述有源区延伸的方向上每相邻两个所述有源区连接。
所述衬底还包括字线结构(未图示)和位线结构(未图示)，其中所述字线结构为埋入式字线结构，该埋入式字线结构的延伸方法与所述位线结构的延伸方向交叉。所述位线结构包括位线结构包括由下至上叠层设置的位线接触插塞、位线和绝缘层230，由下至上指的是由基底至远离基底的方向，所述位线接触插塞底部位于所述半导体衬底上，与所述半导体衬底直接接触；并在形成位线结构后，通过连接结构220将多个位线连接。所述测试结构200 与所述位线结构及连接结构220同步形成的，具体形成过程包括：
步骤一，通过沉积工艺沉积绝缘材料，例如氮化硅、氧化硅和氮氧化硅等，以形成覆盖所述半导体衬底(包括有源区210和浅沟槽隔离结构250)表面的绝缘层230。其中，所述沉积工艺可以包括化学气相沉积(CVD)、低压CVD(LPCVD)、等离子体增强CVD(PECVD)、原子层沉积(ALD)以及等离子体增强ALD(PEALD)等。
步骤二，在形成位线接触孔时，利用刻蚀工艺同步在所述切割道20内的形成用于形成第一连接插塞221和第二连接插塞222的通孔，所述通孔暴露出所述有源区210。
然后，利用沉积工艺依次沉积多晶硅材料以形成多晶硅材料层，所述多晶硅材料层覆盖所述绝缘层230并填满所述通孔。
步骤三，对所述多晶硅材料层进行刻蚀，去除位于绝缘层230的多晶硅材料层，保留的多晶硅材料层在切割道20内形成第一连接插塞和第二连接插塞。本实施例中，所述第一连接插塞和第二连接插塞均位于所述通孔内，并填满所述通孔。
步骤四，通过PC(Periphery Contact，周边区域连接)工艺，在所述芯片区域10内形成位线连接结构，通过所述连接结构220将所述位线结构中的金属层连接在一起；并且，同步形成连接所述第一连接插塞和所述第二连接插塞的金属层223。该步骤四具体包括：
首先，在形成位线结构后，通过沉积和刻蚀工艺先形成覆盖所述位线结构侧面的位线隔离结构；该步骤具体包括：首先，通过沉积绝缘材料形成覆盖所述位线结构的表面以及所述衬底表面的隔离材料层。本实施例中，采用氮化硅制作所述隔离材料层。然后，利用刻蚀工艺对所述隔离材料层进行刻蚀，去除位于所述位线结构顶部以及所述衬底表面的隔离材料层，保留位于所述位线结构侧壁上的隔离材料层，并作为所述位线隔离结构(未图示)。
其次，在形成位线隔离结构之后，利用沉积工艺和刻蚀/化学机械研磨工艺形成填充层240。本实施例中通过沉积氮化硅材料形成所述填充层240。
然后，通过PC工艺形成连接所述金属层223，所述金属层223覆盖所述第一连接插塞221和所述第二连接插塞222，所述第一连接插塞221与所述第二连接插塞222通过所述金属层223连接。在其它一些实施例中，在形成所述金属层之前，还包括形成金属阻挡层的步骤，所述金属阻挡层位于所述第一连接插塞与所述金属层之间以及所述第二连接插塞与所述金属层之间。本实施例中采用氮化钛形成所述金属阻挡层，通过所述金属阻挡层224可以阻挡金属层223中金属原子向多晶硅层中扩散。
在其中一个实施例中，位于同一列上的多个所述有源区210和多个所述连接结构220共同构成“Z”字型测试结构200。本实施例中所述有源区210的延伸方向与行方向之间的夹角在60°～80°范围内，以使得在不影响有源区210划分数量和大小的同时，多个有源区210可以在列方向对齐，以及在列方向上相邻的两个有源区210的首部与尾部之间的距离最短，且相应的连接结构220也沿y方向排列，进而简化制作工艺。本实施例中，通过所述测试结构200将位于同一列上的接触电阻及有源区进行串联，进而测试得到位于同一列上的多个位线接触电阻与有源区的阻值之和，通过与采用其他测试方法获得的有源区阻值测试结果进行减法运算，可以准确得到位线接触孔阻值之和，从而解决了因浅沟槽隔离结构异常所导致的位线接触阻值测试准确度下降的问题。
综上，本申请实施例提供了一种半导体器件及其制作方法，其中所述半导体器件包括半导体衬底30，所述半导体衬底30包括多个芯片区域10以及用于分隔所述芯片区域10的切割道20；其中，所述切割道内形成有测试结构200，所述测试结构200包括有源区210和连接结构220，所述有源区210形成于半导体衬底30内，所述连接结构220位于所述有源区210的端部，通过所述连接结构220将位于同一列上的多个所述有源区210依次首尾连接。本实施例中，所述半导体器件在切割道20内设置有用于测试位线接触电阻的测试结构200，通过位于所述有源区210的端部的连接结构220将位于同一列上的多个所述有源区210依次首尾连接，即将位线接触孔与有源区进行串 联，进而得到位于同一列上的多个位线接触电阻之和，通过与采用其他测试方法获得的有源区阻值测试结果进行减法运算，可以准确得到位线接触孔阻值之和，可以准确得到位线接触孔阻值之和，解决了因浅沟槽隔离结构异常所导致的位线接触阻值测量不准确的问题，提高测试准确度，进而提高产品品质。
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本申请的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干变形和改进，这些都属于本申请的保护范围。因此，本申请专利的保护范围应以所附权利要求为准。

Claims (15)

  1. 一种半导体器件，包括：
    半导体衬底，包括多个芯片区域以及用于分隔所述芯片区域的切割道；
    其中所述切割道内形成有测试结构，所述测试结构用于位线接触电阻测试，所述测试结构包括：
    有源区，位于半导体衬底内；以及
    连接结构，位于所述有源区的端部，通过所述连接结构将位于同一列上的多个所述有源区依次首尾连接。
  2. 如权利要求1所述的半导体器件，其中所述连接结构包括：
    第一连接插塞，位于所述有源区的首部；
    第二连接插塞，位于所述有源区的尾部；以及
    金属层，位于所述第一连接插塞和所述第二连接插塞上方，用于连接所述第一连接插塞与所述第二连接插塞。
  3. 如权利要求2所述的半导体器件，其中所述连接结构还包括金属阻挡层，所述金属阻挡层位于所述第一连接插塞与所述金属层之间以及所述第二连接插塞和所述金属层之间。
  4. 如权利要求2所述的半导体器件，其中所述第一连接插塞和所述第二连接插塞的结构相同。
  5. 如权利要求2所述的半导体器件，其中所述第一连接插塞、所述第二连接插塞的材料包括多晶硅，所述金属层的材料包括金属钨。
  6. 如权利要求2所述的半导体器件，其中半导体衬底包括基底和于基底内形成的浅沟槽结构，通过所述浅沟槽结构定出多个平行交错设置的多个有源区，且所述浅沟槽结构内填充有绝缘材料，以形成浅沟槽隔离结构。
  7. 如权利要求1所述的半导体器件，其中位于同一列上的多个所述有源区和多个所述连接结构共同构成“Z”字型测试结构。
  8. 如权利要求7所述的半导体器件，其中在沿所述有源区延伸的方向上每相邻两个所述有源区连接。
  9. 如权利要求1所述的半导体器件，其中所述测试结构为所述切割道内的多个测试结构之一。
  10. 如权利要求1所述的半导体器件，其中所述芯片区域包括半导体存储芯片区域。
  11. 一种半导体器件的制作方法，其中包括：
    提供半导体衬底；
    在所述半导体衬底上形成多个芯片区域和及用于分隔所述芯片区域的切割道；所述切割道内具有多个与所述芯片区域同步形成的有源区；以及
    形成多个连接结构，所述连接结构位于所述有源区的端部，通过所述连接结构将位于同一列上的多个所述有源区依次首尾连接，其中所述有源区和所述连接结构共同构成用于位线接触电阻测试的测试结构。
  12. 如权利要求11所述的半导体器件的制作方法，其中形成所述连接结构的步骤包括：
    在所述有源区上方形成绝缘层；
    形成贯穿所述绝缘层的第一连接插塞和第二连接插塞，所述第一连接插塞位于所述有源区的首部，所述第二连接插塞位于所述有源区的尾部；以及
    形成金属层，所述金属层覆盖所述第一连接插塞和所述第二连接插塞，所述第一连接插塞与所述第二连接插塞通过所述金属层连接。
  13. 如权利要求12所述的半导体器件，其中所述第一连接插塞和所述第二连接插塞的结构相同。
  14. 如权利要求11所述的半导体器件，其中所述半导体衬底包括基底和形成于基底内形成的浅沟槽结构，通过所述浅沟槽结构定出多个平行交错设置的多个有源区，且所述浅沟槽结构内填充有绝缘材料以形成浅沟槽隔离结构。
  15. 如权利要求11所述的半导体器件的制作方法，其中位于同一列上的多个所述有源区和多个所述连接结构共同构成“Z”字型测试结构。
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