WO2022047915A1 - 顶发光 amoled 显示面板、制作方法以及显示装置 - Google Patents

顶发光 amoled 显示面板、制作方法以及显示装置 Download PDF

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Publication number
WO2022047915A1
WO2022047915A1 PCT/CN2020/122680 CN2020122680W WO2022047915A1 WO 2022047915 A1 WO2022047915 A1 WO 2022047915A1 CN 2020122680 W CN2020122680 W CN 2020122680W WO 2022047915 A1 WO2022047915 A1 WO 2022047915A1
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Prior art keywords
layer
display panel
interlayer insulating
amoled display
passivation
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PCT/CN2020/122680
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English (en)
French (fr)
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郑智琳
唐甲
张晓星
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深圳市华星光电半导体显示技术有限公司
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Priority to US17/056,436 priority Critical patent/US11856811B2/en
Publication of WO2022047915A1 publication Critical patent/WO2022047915A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/84—Passivation; Containers; Encapsulations
    • H10K50/844—Encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/86—Arrangements for improving contrast, e.g. preventing reflection of ambient light
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/87—Passivation; Containers; Encapsulations
    • H10K59/873—Encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K2102/00—Constructional details relating to the organic devices covered by this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K2102/00—Constructional details relating to the organic devices covered by this subclass
    • H10K2102/301—Details of OLEDs
    • H10K2102/302—Details of OLEDs of OLED structures
    • H10K2102/3023—Direction of light emission
    • H10K2102/3026—Top emission
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/126—Shielding, e.g. light-blocking means over the TFTs

Definitions

  • the present application relates to the field of display technology, and in particular, to a top-emitting AMOLED display panel, a manufacturing method and a display device.
  • AMOLED Active-matrix organic light-emitting diode, active matrix organic light-emitting diode or active matrix organic light-emitting diode
  • display technology has the advantages of fast response speed, self-luminescence, excellent display effect and low power consumption. be widely used.
  • AMOLED panels usually use copper or copper alloys with good conductivity as metal traces.
  • Bonding Pad bonding area
  • copper cannot be exposed on the surface as a Bonding Pad.
  • conductive metal oxide ITO Indium Tin Oxides, indium tin oxide
  • ITO/Ag Arxide, silver
  • IZO/Ag/IZO Indium Zinc oxid, indium zinc oxide
  • Pad is a composite layer with metallic silver, in the reliability RA (Reliant Apprais, e reliability) test, Bonding Pad is very prone to the problem of silver oxidation, and the problem of copper
  • the inventor found that there are at least the following problems in the traditional technology: the traditional AMOLED panel has the problem of poor electrical signal transmission.
  • an embodiment of the present application provides a top emission AMOLED display panel, which includes a passivation layer and a protective conductive layer;
  • the passivation layer is sandwiched between the interlayer insulating layer and the planarization layer of the top-emitting AMOLED display panel; the passivation layer is provided with openings corresponding to the metal layer; the metal layer is a metal layer formed on the interlayer insulating layer;
  • the protective conductive layer covers the metal layer and the sidewalls of the opening, and a part of the protective conductive layer extends to the passivation layer.
  • the embodiments of the present application also provide a method for manufacturing a top-emitting AMOLED display panel, including the following steps:
  • a glass substrate is provided; a light-shielding layer, a buffer layer, a semiconductor layer, a gate insulating layer, a gate metal layer, an interlayer insulating layer and a metal layer formed on the interlayer insulating layer are formed on the glass substrate;
  • a protective conductive layer is formed on the sidewalls of the opening, the metal layer and the interlayer insulating layer.
  • an embodiment of the present application further provides a display device, including a top-emission AMOLED display panel;
  • the top-emitting AMOLED display panel includes a passivation layer and a protective conductive layer;
  • the passivation layer is sandwiched between the interlayer insulating layer and the planarization layer of the top-emitting AMOLED display panel; the passivation layer is provided with openings corresponding to the metal layer; the metal layer is a metal layer formed on the interlayer insulating layer;
  • the protective conductive layer covers the metal layer and the sidewalls of the opening, and a part of the protective conductive layer extends to the passivation layer.
  • the top-emission AMOLED display panel provided by each embodiment of the present application includes a passivation layer and a protective conductive layer; the passivation layer is sandwiched between the interlayer insulating layer and the planarization layer of the top-emission AMOLED display panel; the passivation layer corresponds to the
  • the metal layer is provided with an opening; the metal layer is a metal layer formed on the interlayer insulating layer; the protective conductive layer covers the metal layer and the sidewall of the opening, and a part of the protective conductive layer extends to the interlayer insulating layer , wherein the passivation layer is covered on the metal layer formed on the interlayer insulating layer, which can physically protect the metal layer to avoid its oxidation, and protect the conductive layer to cover the metal layer to prevent the metal layer from being engraved by the anode in the subsequent process.
  • the etchant is etched or oxidized, thereby improving the reliability of electrical signal conduction and improving the performance of the top-emitting AMOLED display panel.
  • FIG. 1 is a schematic structural diagram of a top-emitting AMOLED display panel in one embodiment
  • FIG. 2 is a schematic structural diagram of a top-emitting AMOLED display panel in another embodiment
  • FIG. 3 is a schematic structural diagram of a top-emitting AMOLED display panel in yet another embodiment
  • FIG. 4 is a schematic flowchart of a method for fabricating a top-emitting AMOLED display panel in one embodiment
  • FIG. 5 is a schematic flowchart of a method for fabricating a top-emitting AMOLED display panel in yet another embodiment.
  • a top-emitting AMOLED display panel including a passivation layer 11 and a protective conductive layer 13;
  • the passivation layer 11 is sandwiched between the interlayer insulating layer 15 and the planarization layer 17 of the top-emitting AMOLED display panel; the passivation layer 11 is provided with an opening 111 corresponding to the metal layer 19; the metal layer 19 is formed between the layers the metal layer on the insulating layer 15;
  • the protective conductive layer 13 covers the metal layer 19 and the sidewalls of the opening 111 , and a part of the protective conductive layer 13 extends to the passivation layer 11 .
  • the passivation layer is a protective layer formed of insulating materials, which is formed on the interlayer insulating layer of the top-emitting AMOLED display panel, and covers the metal layer on the interlayer insulating layer to physically protect the metal layer.
  • the metal layer includes the source and drain metal layers in the display area and the Bonding The metal layer of the pad area.
  • the passivation layer is patterned, and openings are formed at positions corresponding to the metal layers to expose the metal layers for subsequent processes.
  • the passivation layer is a thin film with a one-layer structure; in another example, the passivation layer is a thin film with a two-layer structure; in yet another example, the passivation layer is a thin film with a multi-layer structure.
  • the specific number of layers can be determined according to actual needs.
  • the passivation layer is a layer of SiOx (silicon oxide) material; in another example, a layer of SiNx (silicon nitride) material.
  • SiOx or SiNx materials can be arbitrarily selected for the thin films of different layers.
  • the protective conductive layer is formed on the metal layer and the sidewall of the opening, and a part of the protective conductive layer extends to the interlayer insulating layer.
  • the protective conductive layer can prevent the metal layer on the interlayer insulating layer from being directly exposed.
  • the etching solution is corroded or oxidized. For example, in the process of etching the pixel electrode layer, it can prevent the acid solution from penetrating into the metal layer on the inter-insulating layer to corrode it, or, Bonding
  • the metal layer on the insulating layer in the pad area is directly exposed, which can avoid oxidation in subsequent processes (eg, reliability RA test).
  • the protective conductive layer also plays the role of conducting electrical signals, and the protective conducting layer has electrical signal conducting properties, which can realize electrical signal conducting between the metal layer and the pixel anode layer.
  • the protective conductive layer may be formed of a material that can conduct electrical signals and resist corrosion by an etching solution.
  • the protective conductive layer is a MoTi (molybdenum-titanium alloy) material layer.
  • the metal layer on the interlayer insulating layer includes the source-drain metal layer of the display region and the metal layer of the Bonding Pad region.
  • the material of the metal layer is, but not limited to, the following: Mo (molybdenum), Ti (titanium), Cu (copper), or other alloys.
  • the interlayer insulating layer is a thin film with a one-layer structure; in another example, the interlayer insulating layer is a thin film with a two-layer structure; in yet another example, the interlayer insulating layer is a thin film with a multi-layer structure. The specific number of layers can be determined according to actual needs.
  • the interlayer insulating layer is a SiOx (silicon oxide) material layer; in another example, a SiNx (silicon nitride) material layer. Further, the interlayer insulating layer is a thin film with two or more layers, and SiOx or SiNx materials can be arbitrarily selected for the thin films of different layers.
  • the planarization layer is used to provide a flat bearing surface for the subsequent process flow.
  • the planarization layer is a thin film with a one-layer structure; in another example, the planarization layer is a thin film with a two-layer structure.
  • the material of the planarization layer is the following but not limited to the following: silicon oxide.
  • the top-emitting AMOLED display panel further includes a glass substrate 21 , a light shielding layer 23 , a buffer layer 25 , a semiconductor layer 27 , a gate insulating layer 29 and a gate metal layer 31 ;
  • the light shielding layer 23 is sandwiched between the glass substrate 21 and the buffer layer 25;
  • the semiconductor layer 27 is arranged on the buffer layer 25;
  • the gate insulating layer 29 is sandwiched between the semiconductor layer 27 and the gate metal layer 31;
  • the interlayer insulating layer 15 is disposed on the buffer layer 25 and covers the semiconductor layer 27 , the gate insulating layer 29 and the gate metal layer 31 .
  • the glass substrate is the support structure of the top-emitting AMOLED display panel.
  • a light-shielding layer is arranged on the glass substrate.
  • the material of the light shielding layer is the following but not limited to the following materials: Mo, Ti, Cu or other alloys.
  • a buffer layer is arranged on the glass substrate, and the buffer layer wraps the light shielding layer.
  • the buffer layer is a film with a one-layer structure; in another example, the buffer layer is a film with a two-layer structure; in yet another example, the buffer layer is a film with a multi-layer structure.
  • the specific number of layers can be determined according to actual needs.
  • the buffer layer is a layer of SiOx (silicon oxide) material; in another example, a layer of SiNx (silicon nitride) material.
  • the buffer layer is a thin film with two or more layers, and SiOx or SiNx materials can be arbitrarily selected for the thin films of different layers.
  • the semiconductor layer is disposed on the buffer layer.
  • the material of the semiconductor layer is the following but not limited to the following materials: IGZO (indium gallium zinc oxide, indium gallium zinc oxide), IZTO (indium zinc tin oxide, indium zinc tin oxide) or IGZTO (indium gallium zinc tin oxide, indium gallium zinc oxide) zinc tin oxide).
  • the gate insulating layer is provided on the semiconductor layer.
  • the gate insulating layer is a thin film with a one-layer structure; in another example, the gate insulating layer is a thin film with a two-layer structure; in yet another example, the gate insulating layer is a thin film with a multi-layer structure.
  • the specific number of layers can be determined according to actual needs.
  • the gate insulating layer is a layer of SiOx (silicon oxide) material; in another example, a layer of SiNx (silicon nitride) material.
  • the gate insulating layer is a thin film with two or more layers, and SiOx or SiNx materials can be arbitrarily selected for the thin films of different layers.
  • the gate metal layer is disposed on the gate insulating layer, and the material of the gate metal layer is the following but not limited to the following materials: Mo, Ti, Cu or other alloys.
  • the top emission AMOLED display panel further includes a pixel electrode layer 33 and a pixel definition layer 35 ;
  • the pixel electrode layer 33 is disposed on the planarization layer 17, and the pixel electrode layer 33 penetrates through the planarization layer 17 and contacts the corresponding protective conductive layer 13;
  • the pixel definition layer 35 is provided on the planarization layer 17 .
  • the pixel electrode layer is disposed on the planarization layer, and the material of the pixel electrode layer is the following but not limited to the following materials: ITO/Ag/ITO, IZO/Ag/IZO, and the like.
  • a passivation layer and a protective conductive layer are included; the passivation layer is sandwiched between the interlayer insulating layer and the planarization layer of the top-emitting AMOLED display panel; the passivation layer corresponds to The metal layer is provided with an opening; the metal layer is a metal layer formed on the interlayer insulating layer; the protective conductive layer covers the metal layer and the sidewall of the opening, and a part of the protective conductive layer extends to the interlayer insulating layer , wherein the passivation layer is covered on the metal layer formed on the interlayer insulating layer, which can physically protect the metal layer to avoid its oxidation, and protect the conductive layer to cover the metal layer to prevent the metal layer from being engraved by the anode in the subsequent process.
  • the etchant is etched or oxidized, thereby improving the reliability of electrical signal conduction and improving the performance of the top-emitting AMOLED display panel.
  • a method for manufacturing a top-emitting AMOLED display panel including the following steps:
  • step S41 a glass substrate is provided; a light shielding layer, a buffer layer, a semiconductor layer, a gate insulating layer, a gate metal layer, an interlayer insulating layer and a metal layer formed on the interlayer insulating layer are formed on the glass substrate.
  • the deposition process, etching process and other processes are used to form a light-shielding layer, a buffer layer, a semiconductor layer, a gate insulating layer, a gate metal layer, an interlayer insulating layer and a layer formed on the glass substrate in sequence.
  • Metal layer on insulating layer is used to form a light-shielding layer, a buffer layer, a semiconductor layer, a gate insulating layer, a gate metal layer, an interlayer insulating layer and a layer formed on the glass substrate in sequence.
  • the deposition process can be any one of the following processes: chemical vapor deposition (Chemical Vapor Deposition) Vapor Deposition, CVD), Physical Vapor Deposition (Physical Vapor Deposition, PVD), Atomic Layer Deposition (atomic layer deposition) deposition, ALD), low pressure chemical vapor deposition (Low Pressure Chemical Vapor Deposition, LPCVD), Laser ablation deposition (Laser ablation deposition, LAD) and Selective Epitaxy (Selective) epitaxial growth, SEG).
  • the etching process is dry etching or wet etching.
  • the glass substrate is the support structure of the top-emitting AMOLED display panel.
  • a light-shielding layer is arranged on the glass substrate.
  • the material of the light shielding layer is the following but not limited to the following materials: Mo, Ti, Cu or other alloys.
  • a buffer layer is arranged on the glass substrate, and the buffer layer wraps the light shielding layer.
  • the buffer layer is a film with a one-layer structure; in another example, the buffer layer is a film with a two-layer structure; in yet another example, the buffer layer is a film with a multi-layer structure.
  • the specific number of layers can be determined according to actual needs.
  • the buffer layer is a layer of SiOx (silicon oxide) material; in another example, a layer of SiNx (silicon nitride) material.
  • the buffer layer is a thin film with two or more layers, and SiOx or SiNx materials can be arbitrarily selected for the thin films of different layers.
  • the semiconductor layer is disposed on the buffer layer.
  • the material of the semiconductor layer is the following but not limited to the following materials: IGZO (indium gallium zinc oxide, indium gallium zinc oxide), IZTO (indium zinc tin oxide, indium zinc tin oxide) or IGZTO (indium gallium zinc tin oxide, indium gallium zinc oxide) zinc tin oxide).
  • the gate insulating layer is provided on the semiconductor layer.
  • the gate insulating layer is a thin film with a one-layer structure; in another example, the gate insulating layer is a thin film with a two-layer structure; in yet another example, the gate insulating layer is a thin film with a multi-layer structure.
  • the specific number of layers can be determined according to actual needs.
  • the gate insulating layer is a layer of SiOx (silicon oxide) material; in another example, a layer of SiNx (silicon nitride) material.
  • the gate insulating layer is a thin film with two or more layers, and SiOx or SiNx materials can be arbitrarily selected for the thin films of different layers.
  • the gate metal layer is disposed on the gate insulating layer, and the material of the gate metal layer is the following but not limited to the following materials: Mo, Ti, Cu or other alloys.
  • the interlayer insulating layer is a thin film with a one-layer structure; in another example, the interlayer insulating layer is a thin film with a two-layer structure; in yet another example, the interlayer insulating layer is a thin film with a multi-layer structure.
  • the specific number of layers can be determined according to actual needs.
  • the interlayer insulating layer is a SiOx (silicon oxide) material layer; in another example, a SiNx (silicon nitride) material layer.
  • the interlayer insulating layer is a thin film with two or more layers, and SiOx or SiNx materials can be arbitrarily selected for the thin films of different layers.
  • the metal layer on the interlayer insulating layer includes the source and drain metal layers of the display area and the Bonding The metal layer of the pad area.
  • the material of the metal layer is, but not limited to, the following: Mo (molybdenum), Ti (titanium), Cu (copper), or other alloys.
  • the planarization layer is used to provide a flat bearing surface for the subsequent process flow.
  • the planarization layer is a thin film with a one-layer structure; in another example, the planarization layer is a thin film with a two-layer structure.
  • the material of the planarization layer is the following but not limited to the following: silicon oxide.
  • Step S43 forming a passivation layer on the interlayer insulating layer.
  • the passivation layer is a protective layer formed of insulating material, which is formed on the interlayer insulating layer of the top-emitting AMOLED display panel, and covers the metal layer on the interlayer insulating layer to physically protect the metal layer.
  • the metal layer includes the source and drain metal layers in the display area and the Bonding The metal layer of the pad area.
  • the passivation layer is patterned, and openings are formed at positions corresponding to the metal layers to expose the metal layers for subsequent processes.
  • the passivation layer is a thin film with a one-layer structure; in another example, the passivation layer is a thin film with a two-layer structure; in yet another example, the passivation layer is a thin film with a multi-layer structure.
  • the specific number of layers can be determined according to actual needs.
  • depositing SiOx material on the interlayer insulating layer to form a passivation layer in one example, in the step of forming a passivation layer: depositing SiOx material on the interlayer insulating layer to form a passivation layer; in another example, in the interlayer insulating layer
  • depositing SiNx material on the interlayer insulating layer to form a passivation layer depositing SiNx material on the interlayer insulating layer to form a passivation layer.
  • SiOx or SiNx materials can be arbitrarily selected for the thin films of different layers.
  • Step S45 forming openings on the passivation layer corresponding to the metal layer.
  • Step S47 forming a protective conductive layer on the sidewall of the opening, the metal layer and the interlayer insulating layer.
  • the protective conductive layer is formed on the metal layer and the sidewall of the opening, and a part of the protective conductive layer extends to the interlayer insulating layer.
  • the protective conductive layer can prevent the metal layer on the interlayer insulating layer from being directly exposed.
  • the etching solution is corroded or oxidized. For example, in the process of etching the pixel electrode layer, it can prevent the acid solution from penetrating into the metal layer on the inter-insulating layer to corrode it, or, Bonding
  • the metal layer on the insulating layer in the pad area is directly exposed, which can avoid oxidation in subsequent processes (eg, reliability RA test).
  • the protective conductive layer also plays the role of conducting electrical signals, and the protective conducting layer has electrical signal conducting properties, which can realize electrical signal conducting between the metal layer and the pixel anode layer.
  • the protective conductive layer can be formed of a material that can both conduct electrical signals and resist corrosion by an etching solution.
  • MoTi material is deposited on the sidewalls of the opening, the metal layer and the interlayer insulating layer to form a protective conductive layer.
  • the method for manufacturing a top-emitting AMOLED display panel further includes the steps of:
  • Step S51 forming a planarization layer on the passivation layer
  • Step S53 forming a through hole on the planarization layer; the cavity of the through hole communicates with the cavity of the opening;
  • Step S55 forming a pixel electrode layer in the cavity of the through hole and on the planarization layer;
  • step S57 a pixel definition layer is formed on the planarization layer and the pixel electrode layer.
  • planarization layer is used to provide a flat bearing surface for the subsequent process flow.
  • the planarization layer is a one-layer structure film; in another example, the planarization layer is a two-layer structure film .
  • the material of the planarization layer is the following but not limited to the following: silicon oxide.
  • the pixel electrode layer is disposed on the planarization layer, and the material of the pixel electrode layer is the following but not limited to the following materials: ITO/Ag/ITO, IZO/Ag/IZO, and the like.
  • the metal layer formed on the interlayer insulating layer can be covered by a passivation layer, so that the metal layer can be physically protected to avoid its oxidation, and the protective conductive layer can cover the metal layer.
  • the protective conduction layer has the performance of conducting electrical signals, which can realize the metal layer on the interlayer insulating layer and the Electrical signal conduction between other metal layers within a top-emitting AMOLED display panel.
  • a display device including the top-emission AMOLED display panel described in each of the embodiments of the top-emission AMOLED display panel of the present application.

Abstract

本申请涉及一种顶发光AMOLED显示面板、制作方法以及显示装置；所述顶发光AMOLED显示面板包括钝化层以及保护传导层；钝化层夹设于顶发光AMOLED显示面板的层间绝缘层与平坦化层之间；保护传导层覆盖在金属层和开孔的侧壁上，钝化层覆盖可对金属层进行物理防护避免其氧化，保护传导层包覆住金属层避免金属层被阳极刻蚀液刻蚀或氧化。

Description

顶发光AMOLED显示面板、制作方法以及显示装置 技术领域
本申请涉及显示技术领域，特别是涉及一种顶发光AMOLED显示面板、制作方法以及显示装置。
 背景技术
AMOLED（Active-matrix organic light-emitting diode，有源矩阵有机发光二极体或主动矩阵有机发光二极体）显示技术具备响应速度快、自发光、显示效果优异以及电能消耗低等优点，而逐渐得到广泛的应用。
AMOLED面板通常采用导电性较好的铜或铜合金做金属走线，对于Bonding Pad（结合区）区，铜无法裸漏在表面作为Bonding Pad。目前，底发光的AMOLED面板中采用导电金属氧化物ITO（Indium Tin Oxides，铟锡氧化物）作为Bonding Pad，但是，在开发顶发光的AMOLED面板时发现，由于顶发光的阳极通常采用ITO/Ag（Argentum，银）/ITO或IZO/Ag/IZO（Indium zinc oxid，氧化铟锌），在蚀刻阳极过程中，若Bonding Pad为ITO，酸液往往会渗透ITO进而蚀刻下方的金属层，最终导致Bonding Pad异常；若Bonding Pad为带有金属银的复合层，在信赖性RA（Reliant Apprais，e信赖性）测试中，Bonding Pad极易出现银氧化的问题，而且在发光区的金属层在刻蚀过程中，也会出现铜氧化的问题。
 技术问题
在实现过程中，发明人发现传统技术中至少存在如下问题：传统AMOLED面板的存在电信号传输不良的问题。
 技术解决方案
基于此，有必要针对传统AMOLED面板的存在电信号传输不良的问题，提供一种顶发光AMOLED显示面板、制作方法以及显示装置。
为了实现上述目的，一方面，本申请实施例提供了一种顶发光AMOLED显示面板，包括钝化层以及保护传导层；
钝化层夹设于顶发光AMOLED显示面板的层间绝缘层与平坦化层之间；钝化层上对应于金属层开设有开孔；金属层为形成于层间绝缘层上的金属层；
保护传导层覆盖在金属层和开孔的侧壁上，且保护传导层的一部分延伸至钝化层上。
另一方面，本申请实施例还提供了一种顶发光AMOLED显示面板制作方法，包括以下步骤：
提供玻璃基板；玻璃基板上形成有避光层、缓冲层、半导体层、栅极绝缘层、栅极金属层、层间绝缘层以及形成于层间绝缘层上的金属层；
在层间绝缘层上形成钝化层；
在钝化层上对应于金属层形成开孔；
在开孔的侧壁、金属层和层间绝缘层上形成保护传导层。
又一方面，本申请实施例还提供了一种显示装置，包括顶发光AMOLED显示面板；
顶发光AMOLED显示面板包括钝化层以及保护传导层；
钝化层夹设于顶发光AMOLED显示面板的层间绝缘层与平坦化层之间；钝化层上对应于金属层开设有开孔；金属层为形成于层间绝缘层上的金属层；
保护传导层覆盖在金属层和开孔的侧壁上，且保护传导层的一部分延伸至钝化层上。
 有益效果
本申请各实施例提供的顶发光AMOLED显示面板，包括钝化层以及保护传导层；钝化层夹设于顶发光AMOLED显示面板的层间绝缘层与平坦化层之间；钝化层上对应于金属层开设有开孔；金属层为形成于层间绝缘层上的金属层；保护传导层覆盖在金属层和开孔的侧壁上，且保护传导层的一部分延伸至层间绝缘层上，其中，钝化层覆盖在形成于层间绝缘层上的金属层上，可对金属层进行物理防护避免其氧化，保护传导层包覆住金属层，避免金属层被后续工艺中的阳极刻蚀液刻蚀或氧化，从而提高电信号传导的可靠性，提高顶发光AMOLED显示面板的性能。
 附图说明
图1为一个实施例中顶发光AMOLED显示面板的结构示意图；
图2为另一个实施例中顶发光AMOLED显示面板的结构示意图；
图3为又一个实施例中顶发光AMOLED显示面板的结构示意图；
图4为一个实施例中顶发光AMOLED显示面板制作方法的流程示意图；
图5为又一个实施例中顶发光AMOLED显示面板制作方法的流程示意图。
 本发明的实施方式
为了便于理解本申请，下面将参照相关附图对本申请进行更全面的描述。附图中给出了本申请的首选实施例。但是，本申请可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本申请的公开内容更加透彻全面。
需要说明的是，当一个元件被认为是“连接”另一个元件，它可以是直接连接到另一个元件并与之结合为一体，或者可能同时存在居中元件。本文所使用的术语“设置”、“接触”、“夹设”以及类似的表述只是为了说明的目的。
除非另有定义，本文所使用的所有的技术和科学术语与属于本申请的技术领域的技术人员通常理解的含义相同。本文中在本申请的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本申请。本文所使用的术语“及／或”包括一个或多个相关的所列项目的任意的和所有的组合。
为了解决传统AMOLED面板的存在电信号传输不良的问题，在一个实施例中，如图1所示，提供了一种顶发光AMOLED显示面板，包括钝化层11以及保护传导层13；
钝化层11夹设于顶发光AMOLED显示面板的层间绝缘层15与平坦化层17之间；钝化层11上对应于金属层19开设有开孔111；金属层19为形成于层间绝缘层15上的金属层；
保护传导层13覆盖在金属层19和开孔111的侧壁上，且保护传导层13的一部分延伸至钝化层11上。
需要说明的是，钝化层是由绝缘材料形成的保护层，其形成在顶发光AMOLED显示面板的层间绝缘层之上，并覆盖层间绝缘层上的金属层，对金属层进行物理防护。其中，金属层包括显示区内的源漏极金属层和Bonding Pad区的金属层。对钝化层进行图形化，在对应金属层的位置形成开孔，以露出金属层，以备后续流程。在一个示例中，钝化层为一层结构的薄膜；在另一个示例中，钝化层为两层结构的薄膜；在又一个示例中，钝化层为多层结构的薄膜。具体层数可根据实际需求而定。为了实现绝缘钝化，在一个示例中，钝化层为SiOx（氧化硅）材料层；在另一个示例中，SiNx（氮化硅）材料层。进一步的，在钝化层为两层及以上结构的薄膜，不同层的薄膜可任意选用SiOx或SiNx材料。
保护传导层形成在金属层和开孔的侧壁上，且保护传导层的一部分延伸至层间绝缘层上，保护传导层可防止层间绝缘层上的金属层直接裸露，在后续工艺中遭受刻蚀液腐蚀或者氧化，例如，在刻蚀像素电极层过程中，可避免酸液渗透到间绝缘层上的金属层对其产生腐蚀，或者，Bonding Pad区间绝缘层上的金属层直接裸露，可避免在后续工艺（例如，信赖性RA测试）中遭受氧化。进一步的，保护传导层还起到电信号传导作用，保护传导层具备电信号传导性能，能实现金属层与像素阳极层的电信号传导。保护传导层可选用即可传导电信号，又可耐刻蚀液腐蚀的材料形成，在一个示例中，保护传导层为MoTi（钼钛合金）材料层。
层间绝缘层上的金属层包括显示区的源漏极金属层和Bonding Pad区的金属层。在一个示例中，金属层的材料为以下但不限于以下：Mo（钼）、Ti（钛）、Cu（铜）或者其它合金。在一个示例中，层间绝缘层为一层结构的薄膜；在另一个示例中，层间绝缘层为两层结构的薄膜；在又一个示例中，层间绝缘层为多层结构的薄膜。具体层数可根据实际需求而定。为了实现绝缘钝化，在一个示例中，层间绝缘层为SiOx（氧化硅）材料层；在另一个示例中，SiNx（氮化硅）材料层。进一步的，在层间绝缘层为两层及以上结构的薄膜，不同层的薄膜可任意选用SiOx或SiNx材料。
平坦化层用于为后续工艺流程提供平坦的承载面，在一个示例中，平坦化层为一层结构的薄膜；在另一个示例中，平坦化层为两层结构的薄膜。平坦化层的材料为以下但不限于以下：氧化硅。
进一步的，如图2所示，顶发光AMOLED显示面板还包括玻璃基板21、避光层23、缓冲层25、半导体层27、栅极绝缘层29以及栅极金属层31；
避光层23夹设于玻璃基板21和缓冲层25之间；
半导体层27设置在缓冲层25上；
栅极绝缘层29夹设于半导体层27和栅极金属层31之间；
层间绝缘层15设置在缓冲层25上，且包覆半导体层27、栅极绝缘层29和栅极金属层31。
需要说明的是，玻璃基板是顶发光AMOLED显示面板的支撑结构。在玻璃基板上设置避光层。避光层的材料为以下但不限于以下材料：Mo、Ti、Cu或其它合金。
在玻璃基板上设置缓冲层，且缓冲层包裹避光层。在一个示例中，缓冲层为一层结构的薄膜；在另一个示例中，缓冲层为两层结构的薄膜；在又一个示例中，缓冲层为多层结构的薄膜。具体层数可根据实际需求而定。为了实现绝缘钝化，在一个示例中，缓冲层为SiOx（氧化硅）材料层；在另一个示例中，SiNx（氮化硅）材料层。进一步的，在缓冲层为两层及以上结构的薄膜，不同层的薄膜可任意选用SiOx或SiNx材料。
半导体层设置在缓冲层上。半导体层的材料为以下但不限于以下材料：IGZO（indium gallium zinc oxide，铟镓锌氧化物）、IZTO（Indium zinc tin oxide，铟锌锡氧化物）或IGZTO（indium gallium zinc tin oxide，铟镓锌锡氧化物）。
栅极绝缘层设置在半导体层。在一个示例中，栅极绝缘层为一层结构的薄膜；在另一个示例中，栅极绝缘层为两层结构的薄膜；在又一个示例中，栅极绝缘层为多层结构的薄膜。具体层数可根据实际需求而定。为了实现绝缘钝化，在一个示例中，栅极绝缘层为SiOx（氧化硅）材料层；在另一个示例中，SiNx（氮化硅）材料层。进一步的，在栅极绝缘层为两层及以上结构的薄膜，不同层的薄膜可任意选用SiOx或SiNx材料。
栅极金属层设置在栅极绝缘层上，栅极金属层的材料为以下但不限于以下材料：Mo、Ti、Cu或其它合金。
进一步的，如图3所示，顶发光AMOLED显示面板还包括像素电极层33以及像素定义层35；
像素电极层33设置在平坦化层17上，且像素电极层33贯穿平坦化层17与对应的保护传导层13接触；
像素定义层35设置在平坦化层17上。
像素电极层设置在平坦化层上，像素电极层的材料为以下但不限于以下材料：ITO/Ag/ITO、IZO/Ag/IZO等。
本申请顶发光AMOLED显示面板的各实施例中，包括钝化层以及保护传导层；钝化层夹设于顶发光AMOLED显示面板的层间绝缘层与平坦化层之间；钝化层上对应于金属层开设有开孔；金属层为形成于层间绝缘层上的金属层；保护传导层覆盖在金属层和开孔的侧壁上，且保护传导层的一部分延伸至层间绝缘层上，其中，钝化层覆盖在形成于层间绝缘层上的金属层上，可对金属层进行物理防护避免其氧化，保护传导层包覆住金属层，避免金属层被后续工艺中的阳极刻蚀液刻蚀或氧化，从而提高电信号传导的可靠性，提高顶发光AMOLED显示面板的性能。
在一个实施例中，如图4所述，还提供了一种顶发光AMOLED显示面板制作方法，包括以下步骤：
步骤S41，提供玻璃基板；玻璃基板上形成有避光层、缓冲层、半导体层、栅极绝缘层、栅极金属层、层间绝缘层以及形成于层间绝缘层上的金属层。
需要说明的是，采用沉积工艺、刻蚀工艺等工艺，在玻璃基板上依次形成避光层、缓冲层、半导体层、栅极绝缘层、栅极金属层、层间绝缘层和形成于层间绝缘层上的金属层。其中，沉积工艺可为以下工艺的任意一种：化学气相沉积法（Chemical Vapor Deposition，CVD）、物理气相沉积法（Physical Vapor Deposition，PVD）、原子层沉积法（atomic layer deposition，ALD）、低压化学气相沉积法（Low Pressure Chemical Vapor Deposition，LPCVD）、激光烧蚀沉积法（Laser ablation deposition，LAD）和选择外延生长法（Selective epitaxial growth，SEG）。刻蚀工艺为干法刻蚀或湿法腐蚀。
玻璃基板是顶发光AMOLED显示面板的支撑结构。在玻璃基板上设置避光层。避光层的材料为以下但不限于以下材料：Mo、Ti、Cu或其它合金。
在玻璃基板上设置缓冲层，且缓冲层包裹避光层。在一个示例中，缓冲层为一层结构的薄膜；在另一个示例中，缓冲层为两层结构的薄膜；在又一个示例中，缓冲层为多层结构的薄膜。具体层数可根据实际需求而定。为了实现绝缘钝化，在一个示例中，缓冲层为SiOx（氧化硅）材料层；在另一个示例中，SiNx（氮化硅）材料层。进一步的，在缓冲层为两层及以上结构的薄膜，不同层的薄膜可任意选用SiOx或SiNx材料。
半导体层设置在缓冲层上。半导体层的材料为以下但不限于以下材料：IGZO（indium gallium zinc oxide，铟镓锌氧化物）、IZTO（Indium zinc tin oxide，铟锌锡氧化物）或IGZTO（indium gallium zinc tin oxide，铟镓锌锡氧化物）。
栅极绝缘层设置在半导体层。在一个示例中，栅极绝缘层为一层结构的薄膜；在另一个示例中，栅极绝缘层为两层结构的薄膜；在又一个示例中，栅极绝缘层为多层结构的薄膜。具体层数可根据实际需求而定。为了实现绝缘钝化，在一个示例中，栅极绝缘层为SiOx（氧化硅）材料层；在另一个示例中，SiNx（氮化硅）材料层。进一步的，在栅极绝缘层为两层及以上结构的薄膜，不同层的薄膜可任意选用SiOx或SiNx材料。
栅极金属层设置在栅极绝缘层上，栅极金属层的材料为以下但不限于以下材料：Mo、Ti、Cu或其它合金。
在一个示例中，层间绝缘层为一层结构的薄膜；在另一个示例中，层间绝缘层为两层结构的薄膜；在又一个示例中，层间绝缘层为多层结构的薄膜。具体层数可根据实际需求而定。为了实现绝缘钝化，在一个示例中，层间绝缘层为SiOx（氧化硅）材料层；在另一个示例中，SiNx（氮化硅）材料层。进一步的，在层间绝缘层为两层及以上结构的薄膜，不同层的薄膜可任意选用SiOx或SiNx材料。层间绝缘层上的金属层包括显示区的源漏极金属层和Bonding Pad区的金属层。在一个示例中，金属层的材料为以下但不限于以下：Mo（钼）、Ti（钛）、Cu（铜）或者其它合金。
平坦化层用于为后续工艺流程提供平坦的承载面，在一个示例中，平坦化层为一层结构的薄膜；在另一个示例中，平坦化层为两层结构的薄膜。平坦化层的材料为以下但不限于以下：氧化硅。
步骤S43，在层间绝缘层上形成钝化层。
钝化层是由绝缘材料形成的保护层，其形成在顶发光AMOLED显示面板的层间绝缘层之上，并覆盖层间绝缘层上的金属层，对金属层进行物理防护。其中，金属层包括显示区内的源漏极金属层和Bonding Pad区的金属层。对钝化层进行图形化，在对应金属层的位置形成开孔，以露出金属层，以备后续流程。在一个示例中，钝化层为一层结构的薄膜；在另一个示例中，钝化层为两层结构的薄膜；在又一个示例中，钝化层为多层结构的薄膜。具体层数可根据实际需求而定。为了实现绝缘钝化，在一个示例中，在层间绝缘层上形成钝化层步骤中：在层间绝缘层上沉积SiOx材料，以形成钝化层；在另一个示例中，在层间绝缘层上形成钝化层步骤中：在层间绝缘层上沉积SiNx材料，以形成钝化层。进一步的，在钝化层为两层及以上结构的薄膜，不同层的薄膜可任意选用SiOx或SiNx材料。
步骤S45，在钝化层上对应于金属层形成开孔。
步骤S47，在开孔的侧壁、金属层和层间绝缘层上形成保护传导层。
保护传导层形成在金属层和开孔的侧壁上，且保护传导层的一部分延伸至层间绝缘层上，保护传导层可防止层间绝缘层上的金属层直接裸露，在后续工艺中遭受刻蚀液腐蚀或者氧化，例如，在刻蚀像素电极层过程中，可避免酸液渗透到间绝缘层上的金属层对其产生腐蚀，或者，Bonding Pad区间绝缘层上的金属层直接裸露，可避免在后续工艺（例如，信赖性RA测试）中遭受氧化。进一步的，保护传导层还起到电信号传导作用，保护传导层具备电信号传导性能，能实现金属层与像素阳极层的电信号传导。保护传导层可选用即可传导电信号，又可耐刻蚀液腐蚀的材料形成，在一个示例中，在开孔的侧壁、金属层和层间绝缘层上形成保护传导层的步骤中：在开孔的侧壁、金属层和层间绝缘层上沉积MoTi材料，以形成保护传导层。
进一步的，如图5所示，顶发光AMOLED显示面板制作方法还包括步骤：
步骤S51，在钝化层上形成平坦化层；
步骤S53，在平坦化层上形成通孔；通孔的腔与开孔的腔连通；
步骤S55，在通孔的腔内和平坦化层上形成像素电极层；
步骤S57，在平坦化层和像素电极层上形成像素定义层。
需要说明的是，平坦化层用于为后续工艺流程提供平坦的承载面，在一个示例中，平坦化层为一层结构的薄膜；在另一个示例中，平坦化层为两层结构的薄膜。平坦化层的材料为以下但不限于以下：氧化硅。
像素电极层设置在平坦化层上，像素电极层的材料为以下但不限于以下材料：ITO/Ag/ITO、IZO/Ag/IZO等。
本申请顶发光AMOLED显示面板制作方法各实施例中，通过钝化层覆盖在形成于层间绝缘层上的金属层上，可对金属层进行物理防护避免其氧化，保护传导层包覆住金属层，避免金属层被后续工艺中的阳极刻蚀液刻蚀或氧化，从而提高电信号传导的可靠性，而且保护传导层有传导电信号的性能，能够实现层间绝缘层上的金属层与顶发光AMOLED显示面板内其它金属层之间的电信号传导。
在一个实施例中，提供了一种显示装置，包括本申请顶发光AMOLED显示面板各实施例所述的顶发光AMOLED显示面板。
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本申请的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对申请专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干变形和改进，这些都属于本申请的保护范围。因此，本申请专利的保护范围应以所附权利要求为准。

Claims (20)

  1. 一种顶发光AMOLED显示面板，其中，包括钝化层以及保护传导层；
    所述钝化层夹设于所述顶发光AMOLED显示面板的层间绝缘层与平坦化层之间；所述钝化层上对应于金属层开设有开孔；所述金属层为形成于所述层间绝缘层上的金属层；
    所述保护传导层覆盖在所述金属层和所述开孔的侧壁上，且所述保护传导层的一部分延伸至所述钝化层上。
  2. 根据权利要求1所述的顶发光AMOLED显示面板，其中，还包括玻璃基板、避光层、缓冲层、半导体层、栅极绝缘层以及栅极金属层；
    所述避光层夹设于所述玻璃基板和所述缓冲层之间；
    所述半导体层设置在所述缓冲层上；
    所述栅极绝缘层夹设于所述半导体层和所述栅极金属层之间；
    所述层间绝缘层设置在所述缓冲层上，且包覆所述半导体层、所述栅极绝缘层和所述栅极金属层。
  3. 根据权利要求2所述的顶发光AMOLED显示面板，其中，还包括像素电极层以及像素定义层；
    所述像素电极层设置在所述平坦化层上，且所述像素电极层贯穿所述平坦化层与对应的所述保护传导层接触；
    所述像素定义层设置在所述平坦化层上。
  4. 根据权利要求1所述的顶发光AMOLED显示面板，其中，所述保护传导层为MoTi材料层。
  5. 根据权利要求2所述的顶发光AMOLED显示面板，其中，所述保护传导层为MoTi材料层。
  6. 根据权利要求3所述的顶发光AMOLED显示面板，其中，所述保护传导层为MoTi材料层。
  7. 根据权利要求1的顶发光AMOLED显示面板，其中，所述钝化层为一层结构、两层结构或多层结构的薄膜。
  8. 根据权利要求2的顶发光AMOLED显示面板，其中，所述钝化层为一层结构、两层结构或多层结构的薄膜。
  9. 根据权利要求3的顶发光AMOLED显示面板，其中，所述钝化层为一层结构、两层结构或多层结构的薄膜。
  10. 根据权利要求7所述的顶发光AMOLED显示面板，其中，所述钝化层为SiOx材料层或SiNx材料层。
  11. 一种顶发光AMOLED显示面板制作方法，其中，包括以下步骤：
    提供玻璃基板；所述玻璃基板上形成有避光层、缓冲层、半导体层、栅极绝缘层、栅极金属层、层间绝缘层以及形成于所述层间绝缘层上的金属层；
    在所述层间绝缘层上形成钝化层；
    在所述钝化层上对应于所述金属层形成开孔；
    在所述开孔的侧壁、所述金属层和所述层间绝缘层上形成保护传导层。
  12. 根据权利要求11所述的顶发光AMOLED显示面板制作方法，其中，还包括步骤：
    在所述钝化层上形成平坦化层；
    在所述平坦化层上形成通孔；所述通孔的腔与所述开孔的腔连通；
    在所述通孔的腔内和所述平坦化层上形成像素电极层；
    在所述平坦化层和所述像素电极层上形成像素定义层。
  13. 根据权利要求11所述的顶发光AMOLED显示面板制作方法，其中，在所述开孔的侧壁、所述金属层和所述层间绝缘层上形成保护传导层的步骤中：
    在所述开孔的侧壁、所述金属层和所述层间绝缘层上沉积MoTi材料，以形成所述保护传导层。
  14. 根据权利要求12所述的顶发光AMOLED显示面板制作方法，其中，在所述开孔的侧壁、所述金属层和所述层间绝缘层上形成保护传导层的步骤中：
    在所述开孔的侧壁、所述金属层和所述层间绝缘层上沉积MoTi材料，以形成所述保护传导层。
  15. 根据权利要求11所述的顶发光AMOLED显示面板制作方法，其中，所述钝化层为一层结构、两层结构或多层结构的薄膜。
  16. 根据权利要求15所述的顶发光AMOLED显示面板制作方法，其中，在所述层间绝缘层上形成钝化层步骤中：
    在所述层间绝缘层上沉积SiOx材料，以形成所述钝化层；或
    在所述层间绝缘层上沉积SiNx材料，以形成所述钝化层。
  17. 一种显示装置，其中，包括顶发光AMOLED显示面板；
    所述顶发光AMOLED显示面板包括钝化层以及保护传导层；
    所述钝化层夹设于所述顶发光AMOLED显示面板的层间绝缘层与平坦化层之间；所述钝化层上对应于金属层开设有开孔；所述金属层为形成于所述层间绝缘层上的金属层；
    所述保护传导层覆盖在所述金属层和所述开孔的侧壁上，且所述保护传导层的一部分延伸至所述钝化层上。
  18. 根据权利要求17所述的显示装置，其中，还包括玻璃基板、避光层、缓冲层、半导体层、栅极绝缘层以及栅极金属层；
    所述避光层夹设于所述玻璃基板和所述缓冲层之间；
    所述半导体层设置在所述缓冲层上；
    所述栅极绝缘层夹设于所述半导体层和所述栅极金属层之间；
    所述层间绝缘层设置在所述缓冲层上，且包覆所述半导体层、所述栅极绝缘层和所述栅极金属层。
  19. 根据权利要求18所述的显示装置，其中，还包括像素电极层以及像素定义层；
    所述像素电极层设置在所述平坦化层上，且所述像素电极层贯穿所述平坦化层与对应的所述保护传导层接触；
    所述像素定义层设置在所述平坦化层上。
  20. 根据权利要求17所述的显示装置，其中，所述保护传导层为MoTi材料层。
PCT/CN2020/122680 2020-09-07 2020-10-22 顶发光 amoled 显示面板、制作方法以及显示装置 WO2022047915A1 (zh)

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