WO2022047673A1 - 电容阵列电路、充放电电路及rc振荡电路 - Google Patents

电容阵列电路、充放电电路及rc振荡电路 Download PDF

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Publication number
WO2022047673A1
WO2022047673A1 PCT/CN2020/113056 CN2020113056W WO2022047673A1 WO 2022047673 A1 WO2022047673 A1 WO 2022047673A1 CN 2020113056 W CN2020113056 W CN 2020113056W WO 2022047673 A1 WO2022047673 A1 WO 2022047673A1
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Prior art keywords
capacitor
mos transistor
nth
resistance
charging
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PCT/CN2020/113056
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English (en)
French (fr)
Inventor
杨江
华超
凌秋蝉
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深圳市汇顶科技股份有限公司
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Priority to EP20951920.6A priority Critical patent/EP4024702A4/en
Priority to PCT/CN2020/113056 priority patent/WO2022047673A1/zh
Publication of WO2022047673A1 publication Critical patent/WO2022047673A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
    • H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
    • H03B5/08—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance
    • H03B5/12—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device
    • H03B5/1237—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device comprising means for varying the frequency of the generator
    • H03B5/1262—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device comprising means for varying the frequency of the generator the means comprising switched elements
    • H03B5/1265—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device comprising means for varying the frequency of the generator the means comprising switched elements switched capacitors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H5/00—One-port networks comprising only passive electrical elements as network components
    • H03H5/12—One-port networks comprising only passive electrical elements as network components with at least one voltage- or current-dependent element
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03J—TUNING RESONANT CIRCUITS; SELECTING RESONANT CIRCUITS
    • H03J3/00—Continuous tuning
    • H03J3/20—Continuous tuning of single resonant circuit by varying inductance only or capacitance only
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/023—Generators characterised by the type of circuit or by the means used for producing pulses by the use of differential amplifiers or comparators, with internal or external positive feedback
    • H03K3/0231—Astable circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
    • H03B2201/00—Aspects of oscillators relating to varying the frequency of the oscillations
    • H03B2201/02—Varying the frequency of the oscillations by electronic means
    • H03B2201/025—Varying the frequency of the oscillations by electronic means the means being an electronic switch for switching in or out oscillator elements
    • H03B2201/0266—Varying the frequency of the oscillations by electronic means the means being an electronic switch for switching in or out oscillator elements the means comprising a transistor

Definitions

  • the present application relates to the technical field of integrated circuits, and in particular, to a capacitor array circuit, a charge-discharge circuit and an RC oscillator circuit.
  • RC oscillators are widely used due to their low cost, low power consumption, and adjustable frequency.
  • the RC oscillator is sensitive to parasitic parameters, and the parasitic parameters are related to the layout design, process and temperature of the RC oscillator. Therefore, the output frequency error of the RC oscillator is relatively large.
  • RC oscillators usually use a capacitor array circuit to adjust the output frequency, but the traditional capacitor array circuit often ignores the influence of parasitic resistance on the total capacitance of the capacitor array circuit, resulting in non-monotonicity in the adjustment of the output frequency of the RC oscillator by the capacitor array circuit. This results in a large error in the output frequency of the RC oscillator.
  • the main purpose of the present application is to provide a capacitor array circuit, a charge-discharge circuit and an RC circuit capable of realizing the monotonic adjustment of the output frequency of the RC oscillator to improve the accuracy of the output frequency of the RC oscillator. oscillator circuit.
  • the application provides a capacitor array circuit, including:
  • the N MOS transistors are in one-to-one correspondence with the N capacitors, wherein the drain of each MOS transistor in the N MOS transistors is connected to one end of the corresponding capacitor through a different metal wire, and each MOS transistor is connected to one end of the corresponding capacitor through a different metal wire.
  • the source of the tube is grounded, and the gate of each MOS tube is used for receiving a control signal to control the turn-on and turn-off of each MOS tube respectively;
  • the other ends of the N capacitors are connected to a common terminal, and the common terminal serves as a capacitor output terminal;
  • the on-resistance of the n-1 th MOS transistor in the N MOS transistors is R onn-1
  • the on-resistance of the n-th MOS transistor is R onn ;
  • the resistance of the metal wire between the n-1 th capacitor and the n-1 th MOS tube is R netn-1
  • the resistance of the metal wire between the n th capacitor and the n th MOS tube is R netn ;
  • the ratio of the width to the length of the n-1th MOS tube is Mn-1
  • the ratio of the width to the length of the nth MOS tube is Mn
  • the ratio of the width to the length of the nth MOS tube Mn is the nth
  • the resistance R netn-1 of the metal line between the n-1th capacitor and the n-1th MOS tube is greater than or equal to A times the resistance R netn of the metal line between the nth capacitor and the nth MOS transistor.
  • the resistance R netn-1 of the metal line between the n-1th capacitor and the n-1th MOS transistor is greater than or equal to the resistance between the nth capacitor and the nth MOS transistor. 2 times the resistance R netn of the metal wire.
  • the number of metal lines between the nth capacitor and the nth MOS transistor is an -1 , the resistance value of each metal line is equal, and the metal line between each capacitor and a corresponding MOS transistor is connected in parallel with each other ; where a is an integer greater than 1.
  • the resistance of the metal line is R netn-1 , and between the n th capacitor and the n th MOS transistor
  • the resistance R netn-1 of the metal wire between the n-1th capacitor and the n-1th MOS tube is the nth capacitor and the nth A times the resistance R netn of the metal line between the MOS transistors.
  • the resistance value of each sheet resistance of the metal wire connected between each of the capacitors and the corresponding one MOS transistor is the same, and the number of sheet resistances of the metal wire between the n-1th capacitor and the n-1th MOS transistor is equal to It is a times the sheet resistance of the metal line between the nth capacitor and the nth MOS transistor.
  • the number of metal lines connected in series between the n-1th capacitor and the n-1th MOS transistor is a times the number of metal lines connected in series between the nth capacitor and the nth MOS transistor,
  • the resistance value per square of the metal wire connected between each of the capacitors and the corresponding one MOS transistor is the same, and the resistance value of each square resistance of the metal wire connected in series between the n-1th capacitor and the n-1th MOS transistor is the same It is the same as the resistance value of each square resistance of the metal line connected in series between the nth capacitor and the nth MOS transistor.
  • the number of metal lines connected in parallel between the nth capacitor and the nth MOS transistor is a times the number of metal lines connected in parallel between the n-1th capacitor and the n-1th MOS transistor,
  • the resistance value per square of the metal wire connected between each of the capacitors and the corresponding one MOS transistor is the same, and the resistance value of each square resistance of the metal wire connected in series between the n-1th capacitor and the n-1th MOS transistor is the same It is the same as the resistance value of each square resistance of the metal line connected in series between the nth capacitor and the nth MOS transistor.
  • the metal wire is a copper wire.
  • control signal is a binary signal.
  • the present application also provides a capacitor charging and discharging circuit, including the above-mentioned capacitor array circuit, a power supply, a first electronic switch, a first resistor and a second electronic switch; the first end of the first electronic switch is connected to the power supply, The second end of the first electronic switch is respectively connected to the first end of the second electronic switch and the capacitor output end through the resistor, the second end of the second electronic switch is grounded, and the first The control terminal of the electronic switch and the control terminal of the second electronic switch are respectively used for receiving a clock signal, and the first electronic switch and the second electronic switch are turned on and off based on the clock signal.
  • the first electronic switch is a PMOS transistor
  • the second electronic switch is an NMOS transistor
  • the present application provides an RC oscillator circuit, including a first charge and discharge circuit, a second charge and discharge circuit, a first comparator, a second comparator, a reference voltage unit, a logic unit and a control unit, a first charge and discharge circuit and a second
  • the charging and discharging circuits are respectively the above-mentioned capacitor charging and discharging circuits; the first input terminal of the first comparator is connected to the capacitor output terminal of the first charging and discharging circuit, and the second input terminal of the first comparator is connected to the capacitor output terminal of the first comparator.
  • the reference voltage unit is connected; the first input end of the second comparator is connected with the capacitor output end of the second charging and discharging circuit, and the second input end of the second comparator is connected with the reference voltage unit;
  • the output end of the first comparator and the output end of the second comparator are both connected to the input end of the logic unit, and the output end of the logic unit is respectively connected to the control end and the control end of the first electronic switch.
  • the control terminal of the second electronic switch is connected; the control unit is respectively connected with the gate of each MOS tube;
  • the reference voltage unit is used for generating a reference voltage
  • the first charging and discharging circuit is used for transmitting a first charging voltage or a first discharging voltage to the first comparator
  • the first comparator is used for comparing the first charging voltage and the reference voltage, or comparing the first discharging voltage and the reference voltage, and outputting a first comparison result to the logic unit ;
  • the second charging and discharging circuit is used for transmitting a second charging voltage or a second discharging voltage to the second comparator
  • the second comparator is used for comparing the second charging voltage and the reference voltage, or comparing the second discharging voltage and the reference voltage, and outputting a second comparison result to the logic unit ;
  • the logic unit is configured to output a clock signal according to the first comparison result and the second comparison result
  • the first charging and discharging circuit and the second charging and discharging circuit are used for charging and discharging according to the clock signal
  • the control unit is used to control the on and off of the MOS transistor through a control signal, so as to adjust the total capacitance of the capacitor array circuit.
  • the logic unit includes an RS flip-flop.
  • the capacitor array circuit, the charging and discharging circuit and the RC oscillation circuit of the present application can make the total capacitance output by the capacitor array circuit change monotonically and improve the accuracy of the output frequency of the RC oscillation circuit.
  • FIG. 1 is a schematic block diagram of an RC oscillator circuit provided by an embodiment of the present application
  • FIG. 2 is a schematic block diagram of an RC oscillator circuit provided by another embodiment of the present application.
  • FIG. 3 is a circuit diagram of a charging and discharging circuit provided by an embodiment of the present application.
  • FIG. 4 is a circuit diagram of a capacitor array circuit provided by an embodiment of the present application.
  • FIG. 5 is a schematic diagram of a connection between a capacitor and a MOS transistor according to an embodiment of the application
  • FIG. 6 is a schematic diagram of a connection between a capacitor and a MOS transistor according to another embodiment of the present application.
  • FIG. 7 is a schematic diagram of a connection between a capacitor and a MOS transistor according to another embodiment of the present application.
  • FIG. 8 is a schematic diagram of a connection between a capacitor and a MOS transistor according to another embodiment of the present application.
  • FIG. 9 is a circuit diagram of an RC oscillator circuit according to an embodiment of the present application.
  • connection can be a fixed connection, a detachable connection, or an integral Connection, or electrical connection; either directly or indirectly through an intermediary.
  • a conventional RC oscillator circuit generally includes a reference voltage module 11 , a charging and discharging module 12 , a comparison module 13 and a logic module 14 .
  • the input end of the comparison module 13 is connected to the reference voltage module 11 and the charging and discharging module 12 respectively, the output end of the comparing module 13 is connected to the input end of the logic module 14 , and the output end of the logic module 14 is connected to the charging and discharging module 12 .
  • the reference voltage module 11 is used for generating a reference voltage.
  • the charging and discharging module 12 is used for transmitting the charging and discharging voltage to the comparison module 13 .
  • the comparison module 13 is used for comparing the reference voltage and the charging and discharging voltage, and outputting the comparison result to the logic module 14 .
  • the logic module 14 is used for outputting a clock signal according to the comparison result.
  • the logic module 14 is also used for feeding back the clock signal to the charging and discharging module 12, and the charging and discharging module 12 is used for charging and discharging according to the clock signal.
  • the logic module 14 feeds back the clock signal to the charging and discharging module 12, so that the charging and discharging module 12 switches from the charging state to the discharging state or from the discharging state to the charging state, so that the charging and discharging module 12 performs cyclic charging and discharging, so that the RC
  • the oscillator circuit continuously outputs the clock signal.
  • the charging and discharging module 12 usually includes a capacitor array circuit, and the RC oscillator circuit adjusts the charging and discharging frequency of the charging and discharging module 12 by adjusting the total capacitance of the capacitor array circuit, thereby adjusting the frequency of the clock signal output by the RC oscillator circuit.
  • the total capacitance of the capacitor array circuit is the sum of the capacitors connected to the charging and discharging module 12 and participating in the charging and discharging of the capacitor array circuit, and the total capacitance of the capacitor array circuit can be adjusted by a switch.
  • the adjustment of the total capacitance of the traditional capacitor array circuit often ignores the influence of parasitic resistance on the total capacitance of the capacitor array circuit connected to the charging and discharging module 12, resulting in non-monotonicity in the adjustment of the frequency of the output clock signal of the RC oscillator circuit.
  • an embodiment of the present application provides an RC oscillator circuit including a capacitor charging and discharging circuit 20 , a first comparator I1 , a second comparator I2 , a reference voltage unit 30 , a logic unit 40 and a control unit 50 .
  • the capacitor charging and discharging circuit 20 includes a first charging and discharging circuit 21 and a second charging and discharging circuit 22 .
  • the first input terminal of the first comparator I1 is connected to the capacitor output terminal of the first charging and discharging circuit 21 , the second input terminal of the first comparator I1 is connected to the reference voltage unit 30 ; the first input terminal of the second comparator I2 It is connected to the capacitor output terminal of the second charging and discharging circuit 22, and the second input terminal of the second comparator I2 is connected to the reference voltage unit 30; the output terminal of the first comparator I1 and the output terminal of the second comparator I2 are connected with the logic The input of the unit 40 is connected.
  • the output terminal of the logic unit 40 is connected to the input terminal of the charging and discharging circuit 20 . Specifically, the output terminal of the logic unit 40 is connected to the input terminal of the first charging and discharging circuit 21 and the input terminal of the second charging and discharging circuit 22 respectively.
  • the reference voltage unit 30 is used to generate a reference voltage.
  • the first charging and discharging circuit 21 is used for transmitting the first charging voltage or the first discharging voltage to the first comparator I1.
  • the clock signal includes a plurality of clock cycles, each clock cycle includes a first half cycle and a second half cycle, and the first charging voltage is the voltage output by the first charging and discharging circuit 21 in the first half cycle of each clock cycle,
  • the first discharge voltage is the voltage output by the first charge and discharge circuit 21 in the second half cycle of each clock cycle.
  • the first comparator I1 is used for comparing the first charging voltage and the reference voltage, or comparing the first discharging voltage and the reference voltage, and outputting the first comparison result to the logic unit 40 .
  • the second charging and discharging circuit 22 is used for transmitting the second charging voltage or the second discharging voltage to the second comparator I2.
  • the second discharge voltage is the voltage output by the second charging and discharging circuit 22 in the first half cycle of each clock cycle
  • the second charging voltage is output by the second charging and discharging circuit 22 in the second half cycle of each clock cycle Voltage.
  • the second comparator I2 is used for comparing the second charging voltage and the reference voltage, or comparing the second discharging voltage and the reference voltage, and outputting the second comparison result to the logic unit 40 .
  • the logic unit 40 is used for outputting a clock signal according to the first comparison result and the second comparison result.
  • the logic unit 40 is also used for feeding back the clock signal to the first charging and discharging circuit 21 and the second charging and discharging circuit 22 respectively, and the first charging and discharging circuit 21 and the second charging and discharging circuit 22 perform charging and discharging according to the clock signal.
  • the logic unit 40 feeds back the clock signal to the charging and discharging module 12, so that the first charging and discharging circuit 21 and the second charging and discharging circuit 22 are switched from the charging state to the discharging state or from the discharging state to the charging state, so that the first charging and discharging circuit 21 and the second charging and discharging circuit 22 perform cyclic charging and discharging, so that the RC oscillator circuit continues to output the clock signal.
  • the charging and discharging circuit 20 (such as the charging and discharging module 12 in FIG. 1 or the first charging and discharging circuit 21 and the second charging and discharging circuit 22 in FIG. 2 ) includes a capacitor array circuit C, a power source V, a first electronic switch Q1, a first resistor R and a second electronic switch Q2.
  • the clock signal includes a plurality of clock cycles, and each clock cycle includes a first half cycle and a second half cycle.
  • first half cycle of each clock cycle the input of the input terminal VIN is at a high level, the first electronic switch Q1 is turned off, the second electronic switch Q2 is turned on, and the charging and discharging circuit 20 discharges;
  • second half cycle the input of the input terminal VIN is at a low level, the first electronic switch Q1 is turned on, the second electronic switch Q2 is turned off, and the charging and discharging circuit 20 is charged.
  • the level input to the input terminal VIN changes according to the cycle of the clock cycle, so that the charging and discharging circuit 20 alternately performs charging and discharging.
  • the capacitor array circuit C (such as the capacitor array circuit C in FIG. 3 ) includes N capacitors and N MOS transistors.
  • the N MOS transistors are in one-to-one correspondence with the N capacitors, wherein the drain of each MOS transistor in the N MOS transistors is connected to one end of the corresponding capacitor through a different metal wire, and the source of each MOS transistor is grounded , the gate of each MOS transistor is used for receiving a control signal to control the on and off of each MOS transistor respectively.
  • the other ends of the N capacitors are connected to a common terminal, and the common terminal serves as the capacitor output terminal Cout of the capacitor array circuit C.
  • Each MOS tube in the N MOS tubes and the corresponding capacitor form a capacitor branch.
  • the first MOS tube and the first capacitor in the N MOS tubes form the first capacitor branch
  • the second MOS tube The tube and the second capacitor form the second capacitor branch
  • the Nth MOS tube and the Nth capacitor form the Nth capacitor branch
  • ..., and so on that is, the nth MOS tube and the nth capacitor form The nth capacitor branch.
  • Each MOS tube is turned on and off under the control of the control signal, so as to control whether the capacitor branch where the MOS tube is located is connected to the capacitor array circuit C.
  • the nth capacitor branch composed of the nth MOS tube and the nth capacitor is connected in parallel with other capacitor branches, that is, the nth capacitor The branch is connected to the capacitor array circuit C.
  • N is an integer greater than or equal to 2.
  • the capacitance of the first capacitor is C1
  • the capacitance of the second capacitor is C2
  • the capacitance of the third capacitor is C3,...
  • the capacitance of the n-1th capacitor is Cn-1
  • the capacitance of the nth capacitor is Cn-1
  • the capacitance of each capacitor is Cn.
  • the on-resistance of the first MOS tube is R on1
  • the on-resistance of the second MOS tube is R on2
  • the on-resistance of the third MOS tube is R on3
  • the n-1th MOS tube The on-resistance of the MOSFET is R onn-1
  • the on-resistance of the nth MOS transistor is R onn .
  • the resistance of the metal line between the first capacitor and the first MOS transistor is R net1
  • the resistance of the metal line between the second capacitor and the second MOS transistor is R net2
  • the third capacitor and the third The resistance of the metal line between the MOS tubes is R net3 , ...
  • the resistance of the metal line between the n-1th capacitor and the n-1th MOS tube is R netn-1
  • the nth capacitor and the th The resistance of the metal line between the n MOS transistors is R netn .
  • the traditional RC oscillator circuit usually ignores the resistance when the N MOS tubes are turned on and the resistance of the metal wire between the capacitor and the MOS tube, that is, the resistance when the N MOS tubes are turned on and the resistance between the capacitor and the MOS tube.
  • the resistance of the metal wire is treated as 0 ohms.
  • each MOS tube has a certain on-resistance when it is turned on, and the metal wire between the capacitor and the MOS tube also has a certain resistance.
  • the parasitic resistance of the RC oscillator circuit includes each The on-resistance of each MOS transistor and the resistance of the metal line between each capacitor and the corresponding MOS transistor.
  • the on-resistance of the MOS tube and the resistance of the metal wire between the capacitor and the MOS tube affect the monotonicity of the total capacitance adjustment of the capacitor array circuit C, thereby affecting the monotonicity of the frequency adjustment of the clock signal output by the RC oscillator circuit, resulting in the RC oscillator circuit.
  • the frequency error of the output clock signal is large.
  • the capacitance values of the N capacitors in the capacitor array circuit C are usually set in a certain proportion.
  • the connection between each of the N capacitors and the corresponding MOS transistor is ignored.
  • the influence of the resistance of the metal wire on the total capacitance of the capacitor array circuit C that is, if the values of R net1 , R net2 , R net3 , ..., R netn-1 , and R netn are all treated as 0, then R on1 ⁇ aR on2 , R on2 ⁇ aR on3 , R on3 ⁇ aR on4 ,...,R onn -1 ⁇ aR onn , that is, the capacitance Cn of the nth capacitor is a times the capacitance Cn-1 of the n-1th capacitor,
  • the on-resistance R onn-1 of the n-1 th MOS transistor is greater than or equal to a times the on-resistance R onn of the n-th
  • each MOS transistor in the N MOS transistors is ignored.
  • the influence of the on-resistance on the total capacitance of the capacitor array circuit C that is, if the values of R on1 , R on2 , R on3 , ..., R onn-1 , and R onn are all treated as 0, then R net1 ⁇ aR net2 , R net2 ⁇ aR net3 , R net3 ⁇ aR net4 , ..., R netn-1 ⁇ aR netn , that is, the capacitance Cn of the nth capacitor is a times the capacitance Cn-1 of the n-1th capacitor,
  • the resistance R netn-1 of the metal line between the n-1th capacitor and the n-1th MOS transistor is greater than or equal to a times the resistance R netn of the metal
  • the resistance of the metal line between each of the N capacitors and the corresponding MOS transistor and the on-resistance of each of the N MOS transistors are considered to affect the total capacitance of the capacitor array circuit C. Influence of capacitance, the values of R net1 , R net2 , R net3 , ..., R netn-1 , R netn and R on1 , R on2 , R on3 , ..., R onn- 1 , R onn are not 0, R net1 +R on1 ⁇ a *(R net2 +R on2 ), R net2 +R on2 ⁇ a*(R net3 +R on3 ), R net3 +R on3 ⁇ a*(R net4 +R on4 ), ..., R netn-1 +R onn- 1 ⁇ a*(R netn +R onn ), that is, the capacitance Cn of the nth capacitor is a times the capacitance Cn-1 of the n-1th capacitor, and the
  • the on-resistance of the MOS tube is inversely proportional to the ratio of the width to the length of the MOS tube. For example, if the ratio of the width to the length of the MOS tube is doubled, the on-resistance of the MOS tube is reduced by half.
  • the ratio of the width to the length of the first MOS tube is M1
  • the ratio of the width to the length of the second MOS tube is M2
  • the ratio of the width to the length of the third MOS tube is M3, ...
  • the n-1th The ratio of the width to the length of the first MOS tube is Mn-1
  • the ratio of the width to the length of the nth MOS tube is Mn.
  • the ratio of the width to the length of the MOS tube is the ratio of the width of the conductive channel of the MOS tube to the length of the conductive channel.
  • the ratio of the capacitance value of the first capacitor in the N capacitors to the capacitance value of the nth capacitor and the ratio of the width and length of the first MOS transistor in the N MOS transistors to the width and length of the nth MOS transistor When the ratio of the ratio is the same, the resistance R netn-1 of the metal line between the n-1th capacitor and the n-1th MOS transistor is greater than or equal to the metal line between the nth capacitor and the nth MOS transistor. A times the resistance R netn of , can make the total capacitance adjustment of the capacitor array circuit C monotonic.
  • trim ⁇ 1>, trim ⁇ 2>, trim ⁇ 3>, ..., trim ⁇ n-1>, trim ⁇ n> corresponding to the N MOS transistors are set in the control unit 50.
  • trim ⁇ 1> When the values corresponding to trim ⁇ 2>, trim ⁇ 3>, ..., trim ⁇ n-1>, trim ⁇ n> change monotonically, the total capacitance output by the capacitor array circuit C is monotonic, and the clock output by the RC oscillator circuit is monotonic. The frequency of the signal varies monotonically.
  • trim ⁇ 1>, trim ⁇ 2>, trim ⁇ 3>, ..., trim ⁇ n-1>, trim ⁇ n> increase, the total capacitance output by the capacitor array circuit C increases, and the output value of the RC oscillator circuit increases.
  • the frequency of the clock signal is decremented.
  • the control unit 50 also converts the binary signals trim ⁇ 1>, trim ⁇ 2>, trim ⁇ 3>, ..., trim ⁇ n-1>, trim ⁇ n> into pulse signals respectively, and transmits the pulse signals to a corresponding MOS
  • the MOS tube is turned on or off under the action of the pulse signal.
  • the sum of the on-resistance R onn-1 of the transistor is greater than or equal to twice the sum of the resistance R netn of the metal line between the capacitor of the nth capacitor branch and the MOS transistor and the on-resistance R onn of the MOS transistor.
  • trim ⁇ 1>, trim ⁇ 2>, trim ⁇ 3>, ..., trim ⁇ n-1> from the first MOS transistor to the nth MOS transistor among the N MOS transistors set by the control unit 50,
  • trim ⁇ n> changes monotonically
  • the frequency of the clock signal output by the RC oscillator circuit changes monotonically
  • the steps of the frequency change of the clock signal output by the RC oscillator circuit are equal.
  • the step of adjusting the total capacitance of the capacitor array circuit C can be an integer multiple of C1, and the minimum step of adjusting the total capacitance of the capacitor array circuit C is C1.
  • a is an integer greater than 1.
  • the monotonicity of the total capacitance adjustment of the capacitor array circuit C can be achieved without setting additional resistors. low cost.
  • the line is 1 and the resistance of the metal line is R net2
  • the metal line between the third capacitor and the third MOS tube is 1 and the resistance of the metal line is R net3 , ..., nth
  • the metal wire between the -1 capacitor and the n-1th MOS tube is 1 and the resistance of the metal wire is R netn-1
  • the metal wire between the nth capacitor and the nth MOS tube is 1 and the resistance of the metal line is R netn
  • Rnet1 : Rnet2 : Rnet3 :...: Rnetn-2 : Rnetn-1 : Rnetn 2n-1 : 2n-2 : 2n-3 :... : 2 2 : 2 1 : 2 0 .
  • a n-1 metal lines are connected in series between the first capacitor and the first MOS transistor, and the resistance value of each square resistance of the an -1 metal lines is the same, and the second capacitor and the second MOS transistor are connected in series.
  • a n-2 metal lines are connected in series between them, and the resistance value of each block of the an n-2 metal lines is the same, and an n-3 metal lines are connected in series between the third capacitor and the third MOS tube, and the a
  • the resistance value of each block of n-3 metal lines is the same, ..., a metal line is connected in series between the n-1th capacitor and the n-1th MOS tube, and the resistance of each block of the a metal line is resistive
  • the value is the same, and a metal line is connected in series between the nth capacitor and the nth MOS tube, that is to say, the number of metal lines connected in series between the n-1th capacitor and the n-1th MOS tube is the th The number of metal lines connected in series between the n
  • the resistance value of each block of the metal line connected in series with the n-1th MOS transistor is the same as the resistance value of each block of the metal line connected in series between the nth capacitor and the nth MOS transistor, that is, each capacitor branch
  • the resistance value per square of the metal wire of the circuit is equal to the resistance value per square of the metal wire of the other capacitor branches.
  • the series-connected metal lines of each capacitor branch can be placed on the same layer of the circuit board. where a is an integer greater than 1.
  • a metal line is connected in parallel between the second capacitor and the second MOS transistor, and the resistance per square of the a metal line is resistive
  • the value is the same
  • a 2 metal lines are connected in parallel between the third capacitor and the third MOS tube, and the resistance value of each square resistance of the a 2 metal lines is the same
  • the n-1th capacitor and the n-th A n-2 metal lines are connected in parallel between a MOS tube, and the resistance value of each block of the an -2 metal lines is the same
  • an n - 1 metal line is connected in parallel between the nth capacitor and the nth MOS tube.
  • the resistance value of each block of the an -1 metal lines is the same, that is, the number of metal lines connected in parallel between the nth capacitor and the nth MOS transistor is the n-1th capacitor and the n-1th A times the number of metal lines connected in parallel between the MOS transistors, each of the capacitors is the same as the resistance value per square of the metal line connected between the corresponding MOS transistors, and the n-1th capacitor is the same as the n-th
  • the resistance value of each block of the metal wire connected in series between one MOS tube is the same as the resistance value of each square of the metal wire connected in series between the nth capacitor and the nth MOS tube, that is, the metal wire of each capacitor branch
  • the resistance value of the resistance per square is equal to the resistance value of the resistance per square of the metal lines of the other capacitor branches.
  • the parallel metal lines of each capacitive branch can be placed on different layers of the circuit board. where a is an integer greater than 1.
  • One or more layers of metal wires in parallel or in series can be set between the capacitor of each capacitor branch and the MOS tube, so as to realize the monotonic change of the metal wire resistance between the capacitors of the multiple capacitor branches of the capacitor array circuit and the MOS tube.
  • the first terminal of the first electronic switch Q1 is connected to the power supply V
  • the second terminal of the first electronic switch Q1 is connected to the first terminal and the capacitor output terminal of the second electronic switch Q2 through the resistor R, respectively.
  • the second terminals of the two electronic switches Q2 are grounded, the control terminal of the first electronic switch Q1 and the control terminal of the second electronic switch Q2 are respectively used to receive the clock signal, and the first electronic switch Q1 and the second electronic switch Q2 conduct conduction based on the clock signal.
  • the output terminals of the logic unit 40 are respectively connected to the control terminal of the first electronic switch Q1 and the control terminal of the second electronic switch Q2.
  • the control terminal of the first electronic switch Q1, the control terminal of the second electronic switch Q2 and the output terminal of the logic unit 40 are respectively connected to the VIN terminal, and the VOUT terminal is the capacitor output terminal.
  • the charging and discharging frequency of the capacitor charging and discharging circuit 20 can be monotonically varied.
  • the first electronic switch Q1 is a PMOS transistor, and the first terminal, the second terminal and the third terminal of the first electronic switch Q1 correspond to the drain, source and gate of the PMOS transistor, respectively.
  • the second electronic switch Q2 is an NMOS transistor, and the first terminal, the second terminal and the third terminal of the second electronic switch Q2 correspond to the drain, source and gate of the NMOS transistor, respectively.
  • the control unit 50 is respectively connected to the gate of each MOS transistor.
  • the control unit 50 is used to control the turn-on and turn-off of each MOS transistor through a control signal, so as to adjust the total capacitance of the capacitor array circuit C.
  • the control unit 50 is used to control the on and off of the MOS transistor through a control signal, so as to adjust the total capacitance of the capacitor array circuit C.
  • the control signal is a pulse signal.
  • the control unit 50 sets the binary signals from the 1st MOS transistor to the nth MOS transistor as trim ⁇ 1>, trim ⁇ 2>, trim ⁇ 3>,..., trim ⁇ n-1>, trim ⁇ n >, and transmit the pulse signal corresponding to each binary signal to the MOS tube, when the binary signal trim ⁇ 1>, trim ⁇ 2>, trim ⁇ 3>, ..., trim ⁇ n-1>, trim ⁇ n> corresponds to the value
  • the charging and discharging frequency of the charging and discharging circuit 20 changes monotonically, so that the frequency of the clock signal output by the RC oscillator circuit changes monotonically, thereby improving the accuracy of the output frequency of the RC oscillator.
  • the total capacitance of the capacitor array circuit C is adjusted by the control unit 50 to change monotonically, so that the charging and discharging frequency of the capacitor charging and discharging circuit 20 changes monotonically, so that the frequency of the clock signal output by the RC oscillator circuit changes monotonically, which improves the The accuracy of the RC oscillator output frequency.
  • the logic unit 40 may include RS flip-flops and inverters.
  • the above-mentioned metal wire can be copper wire, which has good electrical conductivity and low cost.
  • the first charging and discharging circuit 21 includes a capacitor array circuit C1, a power supply V1, a first electronic switch M1, a first resistor R1 and a second electronic switch M2, and the second charging and discharging circuit 22 includes a capacitor array circuit C2, a power supply V1, a first electronic switch The switch M3, the first resistor R2 and the second electronic switch M4.
  • the first electronic switch is a PMOS tube, and the second electronic switch is an NMOS tube.
  • the first input terminal and the second input terminal of the first comparator I1 correspond to the non-inverting input terminal and the inverting input terminal of the first comparator, respectively.
  • the first input terminal and the second input terminal of the second comparator I2 correspond to the non-inverting input terminal and the inverting input terminal of the second comparator, respectively.
  • the logic unit is an RS flip-flop I3, and the RS flip-flop I3 includes an input end S, an input end R, an output end Q and an output end Qn.
  • the output terminal Q and the output terminal Qn of the RS flip-flop I3 output the clock signals CLK and CLKn, respectively.
  • the first electronic switch M1 In the first clock half cycle of the RC oscillator circuit, the previous states of Q and Qn are high level and low level respectively, the first electronic switch M1 is turned on, the second electronic switch M2 is turned off, and the first charging and discharging circuit 21 For charging, the first comparator I1 outputs a high level to the input end R of the RS flip-flop I3; at the same time, the first electronic switch M3 is turned off, the second electronic switch M4 is turned on, the second charging and discharging circuit 22 is discharged, and the second electronic switch M3 is turned off.
  • the comparator I2 outputs a low level to the input S of the RS flip-flop I3, the output Q of the RS flip-flop I3 becomes a low level, the output Qn becomes a high level, and the RC oscillator circuit enters the second clock half cycle .
  • the previous states of Q and Qn are low level and high level respectively, the first electronic switch M1 is turned off, the second electronic switch M2 is turned on, the first charging and discharging circuit 21 is discharging, and the first electronic switch M1 is turned off.
  • a comparator I1 outputs a low level to the input terminal R of the RS flip-flop I3; at the same time, the first electronic switch M3 is turned on, the second electronic switch M4 is turned off, the second charging and discharging circuit 22 is charged, and the second comparator I2 outputs The high level goes to the input end S of the RS flip-flop I3, the output end Q of the RS flip-flop I3 becomes the high level, and the output end Qn becomes the low level.
  • the RC oscillator circuit completes the charge and discharge of a whole clock cycle.

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Abstract

本申请公开了一种电容阵列电路，包括N个电容及与N个电容一一对应的N个MOS管，每个MOS管的漏极通过不同的金属线与对应的电容的一端连接，每个MOS管的源极接地，每个MOS管的栅极用于接收控制信号以分别控制每个MOS管的导通和截止；N个电容的另一端连接至一公共端；N个电容中的第n-1个电容的容值Cn-1为第n个电容的容值Cn的a倍；N个MOS管中的第n-1个MOS管的导通电阻和第n-1个电容与第n-1个MOS管之间的金属线的电阻之和为第n个MOS管的导通电阻和第n个电容与第n个MOS管之间的金属线的电阻之和的a倍。

Description

电容阵列电路、充放电电路及RC振荡电路 技术领域
本申请涉及集成电路技术领域，特别涉及一种电容阵列电路、充放电电路及RC振荡电路。
背景技术
电子设备通常采用振荡器产生所需的时钟信号。振荡器具有多种类型，其中RC振荡器因具有成本低、功耗低、频率可调节等优点，得到了广泛的应用。然而，RC振荡器对寄生参数较敏感，寄生参数与RC振荡器的版图设计、工艺以及温度相关，因此，RC振荡器的输出频率误差较大。
RC振荡器通常采用电容阵列电路调节输出频率，但传统的电容阵列电路往往忽略寄生电阻对电容阵列电路的总电容的影响，从而导致电容阵列电路对RC振荡器输出频率的调节呈现非单调性，导致RC振荡器的输出频率误差较大。
申请内容
为了克服上述现有技术存在的问题，本申请的主要目的在于提供一种能够实现对RC振荡器输出频率的单调性调节从而提高RC振荡器输出频率的精度的电容阵列电路、充放电电路及RC振荡电路。
为了实现上述目的，本申请具体采用以下技术方案：
本申请提供了一种电容阵列电路，包括：
N个电容；
N个MOS管，与所述N个电容一一对应，其中，所述N个MOS管中的每个MOS管的漏极通过不同的金属线与对应的电容的一端连接，所述每个MOS管的源极接地，所述每个MOS管的栅极用于接收控制信号以分别控制所述每个MOS管的导通和截止；
所述N个电容的另一端连接至一公共端，所述公共端作为电容输出端；
所述N个电容中的第n-1个电容的容值为Cn-1，第n个电容的容值为Cn，Cn＝aCn-1；
所述N个MOS管中的第n-1个MOS管的导通电阻为R onn-1，第n个 MOS管的导通电阻为R onn；
第n-1个电容与第n-1个MOS管之间的金属线的电阻为R netn-1，第n个电容与第n个MOS管之间的金属线的电阻为R netn；
其中，R netn-1与R onn-1之和大于或等于R netn与R onn之和的a倍，其中，a大于1，N为大于或等于2的整数，n＝[2，N]。
优选地，第n-1个MOS管的宽度与长度的比值为Mn-1，第n个MOS管的宽度与长度的比值为Mn，第n个MOS管的宽度与长度的比值Mn为第n-1个MOS管的宽度与长度的比值Mn-1的b倍，b＝a，第n-1个电容与第n-1个MOS管之间的金属线的电阻R netn-1大于或等于第n个电容与第n个MOS管之间的金属线的电阻R netn的a倍。
优选地，a＝b＝2，第n-1个电容与第n-1个MOS管之间的金属线的电阻R netn-1大于或等于第n个电容与第n个MOS管之间的金属线的电阻R netn的2倍。
优选地，第n个电容与第n个MOS管之间的金属线为a n-1条，每条金属线的电阻值相等，且每个电容与对应一个MOS管之间的金属线相互并联；其中，a为大于1的整数。
优选地，第n-1个电容与第n-1个MOS管之间的金属线为1条且该条金属线的电阻为R netn-1，第n个电容与第n个MOS管之间的金属线为1条且该条金属线的电阻为R netn，第n-1个电容与第n-1个MOS管之间的金属线的电阻R netn-1为第n个电容与第n个MOS管之间的金属线的电阻R netn的a倍。
优选地，每个所述电容与对应一个MOS管之间连接的金属线的每方块电阻阻值相同，第n-1个电容与第n-1个MOS管之间的金属线的方块电阻数为第n个电容与第n个MOS管之间的金属线的方块电阻数的a倍。
优选地，第n-1个电容与第n-1个MOS管之间串联的金属线的条数为第n个电容与第n个MOS管之间串联的金属线的条数的a倍，每个所述电容与对应一个MOS管之间连接的金属线的每方块电阻阻值相同，第n-1个电容与第n-1个MOS管之间串联的金属线的每方块电阻阻值和第n个电容与第n个MOS管之间串联的金属线的每方块电阻阻值相同。
优选地，第n个电容与第n个MOS管之间并联的金属线的条数为第n-1个电容与第n-1个MOS管之间并联的金属线的条数的a倍，每个所述电容与对应一个MOS管之间连接的金属线的每方块电阻阻值相同，第n-1个电容与第n-1个MOS管之间串联的金属线的每方块电阻阻值和第n个电容与第n个MOS管之间串联的金属线的每方块电阻阻值相同。
优选地，所述金属线为铜线。
优选地，所述控制信号为二进制信号。
本申请还提供一种电容充放电电路，包括上述的电容阵列电路、电源、第一电子开关、第一电阻及第二电子开关；所述第一电子开关的第一端与所述电源连接，所述第一电子开关的第二端通过所述电阻分别与所述第二电子开关的第一端及所述电容输出端连接，所述第二电子开关的第二端接地，所述第一电子开关的控制端与所述第二电子开关的控制端分别用于接收时钟信号，所述第一电子开关及所述第二电子开关基于所述时钟信号进行导通和截止。
优选地，所述第一电子开关为PMOS管，所述第二电子开关为NMOS管。
本申请提供一种RC振荡电路，包括第一充放电电路、第二充放电电路、第一比较器、第二比较器、参考电压单元、逻辑单元及控制单元，第一充放电电路及第二充放电电路分别为上述的电容充放电电路；所述第一比较器的第一输入端与所述第一充放电电路的电容输出端连接，所述第一比较器的第二输入端与所述参考电压单元连接；所述第二比较器的第一输入端与所述第二充放电电路的电容输出端连接，所述第二比较器的第二输入端与所述参考电压单元连接；所述第一比较器的输出端及所述第二比较器的输出端均与所述逻辑单元的输入端连接，所述逻辑单元的输出端分别与所述第一电子开关的控制端及所述第二电子开关的控制端连接；所述控制单元分别与每个MOS管的栅极连接；
所述参考电压单元用于产生基准电压；
所述第一充放电电路用于传输第一充电电压或第一放电电压至所述第一比较器；
所述第一比较器用于对所述第一充电电压及所述基准电压进行比较，或对所述第一放电电压及所述基准电压进行比较，并将第一比较结果输出至所述逻辑单元；
所述第二充放电电路用于传输第二充电电压或第二放电电压至所述第二比较器；
所述第二比较器用于对所述第二充电电压及所述基准电压进行比较，或对所述第二放电电压及所述基准电压进行比较，并将第二比较结果输出至所述逻辑单元；
所述逻辑单元用于根据所述第一比较结果及所述第二比较结果输出时钟信号；
所述第一充放电电路及所述第二充放电电路用于根据所述时钟信号进行充电和放电；
所述控制单元用于通过控制信号控制所述MOS管的导通和截止，以调节所述电容阵列电路的总电容。
优选地，所述逻辑单元包括RS触发器。
相比于现有技术，本申请的电容阵列电路、充放电电路及RC振荡电路，能够使得电容阵列电路输出的总电容呈单调性变化，提高RC振荡电路输出频率的精度。
附图说明
图1为本申请一实施例提供的RC振荡电路的原理框图；
图2为本申请另一实施例提供的RC振荡电路的原理框图；
图3为本申请一实施例提供的充放电电路的电路图；
图4为本申请一实施例提供的电容阵列电路的电路图；
图5为本申请一实施例提供的电容与MOS管的连接示意图；
图6为本申请另一实施例提供的电容与MOS管的连接示意图；
图7为本申请又一实施例提供的电容与MOS管的连接示意图；
图8为本申请再一实施例提供的电容与MOS管的连接示意图；
图9为本申请一实施例提供的RC振荡电路的电路图。
具体实施方式
为了使本申请的目的、技术方案及优点更加清楚明白，以下结合附图及实施例，对本申请进行进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本申请，并不用于限定本申请。
在本申请的描述中，除非另有明确的规定和限定，术语“第一”、“第二”仅用于描述的目的，而不能理解为指示或暗示相对重要性；除非另有规定或说明，术语“多个”是指两个或两个以上；术语“连接”、“固定”等均应做广义理解，例如，“连接”可以是固定连接，也可以是可拆卸连接，或一体地连接，或电连接；可以是直接相连，也可以通过中间媒介间接相连。对于本领域的普通技术人员而言，可以根据具体情况理解上述术语在本发明中的具体含义。
请参考图1，传统的RC振荡电路通常包括参考电压模块11、充放电模块12、比较模块13及逻辑模块14。比较模块13的输入端分别与参考电压模块11及充放电模块12连接，比较模块13的输出端与逻辑模块14的输入端连接，逻辑模块14的输出端与充放电模块12连接。参考电压模块11用于产生参考电压。充放电模块12用于传输充放电电压至比较模块13。比较模块13用于对所述参考电压及所述充放电电压进行比较，并输出比较结果至逻辑模块14。逻辑模块14用于根据比较结果输出时钟信号。逻辑模块14还用于将时钟信号反馈至充放电模块12，充放电模块12用于根据所述时钟信号进行充电和放电。逻辑模块14将时钟信号反馈至充放电模块12，从而使得充放电模块12从充电状态切换至放电状态或者从放电状态切换至充电状态，使得充放电模块12进行循环的充电和放电，从而使得RC振荡电路持续输出时钟信号。
充放电模块12通常包括电容阵列电路，RC振荡电路通过调节电容阵列电路的总电容，进而调节充放电模块12的充放电频率，从而调节RC振荡电路输出的时钟信号的频率。电容阵列电路的总电容为电容阵列电路接入充放电模块12并参与充放电的电容的总和，电容阵列电路的总电容可通过开关进行调节。传统电容阵列电路的总电容的调节往往忽略寄生电阻对电容阵列电路接入充放电模块12的总电容的影响，从而导致RC振荡电路 输出时钟信号频率的调节呈现非单调性。
请参考图2，本申请实施例提供一种RC振荡电路，包括电容充放电电路20、第一比较器I1、第二比较器I2、参考电压单元30、逻辑单元40及控制单元50。电容充放电电路20包括第一充放电电路21和第二充放电电路22。第一比较器I1的第一输入端与第一充放电电路21的电容输出端连接，第一比较器I1的第二输入端与参考电压单元30连接；第二比较器I2的第一输入端与第二充放电电路22的电容输出端连接，第二比较器I2的第二输入端与参考电压单元30连接；第一比较器I1的输出端及第二比较器I2的输出端均与逻辑单元40的输入端连接。逻辑单元40的输出端连接到充放电电路20的输入端，具体的，逻辑单元40的输出端分别与第一充放电电路21的输入端及第二充放电电路22的输入端连接。
参考电压单元30用于产生基准电压。第一充放电电路21用于传输第一充电电压或第一放电电压至第一比较器I1。其中，时钟信号包括多个时钟周期，每个时钟周期包括第一半周期及第二半周期，第一充电电压是第一充放电电路21在每个时钟周期的第一半周期输出的电压，第一放电电压是第一充放电电路21在每个时钟周期的第二半周期输出的电压。第一比较器I1用于对第一充电电压及基准电压进行比较，或对第一放电电压及基准电压进行比较，并输出第一比较结果至逻辑单元40。第二充放电电路22用于传输第二充电电压或第二放电电压至第二比较器I2。其中，第二放电电压是第二充放电电路22在每个时钟周期的第一半周期输出的电压，第二充电电压是第二充放电电路22在每个时钟周期的第二半周期输出的电压。第二比较器I2用于对第二充电电压及基准电压进行比较，或对第二放电电压及基准电压进行比较，并输出第二比较结果至逻辑单元40。逻辑单元40用于根据第一比较结果及第二比较结果输出时钟信号。逻辑单元40还用于将时钟信号分别反馈至第一充放电电路21及第二充放电电路22，第一充放电电路21及第二充放电电路22根据所述时钟信号进行充电和放电。逻辑单元40将时钟信号反馈至充放电模块12，从而使得第一充放电电路21及第二充放电电路22从充电状态切换至放电状态或者从放电状态切换至充电状态，使得第一充放电电路21及第二充放电电路22进行循环的充电和放电， 从而使得RC振荡电路持续输出时钟信号。
请参考图3，作为一种示例，充放电电路20(比如图1中的充放电模块12或图2中的第一充放电电路21、第二充放电电路22)包括电容阵列电路C、电源V、第一电子开关Q1、第一电阻R及第二电子开关Q2。
时钟信号包括多个时钟周期，每个时钟周期包括第一半周期及第二半周期。在每个时钟周期的第一半周期，输入端VIN的输入为高电平，第一电子开关Q1截止，第二电子开关Q2导通，充放电电路20进行放电；在每个时钟周期的第二半周期，输入端VIN的输入为低电平，第一电子开关Q1导通，第二电子开关Q2截止，充放电电路20进行充电。输入端VIN输入的电平根据时钟周期周期变换，从而充放电电路20交替进行充放电。
请一并参考图4，作为示例，电容阵列电路C(比如图3中的电容阵列电路C)包括N个电容及N个MOS管。N个MOS管与N个电容一一对应，其中，N个MOS管中的每个MOS管的漏极通过不同的金属线与对应的电容的一端连接，所述每个MOS管的源极接地，所述每个MOS管的栅极用于接收控制信号以分别控制所述每个MOS管的导通和截止。N个电容的另一端连接至一公共端，该公共端作为电容阵列电路C的电容输出端Cout。N个MOS管中的每个MOS管与对应的电容组成一个电容支路，比如，N个MOS管中的第1个MOS管与第1个电容组成第1个电容支路，第2个MOS管与第2个电容组成第2个电容支路，第N个MOS管与第N个电容组成第N个电容支路，…，以此类推，即第n个MOS管与第n个电容组成第n个电容支路。每个MOS管受控制信号的控制进行导通和截止，从而控制该MOS管所在的电容支路是否接入电容阵列电路C。具体的，当第n个MOS管在控制信号的控制下导通时，第n个MOS管与第n个电容组成的第n个电容支路与其他电容支路并联，也即第n个电容支路接入电容阵列电路C。其中，N为大于或等于2的整数。
第1个电容的容值为C1，第2个电容的容值为C2，第3个电容的容值为C3，...，第n-1个电容的容值为Cn-1，第n个电容的容值为Cn。
第1个MOS管的导通电阻为R on1，第2个MOS管的导通电阻为R on2，第3个MOS管的导通电阻为R on3，...，第n-1个MOS管的导通电阻为R onn-1， 第n个MOS管的导通电阻为R onn。
第1个电容与第1个MOS管之间的金属线的电阻为R net1，第2个电容与第2个MOS管之间的金属线的电阻为R net2，第3个电容与第3个MOS管之间的金属线的电阻为R net3，...，第n-1个电容与第n-1个MOS管之间的金属线的电阻为R netn-1，第n个电容与第n个MOS管之间的金属线的电阻为R netn。
传统的RC振荡电路通常忽略N个MOS管导通时的电阻以及忽略电容与MOS管之间的金属线的电阻，也就是把N个MOS管导通时的电阻及电容与MOS管之间的金属线的电阻当作0欧姆处理，然而，每个MOS管导通时均具有一定的导通电阻，电容与MOS管之间的金属线也存在一定的电阻，RC振荡电路的寄生电阻包括每个MOS管的导通电阻以及每个电容与对应的MOS管之间的金属线的电阻。MOS管的导通电阻以及电容与MOS管之间的金属线的电阻影响电容阵列电路C的总电容调节的单调性，从而影响RC振荡电路输出的时钟信号频率调节的单调性，造成RC振荡电路输出的时钟信号频率误差较大。
在考虑了寄生电阻对电容阵列电路C总电容的影响后，当N个电容支路的MOS管都导通时，N个电容支路的等效电容C1’，C2’，C3’，…，Cn’分别为：
Figure PCTCN2020113056-appb-000001
Figure PCTCN2020113056-appb-000002
Figure PCTCN2020113056-appb-000003
依此类推，
Figure PCTCN2020113056-appb-000004
其中，f为时钟信号频率的一半。电容阵列电路C中的N个电容的容值通常按一定的比例进行设置，当C2＝aC1，C3＝aC2，C4＝aC3，…， Cn-1＝aCn-2，Cn＝aCn-1时，即C1：C2：C3：C4：…：Cn-1：Cn＝a 0：a 1：a 2：a 3：a 4：…：a n-2：a n-1，C2′≥aC1′，C3′≥aC2′，C4′≥aC3′，…，C(n-1)′≥aC(n-2)′，Cn′≥aC(n-1)′，也就是考虑了寄生电阻对电容阵列电路C总电容的影响后，N个电容支路的等效电容C1’，C2’，C3’，…，Cn’符合C2′≥aC1′，C3′≥aC2′，C4′≥aC3′，…，C(n-1)′≥aC(n-2)′，Cn′≥aC(n-1)′时，电容阵列电路C输出的总电容呈单调性变化。其中，a大于1。
当C2′≥aC1′，C3′≥aC2′，C4′≥aC3′，…，C(n-1)′≥aC(n-2)′，Cn′≥aC(n-1)′时，则R net1+R on1≥a*(R net2+R on2)，R net2+R on2≥a*(R net3+R on3)，R net3+R on3≥a*(R net4+R on4)，…，R netn-1+R onn-1≥a*(R netn+R onn)。
在其中一个实施例中，若考虑N个MOS管中的每个MOS管的导通电阻对电容阵列电路C总电容的影响，忽略N个电容中的每个电容与对应的MOS管之间的金属线的电阻对电容阵列电路C总电容的影响，即把R net1、R net2、R net3、...、R netn-1、R netn的值均当作0进行处理，则R on1≥aR on2，R on2≥aR on3，R on3≥aR on4，…，R onn-1≥aR onn，即第n个电容的容值Cn为第n-1个电容的容值Cn-1的a倍，第n-1个MOS管的导通电阻R onn-1大于或等于第n个MOS管的导通电阻R onn的a倍，能够改善电容阵列电路C的总电容调节的单调性。其中，n＝[2，N]。
在其中一个实施例中，若考虑N个电容中的每个电容与对应的MOS管之间的金属线的电阻对电容阵列电路C总电容的影响，忽略N个MOS管中的每个MOS管的导通电阻对电容阵列电路C总电容的影响，即把R on1、R on2、R on3、...、R onn-1、R onn的值均当作0进行处理，则R net1≥aR net2，R net2≥aR net3，R net3≥aR net4，…，R netn-1≥aR netn，即第n个电容的容值Cn为第n-1个电容的容值Cn-1的a倍，第n-1个电容与第n-1个MOS管之间的金属线的电阻R netn-1大于或等于第n个电容与第n个MOS管之间的金属线的电阻R netn的a倍，能够改善电容阵列电路C的总电容调节的单调性。其中，n＝[2，N]。
在其中一个实施例中，同时考虑N个电容中的每个电容与对应的MOS管之间的金属线的电阻和N个MOS管中的每个MOS管的导通电阻对电容阵列电路C总电容的影响，R net1、R net2、R net3、...、R netn-1、R netn和R on1、R on2、R on3、...、R onn-1、R onn的值均不为0，R net1+R on1≥a*(R net2+R on2)，R net2+R on2≥a*(R net3+R on3)，R net3+R on3≥a*(R net4+R on4)，…，R netn-1+R onn-1≥a*(R netn+R onn)，即第n个电容的容值Cn为第n-1个电容的容值Cn-1的a倍，第n-1个电容支路的电容与MOS管之间的金属线的电阻R netn-1与MOS管的导通电阻R onn-1之和大于或等于第n个电容支路的电容与MOS管之间的金属线的电阻R netn与MOS管的导通电阻R onn之和的a倍，从而能够使得电容阵列电路C的总电容调节呈单调性变化。其中，n＝[2，N]。
MOS管的导通电阻与MOS管的宽度与长度的比值成反比，如，若MOS管的宽度与长度的比值增大一倍，则MOS管的导通电阻减小一半。第1个MOS管的宽度与长度的比值为M1，第2个MOS管的宽度与长度的比值为M2，第3个MOS管的宽度与长度的比值为M3，...，第n-1个MOS管的宽度与长度的比值为Mn-1，第n个MOS管的宽度与长度的比值为Mn。MOS管的宽度与长度的比值即MOS管的导电沟道的宽度与导电沟道的长度的比值。
当M1：M2：M3：...：Mn-1：Mn＝b 0：b 1：b 2：...：b n-2：b n-1，即M2＝bM1，M3＝bM2，M4＝bM3，…，Mn-1＝bMn-2，Mn＝bMn-1时，R on1：R on2：R on3：...：R onn-1：R onn＝b n-1：b n-2：...：b 2：b 1：b 0，即当第n个MOS管的宽度与长度的比值Mn为第n-1个MOS管的宽度与长度的比值Mn-1的b倍时，第n个MOS管的导通电阻R onn为第n-1个MOS管的导通电阻R onn-1的1/b倍。
进一步的，当b＝a时，由R net1+R on1≥a*(R net2+R on2)，R net2+R on2≥a*(R net3+R on3)，R net3+R on3≥a*(R net4+R on4)，…，R netn-1+R onn-1≥a*(R netn+R onn)，得到：
R net1≥a*R net2，R net2≥a*R net3，R net3≥a*R net4，...，R netn-1≥a*R netn，即R net1≥a*R net2≥a 2*R net3≥……≥a n-1*R netn，也就是说， 第n-1个电容与第n-1个MOS管之间的金属线的电阻R netn-1大于或等于第n个电容与第n个MOS管之间的金属线的电阻R netn的a倍。
N个电容中的第1个电容的容值至第n个电容的容值的比例与N个MOS管中的第1个MOS管的宽度与长度的比值至第n个MOS管的宽度与长度的比值的比例相同时，第n-1个电容与第n-1个MOS管之间的金属线的电阻R netn-1大于或等于第n个电容与第n个MOS管之间的金属线的电阻R netn的a倍，可以使得电容阵列电路C的总电容调节呈单调性。
控制单元50中设置分别与N个MOS管对应的二进制信号trim<1>，trim<2>，trim<3>，…，trim<n-1>，trim<n>，当trim<1>，trim<2>，trim<3>，…，trim<n-1>，trim<n>对应的数值呈单调性变化时，电容阵列电路C输出的总电容呈单调性，RC振荡电路输出的时钟信号的频率呈单调性变化。如trim<1>，trim<2>，trim<3>，…，trim<n-1>，trim<n>对应的数值递增时，电容阵列电路C输出的总电容递增，RC振荡电路输出的时钟信号的频率递减。控制单元50还将二进制信号trim<1>，trim<2>，trim<3>，…，trim<n-1>，trim<n>分别转换成脉冲信号，并将脉冲信号传输至对应一个MOS管，MOS管在脉冲信号作用下导通或截止。
当a＝b＝2时，C2＝2C1，C3＝2C2，…，Cn-1＝2Cn-2，Cn＝2Cn-1，即C1：C2：C3：C4：…：Cn-1：Cn＝2 0：2 1：2 2：2 3：2 4：…：2 n-2：2 n-1，C2′≥2C1′，C3′≥2C2′，C4′≥2C3′，…，C(n-1)′≥2C(n-2)′，Cn′≥2C(n-1)′，则R net1+R on1≥2*(R net2+R on2)，R net2+R on2≥2*(R net3+R on3)，R net3+R on3≥2*(R net4+R on4)，…，
R netn-1+R onn-1≥2*(R netn+R onn)，也就是说，第n-1个电容支路的电容与MOS管之间的金属线的电阻R netn-1与MOS管的导通电阻R onn-1之和大于或等于第n个电容支路的电容与MOS管之间的金属线的电阻R netn与MOS管的导通电阻R onn之和的2倍。
M1：M2：M3：...：Mn-1：Mn＝2 0：2 1：2 2：...：2 n-2：2 n-1，R on1：R on2：R on3：...：R onn-1：R onn＝2 n-1：2 n-2：...：2 2：2 1：2 0，即当第n个MOS管的宽度与长度的比值Mn为第n-1个MOS管的宽度与长度的比值Mn-1的2倍 时，第n个MOS管的导通电阻R onn为第n-1个MOS管的导通电阻R onn-1的1/2倍，则：
R net1≥2*R net2，R net2≥2*R net3，R net3≥2*R net4，...，R netn-1≥2*R netn，即R net1≥2*R net2≥2 2*R net3≥……≥2 n-1*R netn，也就是说，第n-1个电容与第n-1个MOS管之间的金属线的电阻R netn-1大于或等于第n个电容与第n个MOS管之间的金属线的电阻R netn的2倍。
控制单元50设置的N个MOS管中的第1个MOS管至第n个MOS管的二进制控制信号trim<1>，trim<2>，trim<3>，…，trim<n-1>，trim<n>对应的数值呈单调性变化时，RC振荡电路输出的时钟信号的频率呈单调性变化，且RC振荡电路输出的时钟信号频率变化的步进相等。
当a＝b＝2时，电容阵列电路C总电容调节的步进可以是C1的整数倍，电容阵列电路C总电容调节的最小步进为C1。
在其中一个实施例中，第1个电容与第1个MOS管之间的金属线为1条，第2个电容与第2个MOS管之间的金属线为a条，第3个电容与第3个MOS管之间的金属线为a 2条，...，第n-1个电容与第n-1个MOS管之间的金属线为a n-2条，第n个电容与第n个MOS管之间的金属线为a n-1条，每条金属线的电阻值相等，且每个电容与对应一个MOS管之间的金属线相互并联。其中，a为大于1的整数。
请参考图5，当a＝2时，第1个电容与第1个MOS管之间的金属线为1条，第2个电容与第2个MOS管之间的金属线为2条，第3个电容与第3个MOS管之间的金属线为4条，...，第n-1个电容与第n-1个MOS管之间的金属线为2 n-2条，第n个电容与第n个MOS管之间的金属线为2 n-1条。
通过在第n个电容与第n个MOS管之间设置a n-1条相互并联且电阻值相等金属线，从而可以无需设置额外的电阻就可以实现电容阵列电路C总电容调节的单调性，成本低。
在其中一个实施例中，第1个电容与第1个MOS管之间的金属线为1条且该条金属线的电阻为R net1，第2个电容与第2个MOS管之间的金属线为1条且该条金属线的电阻为R net2，第3个电容与第3个MOS管之间的金属线为1条且该条金属线的电阻为R net3，...，第n-1个电容与第n-1个MOS 管之间的金属线为1条且该条金属线的电阻为R netn-1，第n个电容与第n个MOS管之间的金属线为1条且该条金属线的电阻为R netn，R net1：R net2：R net3：...：R netn-2：R netn-1：R netn＝a n-1：a n-2：a n-3：...：a 2：a 1：a 0。当a＝2时，R net1：R net2：R net3：...：R netn-2：R netn-1：R netn＝2 n-1：2 n-2：2 n-3：...：2 2：2 1：2 0。
该实施例通过在电容与对应一个MOS管之间都只设置一条金属线，从而进一步减小金属线的占用面积，且使得布线操作更简单。
在集成电路制造中，一般以R＝ΡL/W定义金属线的电阻，其中，Ρ为每方块电阻阻值，L为金属线的长度，W为金属线的宽度，L/W为方块电阻数。
请参考图6，当R net1＝a*R net2＝a 2*R net3＝……＝a n-1*R netn时，若每个电容与对应一个MOS管之间采用每方块电阻阻值相同的金属线连接，则第1个电容与第1个MOS管之间的金属线的方块电阻数为a n-1，第2个电容与第2个MOS管之间的金属线的方块电阻数为a n-2，第3个电容与第3个MOS管之间的金属线的方块电阻数为a n-3，...，第n-1个电容与第n-1个MOS管之间的金属线的方块电阻数为a，第n个电容与第n个MOS管之间的金属线的方块电阻数为1，即第n-1个电容与第n-1个MOS管之间的金属线的方块电阻数为第n个电容与第n个MOS管之间的金属线的方块电阻数的a倍。
优选的，第1个电容与第1个MOS管之间串联a n-1条金属线且该a n-1条金属线的每方块电阻阻值相同，第2个电容与第2个MOS管之间串联a n-2条金属线且该a n-2条金属线的每方块电阻阻值相同，第3个电容与第3个MOS管之间串联a n-3条金属线且该a n-3条金属线的每方块电阻阻值相同，...，第n-1个电容与第n-1个MOS管之间串联a条金属线且该a条金属线的每方块电阻阻值相同，第n个电容与第n个MOS管之间串联1条金属线，也就是说，第n-1个电容与第n-1个MOS管之间串联的金属线的条数为第n个电容与第n个MOS管之间串联的金属线的条数的a倍，每个电容与对应一个MOS管之间连接的金属线的每方块电阻阻值相同，第n-1个电容与第n-1个MOS管之间串联的金属线的每方块电阻阻值和第n个电容与第n个MOS管之间串联的金属线的每方块电阻阻值相同，即每个电容支路的金属 线的每方块电阻阻值与其他的电容支路的金属线的每方块电阻阻值相等。每个电容支路的串联的金属线可以设置在电路板的同一层。其中，a为大于1的整数。
请参考图7，当a＝2时，第1个电容与第1个MOS管之间串联2 n-1条金属线且该2 n-1条金属线的每方块电阻阻值相同，第2个电容与第2个MOS管之间串联2 n-2条金属线且该2 n-2条金属线的每方块电阻阻值相同，第3个电容与第3个MOS管之间串联2 n-3条金属线且该2 n-3条金属线的每方块电阻阻值相同，...，第n-1个电容与第n-1个MOS管之间串联2条金属线且该2条金属线的每方块电阻阻值相同，第n个电容与第n个MOS管之间串联1条金属线，每个电容支路的金属线的每方块电阻阻值与其他的电容支路的金属线的每方块电阻阻值相等。每个电容支路的串联的金属线可以设置在电路板的同一层。
优选的，第1个电容与第1个MOS管之间的金属线为1条，第2个电容与第2个MOS管之间并联a条金属线且该a条金属线的每方块电阻阻值相同，第3个电容与第3个MOS管之间并联a 2条金属线且该a 2条金属线的每方块电阻阻值相同，...，第n-1个电容与第n-1个MOS管之间并联a n-2条金属线且该a n-2条金属线的每方块电阻阻值相同，第n个电容与第n个MOS管之间并联a n-1条金属线且该a n-1条金属线的每方块电阻阻值相同，即第n个电容与第n个MOS管之间并联的金属线的条数为第n-1个电容与第n-1个MOS管之间并联的金属线的条数的a倍，每个所述电容与对应一个MOS管之间连接的金属线的每方块电阻阻值相同，第n-1个电容与第n-1个MOS管之间串联的金属线的每方块电阻阻值和第n个电容与第n个MOS管之间串联的金属线的每方块电阻阻值相同，即每个电容支路的金属线的每方块电阻阻值与其他的电容支路的金属线的每方块电阻阻值相等。每个电容支路的并联的金属线可以设置在电路板的不同层上。其中，a为大于1的整数。
请参考图8，当a＝2时，第1个电容与第1个MOS管之间的金属线为1条，第2个电容与第2个MOS管之间并联2条金属线且该2条金属线的每方块电阻阻值相同，第3个电容与第3个MOS管之间并联4条金属线且 该4条金属线的每方块电阻阻值相同，...，第n-1个电容与第n-1个MOS管之间并联2 n-2条金属线且该2 n-2条金属线的每方块电阻阻值相同，第n个电容与第n个MOS管之间并联2 n-1条金属线且该2 n-1条金属线的每方块电阻阻值相同，每个电容支路的金属线的每方块电阻阻值与其他的电容支路的金属线的每方块电阻阻值相等。每个电容支路的并联的金属线可以设置在电路板的不同层上。
每个电容支路的电容与MOS管之间可以设置一层或多层并联或串联的金属线，实现电容阵列电路的多个电容支路的电容与MOS管之间金属线电阻的单调性变化。
请再参考图3，第一电子开关Q1的第一端与电源V连接，第一电子开关Q1的第二端通过电阻R分别与第二电子开关Q2的第一端及电容输出端连接，第二电子开关Q2的第二端接地，第一电子开关Q1的控制端与第二电子开关Q2的控制端分别用于接收时钟信号，第一电子开关Q1及第二电子开关Q2基于时钟信号进行导通和截止。逻辑单元40的输出端分别与第一电子开关Q1的控制端及第二电子开关Q2的控制端连接。图中第一电子开关Q1的控制端、第二电子开关Q2的控制端及逻辑单元40的输出端分别连接至VIN端，VOUT端即电容输出端。
通过电容阵列电路C输出单调性变化的总电容，能够使得电容充放电电路20的充放电频率呈单调性变化。
在其中一个实施例中，第一电子开关Q1为PMOS管，第一电子开关Q1的第一端、第二端及第三端分别对应PMOS管的漏极、源极及栅极。第二电子开关Q2为NMOS管，第二电子开关Q2的第一端、第二端及第三端分别对应NMOS管的漏极、源极及栅极。
控制单元50分别与每个MOS管的栅极连接。控制单元50用于通过控制信号控制每个MOS管的导通和截止，以调节电容阵列电路C的总电容。
控制单元50用于通过控制信号控制MOS管的导通和截止，以调节电容阵列电路C的总电容。所述控制信号为脉冲信号。具体的，控制单元50设置第1个MOS管至第n个MOS管的二进制信号分别为trim<1>，trim<2>，trim<3>，…，trim<n-1>，trim<n>，并传输每个二进制信号对 应的脉冲信号至MOS管，当二进制信号trim<1>，trim<2>，trim<3>，…，trim<n-1>，trim<n>对应的数值呈单调性变化时，充放电电路20的充放电频率呈单调性变化，从而RC振荡电路输出的时钟信号的频率呈单调性变化，从而提高RC振荡器输出频率的精度。
通过控制单元50调节电容阵列电路C的总电容呈单调性变化，进而使得电容充放电电路20的充放电频率呈单调性变化，从而使得RC振荡电路输出的时钟信号的频率呈单调性变化，提高RC振荡器输出频率的精度。
逻辑单元40可以包括RS触发器及反相器。上述的金属线可以是铜线，铜线具有较好的导电性能，成本低。
下面以图9所示的电路图为例对本申请实施例的RC振荡电路的工作原理进行说明。
第一充放电电路21包括电容阵列电路C1、电源V1、第一电子开关M1、第一电阻R1及第二电子开关M2，第二充放电电路22包括电容阵列电路C2、电源V1、第一电子开关M3、第一电阻R2及第二电子开关M4。第一电子开关为PMOS管，第二电子开关为NMOS管。第一比较器I1的第一输入端和第二输入端分别对应第一比较器的同相输入端和反向输入端。第二比较器I2的第一输入端和第二输入端分别对应第二比较器的同相输入端和反向输入端。逻辑单元为RS触发器I3，RS触发器I3包括输入端S、输入端R、输出端Q及输出端Qn。RS触发器I3的输出端Q及输出端Qn分别输出时钟信号CLK与CLKn。
在RC振荡电路的第一个时钟半周期内，Q和Qn的上一状态分别为高电平和低电平，第一电子开关M1导通，第二电子开关M2截止，第一充放电电路21进行充电，第一比较器I1输出高电平至RS触发器I3的输入端R；同时，第一电子开关M3截止，第二电子开关M4导通，第二充放电电路22进行放电，第二比较器I2输出低电平至RS触发器I3的输入端S，RS触发器I3的输出端Q变为低电平，输出端Qn变为高电平，RC振荡电路进入第二个时钟半周期。在第二个时钟半周期时，Q和Qn的上一状态分别为低电平和高电平，第一电子开关M1截止，第二电子开关M2导通，第一充放电电路21进行放电，第一比较器I1输出低电平至RS触发器I3的输入端 R；同时，第一电子开关M3导通，第二电子开关M4截止，第二充放电电路22进行充电，第二比较器I2输出高电平至RS触发器I3的输入端S，RS触发器I3的输出端Q变为高电平，输出端Qn变为低电平。由此，RC振荡电路完成了一整个时钟周期的充放电。
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本发明的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变形和改进，这些都属于本发明的保护范围。因此，本发明专利的保护范围应以所附权利要求为准。

Claims (14)

  1. 一种电容阵列电路，其特征在于，包括：
    N个电容；
    N个MOS管，与所述N个电容一一对应，其中，所述N个MOS管中的每个MOS管的漏极通过不同的金属线与对应的电容的一端连接，所述每个MOS管的源极接地，所述每个MOS管的栅极用于接收控制信号以分别控制所述每个MOS管的导通和截止；
    所述N个电容的另一端连接至一公共端，所述公共端作为电容输出端；
    所述N个电容中的第n-1个电容的容值为Cn-1，第n个电容的容值为Cn，Cn＝aCn-1；
    所述N个MOS管中的第n-1个MOS管的导通电阻为R onn-1，第n个MOS管的导通电阻为R onn；
    第n-1个电容与第n-1个MOS管之间的金属线的电阻为R netn-1，第n个电容与第n个MOS管之间的金属线的电阻为R netn；
    其中，R netn-1与R onn-1之和大于或等于R netn与R onn之和的a倍，其中，a大于1，N为大于或等于2的整数，n＝[2，N]。
  2. 如权利要求1所述的电容阵列电路，其特征在于，第n-1个MOS管的宽度与长度的比值为Mn-1，第n个MOS管的宽度与长度的比值为Mn，第n个MOS管的宽度与长度的比值Mn为第n-1个MOS管的宽度与长度的比值Mn-1的b倍，b＝a，第n-1个电容与第n-1个MOS管之间的金属线的电阻R netn-1大于或等于第n个电容与第n个MOS管之间的金属线的电阻R netn的a倍。
  3. 如权利要求2所述的电容阵列电路，其特征在于，a＝b＝2，第n-1个电容与第n-1个MOS管之间的金属线的电阻R netn-1大于或等于第n个电容与第n个MOS管之间的金属线的电阻R netn的2倍。
  4. 如权利要求1所述的电容阵列电路，其特征在于，第n个电容与第n个MOS管之间的金属线为a n-1条，每条金属线的电阻值相等，且每个电容与对应一个MOS管之间的金属线相互并联；其中，a为大于1的整数。
  5. 如权利要求1所述的电容阵列电路，其特征在于，第n-1个电容与第n-1个MOS管之间的金属线为1条且该条金属线的电阻为R netn-1，第n个电容与第n个MOS管之间的金属线为1条且该条金属线的电阻为R netn，第n-1个电容与第n-1个MOS管之间的金属线的电阻R netn-1为第n个电容与第n个MOS管之间的金属线的电阻R netn的a倍。
  6. 如权利要求1所述的电容阵列电路，其特征在于，每个所述电容与对应一个MOS管之间连接的金属线的每方块电阻阻值相同，第n-1个电容与第n-1个MOS管之间的金属线的方块电阻数为第n个电容与第n个MOS管之间的金属线的方块电阻数的a倍。
  7. 如权利要求1所述的电容阵列电路，其特征在于，第n-1个电容与第n-1个MOS管之间串联的金属线的条数为第n个电容与第n个MOS管之间串联的金属线的条数的a倍，每个所述电容与对应一个MOS管之间连接的金属线的每方块电阻阻值相同，第n-1个电容与第n-1个MOS管之间串联的金属线的每方块电阻阻值和第n个电容与第n个MOS管之间串联的金属线的每方块电阻阻值相同。
  8. 如权利要求1所述的电容阵列电路，其特征在于，第n个电容与第n个MOS管之间并联的金属线的条数为第n-1个电容与第n-1个MOS管之间并联的金属线的条数的a倍，每个所述电容与对应一个MOS管之间连接的金属线的每方块电阻阻值相同，第n-1个电容与第n-1个MOS管之间串联的金属线的每方块电阻阻值和第n个电容与第n个MOS管之间串联的金属线的每方块电阻阻值相同。
  9. 如权利要求1所述的电容阵列电路，其特征在于，所述金属线为铜线。
  10. 如权利要求1所述的电容阵列电路，其特征在于，所述控制信号为脉冲信号。
  11. 一种电容充放电电路，其特征在于，包括如权利要求1-10任一项所述的电容阵列电路、电源、第一电子开关、第一电阻及第二电子开关；所述第一电子开关的第一端与所述电源连接，所述第一电子开关的第二端通过所述电阻分别与所述第二电子开关的第一端及所述电容输出端连接，所述第二电子开关的第二端接地，所述第一电子开关的控制端与所述第二电子开关的控制端分别用于接收时钟信号，所述第一电子开关及所述第二电子开关基于所述时钟信号进行导通和截止。
  12. 如权利要求11所述的电容充放电电路，其特征在于，所述第一电子开关为PMOS管，所述第二电子开关为NMOS管。
  13. 一种RC振荡电路，其特征在于，包括第一充放电电路、第二充放电电路、第一比较器、第二比较器、参考电压单元、逻辑单元及控制单元，第一充放电电路及第二充放电电路分别为如权利要求7-8任一项所述的电容充放电电路；所述第一比较器的第一输入端与所述第一充放电电路的电容输出端连接，所述第一比较器的第二输入端与所述参考电压单元连接；所述第二比较器的第一输入端与所述第二充放电电路的电容输出端连接，所述第二比较器的第二输入端与所述参考电压单元连接；所述第一比较器的输出端及所述第二比较器的输出端均与所述逻辑单元的输入端连接，所述逻辑单元的输出端分别与所述第一电子开关的控制端及所述第二电子开关的控制端连接；所述控制单元分别与每个MOS管的栅极连接；
    所述参考电压单元用于产生基准电压；
    所述第一充放电电路用于传输第一充电电压或第一放电电压至所述第一比较器；
    所述第一比较器用于对所述第一充电电压及所述基准电压进行比较，或对所述第一放电电压及所述基准电压进行比较，并将第一比较结果输出至所述逻辑单元；
    所述第二充放电电路用于传输第二充电电压或第二放电电压至所述第二比较器；
    所述第二比较器用于对所述第二充电电压及所述基准电压进行比较，或对所述第二放电电压及所述基准电压进行比较，并将第二比较结果输出 至所述逻辑单元；
    所述逻辑单元用于根据所述第一比较结果及所述第二比较结果输出时钟信号；
    所述第一充放电电路及所述第二充放电电路用于根据所述时钟信号进行充电和放电；
    所述控制单元用于通过控制信号控制所述MOS管的导通和截止，以调节所述电容阵列电路的总电容。
  14. 如权利要求13所述的RC振荡电路，其特征在于，所述逻辑单元包括RS触发器。
PCT/CN2020/113056 2020-09-02 2020-09-02 电容阵列电路、充放电电路及rc振荡电路 WO2022047673A1 (zh)

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