WO2022036847A1 - 显示装置及其驱动方法 - Google Patents

显示装置及其驱动方法 Download PDF

Info

Publication number
WO2022036847A1
WO2022036847A1 PCT/CN2020/123133 CN2020123133W WO2022036847A1 WO 2022036847 A1 WO2022036847 A1 WO 2022036847A1 CN 2020123133 W CN2020123133 W CN 2020123133W WO 2022036847 A1 WO2022036847 A1 WO 2022036847A1
Authority
WO
WIPO (PCT)
Prior art keywords
sub
pixels
gate
lines
groups
Prior art date
Application number
PCT/CN2020/123133
Other languages
English (en)
French (fr)
Inventor
赵文勤
唐崇伟
Original Assignee
惠科股份有限公司
重庆惠科金渝光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 惠科股份有限公司, 重庆惠科金渝光电科技有限公司 filed Critical 惠科股份有限公司
Publication of WO2022036847A1 publication Critical patent/WO2022036847A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen

Definitions

  • the present application relates to a display device and a driving method thereof, and more particularly, to a display device of a dual-gate driving structure and a driving method thereof.
  • liquid crystal display devices which have gradually replaced traditional cathode ray tube display devices due to their superior characteristics such as thin body, low power consumption and no radiation.
  • electronic products such as mobile phones, portable multimedia devices, notebook computers, LCD TVs and LCD screens, etc.
  • a liquid crystal display panel with a dual-gate driving structure is developed accordingly.
  • a row of pixels is driven simultaneously through two adjacent gate lines.
  • the odd-numbered gate lines are responsible for driving the odd-numbered sub-pixels
  • the even-numbered gate lines are responsible for driving the even-numbered sub-pixels.
  • the dual gate driving technology also brings some problems. With the doubling of the gate line, the time for writing the data voltage to the pixel is reduced to half of the original, so that a data line is driven from positive to positive polarity.
  • the drive from negative polarity to negative polarity can meet the writing time of the liquid crystal, but the drive from positive polarity to negative polarity or from negative polarity to positive polarity will cause the phenomenon that the pixel voltage is not fully charged, resulting in the formation of bright and dark lines or grid problem.
  • the purpose of the present application is to provide a display device and a driving method thereof, which can solve the problem of bright and dark lines or grids caused by the dual gate driving structure.
  • the present application provides a driving method for a display device
  • the display device includes a display panel
  • the display panel includes multiple groups of gate lines, multiple data lines and multiple groups of sub-pixels
  • the multiple groups of sub-pixels are respectively connected with multiple groups of gate lines and multiple groups of sub-pixels.
  • the data lines are electrically connected
  • the gate lines of each group respectively drive a plurality of groups of sub-pixels in the corresponding row
  • the gate lines of each group respectively have a first gate line and a second gate line in sequence.
  • a gate line is respectively electrically connected to one of the multiple groups of sub-pixels in the same row
  • the second gate line is electrically connected to the other of the multiple groups of sub-pixels in the same row, respectively.
  • the driving method includes: in one of two adjacent frames, sequentially transmitting a scan signal to each group of gate lines in the order of the first gate line and the second gate line, and in the adjacent two frames In another frame, the scan signals are sequentially transmitted to the gate lines of each group in the order of the second gate line and the first gate line.
  • a plurality of gate lines and a plurality of data lines are alternately arranged to define a plurality of sub-pixel regions.
  • the first gate lines are respectively electrically connected to the odd-numbered sub-pixels in the same row, and the second gate lines are respectively electrically connected to the even-numbered sub-pixels in the same row.
  • the first gate lines are respectively electrically connected to the even-numbered sub-pixels in the same row, and the second gate lines are respectively electrically connected to the odd-numbered sub-pixels in the same row.
  • the voltage polarities of two adjacent sub-pixels in the column direction are opposite.
  • the voltage polarities of the two sub-pixels in the same group are the same.
  • the voltage polarities of two adjacent sub-pixels in two said groups that are adjacent in the row direction are opposite.
  • the sub-pixels are driven by outputting a data signal in a one-point inversion mode through the data lines.
  • the sub-pixels of each group are respectively electrically connected to the same data line.
  • the display panel is a liquid crystal panel of a dual gate driving structure.
  • the present application further provides a display device including a display panel and a driving circuit.
  • the display panel includes multiple groups of gate lines, multiple data lines and multiple groups of sub-pixels, the multiple groups of sub-pixels are respectively electrically connected with multiple groups of gate lines and multiple data lines, and the gate lines of each group drive corresponding rows respectively a plurality of groups of sub-pixels, the gate lines of each group respectively have a first gate line and a second gate line in sequence, and the first gate lines are respectively electrically connected to one of the plurality of groups of sub-pixels in the same row, The second gate lines are respectively electrically connected to the other one of the plurality of groups of sub-pixels in the same row.
  • the present application further provides a driving method of a display device
  • the display device includes a display panel
  • the display panel includes a plurality of groups of gate lines, a plurality of data lines and a plurality of groups of sub-pixels
  • the plurality of groups of sub-pixels are respectively connected with a plurality of groups of gate electrodes
  • the lines and a plurality of data lines are electrically connected
  • the gate lines of each group respectively drive a plurality of groups of sub-pixels in the corresponding row
  • the gate lines of each group respectively have a first gate line and a second gate in sequence line
  • the first gate line is respectively electrically connected to one of the multiple groups of sub-pixels in the same row
  • the second gate line is electrically connected to the other of the multiple groups of sub-pixels in the same row
  • each of the multiple groups of sub-pixels is respectively connected to the same
  • the data lines are electrically connected
  • the driving method includes: in one of two adjacent frames, sequentially transmitting a scan signal to the gate
  • the scan signals are sequentially transmitted to each group in the order of the first gate line and the second gate line in one of two adjacent frames.
  • the scan signal is sequentially transmitted to the gate lines of each group in the order of the second gate line and the first gate line.
  • FIG. 1A is a functional block diagram of a display device according to an embodiment of the present application.
  • FIG. 1B is a flowchart of a method for driving a display device according to an embodiment of the present application.
  • FIG. 2A and FIG. 2B are schematic diagrams of connection between a display panel, gate lines and data lines of a display device according to an embodiment, respectively.
  • 3A and 3B respectively show schematic diagrams of driving signals of the gate lines and the data lines in one frame time.
  • FIG. 4 and FIG. 5 are schematic diagrams of connection between a display panel, gate lines and data lines of a display device according to different embodiments of the present application, respectively.
  • first and second are only used for descriptive purposes, and should not be construed as indicating or implying relative importance or implying the number of indicated technical features. Thus, a feature defined as “first” or “second” may expressly or implicitly include one or more of that feature.
  • plural means two or more.
  • comprising and any variations thereof are intended to cover the non-exclusive inclusion.
  • the terms “installed”, “connected” and “connected” should be understood in a broad sense, for example, it may be a fixed connection or a detachable connection Connection, or integral connection; can be mechanical connection, can also be electrical connection; can be directly connected, can also be indirectly connected through an intermediate medium, can be internal communication between two elements.
  • installed should be understood in a broad sense, for example, it may be a fixed connection or a detachable connection Connection, or integral connection; can be mechanical connection, can also be electrical connection; can be directly connected, can also be indirectly connected through an intermediate medium, can be internal communication between two elements.
  • FIG. 1A is a functional block diagram of a display device 1 according to an embodiment of the application
  • FIG. 1B is a flowchart of a method for driving a display device according to an embodiment of the application.
  • the display device 1 of this embodiment is a liquid crystal display device, and includes a display panel 11 and a driving circuit 12 .
  • the display panel 11 may include a plurality of gate lines ( G1 , G2 , . . . ), a plurality of data lines ( S1 , S2 , S3 , . . . ) and a plurality of sub-pixels (Sub-pixels), a plurality of gate lines and a plurality of data lines
  • the lines are staggered to define regions of a plurality of sub-pixels, and the plurality of sub-pixels are respectively electrically connected to a plurality of gate lines and a plurality of data lines.
  • the driving circuit 12 is electrically connected to the display panel 11 and can drive the display panel 11 to display images.
  • the driving circuit 12 of this embodiment may include a scan driving unit 121 , a data driving unit 122 and a timing control unit 123 .
  • the scan driving unit 121 can be coupled with the display panel 11 through the gate lines, and the data driving unit 122 can be coupled with the display panel 11 through the data lines.
  • the scan driving unit 121 can respectively output scan signals to turn on the gate lines, and the data driving unit 122 can output a plurality of data signals corresponding to the data lines to drive the corresponding sub-pixels.
  • the display device 1 may further include a timing control unit 123 , and the timing control unit 123 may transmit the vertical synchronization signal and the horizontal synchronization signal to the scan driving unit 121 , and convert the video signal received from the external interface into the data driving unit 122 . and transmits the data signal and the horizontal synchronization signal to the data driving unit 122 .
  • the data driving unit 122 can transmit the data signals corresponding to each row of sub-pixels to each sub-pixel through the data lines , so that the display panel 11 can display images.
  • FIG. 2A and FIG. 2B are schematic diagrams of connection between a display panel, gate lines and data lines of a display device according to an embodiment, respectively.
  • 2A and 2B show the same connection structure, but show different bright and dark line conditions (the gray background is the dark spot position where the pixel voltage of the sub-pixel P is electrically unsaturated).
  • FIG. 2A and FIG. 2B show 6 gate lines G1-G6, 6 data lines S1-S6 and 36 sub-pixels P in three rows as an example, but it is not limited to this. In different embodiments, More gate lines, data lines and sub-pixels can be designed according to their actual needs.
  • the six gate lines G1-G6 can be divided into three groups, each group has two gate lines, namely (G1, G2), (G3, G4), (G5, G6), and the display panel 11 may have multiple groups of sub-pixels P, and each group has two sub-pixels P.
  • two sub-pixels P in each dashed line in FIG. 2A are a group, each row has 6 groups of sub-pixels P, a total of 18 groups, the sub-pixels P of each group are respectively electrically connected to the same data line, and each One group of gate lines can respectively drive the 6 groups of sub-pixels P in the corresponding row.
  • the voltage polarities displayed by the sub-pixels P of each group at the same time are the same.
  • the voltage polarities of the sub-pixels P of the same group connected to the same data line are either positive or negative.
  • the gate lines G1 and G2 are the first group, which can simultaneously drive 6 groups of sub-pixels P in the first row (the sub-pixels P in each group are respectively electrically connected to the same data line); the gate lines G3 and G4 are the second group, which can simultaneously drive 6 groups of sub-pixels P in the second row; gate lines G5 and G6 are the third group, which can simultaneously drive 6 groups of sub-pixels P in the third row, and so on.
  • the display panel 1 of this embodiment is a liquid crystal display panel with a dual gate driving structure.
  • each group of gate lines respectively has two gate lines, which are a first gate line and a second gate line in sequence, and the first gate lines are respectively electrically connected to one of the sub-pixels P in the same row One, and the second gate lines are respectively electrically connected to the other one of the sub-pixels P in the same row.
  • odd-numbered row gate lines may be responsible for connecting and driving odd-numbered sub-pixels P in the same row
  • even-numbered row gate lines may be responsible for connecting and driving even-numbered sub-pixels P in the same row, or vice versa.
  • the first gate line (gate line G1 ) can be connected to the sub-pixels P on the left side (odd number in the same row) of each group of the first row respectively, and the second gate line
  • the pole lines (gate lines G2) can respectively connect the sub-pixels P on the right side (even numbers in the same row) of each group of the first row;
  • the first gate lines (gate lines G3 ) can be respectively connected to the sub-pixels P on the left side of each group in the second row (odd numbers in the same row), and the second gate line (gate line G4) can be respectively connected with the right side of each group in the second row (even numbers in the same row)
  • the first gate line (gate line G5) can be respectively connected to the left (odd number of the same row) sub-pixels P of each group in the third row
  • the The two gate lines (the gate line G6 ) can respectively connect the sub-pixel
  • 3A and 3B respectively show schematic diagrams of driving signals of the gate lines and the data lines in one frame time.
  • the scan driving unit 121 of the driving circuit 12 uses the timing of FIG. 3A to make the gate lines G1 to G6 sequentially When it is turned on (turns on the corresponding TFT), and the data driving unit 122 transmits the data signal corresponding to each row of sub-pixels P to each sub-pixel P through the data lines S1 to S6, the display panel 11 will be turned on.
  • the sub-pixel P produces a problem of light and dark lines or a grid problem.
  • the gate line G2 in sequence to charge the right-numbered sub-pixels P in the first row connected to the gate line G2, because the sub-pixels P in the same group connected with the gate lines G1, G2 and the data line S1 are of the same polarity ( +), so the sub-pixels P on the right side of each group in the first row are more easily charged to the corresponding potential; after that, the gate line G3 is turned on, so that the sub-pixels P on the left side of each group in the second row connected to the gate line G3 Charging, since the sub-pixels P connected to the gate lines G2 and G3 are of different polarities, the sub-pixels P on the left side of each group connected to the gate line G3 are less likely to be charged to the corresponding potential, which in turn leads to the gate line and the gate line.
  • the sub-pixel P connected by G3 is lower in brightness than the sub-pixel P connected by the gate line G2, so that the data line S1 forms a dark spot on the sub-pixel P connected by the gate line G1 and the gate line G3, and the sub-pixel P connected by the gate line G2
  • the sub-pixels P connected to the gate line G4 form bright spots. The same is true for other sub-pixels P, thus forming a dark line as shown by the shadow in Figure 2A. If not changed, this scanning method will make the position of the sub-pixel P that is not fully charged always appear in the same position of the screen, The problem of bright and dark lines is visually formed on the entire screen of the display panel 11 , which reduces the optical quality of the display panel 11 .
  • step S01 drives the display panel 11 by the driving method (step S01 ) shown in FIG. 1B .
  • step S01 is: in one of two adjacent frames, the order of the first gate line and the second gate line are in sequence. A scan signal is transmitted to the gate lines of each group, and in the other one of the adjacent two frames, the scan signal is sequentially transmitted to the gate lines of each group in the order of the second gate line and the first gate line polar line.
  • two adjacent frames are, for example, the nth frame Fn and the n+1th frame (Fn+1).
  • the scan driving unit 121 turns on the gate lines G1 , G2 , G3 , G4 , G5 , and G6 in sequence, so that the corresponding data signals can be transmitted to the sub-pixels P through the data lines S1 ⁇ S6 . Therefore, as described above, as shown in FIG. 2A , the data line S1 forms a dark spot on the sub-pixel P connected to the gate line G1 and the gate line G3, and the data line S1 forms a dark spot on the sub-pixel P connected to the gate line G2 and the gate line G4.
  • the sub-pixels P form bright spots. The same applies to other sub-pixels P connected to the data lines S2 to S6.
  • the scan signals are sequentially transmitted to the gate lines of each group in the order of the second gate line and the first gate line. Therefore, as shown in FIG. 3B , in the n+1th frame (Fn+1), the scan driving unit 121 turns on the gate lines G2 , G1 , G4 , G3 , G6 , and G5 in sequence, so that the corresponding data The signals can be transmitted to the sub-pixels P through the data lines S1-S6. Therefore, as shown in FIG. 2B , the data line S1 will form a bright spot in the sub-pixel P connected to the gate line G1 and the gate line G3, and will be formed in the sub-pixel P connected by the gate line G2 and the gate line G4. dark spot.
  • the scan driving unit 121 turns on the gate lines G1, G2, G3, G4, G5, and G6 in sequence, so that the corresponding data signals can pass through the data line S1 ⁇ S6 is transmitted to the sub-pixel P.
  • the scan driving unit 121 turns on the gate lines G2, G1, G4, G3, G6, and G5 in sequence, so that the corresponding data signals can pass through the data lines S1 ⁇ S6 is transmitted to the sub-pixel P;
  • the scanning driving unit 121 turns on the gate lines G1, G2, G3, G4, G5, and G6 in sequence, so that the corresponding data signals can pass through
  • the data lines S1 to S6 are transmitted to the sub-pixels P.
  • the scan driving unit 121 turns on the gate lines G2, G1, G4, G3, G6, and G5 in sequence, so that the corresponding data signals can pass through the data.
  • Lines S1-S6 are transmitted to sub-pixel P, and so on.
  • the scan driving unit 121 is turned on in the order of the gate lines G2, G1, G4, G3, G6, and G5, so that the corresponding data signals can pass through the data lines S1-S6 It is transmitted to the sub-pixel P.
  • the scan driving unit 121 turns on the gate lines G1, G2, G3, G4, G5, and G6 in sequence, so that the corresponding data signals can be transmitted through the data lines S1 to S6.
  • the scan driving unit 121 turns on the gate lines G2, G1, G4, G3, G6, G5 in sequence, so that the corresponding data signals can pass through the data lines S1 to S6 are transmitted to the sub-pixels P.
  • the scan driving unit 121 turns on the gate lines G1, G2, G3, G4, G5, and G6 in sequence, so that the corresponding data signals can pass through the data line S1.
  • ⁇ S6 is transmitted to sub-pixel P, and so on.
  • the sub-pixel P is driven by outputting a data signal in a dot inversion mode through a data line
  • the sub-pixel P of the display screen can show the display effect of 2-line inversion.
  • the voltage polarities of two adjacent sub-pixels P are opposite, and the voltage polarities of two adjacent sub-pixels P in two adjacent groups in the row direction are also opposite. .
  • the scan signal in one of two adjacent frames, is sequentially transmitted to each of the first gate lines and the second gate lines in the order of the first gate line and the second gate line the gate lines of each group, and in the other of the adjacent two frames, the scan signals are sequentially transmitted to the gate lines of each group in the order of the second gate line and the first gate line, so that the In one of the two adjacent frames, the data line S1 forms a dark spot on the sub-pixel P connected to the gate line G1 and the gate line G3, while the sub-pixel connected to the gate line G2 and the gate line G4 forms a dark spot on the data line S1.
  • each sub-pixel P is switching between light and dark at a frequency of 30Hz. Due to the visual persistence effect of the human eye, this is not the case.
  • the images of two adjacent frames are separated for a short period of time, whereby the display of the display panel 11 can be more uniform, and the optical quality can be improved.
  • the invention of the present application is not limited to transmitting scan signals to the gate lines of each group in the order of G1, G2, G3, G4... in odd-numbered frames, and in the order of G2, G1, G4, G3... in even-numbered frames
  • the drive transmits scan signals to the gate lines of each group.
  • a set of gate lines is also possible to transmit scan signals to the gate lines of each group in the order of G1, G2, G3, G4... in the even-numbered frames.
  • FIG. 4 and FIG. 5 are schematic diagrams showing the connection between the display panel, the gate line and the data line of the display device according to different embodiments of the present application (the gray background is the pixel voltage of the sub-pixel P is not electrically saturated). dark spot).
  • the main difference from the connection method in FIG. 2A is that in this embodiment, in the first group of gate lines, the first gate lines (gate lines G1 ) are respectively connected to the left and right sides of each group of the first row.
  • the sub-pixels P on the side (odd number of the same row), and the second gate line (gate line G2) respectively connects the sub-pixels P on the right side (even number of the same row) of each group of the first row; in addition, in the second group Among the gate lines, the first gate line (gate line G3) is respectively connected to the right (even-numbered) sub-pixels P of each group in the second row, and the second gate line (gate line G4) is respectively connected The sub-pixels P on the left side (odd-numbered in the same row) of each group in the second row; in addition, in the third group of gate lines, the first gate line (gate line G5 ) is connected to the left side of each group in the third row, respectively (odd-numbered in the same row
  • the first gate lines (gate lines G1 ) are respectively connected to each of the first row The right (even-numbered in the same row) sub-pixels P of the group, and the second gate line (gate line G2) respectively connects the left (odd-numbered in the same row) sub-pixels P of each group in the first row;
  • the first gate line (gate line G3) is respectively connected to the right (even-numbered) sub-pixels P of each group in the second row, and the second gate line (gate line G4) Connect the left (odd-numbered in the same row) sub-pixels P of each group in the second row respectively;
  • the first gate line (gate line G5) is connected with the sub-pixels P of each group in the third row respectively The right (even-numbered in the same row) sub-pixels P, and the second gate line
  • FIG. 4 and FIG. 5 can be referred to above, and no further description is given here.
  • the above-mentioned connection manners of the dual-gate structures in FIG. 2A , FIG. 4 and FIG. 5 are only examples and should not be used to limit the present application.
  • the display device and the driving method thereof of the present application in one of two adjacent frames, scan signals are sequentially transmitted to each group in the order of the first gate line and the second gate line In the other of the adjacent two frames, the scan signal is sequentially transmitted to the gate lines of each group in the order of the second gate line and the first gate line.

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

一种显示装置（1）及其驱动方法，显示装置（1）的显示面板（11）的多组子像素（P）分别和多条栅极线（G1,G2,…）及多条数据线（S1,S2,S3,…）电性连接，每一组栅极线分别驱动对应行多组子像素（P），每一组栅极线的第一栅极线分别电连接同一行多组子像素（P）的其中之一，每一组栅极线的第二栅极线分别电连接同一行多组子像素（P）的其中另一，驱动方法包括：在相邻两帧的其中一帧时，以第一栅极线、第二栅极线的顺序依序传送一扫描信号至每一组的栅极线，在相邻两帧的其中另一帧时，以第二栅极线、第一栅极线的顺序依序传送扫描信号至每一组的栅极线（S01）。

Description

显示装置及其驱动方法 技术领域
本申请关于一种显示装置及其驱动方法，特别关于一种双栅极(Dual-gate)驱动架构的显示装置及其驱动方法。
背景技术
随着科技的进步，平面显示装置已经广泛的被运用在各种领域，尤其是液晶显示装置，因具有体型轻薄、低功率消耗及无辐射等优越特性，已经渐渐地取代传统阴极射线管显示装置，而应用至许多种类之电子产品中，例如行动电话、可携式多媒体装置、笔记型计算机、液晶电视及液晶屏幕等等。
为了降低成本、提高竞争力，一种双栅极(dual-gate)驱动架构的液晶显示面板因应而生。在双栅极驱动架构的显示面板中，是通过相邻的两条栅极线同时驱动一行像素，例如奇数行栅极线负责驱动奇数子像素，而偶数行栅极线负责驱动偶数子像素，以通过增加一倍的栅极线来节省一半的数据驱动IC(source IC)用量，达到降低成本的目的。不过，双栅极驱动技术也会带来了一些问题，随着栅极线的倍增，会使数据电压写入像素的时间下降为原来的一半，使得一条数据线在正极性到正极性的驱动或者负极性到负极性的驱动能够满足液晶的写入时间，但是，由正极性到负极性或者由负极性到正极性的驱动会存在像素电压充不饱的现象，导致画面形成亮暗线或是网格问题。
发明内容
有鉴于先前技术的不足，发明人经研发后得本申请。本申请的目的为提供一种显示装置及其驱动方法，可解决双栅极驱动架构所造成的亮暗线或网格问题。
本申请提出一种显示装置的驱动方法，显示装置包括一显示面板，显示面板包括多组栅极线、多条数据线和多组子像素，多组子像素分别和多组栅极线及多条数据线电性连接，每一组的栅极线分别驱动对应行的多组子像素，每一组的栅极线分别依序具有一第一栅极线和一第二栅极线，第一栅极线分别电连接同一行多组子像素的其中之一，第二栅极线分别电连接同一行多组子像素的其中另一。驱动方法包括：在相邻两帧的其中一帧时，以第一栅极线、第二栅极线的顺序依序传送一扫描信号至每一组的栅极线，在相邻两帧的其中另一帧时，以第二栅极线、第一栅极线的顺序依序传送扫描信号至每一组的栅极线。
在一实施例中，多条栅极线和多条数据线交错设置以定义出多个子像素的区域。
在一实施例中，第一栅极线分别电连接同一行的奇数子像素，第二栅极线分别电连接同一行的偶数子像素。
在一实施例中，第一栅极线分别电连接同一行的偶数子像素，第二栅极线分别电连接同一行的奇数子像素。
在一实施例中，沿列方向相邻的两个子像素的电压极性为相反。
在一实施例中，同一个所述组的两个子像素的电压极性为相同。
在一实施例中，沿行方向相邻的两个所述组中的两个相邻子像素的电压 极性为相反。
在一实施例中，在相邻两帧时，是通过数据线以一点反转模式输出一数据信号驱动子像素。
在一实施例中，每一组的子像素分别和同一条数据线电连接。
在一实施例中，显示面板是双栅极驱动架构的液晶面板。
本申请另提出一种显示装置，包括一显示面板以及一驱动电路。显示面板包括多组栅极线、多条数据线和多组子像素，多组子像素分别和多组栅极线及多条数据线电性连接，每一组的栅极线分别驱动对应行的多组子像素，每一组的栅极线分别依序具有一第一栅极线和一第二栅极线，第一栅极线分别电连接同一行多组子像素的其中之一，第二栅极线分别电连接同一行多组子像素的其中另一。驱动电路通过多组栅极线输出一扫描信号驱动显示面板的多组子像素；其中，在相邻两帧的其中一帧时，以第一栅极线、第二栅极线的顺序依序传送扫描信号至每一组的栅极线，且在相邻两帧的其中另一帧时，以第二栅极线、第一栅极线的顺序依序传送扫描信号至每一组的栅极线。
另外，本申请更提出一种显示装置的驱动方法，显示装置包括一显示面板，显示面板包括多组栅极线、多条数据线和多组子像素，多组子像素分别和多组栅极线及多条数据线电性连接，每一组的栅极线分别驱动对应行的多组子像素，每一组的栅极线分别依序具有一第一栅极线和一第二栅极线，第一栅极线分别电连接同一行多组子像素的其中之一，第二栅极线分别电连接同一行多组子像素的其中另一，每一多组子像素分别和同一条数据线电连接，驱动方法包括：在相邻两帧的其中一帧时，以第一栅极线、第二栅极线的顺序依序传送一扫描信号至每一组的栅极线，在相邻两帧的其中另一帧时，以第二栅极线、第一栅极线的顺序依序传送扫描信号至每一组的栅极线；其中， 在相邻两帧时，是通过数据线以一点反转模式输出一数据信号驱动子像素，使沿列方向相邻的两个所述子像素的电压极性为相反，沿行方向相邻的两个所述组中的两个相邻子像素的电压极性为相反。
承上所述，在本申请之显示装置及其驱动方法中，在相邻两帧的其中一帧时以第一栅极线、第二栅极线的顺序依序传送扫描信号至每一组的栅极线，而在相邻两帧的其中另一帧时，则是以第二栅极线、第一栅极线的顺序依序传送扫描信号至每一组的栅极线。借此，本申请的显示装置通过上述的驱动方式，可解决因双栅极架构所造成的亮暗线或网格的问题，使显示面板的显示更加均匀，提升其光学品味。
附图说明
所包括的附图用来提供对本申请实施例的进一步的理解，其构成了说明书的一部分，用于例示本申请的实施方式，并与文字描述一起来阐释本申请的原理。显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。在附图中：
图1A为本申请一实施例之一种显示装置的功能方块图。
图1B为本申请一实施例之一种显示装置的驱动方法的流程步骤图。
图2A与图2B分别为一实施例的显示装置的显示面板与栅极线及数据线的连接示意图
图3A与图3B分别显示了一个帧时间的栅极线与数据线的驱动信号示意图。
图4与图5分别为本申请不同实施态样的显示装置的显示面板与栅极线及数据线的连接示意图。
具体实施方式
这里所公开的具体结构和功能细节仅仅是代表性的，并且是用于描述本申请的示例性实施例的目的。但是本申请可以通过许多替换形式来具体实现，并且不应当被解释成仅仅受限于这里所阐述的实施例。
在本申请的描述中，需要理解的是，术语“中心”、“横向”、“上”、“下”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本申请的描述中，除非另有说明，“多个”的含义是两个或两个以上。另外，术语“包括”及其任何变形，意图在于覆盖不排他的包括。
在本申请的描述中，需要说明的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本申请中的具体含义。
这里所使用的术语仅仅是为了描述具体实施例而不意图限制示例性实施例。除非上下文明确地另有所指，否则这里所使用的单数形式“一个”、“一 项”还意图包括复数。还应当理解的是，这里所使用的术语“包括”和/或“包括”规定所陈述的特征、整数、步骤、操作、单元和/或组件的存在，而不排除存在或添加一个或更多其他特征、整数、步骤、操作、单元、组件和/或其组合。
以下将参照相关图式，说明依本申请较佳实施例之显示装置及其驱动方法，其中相同的组件将以相同的参照符号加以说明。
图1A为本申请一实施例之一种显示装置1的功能方块图，而图1B为本申请一实施例之一种显示装置的驱动方法的流程步骤图。
如图1A所示，本实施例的显示装置1为一液晶显示装置，并包括一显示面板11以及一驱动电路12。显示面板11可包括多条栅极线(G1、G2、…)、多条数据线(S1、S2、S3、…)和多个子像素(Sub-pixels)，多条栅极线和多条数据线交错设置以定义出多个子像素的区域，且多个子像素分別與多条栅极线和多条数据线电性连接。
驱动电路12和显示面板11电性连接，并可驱动显示面板11显示影像。本实施例的驱动电路12可包括一扫描驱动单元121、一数据驱动单元122及一时序控制单元123。
扫描驱动单元121可通过该些栅极线和显示面板11耦接，而数据驱动单元122可通过该些数据线和显示面板11耦接。扫描驱动单元121可分别输出扫描信号导通该些栅极线，而数据驱动单元122可输出与该些数据线对应的多个数据信号驱动对应的该些子像素。另外，显示装置1更可包括一时序控制单元123，时序控制单元123可传送垂直同步信号及水平同步信号至扫描驱动单元121，并将自外部接口所接收的视讯信号转换成数据驱动单元122所用的数据信号，并传送数据信号及水平同步信号至数据驱动单元122。在 一个帧时间(frame time)时，当该些栅极线分别被该些扫描信号导通时，数据驱动单元122可将对应每一行子像素的数据信号通过该些数据线传送至各子像素，使显示面板11可显示影像。
请先参照图2A与图2B所示，其分别为一实施例的显示装置的显示面板与栅极线及数据线的连接示意图。图2A和图2B显示了相同的连接架构，但显示不同的亮暗线状况(灰色背景为子像素P的像素电压电不饱和的暗点位置)。图2A和图2B中显示了6条栅极线G1～G6、6条数据线S1～S6和三行共36个子像素P为例，然并不以此为限，在不同的实施例中，可依据其实际需求设计更多的栅极线、数据线和子像素。
在图2A中，6条栅极线G1～G6可区分成3组，每一组有二条栅极线，即(G1，G2)、(G3，G4)、(G5，G6)，而显示面板11可具有多组的子像素P，每一组有二个子像素P。于此，图2A的每一虚线内的2个子像素P为一组，每一行有6组子像素P，共有18组，每一组的子像素P分别和同一条数据线电连接，且每一组的栅极线可分别驱动对应行的6组的子像素P。由于每一组的子像素P分别和同一条数据线电连接，因此，每一组的子像素P于同一时间所显现的电压极性相同。换言之，当数据信号通过数据线传送至子像素P时，和同一条数据线连接的同一组的子像素P的电压极性同为正极性或同为负极性。
具体来说，例如栅极线G1、G2为第一组，其可同时驱动第一行的6组子像素P(每一组的子像素P分别和同一条数据线电连接)；栅极线G3、G4为第二组，其可同时驱动第二行的6组子像素P；栅极线G5、G6为第三组，其可同时驱动第三行的6组子像素P，以此类推。因此，本实施例的显示面板1为一双栅极驱动架构的液晶显示面板。
其中，每一组栅极线分别具有二条栅极线，其依序为一第一栅极线和一第二栅极线，第一栅极线分别电连接同一行的子像素P的其中之一，而第二栅极线分别电连接同一行的子像素P的其中另一。例如，奇数行栅极线可负责连接及驱动同一行的奇数子像素P，而偶数行的栅极线可负责连接及驱动同一行偶数的子像素P，或相反。
在本实施例的第一组栅极线中，其第一栅极线(栅极线G1)可分别连接第一行各组左侧(同一行的奇数)的子像素P，而第二栅极线(栅极线G2)可分别连接第一行各组右侧(同一行的偶数)的子像素P；另外，在第二组栅极线中，第一栅极线(栅极线G3)可分别连接第二行各组左侧(同一行的奇数)的子像素P，而第二栅极线(栅极线G4)可分别连接第二行各组右侧(同一行的偶数)的子像素P；此外，在第三组栅极线中，第一栅极线(栅极线G5)可分别连接第三行各组的左侧(同一行的奇数)子像素P，而第二栅极线(栅极线G6)可分别连接第三行各组右侧(同一行的偶数)的子像素P。
图3A与图3B分别显示了一个帧时间的栅极线与数据线的驱动信号示意图。请先参照图3A所示，在每一个帧时间，且在图2A的双栅极架构下，若驱动电路12的扫描驱动单元121皆以图3A的时序使栅极线G1～G6分别依序导通(使对应的TFT导通)，并使数据驱动单元122将对应每一行子像素P的数据信号通过该些数据线S1～S6传送至各子像素P时，则会使显示面板11的子像素P产生亮暗线的问题或网格问题。
具体来说，以图2A的数据线S1(数据线S3、S6也有相同情况)为例，在栅极线G1打开而使和其连接的第一行各组左侧数子像素P先充电，接着依序打开栅极线G2，使和栅极线G2连接的第一行各组右数子像素P充电，由 于栅极线G1、G2和数据线S1连接的同组子像素P是同一极性(+)，因此第一行各组右侧的子像素P更容易充电到相应的电位；之后，打开栅极线G3，使和栅极线G3连接的第二行各组的左侧子像素P充电，由于栅极线G2、G3连接的子像素P为不同极性，导致和栅极线G3连接的各组左侧的子像素P更不容易充电到相应的电位，进而导致和栅极线G3连接的子像素P比栅极线G2连接的子像素P的亮度低，使得数据线S1在栅极线G1和栅极线G3所连接的子像素P形成暗点，而在栅极线G2和栅极线G4所连接的子像素P则形成亮点。其它子像素P是同样的道理，因而形成如图2A的阴影所示的暗线，如果不改变的话，这样的扫描方式将使得充电不饱和的子像素P的位置总是出现在画面的相同位置，使整个显示面板11的画面在视觉上形成亮暗线问题，降低了显示面板11的光学品味。
为了解决亮暗线或网格问题，本实施例的驱动电路12是以图1B的驱动方法(步骤S01)来驱动显示面板11。请参照图1B并配合图2A至图3B所示，在图1B中，步骤S01为：在相邻两帧的其中一帧时，以第一栅极线、第二栅极线的顺序依序传送一扫描信号至每一组的栅极线，在相邻两帧的其中另一帧时，以第二栅极线、第一栅极线的顺序依序传送扫描信号至每一组的栅极线。
如图3A所示，相邻两帧例如为第n帧Fn与第n+1帧(Fn+1)。在第n帧Fn时，扫描驱动单元121以栅极线G1、G2、G3、G4、G5、G6的顺序依序打开，使对应的数据信号可通过数据线S1～S6传送至子像素P。因此，同上述所言，如图2A所示，数据线S1在栅极线G1和栅极线G3所连接的子像素P形成暗点，而在栅极线G2和栅极线G4所连接的子像素P形成亮点。其它和数据线S2～S6连接的子像素P也有相同情况。
另外，在第n+1帧(Fn+1)时，则以第二栅极线、第一栅极线的顺序依序传送扫描信号至每一组的栅极线。因此，如图3B所示，在第n+1帧(Fn+1)时，扫描驱动单元121以栅极线G2、G1、G4、G3、G6、G5的顺序依序打开，使对应的数据信号可通过数据线S1～S6传送至子像素P。因此，如图2B所示，将使数据线S1在栅极线G1和栅极线G3所连接的子像素P形成亮点，而在栅极线G2和栅极线G4所连接的子像素P形成暗点。
举例来说，当第一帧(n＝1)时，扫描驱动单元121以栅极线G1、G2、G3、G4、G5、G6的顺序依序打开，使对应的数据信号可通过数据线S1～S6传送至子像素P，在第二帧时，扫描驱动单元121以栅极线G2、G1、G4、G3、G6、G5的顺序依序打开，使对应的数据信号可通过数据线S1～S6传送至子像素P；当第三帧(n＝3)时，扫描驱动单元121以栅极线G1、G2、G3、G4、G5、G6的顺序依序打开，使对应的数据信号可通过数据线S1～S6传送至子像素P，在第四帧时，扫描驱动单元121以栅极线G2、G1、G4、G3、G6、G5的顺序依序打开，使对应的数据信号可通过数据线S1～S6传送至子像素P，以此类推。或者，当第一帧(n＝1)时，扫描驱动单元121以栅极线G2、G1、G4、G3、G6、G5的顺序依序打开，使对应的数据信号可通过数据线S1～S6传送至子像素P，在第二帧时，扫描驱动单元121以栅极线G1、G2、G3、G4、G5、G6的顺序依序打开，使对应的数据信号可通过数据线S1～S6传送至子像素P；当第三帧(n＝3)时，扫描驱动单元121以栅极线G2、G1、G4、G3、G6、G5的顺序依序打开，使对应的数据信号可通过数据线S1～S6传送至子像素P，在第四帧时，扫描驱动单元121以栅极线G1、G2、G3、G4、G5、G6的顺序依序打开，使对应的数据信号可通过数据线S1～S6传送至子像素P，以此类推。
本实施例在上述的相邻两帧(第n帧Fn和第n+1帧(Fn+1))时，是通过数据线以一点反转(dot inversion)模式输出数据信号驱动子像素P，使显示画面的子画素P可呈现2列极性反转(2 line inversion)的显示效果，如图2A与图2B所示，在相邻两帧的其中一帧时，可使沿列方向相邻的两个子像素P的电压极性为相反，沿行方向相邻的两个组中的两个相邻子像素P的电压极性也是相反。。
承上，在本实施例的显示面板11的驱动方法中，是通过在相邻两帧的其中一帧时以第一栅极线、第二栅极线的顺序依序传送扫描信号至每一组的栅极线，而在相邻两帧的其中另一帧时，则是以第二栅极线、第一栅极线的顺序依序传送扫描信号至每一组的栅极线，使在相邻两帧的其中一帧时，数据线S1在栅极线G1和栅极线G3所连接的子像素P形成暗点，而在栅极线G2和栅极线G4所连接的子像素P形成亮点，更使在相邻两帧的其中另一帧时，数据线S1在栅极线G1和栅极线G3所连接的子像素P形成亮点，而在栅极线G2和栅极线G4所连接的子像素P形成暗点，因此，相邻两帧出现暗点的位置正好相反。由于常规显示中，是按60帧/每秒的速度在刷新显示画面，因此每一个子像素P都在以30Hz的频率进行亮暗切换，由于人眼的视觉暂留效应，并不会在如此短暂的时间区分开相邻两帧的画面，借此，使显示面板11的显示可更加均匀，可提升光学品味。
特别一提的是，本案发明并不限于奇数帧按照G1、G2、G3、G4…的顺序传送扫描信号至每一组的栅极线，而偶数帧按照G2、G1、G4、G3…的顺序驱动传送扫描信号至每一组的栅极线。当然，也可偶数帧时按照G1、G2、G3、G4…的顺序传送扫描信号至每一组的栅极线，而奇数帧按照G2、G1、G4、G3…的顺序驱动传送扫描信号至每一组的栅极线。
上述的驱动方法也可应用于不同连接方式的双栅极驱动架构的显示装置。请分别参照图4与图5所示，其分别为本申请不同实施态样的显示装置的显示面板与栅极线及数据线的连接示意图(灰色背景为子像素P的像素电压电不饱和的暗点位置)。
如图4所示，与图2A的连接方式主要的不同在于，在本实施例在第一组栅极线中，其第一栅极线(栅极线G1)分别连接第一行各组左侧(同一行的奇数)的子像素P，而第二栅极线(栅极线G2)分别连接第一行各组右侧(同一行的偶数)的子像素P；另外，在第二组栅极线中，第一栅极线(栅极线G3)分别连接第二行各组的右侧(同一行的偶数)子像素P，而第二栅极线(栅极线G4)分别连接第二行各组的左侧(同一行的奇数)子像素P；此外，在第三组栅极线中，第一栅极线(栅极线G5)分别连接第三行各组的左侧(同一行的奇数)子像素P，而第二栅极线(栅极线G6)分别连接第三行各组的右侧(同一行的偶数)子像素P，以此类推。
另外，如图5所示，与图2A的连接方式主要的不同在于，在本实施例在第一组栅极线中，其第一栅极线(栅极线G1)分别连接第一行各组的右侧(同一行的偶数)子像素P，而第二栅极线(栅极线G2)分别连接第一行各组的左侧(同一行的奇数)子像素P；另外，在第二组栅极线中，第一栅极线(栅极线G3)分别连接第二行各组的右侧(同一行的偶数)子像素P，而第二栅极线(栅极线G4)分别连接第二行各组的左侧(同一行的奇数)子像素P；此外，在第三组栅极线中，第一栅极线(栅极线G5)分别连接第三行各组的右侧(同一行的偶数)子像素P，而第二栅极线(栅极线G6)分别连接第三行各组的左侧(同一行的奇数)子像素P，以此类推。
此外，图4和图5的驱动方法可参照上述，于此不再多做说明。上述的 图2A、图4和图5的双栅极架构的连接方式只是举例，不可用以限制本申请。
综上所述，在本申请之显示装置及其驱动方法中，在相邻两帧的其中一帧时以第一栅极线、第二栅极线的顺序依序传送扫描信号至每一组的栅极线，而在相邻两帧的其中另一帧时，则是以第二栅极线、第一栅极线的顺序依序传送扫描信号至每一组的栅极线。借此，本申请的显示装置通过上述的驱动方式，可解决因双栅极架构所造成的亮暗线或网格的问题，使显示面板的显示更加均匀，提升其光学品味。
以上所述仅为举例性，而非为限制性者。任何未脱离本申请的精神与范畴，而对其进行的等效修改或变更，均应包括于权利要求书范围中。

Claims (20)

  1. 一种显示装置的驱动方法，所述显示装置包括一显示面板，所述显示面板包括多组栅极线、多条数据线和多组子像素，所述多组子像素分别和所述多组栅极线及所述多条数据线电性连接，每一所述组的所述栅极线分别驱动对应行的所述多组的所述子像素，每一所述组的所述栅极线分别依序具有一第一栅极线和一第二栅极线，所述第一栅极线分别电连接同一行所述多组的所述子像素的其中之一，所述第二栅极线分别电连接同一行所述多组的所述子像素的其中另一，所述驱动方法包括：
    在相邻两帧的其中一帧时，以所述第一栅极线、所述第二栅极线的顺序依序传送一扫描信号至每一所述组的所述栅极线，在所述相邻两帧的其中另一帧时，以所述第二栅极线、所述第一栅极线的顺序依序传送所述扫描信号至每一所述组的所述栅极线。
  2. 如权利要求1所述的驱动方法，其中，所述多条栅极线和所述多条数据线交错设置以定义出多个所述子像素的区域。
  3. 如权利要求1所述的驱动方法，其中，所述第一栅极线分别电连接同一行的奇数所述子像素，所述第二栅极线分别电连接同一行的偶数所述子像素。
  4. 如权利要求1所述的驱动方法，其中，所述第一栅极线分别电连接同一行的偶数所述子像素，所述第二栅极线分别电连接同一行的奇数所述子像素。
  5. 如权利要求1所述的驱动方法，其中，沿列方向相邻的两个所述子像素的电压极性为相反。
  6. 如权利要求1所述的驱动方法，其中，同一个所述组的两个所述子像素的电压极性为相同。
  7. 如权利要求1所述的驱动方法，其中，沿行方向相邻的两个所述组中的两个相邻子像素的电压极性为相反。
  8. 如权利要求1所述的驱动方法，其中，在所述相邻两帧时，是通过所述数据线以一点反转模式输出一数据信号驱动所述子像素。
  9. 如权利要求1所述的驱动方法，其中，每一所述组的所述子像素分别和同一条所述数据线电连接。
  10. 一种显示装置，包括：
    一显示面板，包括多组栅极线、多条数据线和多组子像素，所述多组子像素分别和所述多组栅极线及所述多条数据线电性连接，每一所述组的所述栅极线分别驱动对应行的所述多组的所述子像素，每一所述组的所述栅极线分别依序具有一第一栅极线和一第二栅极线，所述第一栅极线分别电连接同一行所述多组的所述子像素的其中之一，所述第二栅极线分别电连接同一行所述多组的所述子像素的其中另一；以及
    一驱动电路，通过所述多组栅极线输出一扫描信号驱动所述显示面板的所述多组的所述子像素；
    其中，在相邻两帧的其中一帧时，以所述第一栅极线、所述第二栅极线的顺序依序传送所述扫描信号至每一所述组的所述栅极线，且在所述相邻两帧的其中另一帧时，以所述第二栅极线、所述第一栅极线的顺序依序传送所述扫描信号至每一所述组的所述栅极线。
  11. 如权利要求10所述的显示装置，其中，所述多条栅极线和所述多条数据线交错设置以定义出多个所述子像素的区域。
  12. 如权利要求10所述的显示装置，其中，所述第一栅极线分别电连接同一行的奇数所述子像素，所述第二栅极线分别电连接同一行的偶数所述子像素。
  13. 如权利要求10所述的显示装置，其中，所述第一栅极线分别电连接同一行的偶数所述子像素，所述第二栅极线分别电连接同一行的奇数所述子像素。
  14. 如权利要求10所述的显示装置，其中，沿列方向相邻的两个所述子像素的电压极性为相反。
  15. 如权利要求10所述的显示装置，其中，同一个所述组的两个所述子像素的电压极性为相同。
  16. 如权利要求10所述的显示装置，其中，沿行方向相邻的两个所述组中的两个相邻子像素的电压极性为相反。
  17. 如权利要求10所述的显示装置，其中，在所述相邻两帧时，所述驱动电路更通过所述数据线以一点反转模式输出一数据信号驱动所述子像素。
  18. 如权利要求10所述的显示装置，其中，每一所述组的所述子像素分别和同一条所述数据线电连接。
  19. 如权利要求10所述的显示装置，其中，所述显示面板是双栅极驱动架构的液晶面板。
  20. 一种显示装置的驱动方法，所述显示装置包括一显示面板，所述显示面板包括多组栅极线、多条数据线和多组子像素，所述多组子像素分别和所述多组栅极线及所述多条数据线电性连接，每一所述组的所述栅极线分别驱动对应行的所述多组的所述子像素，每一所述组的所述栅极线分别依序具有一第一栅极线和一第二栅极线，所述第一栅极线分别电连接同一行所述多 组的所述子像素的其中之一，所述第二栅极线分别电连接同一行所述多组的所述子像素的其中另一，每一所述多组的所述子像素分别和同一条所述数据线电连接，所述驱动方法包括：
    在相邻两帧的其中一帧时，以所述第一栅极线、所述第二栅极线的顺序依序传送一扫描信号至每一所述组的所述栅极线，在所述相邻两帧的其中另一帧时，以所述第二栅极线、所述第一栅极线的顺序依序传送所述扫描信号至每一所述组的所述栅极线；
    其中，在所述相邻两帧时，是通过所述数据线以一点反转模式输出一数据信号驱动所述子像素，使沿列方向相邻的两个所述子像素的电压极性为相反，沿行方向相邻的两个所述组中的两个相邻子像素的电压极性为相反。
PCT/CN2020/123133 2020-08-19 2020-10-23 显示装置及其驱动方法 WO2022036847A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202010837291.5A CN111916034A (zh) 2020-08-19 2020-08-19 显示装置及其驱动方法
CN202010837291.5 2020-08-19

Publications (1)

Publication Number Publication Date
WO2022036847A1 true WO2022036847A1 (zh) 2022-02-24

Family

ID=73279116

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2020/123133 WO2022036847A1 (zh) 2020-08-19 2020-10-23 显示装置及其驱动方法

Country Status (2)

Country Link
CN (1) CN111916034A (zh)
WO (1) WO2022036847A1 (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113920919A (zh) * 2021-10-26 2022-01-11 深圳市华星光电半导体显示技术有限公司 显示面板

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101055708A (zh) * 2007-05-09 2007-10-17 友达光电股份有限公司 驱动方法
US20080224984A1 (en) * 2007-03-12 2008-09-18 Orise Technology Co., Ltd. Method for driving a display panel
CN101271658A (zh) * 2007-03-23 2008-09-24 旭曜科技股份有限公司 显示面板的驱动方法
US20110254818A1 (en) * 2010-04-19 2011-10-20 Chunghwa Picture Tubes, Ltd. Display
CN102881268A (zh) * 2012-09-07 2013-01-16 北京京东方光电科技有限公司 一种液晶显示器驱动方法及液晶显示器
CN103700358A (zh) * 2013-12-31 2014-04-02 合肥京东方光电科技有限公司 一种gip型液晶显示装置
CN103761944A (zh) * 2013-12-25 2014-04-30 合肥京东方光电科技有限公司 一种栅极驱动电路、显示装置及驱动方法
US20140198023A1 (en) * 2013-01-14 2014-07-17 Novatek Microelectronics Corp. Gate driver on array and method for driving gate lines of display panel
CN107689204A (zh) * 2017-10-12 2018-02-13 惠科股份有限公司 一种显示面板的驱动装置及驱动方法以及显示装置

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3504496B2 (ja) * 1998-05-11 2004-03-08 アルプス電気株式会社 液晶表示装置の駆動方法および駆動回路
JP5035671B2 (ja) * 2007-05-30 2012-09-26 奇美電子股▲ふん▼有限公司 表示装置の駆動装置および駆動方法
KR102028603B1 (ko) * 2012-10-29 2019-10-08 삼성디스플레이 주식회사 액정 표시장치 및 그의 구동방법
CN105319793B (zh) * 2015-11-26 2019-09-24 深圳市华星光电技术有限公司 具有数据线共享架构的阵列基板
CN105511184B (zh) * 2016-01-13 2019-04-02 深圳市华星光电技术有限公司 液晶显示面板及其驱动方法
CN106710555A (zh) * 2017-01-22 2017-05-24 京东方科技集团股份有限公司 显示面板、显示装置和显示装置的驱动方法
CN109283762B (zh) * 2018-11-09 2021-03-30 惠科股份有限公司 显示面板及其驱动方法
CN109872702B (zh) * 2019-04-22 2021-10-01 合肥京东方光电科技有限公司 液晶显示面板的显示驱动方法和液晶显示面板

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080224984A1 (en) * 2007-03-12 2008-09-18 Orise Technology Co., Ltd. Method for driving a display panel
CN101271658A (zh) * 2007-03-23 2008-09-24 旭曜科技股份有限公司 显示面板的驱动方法
CN101055708A (zh) * 2007-05-09 2007-10-17 友达光电股份有限公司 驱动方法
US20110254818A1 (en) * 2010-04-19 2011-10-20 Chunghwa Picture Tubes, Ltd. Display
CN102881268A (zh) * 2012-09-07 2013-01-16 北京京东方光电科技有限公司 一种液晶显示器驱动方法及液晶显示器
US20140198023A1 (en) * 2013-01-14 2014-07-17 Novatek Microelectronics Corp. Gate driver on array and method for driving gate lines of display panel
CN103761944A (zh) * 2013-12-25 2014-04-30 合肥京东方光电科技有限公司 一种栅极驱动电路、显示装置及驱动方法
CN103700358A (zh) * 2013-12-31 2014-04-02 合肥京东方光电科技有限公司 一种gip型液晶显示装置
CN107689204A (zh) * 2017-10-12 2018-02-13 惠科股份有限公司 一种显示面板的驱动装置及驱动方法以及显示装置

Also Published As

Publication number Publication date
CN111916034A (zh) 2020-11-10

Similar Documents

Publication Publication Date Title
WO2019134613A1 (zh) 显示装置
TWI485677B (zh) 液晶顯示器
US20180053478A1 (en) Liquid crystal display panel and driving method thereof
WO2019134614A1 (zh) 显示装置
WO2019134616A1 (zh) 显示装置
WO2018121302A1 (zh) 液晶显示器
WO2018120324A1 (zh) 像素结构、阵列基板及显示面板
WO2012124660A1 (ja) 表示装置、駆動装置、及び、駆動方法
WO2018040769A1 (zh) 阵列基板及显示面板、显示装置
WO2022116310A1 (zh) 显示面板及其驱动方法
US8456398B2 (en) Liquid crystal display module
KR20140020783A (ko) 화소 유닛, 화소 구조, 디스플레이 장치 및 화소 구동 방법
JP2008033312A (ja) 画像表示システムとその駆動方法
JP2007219469A (ja) マルチプレクサ、ディスプレイパネル及び電子装置
WO2020237760A1 (zh) 像素驱动电路及像素驱动方法
WO2022057027A1 (zh) 一种阵列基板及液晶显示面板
US11127362B2 (en) Driving method and device of display panel, and display apparatus
TW201312535A (zh) 雙閘極液晶顯示面板驅動結構及驅動方法
US20080150869A1 (en) Display panel and plane display device using the same
WO2022036847A1 (zh) 显示装置及其驱动方法
KR100898785B1 (ko) 액정표시장치
WO2019134612A1 (zh) 液晶显示装置及其驱动方法
KR102027170B1 (ko) 액정표시장치 및 그 구동방법
WO2022036846A1 (zh) 显示装置及其驱动方法
KR100469351B1 (ko) 액정표시장치의 구동방법

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 20950051

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 20950051

Country of ref document: EP

Kind code of ref document: A1