WO2022027325A1 - Générateur de nombres aléatoires reconfigurable et son procédé de mise en œuvre - Google Patents

Générateur de nombres aléatoires reconfigurable et son procédé de mise en œuvre Download PDF

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Publication number
WO2022027325A1
WO2022027325A1 PCT/CN2020/107140 CN2020107140W WO2022027325A1 WO 2022027325 A1 WO2022027325 A1 WO 2022027325A1 CN 2020107140 W CN2020107140 W CN 2020107140W WO 2022027325 A1 WO2022027325 A1 WO 2022027325A1
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ring oscillator
random number
inverter
output
ring
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PCT/CN2020/107140
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English (en)
Chinese (zh)
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曹元�
陈帅
张睿
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武汉飞思灵微电子技术有限公司
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Priority to PCT/CN2020/107140 priority Critical patent/WO2022027325A1/fr
Priority to CN202080080465.6A priority patent/CN114902174A/zh
Publication of WO2022027325A1 publication Critical patent/WO2022027325A1/fr

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/58—Random or pseudo-random number generators

Definitions

  • the invention relates to the technical field of random number generators, in particular to a reconfigurable random number generator and an implementation method thereof.
  • Random numbers are widely used in cryptography, Monte Carlo simulation, spread spectrum communication, statistical research, artificial intelligence, neural network and other engineering technology and scientific research fields.
  • the random number (key) used is completely random, and the length of the information to be encrypted is consistent and used once, the entire system will be absolutely secure. , unbreakable. Therefore, how to generate safe and reliable random numbers is of great significance to the entire cryptographic system, and thus to my country's national defense security, financial development, social stability and personal privacy.
  • true random number generators can be divided into four categories according to different entropy sources: 1. Based on environmental noise; 2. Based on chaos model; 3. Based on clock jitter; 4. Based on True random number generator for metastable circuits.
  • thermal noise is a good source of random entropy because its spectral distribution is relatively uniform and does not vary with the CMOS process. In early integrated circuits, this method was mostly used to extract random numbers. However, thermal noise is difficult to obtain, and an ultra-wide bandwidth, high-gain amplifier is usually required to amplify the noise, which is difficult to quantify.
  • the second type of chaotic system equations based on deterministic descriptions generate random numbers.
  • the third type is to use the jitter of the Ring Oscillator (Ring Oscillator, abbreviated as: RO) to generate true random numbers.
  • Ring Oscillator abbreviated as: RO
  • the advantage of this method is that it can be implemented on FPGA or ASIC conveniently and flexibly.
  • the principle is to use a clock with a slow jitter frequency to sample a fast jitter clock.
  • the fourth type is that the resource consumption and power consumption of the broadband amplifier are large.
  • a latch or static random access memory (SRAM) in metastable state can also be used to generate true random numbers, however, a true random generator for this entropy source generally requires a complex post-processing unit.
  • the random number generator As a widely used random number generator in the industry, although the random number generator based on ring oscillator has the advantages of easy implementation and small area, the mechanism is susceptible to process variations, temperature and voltage variations (process variations, voltage, thermal, Abbreviated as: PVT), which causes the random number output to be biased and affects the entropy value.
  • PVT process variations, voltage, thermal, Abbreviated as: PVT
  • the technical problem to be solved by the embodiments of the present invention is that although the random number generator based on the ring oscillator in the prior art has the advantages of easy implementation and small area, the mechanism is easily affected by process differences, temperature and voltage changes, resulting in The random number output is biased, affecting the entropy value.
  • the present invention provides a reconfigurable random number generator, comprising at least two ring oscillators, a sampling circuit, a counter and a logic control unit, specifically:
  • the ring oscillator includes n inverter groups, each inverter group is composed of at least two inverters arranged in parallel, and two selectors respectively arranged on the input side and the output side of the inverters ; where n is a natural number;
  • the control terminal of the corresponding selector in each inverter group is electrically connected with the logic control unit, and is used for receiving the reconstruction signal of the logic control unit and completing the specified inverter in each inverter group and its two
  • the selector on the side completes the conduction of the electrical signal channel;
  • the output terminals of the at least two ring oscillators are coupled to the input terminals of the counter; the output terminals of the counter are connected to the logic control unit; the sampling circuit obtains samples from the at least two ring oscillators an electrical signal, so as to output a random number according to the sampled electrical signal.
  • the logic control unit obtains the difference between the oscillation frequencies of the at least two ring oscillators through the counter, and is used to send a reconstruction signal to each selector in the ring oscillator, so as to adjust the frequency difference in the inverter group by adjusting
  • the selected inverters are passed through to complete the oscillation frequency difference between the ring oscillators is less than a preset threshold.
  • the output ends of the at least two ring oscillators are coupled to the input end of the counter, which specifically includes:
  • the output ends of the at least two ring oscillators are respectively connected to different input ports of the counter, so that the counter can complete the counting corresponding to the oscillation frequencies of different ring oscillators; or,
  • the output terminals of the at least two ring oscillators are connected to at least two input terminals of a count selector, and the output terminals of the count selector are connected to the input terminals of the counter, so that the logic control unit controls all the
  • the corresponding relationship between the input terminal and the output terminal that the counting selector is turned on is used to realize the counting of the oscillation frequency of the ring oscillator in sequence.
  • the ring oscillator further includes a NAND gate, and the inverter groups in the ring oscillator are cascaded, specifically:
  • the first input end of the NAND gate is connected with the enable signal; the second input end of the NAND gate is connected with the output port of the inverter group at the end of the cascade connection; the output of the NAND gate The terminal is used to connect the input port of the inverter group at the head of the cascade.
  • a random number source is formed by a first ring oscillator and a second ring oscillator in the random number generator, and the sampling circuit is formed by n D flip-flops, specifically:
  • each inverter group in the first ring oscillator is also respectively connected with the signal input port of a D flip-flop;
  • each inverter group in the second ring oscillator is also respectively connected with the clock input port of a D flip-flop;
  • the electrical signals of the output ports of the n D flip-flops in the sampling circuit form a random number.
  • the ring oscillator further includes m ordinary inverters, specifically:
  • the m ordinary inverters and the n inverter groups are cascaded according to a preset arrangement sequence
  • the preset sorting order includes:
  • the m ordinary inverters are cascaded, and the n inverter groups are cascaded; the m ordinary inverters after the cascade and the n inverters after the cascade to complete the cascade between; or,
  • the cascading is performed in a manner that the common inverters and the inverter groups are spaced apart from each other, wherein the distances spaced from each other are determined according to the proportional relationship between the m common inverters and the n inverter groups; or,
  • a random number source is composed of a third ring oscillator and a fourth ring oscillator in the random number generator, and the sampling circuit is composed of p D flip-flops, wherein n ⁇ p ⁇ m+n ,specific:
  • the output terminals of the specified inverter and/or the inverter group in the third ring oscillator are also respectively connected with the signal input ports of a D flip-flop;
  • the specified inverter group and/or the output terminals of the inverters are respectively connected with the clock input port of a D flip-flop;
  • the electrical signals of the output ports of the n D flip-flops in the sampling circuit form a random number.
  • the logic control unit is further configured to acquire excitation signals of one or more ring oscillators, specifically:
  • the logic control unit converts the excitation signal into a reconstructed signal corresponding to one or more ring oscillators
  • the logic control unit acquires the output oscillation frequency of one or more ring oscillators triggered by the excitation signal, and calculates a physically unclonable output result according to the corresponding oscillation frequency or the difference between the oscillation frequencies.
  • the excitation signal of the ring oscillator is specifically the output of a specified inverter group in the ring oscillator as a data source for calculating a physically unclonable output result.
  • the physical unclonable output result is calculated and obtained according to the corresponding oscillation frequency or the difference between the oscillation frequencies, which specifically includes:
  • the inverter is specifically one or more of a TTL NOT gate inverter, a CMOS inverter, a HPM disturbance effect inverter or a starvation inverter.
  • the at least two ring oscillators include a first ring oscillator, a second ring oscillator and a third ring oscillator
  • the first ring oscillator and the second ring oscillator form a random number source
  • the second ring oscillator and the third ring oscillator form a random number source
  • the first ring oscillator and the third ring oscillator constitute a random number source, and the second ring oscillator and the third ring oscillator constitute a random number source; or,
  • the first ring oscillator and the second ring oscillator constitute a random number source
  • the first ring oscillator and the third ring oscillator constitute a random number source
  • the present invention provides a method for implementing a reconfigurable random number generator, using the reconfigurable random number generator described in the first aspect, and the implementation method includes:
  • the logic control unit obtains the oscillation frequencies of the at least two ring oscillators through the counter;
  • the logic control unit determines the first ring oscillator and the second ring oscillator as a random number source, and analyzes the oscillation frequency difference of the first ring oscillator and the second ring oscillator;
  • the logic control unit sends a reconstruction signal to the first ring oscillator and/or the second ring oscillator, so as to control the first ring oscillator and the second ring oscillator
  • the selector in the oscillator completes the turn-on operation of the specified inverter signal channel in the corresponding inverter group;
  • the difference between the oscillation frequencies of the first ring oscillator and the second ring oscillator is less than a preset threshold.
  • the adjustment of the reconstructed signal by the logic control unit one or more times, so that the difference between the oscillation frequencies of the first ring oscillator and the second ring oscillator is less than a preset threshold specifically includes:
  • each time the reconstruction signal is adjusted if the difference between the oscillation frequencies of the first ring oscillator and the second ring oscillator can be reduced, the reconstruction signal at this time is retained as the reconstruction signal of the current state.
  • the oscillating frequency difference corresponding to the reconstructed signal in the current state is used to compare with the oscillating frequency difference under the next adjusted reconstructed signal, and the reconstructed signal with the smaller oscillating frequency difference is updated as the The reconstructed signal of the current state;
  • the traversing process is stopped until the difference between the oscillation frequencies of the first ring oscillator and the second ring oscillator is smaller than a preset threshold.
  • the method further includes:
  • the logic control unit After completing the adjustment of the reconstructed signal by the logic control unit one or more times, so that the difference between the oscillation frequencies of the first ring oscillator and the second ring oscillator is less than the preset threshold, the logic control unit will pass one or more times of logic The control unit adjusts the reconstruction signal of the third ring oscillator so that the difference between the oscillation frequencies of the first ring oscillator and the third ring oscillator is smaller than a preset threshold.
  • the reconfigurable ring oscillator proposed by the present invention can realize the calculation of the oscillation frequency difference between the output signals of different ring oscillators through the counter, and transmit it to the logic control unit as the result, and is controlled by the logic
  • the unit is used to further adjust the inverter group in the associated ring oscillator, so as to obtain the ring oscillator output that meets the conditions.
  • a solution for realizing a physically unclonable output result based on the reconfigurable ring oscillator is also proposed, and the implementation of the solution still relies on the present invention.
  • the core innovation point is the structure of the inverter group and the reconfiguration control of each inverter group in the ring oscillator by the logic control unit.
  • the reconfigurable function of each inverter group can keep the difference between the oscillation frequencies of the output data of the at least two ring oscillators for outputting random numbers within a preset threshold, thereby reducing the generation of random sequences
  • the bias of the circuit improves the adaptability to the environment, so that the circuit has the best performance in terms of power consumption, area, and efficiency of generating random numbers.
  • FIG. 1 is a schematic structural diagram of a reconfigurable random number generator provided by an embodiment of the present invention
  • FIG. 2 is a schematic structural diagram of an inverter group in a reconfigurable random number generator provided by an embodiment of the present invention
  • Fig. 3 is the structure schematic diagram of inverter group working state in a kind of reconfigurable random number generator provided by the embodiment of the present invention
  • FIG. 4 is a schematic structural diagram of a working state of an inverter group in a reconfigurable random number generator provided by an embodiment of the present invention
  • FIG. 5 is a schematic structural diagram of another reconfigurable random number generator provided by an embodiment of the present invention.
  • FIG. 6 is a schematic structural diagram of another reconfigurable random number generator provided by an embodiment of the present invention.
  • FIG. 7 is a schematic structural diagram of a ring oscillator provided by an embodiment of the present invention.
  • FIG. 8 is a schematic structural diagram of another ring oscillator provided by an embodiment of the present invention.
  • FIG. 9 is a schematic structural diagram of another reconfigurable random number generator provided by an embodiment of the present invention.
  • FIG. 10 is a schematic structural diagram of another reconfigurable random number generator provided by an embodiment of the present invention.
  • FIG. 11 is a schematic flowchart of a method for implementing a reconfigurable random number generator according to an embodiment of the present invention
  • FIG. 12 is a schematic flowchart of a method for implementing a reconfigurable random number generator provided by an embodiment of the present invention
  • FIG. 13 is a schematic flowchart of a method for implementing a reconfigurable random number generator according to an embodiment of the present invention
  • FIG. 14 is a schematic structural diagram of a specific reconfigurable random number generator provided by an embodiment of the present invention.
  • 15 is a schematic structural diagram of a current starved inverter provided by an embodiment of the present invention.
  • 16 is a structural diagram of a D flip-flop provided by an embodiment of the present invention.
  • 17 is a timing diagram of a D flip-flop provided by an embodiment of the present invention.
  • FIG. 18 is a schematic flowchart of completing the reconstructed signal locking according to an embodiment of the present invention.
  • Embodiment 1 is a diagrammatic representation of Embodiment 1:
  • Embodiment 1 of the present invention provides a reconfigurable random number generator, as shown in FIG. 1 , including at least two ring oscillators (in FIG. 1 , the first ring oscillator to the yth ring oscillator are exemplified),
  • the sampling circuit, the counter and the logic control unit are described as at least two ring oscillators because in the specific implementation of the present invention, two ring oscillators are the minimum configuration requirements for forming a random number output,
  • the reconfigurable random number generator proposed in the embodiment of the present invention needs to output two or more random numbers at the same time in an actual application scenario, in this case, the corresponding ring oscillator will More than two or even more ring oscillators need to be configured.
  • the more ring oscillators are configured, the more random numbers that can be generated concurrently.
  • the reconfigurable random number generator includes:
  • the ring oscillator includes n inverter groups, as shown in FIG. 2 , each inverter group consists of at least two inverters arranged in parallel, and are respectively arranged on the input side of the inverters (ie, FIG. 2 ). 2) and two selectors on the output side (ie, the right side of the parallel inverters shown in FIG. 2); where n is a natural number.
  • the n has a certain correlation with the number of random numbers to be actually generated. Generally, the more the number of random numbers, the larger the corresponding value of n will be.
  • the description of the parallel-arranged inverters refers to the technical meaning that the selectors arranged on both sides of the inverters can be used to selectively perform electrical signals on at least two parallel-arranged inverters.
  • the function of channel conduction, in an inverter group, relative to the inverter with electrical signal conduction, other inverters will be in the state of electrical signal channel blocking, because they are located before and after the corresponding inverter.
  • the selector does not specify that the interface to which it is connected is turned on.
  • the control terminal of the corresponding selector in each inverter group is electrically connected with the logic control unit, and is used for receiving the reconstruction signal of the logic control unit and completing the specified inverter in each inverter group and its two
  • the selector on the side completes the conduction of the electrical signal channel.
  • the selector is controlled, and the inverter labeled 1 is selected to enter the conduction state of the electrical channel, while the other inverters labeled 2 to x are in the electrical channel blocking state.
  • the output terminals of the at least two ring oscillators are coupled to the input terminals of the counter; the output terminals of the counter are connected to the logic control unit; the sampling circuit obtains samples from the at least two ring oscillators an electrical signal, so as to output a random number according to the sampled electrical signal.
  • the reconfigurable ring oscillator proposed by the embodiment of the present invention can realize the calculation of the oscillation frequency difference between the output signals of different ring oscillators through a counter, and transmit it to the logic control unit as the result, and based on the above
  • the logic control unit further adjusts the inverter group in the associated ring oscillator (which can be understood as a control signal for outputting a random number), so as to obtain a ring oscillator output that meets the conditions.
  • the reconfigurable function of each inverter group can keep the difference between the oscillation frequencies of the output data of the at least two ring oscillators for outputting random numbers within a preset threshold, thereby reducing the generation of The bias of the random sequence improves the adaptability to the environment, so that the circuit has the best performance in terms of power consumption, area, and efficiency of generating random numbers.
  • the logic control unit acquires the difference between the oscillation frequencies of the at least two ring oscillators through the counter, and is used to send a reconstruction signal (the value of the reconstruction signal) to each selector in the ring oscillator.
  • the function is to select the strobe of the parallel inverters configured in each inverter group.
  • the reconstructed signal sent to each inverter group should be greater than 1bit), so that the oscillation frequency difference between ring oscillators can be completed by adjusting the selected inverters in the inverter group to be less than the preset threshold or the minimum value in the range.
  • the preset threshold here is an empirical value, which can be verified by testing the repeatability of random numbers.
  • the oscillation frequency difference obtained when the repeatability of random numbers meets the specified requirements can be set as the preset threshold. parameter value. Specifically, it can be verified in the early stage that the random number generated by the frequency difference between the two inverters can pass the random number standard test (for example, the NIST random number test standard).
  • the output terminals of the at least two ring oscillators can be coupled with the input terminals of the counter in various ways.
  • the counter itself includes a plurality of counting input ports, similar to In the connection structure relationship shown in FIG. 1, the counter can count the output oscillation frequencies of at least two ring oscillators at the same time, then the output ends of the at least two ring oscillators are respectively connected to different input ports of the counter, so that the The counters complete the counting of the oscillation frequencies corresponding to different ring oscillators; in practical applications, the number of counters has no direct correspondence with the output of the random number to be generated, and a counter can be provided for each output of the random number (as shown in Figure 1).
  • the output terminals of the at least two ring oscillators are connected to at least two input terminals of a count selector, and the output terminals of the count selector are connected to the input terminals of the counter, so that the logic control unit controls all the
  • the corresponding relationship between the input terminal and the output terminal that the counting selector is turned on is used to realize the counting of the oscillation frequency of the ring oscillator in sequence.
  • a NAND gate is usually set on the input port side of the ring oscillator, and the inverting phase in the ring oscillator is The cascade mode is formed between the device groups, specifically:
  • the first input terminal of the NAND gate is connected with the enable signal; the second input terminal of the NAND gate is connected to the inverter group at the end of the cascade (for example, the rightmost inverter in FIG. 5 )
  • the output port of the NAND gate is used to connect to the input port of the inverter group located in the cascade header (for example, the leftmost inverter group in FIG. 5 ).
  • a random number source is formed by a first ring oscillator and a second ring oscillator in the random number generator, and the sampling circuit is formed by n D flip-flops, as shown in FIG. 6 . ,specific:
  • each inverter group in the first ring oscillator is also respectively connected with the signal input port of a D flip-flop; in the second ring oscillator, the output ends of each inverter group are also respectively connected with a D flip-flop
  • the clock input ports of the n D flip-flops are connected to each other; the electrical signals of the output ports of the n D flip-flops in the sampling circuit form a random number.
  • the ring oscillator in addition to the cascaded implementation of a single inverter group similar to that illustrated in FIG. 1 , FIG. 5 and FIG.
  • the ring oscillator also includes m ordinary inverters (that is, in FIG. 8 and FIG. 7, the ordinary inverters that are cascaded with the above-mentioned inverter group), specifically of:
  • the m ordinary inverters and the n inverter groups are cascaded according to a preset arrangement sequence
  • the preset sorting order includes:
  • Mode 1 As shown in FIG. 7 , the m ordinary inverters are cascaded, and the n inverter groups are cascaded; the m ordinary inverters after the cascade are connected to the The cascade is completed between the n inverters after the cascade.
  • Mode 2 cascade the common inverters and inverter groups in a way that they are spaced apart from each other, wherein the distances spaced from each other are based on the m common inverters and n inverter groups.
  • the proportional relationship between them is determined. It should be noted here that both m and n here are natural numbers, and the values of n here and n corresponding to Figure 5 can be adjusted according to the needs of their respective application scenarios, which do not necessarily mean that the two are in their respective scenarios. The value below needs to be consistent between the two.
  • Mode 3 Between the m ordinary inverters and the n inverter groups, the cascading of the ordinary inverters and the inverter groups is completed in a random order.
  • the three-phase comparison method of method 2 forms a structure by cascading the regular expressions of each other at intervals.
  • Method 3 emphasizes that the settings are not set according to the specified rules. From a certain realization possibility, method 3 can bring more possibilities. , it can be understood that the uncertainty in the process of processing is further weakened by the random sorting method, so that it is possible to find a ring oscillator whose oscillation frequency characteristics exceed the regular mutual interval setting in the later testing process. .
  • the random ordering here is relative to the design circuit, and for the completed reconfigurable random number generator, the arrangement relationship between the inverter group in the corresponding ring oscillator and the ordinary inverter is a kind of The relationship is confirmed.
  • the random number generator is composed of a third ring oscillator and a fourth ring oscillator. a random number source, the random number generator further includes a sampling circuit, wherein the sampling circuit is composed of p D flip-flops, where n ⁇ p ⁇ m+n, as shown in FIG. 9, specifically:
  • the outputs of the specified inverters and/or inverter groups in the third ring oscillator are also respectively connected to the signal input ports of a D flip-flop; the inverter groups and/or inverter groups are specified in the fourth ring oscillator.
  • the output ends of the phaser are also respectively connected with the clock input ports of a D flip-flop; the electrical signals of the output ports of the n D flip-flops in the sampling circuit form a random number.
  • n refer to the structure shown in FIG. 10 .
  • the structures similar to those shown in Fig. 9 and Fig. 10 are only feasible solutions to present the key difference structures through the most concise diagrams.
  • the structures similar to those shown in Figs. 9 and 10 can be added to the above-mentioned expansion solutions.
  • a NAND gate is added to complete the enable signal control, and an extended implementation scheme of a single-input port counter similar to that shown in FIG. 5 can also be used.
  • An organic combination can be performed in each implementation scheme of the present invention, which will not be repeated here.
  • PAFs Physical Unclonable Functions
  • the present invention can further multiplex the above-mentioned reconfigurable random number generator into a physical unclonable function, realize circuit multiplexing, and save resources; the present invention can reconfigure the ring oscillator to adjust the two ring oscillators The relative frequency of , removes deterministic noise (such as manufacturing variance) or inherent bias caused by PVT, thereby ensuring the randomness of the output random number.
  • the reconfigurable random number generator proposed by the embodiment of the present invention is further multiplexed into a physical unclonable function, specifically:
  • the logic control unit is also used to obtain excitation signals of one or more ring oscillators (for example: directly input the excitation signals of one or more ring oscillators to the logic control unit through the host computer; the excitation signals may represent For the selection of the working output of the specified reflector group in each ring oscillator, the combination form of the reflector group working in the ring oscillator can be dynamically changed by adjusting the excitation signal, so that the ring oscillator can meet the requirements of a specific environment. ), the logic control unit converts the excitation signal into a reconstructed signal corresponding to one or more ring oscillators;
  • the logic control unit acquires the output oscillation frequency of one or more ring oscillators triggered by the excitation signal, and calculates a physically unclonable output result according to the corresponding oscillation frequency or the difference between the oscillation frequencies.
  • the physical unclonable output result is calculated and obtained according to the corresponding oscillation frequency or the difference between the oscillation frequencies, specifically including:
  • the method process integrates the true random number mode and the physical unclonable mode, and the working mode can be selected between the two in the specific method implementation process.
  • the corresponding method process includes:
  • step 101 the logic control unit performs frequency statistics on at least two ring oscillators through the counter to obtain a frequency difference.
  • the logic control unit performs frequency statistics on at least two ring oscillators through the counter to obtain a frequency difference.
  • step 102 if it is a true random number mode, then go to step 102 , if it is a physical unclonable mode, go to step 104 .
  • step 102 by adjusting the reconstructed signal one or more times by the logic control unit, different inverters are gated, so that the difference between the oscillation frequencies of the first ring oscillator and the second ring oscillator is less than a preset value threshold.
  • step 103 the oscillator jitter caused by the phase noise of the two ring oscillators is sampled, and a random number is generated.
  • step 104 the logic control unit adjusts the reconstructed signal multiple times, selects different inverters, and obtains the oscillation frequency or the frequency difference of the ring oscillator each time.
  • step 105 a physical unclonable output result is calculated according to the corresponding oscillation frequency or the difference between the oscillation frequencies.
  • An embodiment of the present invention proposes a method for implementing a reconfigurable random number generator, using the reconfigurable random number generator described in Embodiment 1, as shown in FIG. 12 , the implementation method includes:
  • step 201 the logic control unit acquires the oscillation frequencies of the at least two ring oscillators through the counter.
  • step 202 the logic control unit determines the first ring oscillator and the second ring oscillator as a random number source, and analyzes the oscillation frequency difference of the first ring oscillator and the second ring oscillator.
  • step 203 if the oscillation frequency is greater than a preset threshold, the logic control unit sends a reconstruction signal to the first ring oscillator and/or the second ring oscillator, so as to control the first ring oscillator
  • the selector and the selector in the second ring oscillator complete the turn-on operation of the signal channel of the designated inverter in the corresponding inverter group.
  • step 204 the reconstructed signal is adjusted one or more times by the logic control unit, so that the difference between the oscillation frequencies of the first ring oscillator and the second ring oscillator is smaller than a preset threshold.
  • the method for realizing the reconfigurable ring oscillator proposed by the embodiment of the present invention can realize the calculation of the oscillation frequency difference between the output signals of different ring oscillators through the counter, and transmit the difference to the logic control unit as the result, and based on the The logic control unit further adjusts the inverter group in the associated ring oscillator, so as to obtain the ring oscillator output that meets the conditions.
  • the difference between the oscillation frequencies of the first ring oscillator and the second ring oscillator is less than a preset threshold, as shown in the figure. 12, including:
  • step 2041 by adjusting the reconstructed signal multiple times, the traversal of the selection control of the inverters for conducting electrical signals in each inverter group is completed one by one.
  • step 2042 each time the reconstructed signal is adjusted, if the difference between the oscillation frequencies of the first ring oscillator and the second ring oscillator can be reduced, the reconstructed signal at this time is kept as the current state.
  • the reconstructed signal, the oscillation frequency difference corresponding to the reconstructed signal in the current state is used to compare with the oscillation frequency difference under the reconstructed signal after the next adjustment, and the reconstructed signal with the smaller oscillation frequency difference is updated is the reconstructed signal of the current state.
  • step 2043 the traversal process is stopped until the difference between the oscillation frequencies of the first ring oscillator and the second ring oscillator is less than a preset threshold.
  • Embodiment 1 and Embodiment 2 will further combine an example situation in the specific implementation process, and describe the process details of the implementation of the complete solution with the corresponding drawings.
  • a current starved inverter is further used to form a corresponding inverter group, thereby further improving the performance.
  • the circuit structure of this configurable random number generator is shown in Figure 14. It mainly includes two ring oscillators (ring oscillator RO1 and ring oscillator RO2), a counter, a group of D flip-flops, and a parallel-to-serial interface circuit (it can be seen that in the implementation scheme of Embodiment 1, the The parallel-to-serial interface circuit is not directly introduced, because, as an optional implementation solution, the parallel-to-serial interface circuit does not necessarily need to be integrated and implemented by the technical solutions of the embodiments of the present invention. It is realized by combining with peripheral circuits), and a group of control logic (C 0 ⁇ C 2n-1 , EN).
  • the control logic is responsible for switching the operating mode of the ring oscillator.
  • the reconfigurable random number generator in the embodiment of the present invention has two working modes: a random number generator mode and a physical unclonable function mode.
  • the two ring oscillators RO1 and RO2 are each composed of a NAND gate (NAND1, NAND2) and n inverter groups (IVs0 ⁇ IVsn-1, IVsn ⁇ IVs2n-1); each The inverter group is composed of a multiplexer (the one-of-two selector is taken as an example in the figure, which can be any multiplexer) and a current- starved inverter .
  • n D triggers
  • the generators (D 0 ⁇ D n-1 ) form a sampling circuit, which samples the oscillator jitter caused by the phase noise of the two ring oscillators to generate random numbers;
  • the count selection circuit is used in the random number generator mode to detect the ring oscillators
  • the working state is used to generate the output of the physical unclonable function in the physical unclonable function mode;
  • the logic control unit is used to configure the working state of the circuit (random number mode or physical unclonable function mode), and according to the output of the counting circuit, by reconstructing the signal (C 0 to C 2n-1 ) reconstruct the ring oscillator.
  • the two reconfigurable current-starved ring oscillators can be used as high-entropy random number generators or physically unclonable functions.
  • the parallel-to-serial interface output circuit is used to serially output the random numbers generated by the random number generator.
  • the jitter noises of the two current-starved ring oscillators operating in the subthreshold range are sampled from each other to generate high-entropy random numbers.
  • the current-starved ring oscillator works in the sub-threshold region, the noise of each stage of the current-starved ring oscillator will be larger, and the random number entropy value will be higher; in addition, working in the sub-threshold region can facilitate the control of the inverter. Therefore, the charging and discharging time of the inverter is controlled, the purpose of controlling the frequency of the ring oscillator is achieved, and the power consumption of the ring oscillator is controlled and reduced at the same time.
  • the sub-threshold region ring oscillator can reconstruct the inverter group (IVs 0 ⁇ IVs n-1 , IVs n ⁇ IVs 2n-1 ) by reconstructing the signals C 0 ⁇ C 2n -1 , so as to select Different current-starved inverters form an oscillator, which in turn adjusts the oscillation frequencies f RO1 and f RO2 of the ring oscillator.
  • the frequencies f RO1 and f RO2 of the two groups of ring oscillators are calculated by the bidirectional counter to calculate the frequency difference; the logic processing control circuit analyzes the frequency difference, and if the frequency difference does not meet the preset threshold, the reconstructed signals C 0 ⁇ C 2n- 1 to adjust the output frequency of the ring oscillator; when the frequency count difference between f RO1 and f RO2 is less than the preset threshold, the reconstruction signal is fixed; after that, each stage of the two groups of ring oscillators is reconstructed to the inverter
  • the output of the D flip-flop (D 0 ⁇ D n-1 ) is used as the data signal and clock signal to complete the sampling; using the oscillator jitter caused by the phase noise, the D flip-flop (D 0 ⁇ D n-1 ) will Continuously output random numbers in parallel; and then output a serial true random number bit stream through a parallel-to-serial interface circuit.
  • C 0 ⁇ C 2n-1 When working in the physical unclonable function mode, C 0 ⁇ C 2n-1 will be used as the excitation of the physical unclonable function; due to the random deviation generated in the manufacturing process of the integrated circuit, the output terminals of the two cascaded oscillators are extracted by the counter. Oscillation frequency difference; then the output of the physical unclonable function is obtained; by changing the excitation C 0 ⁇ C 2n-1 in the exponential space, the physical unclonable function generates a unique response based on a certain excitation C 0 ⁇ C 2n-1 .
  • the random number generator is an indispensable and important part of the existing information security system.
  • the physical unclonable function is used for security authentication or key generation, and is used to replace the existing key storage and security authentication mechanism based on volatile memory. It can effectively resist various physical attacks such as intrusive attacks.
  • the invention can configure the same circuit as a random number generator or a physical unclonable function, realizes circuit multiplexing and saves resources; the invention can reconstruct the ring oscillator to adjust the relative frequencies of the two ring oscillators, Remove deterministic noise (such as manufacturing differences) or inherent bias caused by PVT, thereby ensuring the randomness of output random numbers; the embodiment of the present invention uses a current starvation inverter to construct a random number generator, which has a better energy efficiency ratio; In the embodiment of the present invention, the current starved inverter is operated in a zero temperature state (Zero-TC), thereby further reducing the influence of temperature.
  • Zero-TC zero temperature state
  • the parallel-to-serial interface circuit includes n D flip-flops and (n-1) data selectors MUX;
  • the clock control terminals CLK of the N D flip-flops are connected to the clock signal Nf0, and the data selection control terminals of the (N-1) data selectors MUX are connected to the clock signal f0;
  • the input terminal D of the first D flip-flop is connected to the parallel input signal P0, the output terminal Q is connected to an input terminal of the first data selector MUX, and the output terminal of the first data selector is connected to the input of the second D flip-flop.
  • Terminal D the output terminal of the second D flip-flop is connected to an input terminal of the second data selector, and so on, the output terminal of the (N-1)th D flip-flop is connected to the (N-1)th data
  • the parallel output signals P1, P2...PN are sequentially connected to the other input terminals of the (N-1) data selectors MUX.
  • the inverter shown in FIG. 15 By adjusting the inverter shown in FIG. 15 to be a current starved inverter used in the embodiment of the present invention, it includes two PMOS devices M1 and M2 and two NMOS devices M3 and M4; the source of M1 is connected to a high power supply Voltage V dd ; the drain of M1 is connected to the source of M2, the drain of M2 is connected to the drain of M3, the source of M3 is connected to the drain of M4, and the source of M4 is grounded; the gate of M1 is connected to the bias voltage V p , the gate of M4 is connected to the bias voltage V n ; the gates of M2 and M3 are input terminals V i , and the drains of M2 and M3 are output terminals V o .
  • the bias voltages V P and V n make the inverter work in a zero temperature state (Zero-Tc), so that the random number generator is not easily affected by temperature.
  • the model principle is that the frequency of the ring oscillators RO1 and RO2 is determined by the delay of each stage of the inverter:
  • C 0 is the total circuit load
  • V dd is the power supply voltage
  • ⁇ is the inverter circuit constant
  • ID is the saturation current
  • the channel length W, the channel width L, the gate-source voltage V GS , the gate capacitance C OX , the threshold voltage V t , and the carrier mobility ⁇ are the channel length, the channel width, the gate - source voltage, gate capacitance, threshold voltage and carrier mobility; further, the temperature coefficient of the switching current of the saturation current at temperature T is:
  • bias voltages V P and V n need to follow the following principles: that is, on the premise that the circuit can switch normally, make V GS as much as possible small.
  • FIG. 16 it is a schematic structural diagram of a D flip-flop (D 0 to Dn-1 ) provided by an embodiment of the present invention.
  • the D flip-flop includes two AND gates (AND_1, AND_2), two OR gates (AND_1, AND_2). NOT gate (NOR_1, NOR_2), 1 inverter (inverter), 1 capacitor C and 1 resistor R.
  • the clock control signal CLK is input to an input end of the AND gate AND_1 and an input end of the AND gate AND_2 respectively through the capacitor C.
  • a resistor R is connected to the connection between the capacitor C and the AND gate AND_1 and the AND gate AND_2, and the other end of the resistor R ground;
  • the input terminal of the inverter inverter is connected to the input signal D, and the output terminal is connected to the AND gate AND_1; the input terminal of the AND gate AND_1 is respectively connected to the output terminal of the inverter inverter and an input terminal of the AND gate AND_2; the input terminals of the AND gate AND_2 are respectively The input signal D and the AND gate AND_1 are connected, and the output terminal is connected to an input terminal of the NOR gate NOR_2; the input terminal of the NOR gate NOR_1 is respectively connected to the output terminal of the NOR gate NOR_2 of the output terminal of the AND gate AND_1, and the output terminal is connected to the NOR gate.
  • An input terminal of NOR_2 simultaneously outputs the output signal Q of the D flip-flop; the input terminal of the NOR gate NOR_2 is respectively connected to the output terminal of the NOR gate NOR_1 of the output terminal of the AND gate AND_2, and the output terminal is connected to an input terminal of the NOR gate NOR_1 , while outputting the output signal of the D flip-flop
  • the timing diagram when the D flip-flop generates a random signal is shown in Figure 17.
  • the trigger signal and clock control signal with similar frequencies are generated by two oscillators and input to the D and CLK terminals. Due to the deviation caused by jitter noise, the signals on CLK and D are not completely corresponding.
  • the rising edge of CLK corresponds to the high level on D
  • output 1 the falling edge of CLK corresponds to the low level on D
  • the rising edge of the next clock cycle corresponds to The low level on D outputs 0.
  • the frequencies of the two ring oscillators need to be as close as possible to generate enough frequency jitter to generate random numbers with high entropy.
  • the flowchart of the control logic unit searching for the optimal reconstruction signal C 0 -C 2n-1 is shown in FIG. 18 .
  • N1 is the count value of the oscillation frequency of the ring oscillator R01
  • N2 is the count value of the oscillation frequency of the ring oscillator R02
  • these C 0 ⁇ C 2n-1 can be directly input from the outside, and by comparing the frequency values of the two oscillators, under each input excitation, a unique response is generated; a typical response generation
  • the method is: if f RO1 >f RO2 , output 0, if f RO1 ⁇ f RO2 , output 1, and vice versa; different from the true random number generator, the frequency difference is sent to the control logic, only those frequency differences Outputs with a value large enough to be marked as stable bit outputs are discarded otherwise. In this way, the stability of the designed physical unclonable function is improved.
  • the delay unit as the basic structure of the oscillator, and use the E-TSPC type flip-flop as the counting unit of the bidirectional counter.
  • test result is also provided:
  • the circuit of this solution is implemented in a pure digital circuit on Xilinx Artix-7FPGA (using a common inverter instead of a current-starved inverter, because there are only common inverters in the FPGA ), use an oscilloscope to test the frequencies of the two ring oscillators RO, so as to observe whether the expected effect can be achieved through the reconstruction of the circuit of this scheme.
  • the first row is the frequency and frequency difference of the ring oscillator RO of the automatic layout and routing;
  • the second row is the frequency difference of the automatic placement and routing ring oscillator RO through the reconfiguration process
  • the third row is the frequency difference of the ring oscillator RO through the reconstruction process using manual placement and routing;

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Abstract

Générateur de nombres aléatoires reconfigurable et son procédé de mise en œuvre, le générateur comprenant au moins deux oscillateurs en anneau, un circuit d'échantillonnage, un compteur et une unité de commande logique, une extrémité de commande d'un sélecteur correspondant dans chaque groupe d'onduleurs étant électriquement connectée à l'unité de commande logique, ladite extrémité de commande étant utilisée pour recevoir un signal de reconfiguration de l'unité de commande logique et pour réaliser la conduction de canal de signal électrique d'un onduleur désigné et de sélecteurs sur deux côtés correspondants parmi les groupes d'onduleurs; les extrémités de sortie desdits oscillateurs en anneau étant couplées à une extrémité d'entrée du compteur; une extrémité de sortie du compteur étant connectée à l'unité de commande logique; et le circuit d'échantillonnage obtenant un signal électrique échantillonné parmi lesdits oscillateurs en anneau, de façon à faciliter la sortie d'un nombre aléatoire en fonction du signal électrique échantillonné. Le présent générateur peut améliorer l'adaptabilité environnementale et permet à un circuit d'obtenir une performance optimale en ce qui concerne la consommation d'énergie, la taille, l'efficacité dans la génération de nombres aléatoires, etc.
PCT/CN2020/107140 2020-08-05 2020-08-05 Générateur de nombres aléatoires reconfigurable et son procédé de mise en œuvre WO2022027325A1 (fr)

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