WO2022021291A1

WO2022021291A1 - Package structure and manufacturing method therefor, and device structure

Info

Publication number: WO2022021291A1
Application number: PCT/CN2020/106118
Authority: WO
Inventors: 龚顺强; 李晓波; 徐向明; 曾山
Original assignee: 华为技术有限公司
Priority date: 2020-07-31
Filing date: 2020-07-31
Publication date: 2022-02-03
Also published as: CN115868022A

Abstract

The present application discloses a package structure and a manufacturing method therefor, and a device structure. The semiconductor package structure comprises a first chip, a second chip, a substrate, and a conductive filler. The first chip and the second chip are fixed on the substrate. A first ground pad is formed on the upper surface of the side of the first chip facing the second chip. The substrate is grounded. The conductive filler covers the first ground pad and the side wall of at least one side of the first chip to electrically connect the first ground pad and the substrate. Because the conductive filler has both electrically-conducting and bonding functions, the cost is low and the operation is convenient; in addition, because the first ground pad and the substrate are connected by means of the conductive filler, grounding of the first chip can be achieved without forming a through-silicon-via penetrating through the chip, thereby simplifying the process and reducing the cost. Moreover, the lateral area required by the conductive filler is small, thus a small-sized package structure is achieved.

Description

A package structure, its manufacturing method, and device structure

technical field

The present application relates to the field of semiconductor technology, and in particular, to a package structure, a manufacturing method thereof, and a device structure.

Background technique

At present, the chip can be packaged after the chip is manufactured. Specifically, the chip can be fixed on the substrate, and then the ground pad (PAD) in the chip and the substrate below can be connected by bonding wires. When the substrate is grounded (ground, GND), the grounding of the chip can be realized. However, with the continuous development of semiconductor technology, the overall size of the chip is gradually reduced, and the distance between the chips is gradually reduced. The method of using bonding wires to realize chip grounding can no longer meet the demand.

SUMMARY OF THE INVENTION

In view of this, the first aspect of the present application provides a package structure, a manufacturing method thereof, and a device structure, which realizes the grounding of the chip through conductive fillers, can realize a small-sized package structure, simplifies the process, and saves costs.

In a first aspect of the embodiments of the present application, a package structure is provided, including a first chip, a second chip, a substrate, and a conductive filler, wherein the first chip and the second chip are fixed on the substrate, and the first chip faces the first chip. A first ground pad is formed on the upper surface of one side of the two chips, the substrate is grounded, and the conductive filler covers the first ground pad and at least one sidewall of the first chip to electrically connect the first ground pad and the substrate. Since the conductive filler has the functions of conducting electricity and bonding at the same time, the cost is low and the operation is convenient. At the same time, the first ground pad and the substrate are connected by the conductive filler, and the chip can be realized without forming a through-silicon via through the first chip. grounding, which simplifies the process and reduces the cost, and the lateral area required by the conductive filler is small, and there is no need to set up the first chip and the second chip in order to connect the ground pad and the substrate under it with the bonding wire. Larger distance, so as to realize the small size of the package structure.

As a possible implementation manner, the substrate is a conductor material, and the conductive filler covers part of the surface of the substrate.

In the embodiment of the present application, the substrate may be a conductor material. Since the substrate is grounded, the conductive filler may directly cover part of the surface of the substrate to achieve grounding, and the operation is relatively simple.

As a possible implementation manner, the package structure further includes a conductor part;

The conductor parts are formed on the substrate, and the conductor parts are electrically connected to the substrate and the conductive filler, respectively.

In the embodiment of the present application, the package structure further includes a conductor part on the substrate, and both the substrate and the conductive filler can be electrically connected through the conductor part. When the substrate and the conductive filler are not in contact, the substrate and the conductive filler can be electrically connected through the conductive part. connection, so as to realize the grounding of the substrate, and the operation is relatively simple.

As a possible implementation manner, the conductor components include at least one of interconnecting lines, grounding pads or grounding conductor blocks.

In this embodiment of the present application, the conductor component may include at least one of interconnection lines, ground pads, or ground conductor blocks, and the conductive filler may be conveniently electrically connected to the conductor component.

As a possible implementation manner, the conductor component is disposed between the first chip and the second chip.

In the embodiment of the present application, the conductor member may be disposed between the first chip and the second chip, so that the conductive filler may not cover the entire sidewall of the first chip facing the second chip, which is convenient for operation.

As a possible implementation manner, the ground conductor block includes a support member and a conductor film on a side wall of the support member, the support member is fixed on the substrate, and is used to support the second chip, so The conductor films are electrically connected to the substrate and the conductive filler, respectively.

In the embodiment of the present application, the grounding conductor block includes a support member and a conductor film on the side wall of the support member. The conductor film is electrically connected to the substrate and the conductive filler respectively, and the support member can support the second chip, reducing the impact of the conductive filler on the first chip. The effect of the second chip.

As a possible implementation manner, the support member is an insulating material, an interconnection layer is formed on the upper surface of the support member, the second chip is flip-chip disposed on the support member, and the interconnection layer is connected to the support member. The second chip is connected as a lead-out part of the second chip.

In the embodiment of the present application, the second chip may be flip-chip mounted on the support member, and the interconnection layer on the support member is used as the lead-out member, thereby reducing the connection distance between the first chip and the second chip.

As a possible implementation manner, the first chip further includes a second ground pad located on the upper surface of the other side of the first chip, and the conductive filler is further used to cover the second ground pad , to electrically connect the second ground pad and the substrate.

In the embodiment of the present application, in addition to the first ground pad on one side facing the second chip, the first chip may further include second ground pads on the other side, and in this case, the conductive filler may simultaneously cover the second ground pad The pad is used to electrically connect the second ground pad and the substrate. Since the shape of the conductive filler is easier to define, it is beneficial to the grounding of multiple ground pads.

As a possible implementation manner, the first chip is an electrical chip, and the second chip is an electrical chip or an optical chip.

In the embodiment of the present application, the first chip may be an electrical chip, and the second chip may be an electrical chip or an optical chip, so that the grounding method of the grounding pad by using the conductive filler is suitable for more scenarios.

As a possible implementation manner, the surface of the second chip further includes a third ground pad, and the conductive filler is further used to cover the third ground pad, so as to be electrically connected to the third ground pad and the substrate.

In the embodiment of the present application, the conductive filler can also cover the third ground pad on the second chip at the same time, so as to electrically connect the third ground pad and the substrate, so as to realize the grounding of the second chip. Bonding with the second chip simplifies the process and reduces the size of the device.

As a possible implementation manner, the structure further includes a third chip;

The third chip is fixed on the substrate, a fourth ground pad is formed on the surface of the third chip, and the conductive filler is also used to cover the fourth ground pad to electrically connect the first ground pad. four ground pads and the substrate.

In the embodiment of the present application, in addition to the first chip, the metal filler can also realize the grounding of other chips. For example, it can cover the fourth grounding pad on the third chip, so that the grounding of the third chip can be realized at the same time. Each chip is wired, which simplifies the process and reduces the size of the device.

As a possible implementation manner, a first interconnection pad is further formed on the first chip, a second interconnection pad is further formed on the second chip, and the first interconnection pad and all the The second interconnection pads are connected by bonding wires.

In this embodiment of the present application, the first chip and the second chip may also be connected by bonding wires. In this scenario, grounding the first chip using a metal filling layer has higher reliability than using bonding wires for grounding. Reduce the possibility of short circuits.

As a possible implementation manner, the conductive filler includes conductive particles and an adhesive material, and the adhesive material includes at least one of epoxy resin, polyurethane, and phenolic.

In a second aspect of the embodiments of the present application, a method for manufacturing a package structure is provided, including:

A first chip and a second chip are provided, the first chip and the second chip are fixed on the same substrate, and a first ground pad is formed on the upper surface of the first chip facing the second chip side, the substrate is grounded;

A conductive filler is formed to electrically connect the first ground pad and the substrate, and the conductive filler covers the first ground pad and at least one sidewall of the first chip.

As a possible implementation manner, the substrate is a conductor material, and the conductive filler covers part of the substrate.

As a possible implementation manner, conductor parts are further formed on the grounding substrate, and the conductor parts are respectively electrically connected to the substrate and the conductive filler.

As a possible implementation manner, the grounding conductor block includes a support member and a conductor film on the side wall of the support member, the support member is fixed on the substrate, and is used to support the second chip, and the conductor Films are electrically connected to the substrate and the conductive filler, respectively.

As a possible implementation manner, the forming of the conductive filler is formed by coating, spraying or printing.

As a possible implementation manner, a third chip is further fixed on the substrate, a fourth ground pad is formed on the surface of the third chip, and the conductive filler is further used to cover the fourth ground pad , to electrically connect the fourth ground pad and the substrate.

As a possible implementation manner, a first interconnect pad is further formed on the first chip, and a second interconnect pad is further formed on the second chip, and the method further includes:

The first interconnection pad and the second interconnection pad are connected with bonding wires.

In a third aspect of the embodiments of the present application, a device structure is provided, including the package structure provided in the first aspect of the embodiments of the present application.

In a fourth aspect of the embodiments of the present application, another packaging structure is provided, including: a first chip, a second chip, a substrate, and a conductive member;

The first chip and the second chip are fixed on the substrate, and a first ground pad is formed on the upper surface of the first chip facing the second chip side;

the substrate is grounded;

The conductive member is fixed on the substrate and is electrically connected to the substrate, and the conductive member and the first ground pad are electrically connected by bonding wires.

In this embodiment of the present application, the package structure may include a first chip, a second chip, a substrate, and a conductive component, the first chip and the second chip may be fixed on the substrate, and an upper surface of the first chip on the side facing the second chip may be formed There is a first ground pad, the substrate can be grounded, the conductive member can be fixed on the substrate and electrically connected to the substrate, and the conductive member and the first ground pad are connected by bonding wires, which is compared with the bonding wire to connect the first chip and the substrate. In other words, the conductive member raises the surface to be connected and reduces the distance between the first ground pad and the ground terminal, thus reducing the space required for wire bonding to a certain extent, which is conducive to realizing a small-sized package structure.

In the embodiment of the present application, the conductor part may include at least one of interconnection lines, ground pads or ground conductor blocks, so as to facilitate the electrical connection between the conductive filler and the conductor part.

As a possible implementation manner, the conductive member is disposed between the first chip and the second chip.

In the embodiment of the present application, the conductor part may be located between the first chip and the second chip, which further reduces the distance between the first ground pad and the conductor part, which is beneficial to reduce the space required for wire bonding.

As a possible implementation manner, the ground conductor block includes a support member and a conductor film on a side wall of the support member, the support member is fixed on the substrate, and is used to support the second chip, so The conductor film is electrically connected to the substrate, and the first ground pad and the conductor film are connected by the bonding wire.

A fifth aspect of the embodiments of the present application provides another method for manufacturing a packaging structure, including:

A first chip and a second chip are provided, the first chip and the second chip are fixed on the same substrate, and a first ground pad is formed on the upper surface of the first chip facing the second chip side, the substrate is grounded; a conductive component is also fixed on the substrate, and the conductive component is electrically connected to the substrate;

Bonding wires are formed to achieve electrical connection between the conductive member and the first ground pad.

In a sixth aspect of the embodiments of the present application, a device structure is provided, including the package structure provided in the fourth aspect of the embodiments of the present application.

Compared with the prior art, the present application has the following beneficial effects:

Based on the above technical solutions, the present application provides a package structure, a manufacturing method thereof, and a device structure, wherein the semiconductor package structure includes a first chip, a second chip, a substrate and a conductive filler, and the first chip and the second chip may be Fixed on the substrate, the substrate is grounded, a first ground pad is formed on the upper surface of the first chip on the side facing the second chip, and the conductive filler can be used to cover the first ground pad and at least one sidewall of the first chip , so as to electrically connect the first ground pad and the substrate, so as to realize the grounding of the first ground pad on the first chip. Since the conductive filler has the functions of conducting electricity and bonding at the same time, the cost is low and the operation is convenient. At the same time, the first ground pad and the substrate are connected by the conductive filler, and the chip can be realized without forming a through-silicon via through the first chip. grounding, which simplifies the process and reduces the cost, and the lateral area required by the conductive filler is small, and there is no need to set up the first chip and the second chip in order to connect the ground pad and the substrate under it with the bonding wire. Larger distance, so as to realize the small size of the package structure.

Description of drawings

In order to clearly understand the specific embodiments of the present application, the accompanying drawings used in describing the specific embodiments of the present application will be briefly described below. Obviously, these drawings are only some embodiments of the present application.

1 is a schematic diagram of a packaging structure provided by an embodiment of the present application;

2 is a cross-sectional view of the package structure shown in FIG. 1 along the AA direction;

3 is a schematic diagram of a semiconductor packaging structure provided by an embodiment of the present application;

4 is a cross-sectional view of the package structure shown in FIG. 3 along the AA direction;

FIG. 5 is a schematic diagram of a packaging structure provided by an embodiment of the present application;

6 is a cross-sectional view of the package structure shown in FIG. 5 along the AA direction;

7 is a schematic diagram of a packaging structure provided by an embodiment of the present application;

8 is a cross-sectional view of the package structure shown in FIG. 7 along the AA direction;

FIG. 9 is a schematic diagram of a packaging structure provided by an embodiment of the present application;

10 is a cross-sectional view of the package structure shown in FIG. 9 along the AA direction;

11 is a schematic diagram of a packaging structure provided by an embodiment of the present application;

12 is a cross-sectional view of the package structure shown in FIG. 11 along the AA direction;

13 is a schematic diagram of a packaging structure provided by an embodiment of the present application;

14 is a cross-sectional view of the package structure shown in FIG. 13 along the AA direction;

FIG. 15 is a schematic diagram of a packaging structure provided by an embodiment of the present application

16 is a cross-sectional view of the package structure shown in FIG. 15 along the AA direction;

FIG. 17 is a schematic diagram of a packaging structure provided by an embodiment of the present application

18 is a cross-sectional view of the package structure shown in FIG. 17 along the AA direction;

FIG. 19 shows a method for manufacturing a package structure provided by an embodiment of the present application.

detailed description

In view of this, the present application provides a semiconductor packaging structure and a manufacturing method thereof, in which the grounding of the chip is realized through conductive fillers, so as to simplify the packaging process and reduce the cost.

In order to make the above objects, features and advantages of the present application more clearly understood, the specific embodiments of the present application will be described in detail below with reference to the accompanying drawings.

Many specific details are set forth in the following description to facilitate a full understanding of the present application, but the present application can also be implemented in other ways different from those described herein, and those skilled in the art can do so without departing from the connotation of the present application. Similar promotion, therefore, the present application is not limited by the specific embodiments disclosed below.

Next, the present application will be described in detail with reference to the schematic diagrams. When describing the embodiments of the present application in detail, for the convenience of explanation, the cross-sectional views showing the device structure will not be partially enlarged according to the general scale, and the schematic diagrams are only examples, which should not be limited here. The scope of protection of this application. In addition, the three-dimensional spatial dimensions of length, width and depth should be included in the actual production.

At present, the chip can be packaged after the chip is manufactured. Specifically, the chip can be fixed on the substrate, and then the ground pad in the chip can be connected to the substrate under it by using bonding wires. When the substrate is grounded, it can be realized Chip ground. However, with the continuous development of semiconductor technology, the overall size of the chip is gradually reduced, and the distance between the chips is gradually reduced. The method of using bonding wires to realize chip grounding can no longer meet the demand.

For example, in some scenarios, due to the limitation of the package, many ground pads cannot be wired, so the chip cannot be grounded through bonding wires, while in other scenarios, the distance between the two chips is small, Referring to FIG. 1 and FIG. 2 , it is a schematic diagram of a package structure provided by an embodiment of the present application, wherein FIG. 2 is a cross-sectional view of the package structure shown in FIG. 1 along the AA direction, and the chip 200 and the chip 300 are fixed on the substrate 100 On the other hand, the distance between the two chips is small, and there is not enough space to set the bonding wires connecting the ground pads 201/203 on the upper surface of the chip 200 and the substrate 100 to ground the chip 200, so the two chips will be inconvenient for grounding. , especially the grounding pads 201 provided on the adjacent sides of the two chips cannot be grounded.

In addition, in the grounding method of the chip using through silicon via (TSV) through the chip, it is necessary to form a through hole through the chip first, and then fill the conductive material in the through hole, and the conductive material can connect the upper surface of the chip. The grounding component and the substrate under the chip are used to connect the chip and the grounded substrate. However, this method often has special requirements on the chip process and is expensive. Based on technical problems, the embodiments of the present application provide a packaging structure and a manufacturing method thereof. , wherein the semiconductor package structure includes a first chip, a second chip, a substrate and a conductive filler, the first chip and the second chip can be fixed on the substrate, the substrate is grounded, and the upper surface of the first chip facing the second chip side is formed There is a first ground pad, and the conductive filler can be used to cover the first ground pad and at least one sidewall of the first chip to electrically connect the first ground pad and the substrate, so as to realize the first ground pad on the first chip. Ground for the ground pad. Since the conductive filler has the functions of conducting electricity and bonding at the same time, the cost is low and the operation is convenient. At the same time, the first ground pad and the substrate are connected by the conductive filler, and the chip can be realized without forming a through-silicon via through the first chip. grounding, which simplifies the process and reduces the cost, and the lateral area required by the conductive filler is small, and there is no need to set up the first chip and the second chip in order to connect the ground pad and the substrate under it with the bonding wire. Larger distance, so as to realize the small size of the package structure.

The technical solutions of the embodiments of the present application will be described in detail below with reference to the accompanying drawings.

Referring to FIGS. 3-16 , which are schematic diagrams of various semiconductor packaging structures provided in embodiments of the present application, FIG. 4 is a cross-sectional view of the packaging structure shown in FIG. 3 along the AA direction, and FIG. 6 is FIG. 5 The sectional view of the package structure shown in FIG. 8 is shown along the AA direction, FIG. 8 is a sectional view of the package structure shown in FIG. 7 along the AA direction, FIG. 10 is a sectional view of the package structure shown in FIG. 11 is a cross-sectional view of the package structure shown in FIG. 11 along the AA direction, FIG. 14 is a cross-sectional view of the package structure shown in FIG. 13 along the AA direction, and FIG. 16 is a cross-sectional view of the package structure shown in FIG. 15 along the AA direction. , the semiconductor package structure may include a first chip 200 , a second chip 300 , a substrate 100 and a conductive filler 202 .

In the embodiment of the present application, the first chip 200 may be a chip with a grounding requirement, and the first chip 200 may be an electrical chip. Specifically, the first chip 200 may include at least one device structure, and the device structure may be a MOS device, For storage devices, sensor devices and/or other passive devices, the first chip 200 may also include a radio frequency circuit, and the radio frequency circuit often requires more bonding wires to achieve grounding to reduce parasitic inductance. As the operating frequency of the radio frequency circuit increases , the number of bonding wires is also increased, and it is more and more difficult to realize the grounding of the first chip 200 by using the bonding wires.

The second chip 300 may be a chip with a grounding requirement, for example, an electrical chip, and its device structure may be consistent with the first chip, or may not be consistent. The second chip 300 may also be a chip without grounding requirements, such as an optical chip, for example, may include a laser diode (LD), a semiconductor optical amplifier (SOA), or a photo detector (PD) )Wait.

In the scenario where the second chip 300 is an optical chip, as the transmission rate of the optical module in the optical communication circuit is getting higher and higher, for example, from 50Gbps, 100Gbps, 200Gbps to 400Gbps, 800Gbps, the bandwidth of the matching electrical chip is also getting larger and larger. , causing the grounding requirements of the electrical chip to become higher and higher to meet the high-speed RF signal return. Therefore, in the scenario where the first chip 200 and the second chip 300 are cascaded, the grounding requirement of the first chip 200 is relatively high, so as to ensure the cascade performance of the optoelectronic chips.

The substrate 100 may be a printed circuit board or a ceramic circuit board, or a conductor substrate, such as a metal substrate. The substrate 100 may be grounded, for example, through interconnecting wires in the circuit board.

The first chip 200 and the second chip 300 may be fixed on the same substrate 100 , the first chip 200 and the second chip 300 are two adjacent chips on the substrate 100 , and the distance between them may be small. Specifically, the first chip 200 and the second chip 300 may be bonded and fixed on the substrate 100 .

Since the first chip 200 has a grounding requirement, a first ground pad 201 for grounding may be provided on the first chip 200 , and the first ground pad 201 may be provided on the upper surface of the first chip 200 facing the second chip 300 . On one side, the conventional method can only connect the first ground pad 201 and the substrate 100 between the first chip 200 and the second chip 300 through bonding wires. This method has its limitations. When the distance before the second chip 300 is relatively short, it is inconvenient to set bonding wires.

In this embodiment of the present application, the grounding of the first chip 200 may be realized by using the conductive filler 202 . Specifically, the conductive filler 202 may be used to cover the first grounding pad 201 and at least one sidewall of the first chip 200 , thereby realizing The first ground pad 201 in the first chip 200 is electrically connected to the grounded substrate 100 to realize the grounding of the first chip 200 . The conductive filler 202 may be, for example, conductive adhesives. The conductive adhesive is an adhesive that has a certain conductivity after curing or drying, and has both conductivity and adhesion. The conductive adhesive may include isotropic conductive adhesives. conductive adhesives (ICAs) and anisotropic conductive adhesives (ACAs). As an example, the conductive filler 202 may be an isotropic conductive adhesive. The conductive adhesive may include conductive particles and adhesive materials, the conductive particles may be copper, aluminum, etc., and the adhesive material may be epoxy resin, polyurethane, phenolic, etc., for example, the conductive adhesive may be silver epoxy, etc. .

The sidewall of the first chip 200 covered by the conductive filler 202 may be located on the same side as the first ground pad 201, or may be located on different sides. For example, the upper surface of the first chip 200 is rectangular, corresponding to the four sides of the rectangle, The first chip may include a first side, a second side, a third side and a fourth side, the first side of the first chip 200 faces the second chip 300 , and the first ground pad 201 may be located on the first chip 200 On the first side of the surface, the conductive filler 202 may cover the first ground pad 201, and at least one sidewall of the first, second, third and fourth sides of the first chip 200, eg, cover the first A ground pad and the first sidewall of the first chip 200 are shown with reference to FIGS. 3 and 4 .

When there is a certain distance between the first ground pad 201 and the sidewall of the first chip 200 covered by the conductive filler 202, the conductive filler 202 may also cover the upper surface between the first ground pad 201 and the sidewall. surface. When the substrate 100 is a conductor substrate, the conductive filler 202 may cover part of the surface of the conductor substrate, so that the first chip 200 is grounded through the first ground pad 201 , the conductive filler 202 and the conductor substrate.

Of course, the conductive filler 202 may cover the entire surface of one side wall, or only a part of the surface. Referring to FIG. 4 , the conductive filler 202 only covers the part that needs to pass between the first ground pad 201 and the substrate 100 . side wall.

When the conductive filler 202 covers one sidewall of the first chip 200, the formation process of the conductive filler 202 is relatively simple, and when the conductive filler 202 covers multiple sidewalls, the first chip 200 can be protected. The conductivity of the conductive filler 202 can form a shielding effect on the first chip 200 to avoid signal interference between different chips. Referring to FIGS. 5 and 6 , the conductive filler 202 may completely cover each sidewall of the first chip 200 .

The first chip 200 may further include a second ground pad 203 located on the upper surface of the first chip 200 not facing the other side of the second chip 300, and the conductive filler 202 may also be used to implement the second ground pad The grounding of 203, that is, the conductive filler 202 can also cover the second ground pad 203, the first ground pad 201 and the second ground pad 203 are electrically connected through the conductive filler 202, and grounding is realized at the same time, refer to FIG. 5 and FIG. 6 shown. Specifically, the conductive filler 202 may extend from the first ground pad 201 to the second ground pad 203 through the upper surface, and may also extend to the second ground pad 203 through the sidewall of the first chip 200 .

In addition, the conductive filler 202 may also cover the sidewalls of the second chip 300 to protect the second chip 300 and shield the second chip 300 , as shown in FIGS. 7 and 8 . When the second chip 300 is an electrical chip, and a third ground pad 209 is further formed on the surface of the second chip 300 , the third ground pad 209 and at least one side of the second chip 300 may be covered with a conductive filler 202 wall to electrically connect the third grounding pad 209 and the substrate 100 , as shown in FIG. 9 and FIG. 10 , so as to realize the grounding of the third grounding pad 209 .

When there is a requirement for electrical connection between the first chip 200 and the second chip 300, the electrical connection between the two can be realized by using a bonding wire 206, and the bonding wire 206 can be a gold wire or a copper wire or the like. Specifically, the first chip 200 and the second chip 300 can be interconnected by connecting the first interconnect pad 205 on the first chip 200 and the second interconnect pad 207 on the second chip 300 by using the bonding wire 206 3-16, the first interconnection pad 205 is formed on the upper surface of the first chip 200, and the second interconnection pad 207 is formed on the upper surface of the second chip 300.

The substrate 100 may be provided with a grounding member, and the grounding member is electrically connected to the substrate 100 for grounding the chips thereon. The grounding member has a conductive function, so that the grounding member is in contact with the substrate 100 , which is equivalent to the grounding end extended from the substrate 100 , and the first chip 200 can be connected to the grounding member to realize grounding. For example, the grounding member may be at least one of interconnect lines, grounding pads, grounding conductor blocks, etc. on the surface of the substrate 100, wherein the grounding member may be disposed between the first chip and the second chip, or may be disposed between the first chip and the second chip. A chip is adjacent to other locations. The grounding conductor block may be a conductor material or an insulating material fixed on the substrate 100 , and a conductor film is provided on the surface of the insulating material.

Specifically, when interconnect lines are provided on the substrate 100, the conductive filler may cover part of the interconnect lines, so that the first chip 200 can be grounded through the first ground pad 201, the conductive filler 202 and the interconnect lines; When a ground pad is provided on the substrate 100, the conductive filler 202 can cover the conductive pad, so that the first chip 200 can be grounded through the first ground pad 201, the conductive filler 202 and the conductive pad; When there is a ground conductor block, the conductive filler 202 may cover part or all of the surface of the ground conductor block, so that the conductive filler 202 and the substrate 100 are electrically connected through the ground conductor block, and the first chip 200 passes through the first ground pad 201, the conductive filler 202, the ground conductor block and the substrate 100 are grounded.

Referring to FIGS. 11 and 12 , a grounding conductor block 102 is provided on the substrate 100 . The grounding conductor block 102 is connected to the substrate 10 at a point to realize grounding, and the conductive filler 202 can be filled between the first chip 200 and the grounding conductor block 102 , that is, covering the first ground pad 201 , at least one side wall of the first chip 200 , and part or all of the side wall of the ground conductor block 102 to realize the electrical connection between the first ground pad and the substrate, so that the first ground The pad 201 is grounded. When the conductive filler 202 covers part of the sidewall of the ground conductor block 102 , the conductive filler 202 is electrically connected to the substrate 100 through the ground conductor block 102 .

In addition, since the grounding conductor block 102 is disposed on the substrate 100, its upper surface is bound to be higher than the upper surface of the substrate 100, so the grounding conductor block 102 and the first grounding pad 201 can be connected by the bonding wire 210. At this time, the grounding conductor The height difference between the upper surface of the block 102 and the upper surface of the first ground pad 201 is small, and the required length of the bonding wire 210 is also short, which is convenient for operation, as shown in FIG. 13 and FIG. 14 .

Referring to FIG. 15 and FIG. 16 , a ground conductor block is provided on the substrate. The ground conductor block includes a support member 104 and a conductor film 106 on the side wall of the support member 104 . The support member 106 can be fixed on the substrate 100 for supporting In the second chip 300 , the conductor film 106 is electrically connected to the substrate 100 , and the conductor film 106 is also grounded. At this time, the conductive filler 202 can be filled between the first chip 200 and the conductor film 106 , that is, covering the first ground pad 201 , At least one side wall of the first chip 200 and part or all of the surface of the conductor film 106 are electrically connected to the first ground pad 201 and the substrate 100 , so that the first ground pad 201 is grounded. When the conductive filler 202 covers part of the sidewall of the conductor film 106 , the conductive filler 202 is electrically connected to the substrate 100 through the ground conductor block.

The support member 104 may be an insulating material, such as ceramics, and the second chip 300 may be flip-chip mounted on the support member 104 , that is, the substrate of the second chip 300 faces the side away from the support member 104 . The surface of the side of the 300 with the lead-out pads is close to the support member 104, and an interconnect layer 105 may be formed on the support member 104, and the interconnect layer 105 is connected to the lead-out pads in the second chip 300, so that the interconnect layer 105 acts as a The lead-out part of the second chip 300 . The connection between the interconnection layer 105 and the lead wires on the second chip 300 can be realized by soldering, for example, tin lead balls can be deposited on the lead pads of the second chip 300, and then the second chip 300 can be reversely heated, such as melting The tin lead ball is combined with the support member 104 .

When there is a need for electrical connection between the first chip and the second chip, the first interconnect pad 205 and the interconnect layer 105 on the first chip 200 can be connected by using the bonding wires 206, so as to realize the first chip 200 and the interconnect layer 105. Electrical connection of the second chip 300 .

In addition, since the grounding conductor block is disposed on the substrate 100, its upper surface is bound to be higher than the upper surface of the substrate 100, so the conductor film 106 in the grounding conductor block and the first grounding pad 201 can be connected by the bonding wire 210. In this case, the lateral thickness of the conductor film needs to be thicker, that is, the upper surface of the conductor film is wider, with sufficient wire bonding positions, the height difference between the upper surface of the conductor film 106 and the upper surface of the first ground pad 201 is small, and the required bonding wire The length of 210 is also short, which is convenient for operation, as shown in FIG. 17 and FIG. 18 .

It should be noted that, in the embodiment of the present application, the adjacent first chip and second chip fixed on the substrate are used as examples for description, but there may be other chips actually fixed on the substrate, and these chips are adjacent to each other. Both of the two chips can be used as a new first chip and a second chip, so as to have the structure of the first chip and the second chip. Of course, the first chip may be adjacent to a plurality of chips at the same time, and the positional relationship of the first chip of other chips can refer to the positional relationship between the second chip and the first chip, which will not be repeated here.

In the embodiment of the present application, other chips not adjacent to the first chip may also be fixed on the substrate, for example, a third chip is also fixed, a fourth ground pad is formed on the surface of the third chip, and the conductive filler is also The fourth ground pad is covered to electrically connect the fourth ground pad and the substrate. Of course, the conductive filler can also cover the sidewalls of the third chip.

The present application provides a package structure, including a first chip, a second chip, a substrate and conductive fillers. The first chip and the second chip can be fixed on the substrate, the substrate is grounded, and the first chip faces the side of the second chip. A first grounding pad is formed on the upper surface, and the conductive filler can be used to cover the first grounding pad and at least one sidewall of the first chip to electrically connect the first grounding pad and the substrate, so as to realize the first grounding pad on the first chip. the ground of the first ground pad. Since the conductive filler has the functions of conducting electricity and bonding at the same time, the cost is low and the operation is convenient. At the same time, the first ground pad and the substrate are connected by the conductive filler, and the chip can be realized without forming a through-silicon via through the first chip. grounding, which simplifies the process and reduces the cost, and the lateral area required by the conductive filler is small, and there is no need to set up the first chip and the second chip in order to connect the ground pad and the substrate under it with the bonding wire. Larger distance, so as to realize the small size of the package structure.

Based on the packaging structure provided by the above embodiments, the embodiments of the present application also provide a method for manufacturing a packaging structure. Referring to FIG. 19 , which is a schematic flowchart of a method for manufacturing a packaging structure provided by the embodiments of the present application, The method may include the following steps:

S101, providing a first chip and a second chip, the first chip and the second chip are fixed on the same substrate, a first ground pad is formed on the first chip, and the substrate is grounded.

In this embodiment of the present application, the first chip 200 may be a chip with a grounding requirement, and the first chip 200 may be an electrical chip. The second chip 300 may be a chip with a grounding requirement, such as an electrical chip, or a chip without a grounding requirement, such as an optical chip.

The substrate 100 may be a printed circuit board or a ceramic circuit board, or a conductor substrate, such as a metal substrate, and the substrate 100 may be grounded.

The first chip 200 and the second chip 300 may be fixed on the same substrate 100 , the first chip 200 and the second chip 300 are two adjacent chips on the substrate 100 , and the distance between them may be small. Specifically, the first chip 200 and the second chip 300 may be bonded and fixed on the substrate 100 . Afterwards, surface cleaning of the first chip and the second chip may be performed.

Since the first chip 200 has a grounding requirement, a first ground pad 201 for grounding may be provided on the first chip 200 , and the first ground pad 201 may be provided on the upper surface of the first chip 200 facing the second chip 300 . side. On the first chip 200 , a second ground pad 203 located on the other side of the first chip 200 not facing the second chip 300 may also be included. The first chip 200 is also provided with a first interconnection pad 205 .

Second interconnect pads 207 may be disposed on the second chip 300 . When the second chip 300 is an electrical chip, a third ground pad 209 for grounding may be provided.

S102, forming a conductive filler to electrically connect the first ground pad and the substrate.

In the embodiment of the present application, the grounding of the first chip 200 may be realized by using the conductive filler 202 . Specifically, the conductive filler 202 may be used to cover the first grounding pad 201 and at least one sidewall of the first chip 200 , thereby realizing The first ground pad 201 in the first chip 200 is electrically connected to the grounded substrate 100 to realize the grounding of the first chip 200 . The conductive filler 202 can be, for example, conductive glue, the conductive glue can include conductive particles and an adhesive material, the conductive particles can be copper, aluminum, etc., and the adhesive material can be epoxy resin, polyurethane, phenolic, etc., for example, the conductive glue can be Epoxy silver glue, etc.

The conductive filler 202 can also be used to ground the second ground pad 203, that is, the conductive filler 202 can also cover the second ground pad 203, and the first ground pad 201 and the second ground pad 203 pass through the conductive filler 202 is electrically connected and grounded at the same time. The third grounding pad 209 and at least one sidewall of the second chip 300 are also covered with the conductive filler 202 to electrically connect the third grounding pad 209 and the substrate 100 so as to realize the grounding of the third grounding pad 209

When there is a requirement for electrical connection between the first chip 200 and the second chip 300, the electrical connection between the two can be realized by using a bonding wire 206, and the bonding wire 206 can be a gold wire or a copper wire or the like. Specifically, the first chip 200 and the second chip 300 can be interconnected by connecting the first interconnect pad 205 on the first chip 200 and the second interconnect pad 207 on the second chip 300 by using the bonding wire 206 .

Specifically, the conductive filler 202 can be formed by coating, spraying or printing, and then heating and curing to fix the conductive filler 202 into shape.

A ground component may be provided on the substrate 100 for grounding the chips thereon. The grounding member has a conductive function, so that the grounding member is in contact with the substrate 100 , which is equivalent to the grounding end extended from the substrate 100 , and the first chip 200 can be connected to the grounding member to realize grounding. For example, the grounding member may be at least one of interconnect lines, grounding pads, grounding conductor blocks, etc. on the surface of the substrate 100, wherein the grounding member may be disposed between the first chip and the second chip, or may be disposed between the first chip and the second chip. A chip is adjacent to other locations. The grounding conductor block may be a conductor material or an insulating material fixed on the substrate 100 , and a conductor film is provided on the surface of the insulating material.

11 and 12 , the substrate 100 is provided with a ground conductor block 102 , and the conductive filler 202 can be filled between the first chip 200 and the ground conductor block 102 , that is, cover the first ground pad 201 and the first chip 200 At least one sidewall of the grounding conductor block 102 and part or all of the sidewall of the grounding conductor block 102 are electrically connected to the first grounding pad and the substrate, so that the first grounding pad 201 is grounded. When the conductive filler 202 covers part of the sidewall of the ground conductor block 102 , the conductive filler 202 is electrically connected to the substrate 100 through the ground conductor block 102 .

The support member 104 may be an insulating material, such as ceramics, and the second chip 300 may be flip-chip disposed on the support member 104, that is, the substrate of the second chip 300 faces the side away from the support member 104, and the second chip 300 has One side surface of the lead-out pad is close to the support member 104, an interconnection layer 105 may be formed on the support member 104, and the interconnection layer 105 is connected to the lead-out pad in the second chip 300, so that the interconnection layer 105 acts as the second chip 300 lead-out parts. The connection between the interconnection layer 105 and the lead wires on the second chip 300 can be realized by soldering, for example, tin lead balls can be deposited on the lead pads of the second chip 300, and then the second chip 300 can be reversely heated, such as melting The tin lead ball is combined with the support member 104 .

In addition, since the grounding conductor block is disposed on the substrate 100, its upper surface is bound to be higher than the upper surface of the substrate 100, so the conductor film 106 in the grounding conductor block and the first grounding pad 201 can be connected by the bonding wire 210. In this case, the lateral thickness of the conductor film needs to be thicker, that is, the upper surface of the conductor film is wider, with sufficient wire bonding positions, the height difference between the upper surface of the conductor film 106 and the upper surface of the first ground pad 201 is small, and the required bonding wire The length of 210 is also short, and the space occupied is also small, which is convenient for operation, as shown in FIG. 17 and FIG. 18 .

An embodiment of the present application provides a method for manufacturing a package structure, providing a first chip and a second chip, the first chip and the second chip are fixed on the same substrate, a first ground pad is formed on the first chip, and the substrate is grounded , and then a conductive filler can be formed to electrically connect the first ground pad and the substrate. Since the conductive filler has the functions of conducting and bonding at the same time, the cost is low and the operation is convenient. The conductive filler is connected, and the grounding of the chip can be realized without forming a through-silicon via through the first chip, which simplifies the process and reduces the cost. A larger distance between the first chip and the second chip is provided by the bonding pad and the substrate thereunder, thereby realizing a small-sized package structure.

An embodiment of the present application further provides a device structure, which may include the aforementioned package structure, and the device structure may be an optoelectronic device or an electrical device.

The "first" in the names such as "first ground pad", "first interconnect pad", "first chip" mentioned in the embodiments of the present application is only used for name identification, and does not represent the sequence number one. The same rule applies to "second" etc.

Each embodiment in this specification is described in a progressive manner, and the same and similar parts between the various embodiments may be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the method embodiment, since it is basically similar to the structural embodiment, the description is relatively simple, and for related parts, please refer to the partial description of the structural embodiment.

The above is a specific implementation manner of the application. It should be understood that the above-mentioned embodiments are only used to illustrate the technical solutions of the present application, but not to limit them; although the present application has been described in detail with reference to the above-mentioned embodiments, those of ordinary skill in the art should understand that it can still be used for The technical solutions described in the foregoing embodiments are modified, or some technical features thereof are equivalently replaced; and these modifications or replacements do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present application.

Claims

A package structure, comprising: a first chip, a second chip, a substrate and a conductive filler;

The first chip and the second chip are fixed on the substrate, and a first ground pad is formed on the upper surface of the first chip facing the second chip side;

the substrate is grounded;

The conductive filler covers the first ground pad and at least one sidewall of the first chip to electrically connect the first ground pad and the substrate.
The structure of claim 1, wherein the substrate is a conductor material, and the conductive filler covers part of the surface of the substrate.
The structure of claim 1, further comprising a conductor member;

The conductor parts are formed on the substrate, and the conductor parts are electrically connected to the substrate and the conductive filler, respectively.
4. The structure of claim 3, wherein the conductor member includes at least one of an interconnection line, a ground pad, or a ground conductor block.
The structure according to claim 3 or 4, wherein the conductor member is provided between the first chip and the second chip.
The structure according to claim 4 or 5, wherein the ground conductor block comprises a support member and a conductor film on the side wall of the support member, and the support member is fixed on the substrate for supporting The second chip and the conductor film are respectively electrically connected to the substrate and the conductive filler.
The structure according to claim 6, wherein the support member is an insulating material, an interconnect layer is formed on the upper surface of the support member, and the second chip is flip-chip mounted on the support member, so The interconnection layer is connected to the second chip as a lead-out part of the second chip.
The structure according to any one of claims 1-7, wherein the first chip further comprises a second ground pad located on the upper surface of the other side of the first chip, and the conductive filler further comprises for covering the second ground pad to electrically connect the second ground pad and the substrate.
The structure according to any one of claims 1-8, wherein the first chip is an electrical chip, and the second chip is an electrical chip or an optical chip.
The structure according to any one of claims 1-9, wherein the surface of the second chip further comprises a third ground pad, and the conductive filler is further used to cover the third ground pad, to electrically connect the third ground pad and the substrate.
The structure according to any one of claims 1-10, wherein the structure further comprises a third chip;

The third chip is fixed on the substrate, a fourth ground pad is formed on the surface of the third chip, and the conductive filler is also used to cover the fourth ground pad to electrically connect the first ground pad. four ground pads and the substrate.
The structure according to any one of claims 1-11, wherein a first interconnect pad is further formed on the first chip, and a second interconnect pad is further formed on the second chip, The first interconnection pad and the second interconnection pad are connected by bonding wires.
The structure according to any one of claims 1-12, wherein the conductive filler comprises conductive particles and an adhesive material, and the adhesive material comprises at least one of epoxy resin, polyurethane, and phenolic.
A method for manufacturing a packaging structure, comprising:

A first chip and a second chip are provided, the first chip and the second chip are fixed on the same substrate, and a first ground pad is formed on the upper surface of the first chip facing the second chip side, the substrate is grounded;

A conductive filler is formed to electrically connect the first ground pad and the substrate, and the conductive filler covers the first ground pad and at least one sidewall of the first chip.
The method of claim 14, wherein the substrate is a conductor material, and the conductive filler covers part of the substrate.
The method according to claim 14, wherein conductor parts are further formed on the grounding substrate, and the conductor parts are respectively electrically connected to the substrate and the conductive filler.
17. The method of claim 16, wherein the conductor components comprise at least one of interconnect lines, ground pads, or ground conductor blocks.
The method of claim 16 or 17, wherein the conductor member is provided between the first chip and the second chip.
The method according to claim 16, wherein the grounding conductor block comprises a support member and a conductor film on the side wall of the support member, the support member is fixed on the substrate for supporting the second A chip, the conductor film is electrically connected to the substrate and the conductive filler, respectively.
The method according to claim 19, wherein the support member is made of insulating material, an interconnect layer is formed on the upper surface of the support member, the second chip is flip-chip mounted on the support member, the The interconnection layer is connected to the second chip as a lead-out part of the second chip.
The method according to any one of claims 14-20, wherein the first chip further comprises a second ground pad located on the upper surface of the other side of the first chip, and the conductive filler further comprises for covering the second ground pad to electrically connect the second ground pad and the substrate.
The method according to any one of claims 14-21, wherein the forming the conductive filler is formed by coating, spraying or printing.
The method according to any one of claims 14-22, wherein the first chip is an electrical chip, and the second chip is an electrical chip or an optical chip.
The method according to any one of claims 14-23, wherein the surface of the second chip further comprises a third ground pad, and the conductive filler is further used to cover the third ground pad, to electrically connect the third ground pad and the substrate.
The method according to any one of claims 14-24, wherein a third chip is further fixed on the substrate, a fourth ground pad is formed on the surface of the third chip, and the conductive filler is further for covering the fourth ground pad to electrically connect the fourth ground pad and the substrate.
The method according to any one of claims 14-25, wherein a first interconnect pad is further formed on the first chip, and a second interconnect pad is further formed on the second chip, The method also includes:

The first interconnection pad and the second interconnection pad are connected with bonding wires.
The method according to any one of claims 14-26, wherein the conductive filler comprises conductive particles and an adhesive material, and the adhesive material comprises at least one of epoxy resin, polyurethane, and phenolic.
A device structure, characterized by comprising the package structure according to any one of claims 1-13.