WO2022021123A1 - 显示驱动电路及方法、led显示板和显示装置 - Google Patents

显示驱动电路及方法、led显示板和显示装置 Download PDF

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Publication number
WO2022021123A1
WO2022021123A1 PCT/CN2020/105425 CN2020105425W WO2022021123A1 WO 2022021123 A1 WO2022021123 A1 WO 2022021123A1 CN 2020105425 W CN2020105425 W CN 2020105425W WO 2022021123 A1 WO2022021123 A1 WO 2022021123A1
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WIPO (PCT)
Prior art keywords
data
circuit
grayscale
channel
current gain
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PCT/CN2020/105425
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English (en)
French (fr)
Inventor
韦科
刘德福
王伙荣
宗靖国
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西安钛铂锶电子科技有限公司
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Application filed by 西安钛铂锶电子科技有限公司 filed Critical 西安钛铂锶电子科技有限公司
Priority to CN202080102691.XA priority Critical patent/CN115968492A/zh
Priority to US18/015,845 priority patent/US20230267875A1/en
Priority to PCT/CN2020/105425 priority patent/WO2022021123A1/zh
Priority to KR1020237000268A priority patent/KR20230022953A/ko
Publication of WO2022021123A1 publication Critical patent/WO2022021123A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0291—Details of output amplifiers or buffers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0271—Adjustment of the gradation levels within the range of the gradation scale, e.g. by redistribution or clipping
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/12—Frame memory handling
    • G09G2360/121—Frame memory handling using a cache memory

Definitions

  • the present application relates to the technical field of display control, and in particular, to a display driving circuit, an LED display panel, a display device, and a display driving method.
  • LED Light Emitting Diode, light-emitting diode
  • LED display devices are applied to various fields due to their advantages of low cost, low power consumption, high visibility, and freedom of assembly.
  • people have higher and higher requirements for the display quality. Therefore, how to improve the display quality of LED display devices has become a research hotspot in this field.
  • LEDs can be applied to outdoor high-brightness screens and indoor low-brightness conference screens; more and more customers require LED display devices to adjust the brightness according to their own needs.
  • An existing sixteen output channel PWM (Pulse Width Modulation, pulse width modulation) LED display driver chip based on the grayscale clock signal GCLK, and its channel control circuit typically includes a plurality of corresponding to the sixteen output channels.
  • a comparator a plurality of current sources corresponding to the sixteen output channels, an output buffer electrically coupled between the plurality of comparators and the plurality of current sources, and an output buffer electrically coupled to the Global current gain regulator for multiple current sources.
  • the PWM drive control method is adopted, and the brightness of the LED display device used is between 1000-20000nit, the 16-bit grayscale data can only be displayed in 10-14 bits, so it is difficult to achieve an effective improvement simply by relying on the PWM drive control method. Displays the effect of bit depth. Furthermore, with the gradual popularization of small-pitch LED display devices, the brightness of indoor small-pitch display devices is generally controlled between 100-1000nit, while the existing PWM LED display driver chips need to dim the LED brightness in some scenarios.
  • embodiments of the present application provide a display driving circuit, an LED display panel, a display device, and a display driving method.
  • a display driving circuit provided by an embodiment of the present application includes: an interface circuit, used for acquiring multiple grayscale data and multiple current gain data; a command processing circuit, electrically coupled to the interface circuit; and a cache circuit , electrically coupled to the interface circuit for buffering the multiple grayscale data and the multiple current gain data; a current source circuit electrically coupled to the command processing circuit and including multiple channel current sources; a channel grayscale control circuit, electrically coupled to the command processing circuit, the cache circuit and the current source circuit, and configured to respectively control the on-duration of the current sources of the multiple channels according to the multiple grayscale data; and a channel current control circuit, electrically coupled to the buffer circuit and the current source circuit, for respectively controlling the output currents of the plurality of channel current sources according to the plurality of current gain data.
  • a display driving circuit By designing a display driving circuit in the embodiments of the present application, it can acquire grayscale data and current gain data, and can control the on-time of the current source of each channel based on the grayscale data, and control each channel based on the current gain data
  • the output current of the current source can dynamically adjust the channel current; in this way, the grayscale data can be improved by reducing the output current (corresponding to the driving current of the display point), that is, the display bit depth can be improved.
  • the display effect of the LED display device is related to the refresh rate and the driving current of each gray scale, by reducing the driving current of the display point such as the LED light point and increasing the gray scale data at a low gray scale, the low brightness can be effectively improved. Grayscale refresh rate at low grayscale.
  • the desired brightness value can be accurately obtained, thereby improving the display accuracy of the entire LED display device at low gray levels, so as to solve the problem of uneven grayscale transition in low brightness and low gray levels. The problem.
  • the interface circuit includes a shift buffer circuit and is used to access a data clock signal, a latch signal and serial data; the shift buffer circuit is used to receive the serial data to obtain the plurality of grayscale data and the plurality of current gain data and accept the control of the data clock signal and the latch signal; the command processing circuit is electrically coupled to the shift register circuit and is controlled by the data clock signal and the latch signal; the buffer circuit is electrically coupled to the shift register circuit to obtain the plurality of grayscale data and the plurality of current gain data; and , the channel grayscale control circuit is controlled by the data clock signal.
  • the interface circuit of this embodiment can realize serial input and output of grayscale data and current gain data, which is beneficial to the cascade connection between multiple display driving circuits; and the channel grayscale control circuit accepts the data clock signal. Control facilitates reducing the number of input ports of the interface circuit.
  • the channel grayscale control circuit includes: a counter electrically coupled to the command processing circuit for receiving a grayscale clock signal and generating under the control of the grayscale clock signal A grayscale clock count value; a grayscale breaking processing circuit, electrically coupled to the command processing circuit and the counter, for receiving the control of the command processing circuit to control the counting operation of the counter and generate grayscale groups a control signal; an output buffer, electrically coupled to the plurality of channel current sources of the current source circuit; and a plurality of comparators, electrically coupled to the buffer circuit, the counter, and the grayscale breakup
  • the processing circuit and the output buffer are used to obtain the plurality of grayscale data from the buffer circuit respectively, and generate a plurality of grayscale data under the control of the grayscale clock count value and the grayscale grouping control signal
  • the degree display control signal is respectively transmitted to the plurality of channel current sources through the output buffer.
  • the channel grayscale control circuit further includes: a frequency multiplier circuit, electrically coupled to the counter, for generating the grayscale clock signal and transmitting it to the counter.
  • a frequency multiplier circuit electrically coupled to the counter, for generating the grayscale clock signal and transmitting it to the counter.
  • the current source circuit further includes a plurality of color component global current gain adjusters, and each of the color component global current gain adjusters is electrically coupled to the plurality of channel current sources a plurality of channel current sources for carrying sub-pixels of the same color;
  • the channel current control circuit includes a plurality of channel current gain regulators, and the plurality of channel current gain regulators are respectively electrically coupled to the plurality of channels
  • the current source is controlled by the plurality of current gain data respectively.
  • the setting of the color component global current gain adjuster is beneficial to the global adjustment of the channel current sources of the sub-pixels of the same color.
  • the interface circuit includes a shift buffer circuit and is used to access a data clock signal, a latch signal, serial data and a second clock signal different from the data clock signal;
  • the shift temporary storage circuit is used to receive the serial data to obtain the plurality of grayscale data and the plurality of current gain data and to accept the control of the data clock signal and the latch signal;
  • the command The processing circuit is electrically coupled to the shift register circuit and is controlled by the data clock signal and the latch signal;
  • the cache circuit is electrically coupled to the shift register circuit to obtain the plurality of grayscale data and the plurality of current gain data; and the channel grayscale control circuit is controlled by the second clock signal.
  • the interface circuit of this embodiment can realize serial input and output of grayscale data and current gain data, which is beneficial to the cascade connection between multiple display driving circuits; and the channel grayscale control circuit accepts a second signal different from the data clock signal.
  • the control of the clock signal makes the generation of the grayscale clock signal no longer limited by the data clock signal, and improves the flexibility of the generation of the grayscale clock signal.
  • the display driving circuit further includes: a scan control circuit, electrically coupled to the channel grayscale control circuit, for generating a plurality of row scan signals in sequence.
  • a scan control circuit electrically coupled to the channel grayscale control circuit, for generating a plurality of row scan signals in sequence.
  • the buffer circuit includes a grayscale data storage area and a current gain data storage area, the grayscale data storage area is used for buffering the plurality of grayscale data, and the current gain data storage area The area is used for buffering the plurality of current gain data.
  • grayscale data and current gain data are stored separately, which is beneficial to simplify data read and write operations.
  • the grayscale data storage area includes two storage sub-areas for buffering grayscale data frame by frame in a ping-pong storage manner
  • the current gain data storage area includes two storage sub-areas to It is used to buffer the current gain data frame by frame using ping-pong storage.
  • Both the grayscale data and the current gain data in this embodiment adopt the ping-pong storage method, which is beneficial to improve the processing speed and performance of the display driving circuit.
  • the interface circuit, the command processing circuit, the buffer circuit, the current source circuit, the channel grayscale control circuit, and the channel current control circuit are integrated into the same chip Inside.
  • each circuit is integrated into the same chip, that is, the display driving circuit is chipped, which is beneficial to improve the integration degree of the display driving circuit.
  • the plurality of current gain data are point-by-point current gain data, so that the same channel current source among the plurality of channel current sources uses the same method as the channel current source when driving different display points.
  • Current gain data corresponding to different display points.
  • the point-by-point current gain data in this embodiment is beneficial to improve the precision of dynamic current adjustment.
  • the plurality of current gain data are channel-by-channel current gain data, so that the same current gain data of the channel current source among the plurality of channel current sources is used in different display frames different.
  • the use of channel-by-channel circuit gain data in this embodiment can at least realize frame-by-frame current dynamic adjustment.
  • an LED display panel provided by an embodiment of the present application includes: a pixel array, including a plurality of pixel points, and each of the pixel points includes a plurality of LEDs of different colors; and at least one of the LEDs according to any one of the foregoing embodiments
  • the display driving circuit wherein the plurality of channel current sources of the display driving circuit are electrically coupled to the pixel array.
  • the LED display panel of this embodiment can realize the dynamic adjustment of channel current, which is beneficial to improve the display bit depth, improve the grayscale refresh rate under low brightness and low gray, and improve the display accuracy of the entire LED display device under low gray to solve the problem of low brightness.
  • a display device provided by an embodiment of the present application includes: a front-end display control card for outputting multiple grayscale data and multiple current gain data; and the aforementioned LED display panel, wherein the LED displays
  • the display driving circuit of the panel is electrically coupled to the front-end display control card to receive the plurality of grayscale data and the plurality of current gain data.
  • the display device of this embodiment can realize dynamic adjustment of channel current, which is beneficial to increase the display bit depth, improve the grayscale refresh rate under low brightness and low gray, and improve the display accuracy of the entire LED display device under low gray to solve the problem of low brightness The problem of uneven grayscale transition under low grayscale.
  • a display driving method includes: acquiring multiple grayscale data and multiple current gain data; buffering the multiple grayscale data and the multiple current gain data; The pieces of grayscale data respectively control the turn-on durations of the current sources of the multiple channels; and the magnitudes of the output currents of the current sources of the multiple channels are controlled respectively according to the multiple pieces of current gain data.
  • the display driving method of the present embodiment can realize dynamic adjustment of channel current, which is beneficial to improve the display bit depth, improve the grayscale refresh rate in low brightness and low gray, and improve the display accuracy of the entire LED display device in low gray to solve the problem of low brightness.
  • the controlling the on-duration of the current sources of the multiple channels respectively according to the multiple grayscale data includes: receiving a grayscale clock signal and generating under the control of the grayscale clock signal The grayscale clock count value; control the counting operation of the counter and generate the grayscale grouping control signal based on the grayscale smashing algorithm; obtain the plurality of grayscale data respectively, and use the grayscale clock count value and the grayscale clock count value and the grayscale.
  • a plurality of grayscale display control signals are generated and transmitted to the plurality of channel current sources respectively, so as to control the on-time of the plurality of channel current sources.
  • the high-gray part and the low-gray part can be uniformly scattered and distributed, so that in some scenes where the gray-scale realization is incomplete, it can be ensured that most of the gray-scale can be realized as much as possible. .
  • controlling the turn-on duration of the current sources of the multiple channels according to the multiple grayscale data further includes: performing frequency multiplication processing on the input clock signal to generate the grayscale clock signal.
  • the frequency doubling processing in this embodiment is beneficial to increase the elasticity of the gray-scale clock signal generation.
  • the controlling the output currents of the multiple channel current sources respectively according to the multiple current gain data includes: controlling the multiple channels respectively according to the multiple point-by-point current gain data The magnitude of the output current of the current source.
  • the use of point-by-point current gain data in this embodiment enables the same channel current source to use the current gain data corresponding to the different display points when driving different display points (such as LED light points), which is beneficial to improve The accuracy of the current dynamic adjustment.
  • the caching of the plurality of grayscale data and the plurality of current gain data includes: buffering the point-by-point grayscale data frame by frame using a ping-pong storage method; and adopting a ping-pong storage method frame by frame Cache point-by-point current gain data.
  • Both the grayscale data and the current gain data in this embodiment adopt a ping-pong storage method, which is beneficial to improve processing speed and performance.
  • the controlling the output currents of the multiple channel current sources respectively according to the multiple current gain data includes: controlling the multiple channels respectively according to the multiple channel-by-channel current gain data The magnitude of the output current of the current source.
  • the use of the channel-by-channel current gain data in this embodiment can make the current gain data used by the same channel current source differ in different display frames, and at least it can realize frame-by-frame current dynamic adjustment.
  • the above technical solution may have the following advantages or beneficial effects: by designing the display driving circuit, it can obtain grayscale data and current gain data, and can control the on-time of each channel current source based on the grayscale data, and based on the The current gain data controls the output current of each channel current source, so that the channel current can be dynamically adjusted; in this way, the grayscale data can be improved by reducing the output current (corresponding to the driving current of the display point), that is, the display can be improved. bit depth. Furthermore, since the display effect of the LED display device is related to the refresh rate and the driving current of each gray scale, by reducing the driving current of the display point such as the LED light point and increasing the gray scale data at a low gray scale, the low brightness can be effectively improved.
  • Grayscale refresh rate at low grayscale by reducing the output current and increasing the grayscale data, the desired brightness value can be accurately obtained, thereby improving the display accuracy of the entire LED display device at low gray levels, so as to solve the problem of uneven grayscale transition in low brightness and low gray levels. The problem.
  • FIG. 1A is a schematic structural diagram of a display driving circuit according to an embodiment of the present application.
  • FIG. 1B is a schematic diagram of a specific structure of the display driving circuit shown in FIG. 1A .
  • FIG. 1C is a schematic diagram related to a specific structure of the current source circuit, the channel grayscale control circuit and the channel current control circuit in the display driving circuit shown in FIG. 1A .
  • FIG. 2 is a schematic diagram of a specific structure of another display driving circuit provided by an embodiment of the present application.
  • FIG. 3 is a schematic diagram of a specific structure of still another display driving circuit according to an embodiment of the present application.
  • FIG. 4 is a schematic diagram of a specific structure of another display driving circuit according to an embodiment of the present application.
  • FIG. 5 is a partial structural schematic diagram of an LED display panel according to an embodiment of the present application.
  • FIG. 6 is a schematic partial structure diagram of another LED display panel according to an embodiment of the present application.
  • FIG. 7 is a schematic partial structure diagram of still another LED display panel according to an embodiment of the present application.
  • FIG. 8 is a partial structural schematic diagram of still another LED display panel according to an embodiment of the present application.
  • FIG. 9 is a schematic structural diagram of a display device according to an embodiment of the present application.
  • FIG. 10 is a schematic flowchart of a display driving method according to an embodiment of the present application.
  • FIG. 1A is a schematic structural diagram of a display driving circuit 10 according to an embodiment of the present application.
  • the display driving circuit 10 includes: an interface circuit 11 , a command processing circuit 12 , a buffer circuit 13 , a current source circuit 15 , a channel grayscale control circuit 17 and a channel current control circuit 19 .
  • the interface circuit 11 is used for acquiring multiple grayscale data and multiple current gain data.
  • the command processing circuit 12 is electrically coupled to the interface circuit 11 , and includes, for example, a configuration register and circuit logic for responding to commands.
  • the buffer circuit 13 is electrically coupled to the interface circuit 11 for buffering the plurality of grayscale data and the plurality of current gain data.
  • the current source circuit 15 is electrically coupled to the command processing circuit 12 and includes a plurality of channel current sources.
  • the channel grayscale control circuit 17 is electrically coupled to the command processing circuit 12, the buffer circuit 13 and the current source circuit 15, and is used to control the currents of the channels according to the grayscale data. How long the source is open.
  • the channel current control circuit 19 is electrically coupled to the buffer circuit 13 and the current source circuit 15, and is configured to respectively control the output currents of the plurality of channel current sources according to the plurality of current gain data.
  • the display driving circuit 10 By designing the display driving circuit 10 in this embodiment, it can acquire grayscale data and current gain data, and can control the on-time of the current source of each channel based on the grayscale data, and control each channel based on the current gain data
  • the output current of the current source can be adjusted dynamically, so that the channel current can be dynamically adjusted; in this way, the grayscale data can be improved by reducing the output current, that is, the display bit depth can be improved.
  • the display effect of the LED display device is related to the refresh rate and the driving current of each gray scale, by reducing the driving current of the display point such as the LED light point and increasing the gray scale data at a low gray scale, the low brightness can be effectively improved. Grayscale refresh rate at low grayscale.
  • the interface circuit 11 , the command processing circuit 12 , the buffer circuit 13 , the current source circuit 15 , the channel grayscale control circuit 17 and the channel current control circuit 19 It can be integrated in the same chip to improve the integration of the entire display driving circuit 10 , but the present application is not limited to this.
  • the interface circuit 11 includes, for example, a shift register circuit 111 and is used to access the data clock signal DCLK, the latch signal LE and the serial data DIN[2:0].
  • the shift register circuit 111 is used for receiving the serial data to obtain the plurality of grayscale data and the plurality of current gain data, and is controlled by the data clock signal DCLK and the latch signal LE .
  • the shift register circuit 111 of this embodiment includes a shift register (Shift Register) and circuit logic for command response and data transfer (eg, DMA transfer).
  • DMA here is the abbreviation of Direct Memory Access, and the Chinese name is direct memory access.
  • the command processing circuit 12 is electrically coupled to the shift register circuit 111 and is controlled by the data clock signal DCLK and the latch signal LE.
  • the buffer circuit 13 is electrically coupled to the shift register circuit 111 to acquire the plurality of grayscale data and the plurality of current gain data.
  • the cache circuit 13 of this embodiment includes a SRAM (Static Random Access Memory, static random access memory) buffer memory and a RAM controller (RAM Controller).
  • the buffer circuit 13 is configured with two independent storage areas, a grayscale data storage area 131 and a current gain data storage area 133, for storing the plurality of grayscale data and the plurality of current gains respectively.
  • grayscale data and current gain data are stored separately, which is beneficial to simplify data read and write operations.
  • each of the grayscale data storage area 131 and the current gain data storage area 133 is further divided into two storage sub-areas, which are used for frame-by-frame buffering of grayscale data or current in a ping-pong storage manner.
  • Gain data both the grayscale data and the current gain data adopt the ping-pong storage method, which is beneficial to improve the processing speed and performance of the display driving circuit 10.
  • the grayscale data and the current gain data can also be Other storage methods are used to access data, and ping-pong storage is not limited here.
  • the channel grayscale control circuit 17 accepts the control of the data clock signal DCLK, which includes, for example, a frequency multiplier circuit 171, a counter 172, a grayscale breaking processing circuit 173, an output buffer (Output Buffer) 174 and a plurality of comparisons Comparator 175.
  • the frequency multiplying circuit 171 is used for multiplying the data clock signal DCLK to obtain the grayscale clock signal GCLK.
  • the frequency multiplier circuit 171 of this embodiment includes a PLL (Phase Locked Loop) circuit or a PLL-like circuit, which can, for example, generate a grayscale clock signal GCLK of 160 MHz through frequency multiplication processing, but this embodiment does not Not limited to this.
  • the frequency multiplier circuit 171 in this embodiment uses the data clock signal DCLK as the input clock signal for generating the grayscale clock signal GCLK, which can reduce the number of input ports of the display driving circuit 10 .
  • the counter 172 is electrically coupled to the command processing circuit 12 and the frequency multiplying circuit 171, and is used for receiving the grayscale clock signal GCLK and generating a grayscale clock count value under the control of the grayscale clock signal GCLK.
  • the counter 172 in this embodiment is mainly used to count the pulses of the grayscale clock signal GCLK, which may be a 16-bit counter (16-bit Counter), but this embodiment is not limited thereto.
  • the counter 172 is configured by the command processing circuit 12. For example, when the gray clock count value is cleared to 1024, the gray clock count value of the counter 172 reaches 1024, then the counter 172 is reset to zero and starts counting again. Or when the reset value of the gray clock count is 256, the gray clock count value of the counter 172 reaches 256 and then resets and starts counting again.
  • the reset value of the gray clock count in this embodiment is not limited to those listed above. numerical value.
  • the gray scale breaking processing circuit 173 is electrically coupled to the command processing circuit 12 and the counter 172, and is used to accept the control of the command processing circuit 12, thereby controlling the counting operation of the counter 172 and generating gray scales Packet control signal.
  • the gray scale breaking processing circuit 173 is, for example, a processing circuit capable of running a gray scale breaking algorithm, and typically includes a memory storing the code of the gray scale breaking algorithm, and a memory that is electrically coupled to the memory and used for A processor that executes the code of the grayscale scattering algorithm; the grayscale scattering processing circuit 173 can generate grayscale according to the grayscale data scattering mode configured for it by the command processing circuit 12 and the grayscale depth that needs to be realized
  • the control signal is displayed in groups; as for the grayscale scattering algorithm, an existing mature algorithm can be used, and details are not repeated here.
  • the display control data of a single LED pixel includes red (R) component display control data and green (G) component display control data.
  • Control data and blue (B) component display control data single-color component display control data, for example, includes 16bit grayscale data and 8bit current gain data; for 16bit grayscale data, it can be divided into 64 according to the grayscale scattering algorithm.
  • 16 grayscale groups can be achieved through 64 grayscale groups; or, if the grayscale of a single grayscale grouping is 1024 If the degree level is set to 256, the display of 16-bit grayscale data needs to be divided into 256 grayscale groups; of course, the number of grayscale groups and the grayscale level of a single grayscale group in this embodiment are not limited to the values listed above.
  • the output buffer 174 is electrically coupled to the plurality of channel current sources 151 of the current source circuit 15 .
  • the plurality of comparators 175 are electrically coupled to the buffer circuit 13 , the counter 172 , the gray scale breaking processing circuit 173 and the output buffer 174 , and are used to obtain the data from the buffer circuit 13 respectively.
  • the plurality of grayscale data is generated, and a plurality of grayscale display control signals are generated under the control of the grayscale clock count value and the grayscale grouping control signal, and are respectively transmitted to the plurality of channels via the output buffer 174
  • the current source 151 is used to control the turn-on duration of the current source 151 of each channel.
  • the display driving circuit 10 has, for example, 96 output channels DOUT[95:0], so that 96 columns of LED light points (display points) can be loaded/driven; For example, one LED pixel is formed by 1 LED light points, then it can carry 32 columns of RGB full-color LED pixels, that is, 96 output channels DOUT[95:0] are divided into 32 red (R) component output channels, 32 Green (G) component output channel and 32 blue (B) component output channels.
  • the current source circuit 15 also includes, for example, an R-component global current gain regulator 15R, a G-component global current gain regulator 15G and B Component global current gain adjuster 15B.
  • the R-component global current gain regulator 15R is electrically coupled to multiple channels of the multiple-channel current sources 151 for carrying red (R-component) sub-pixels (or display points such as LED light points) a current source
  • the G-component global current gain regulator 15G is electrically coupled to the plurality of channel current sources for carrying green (G-component) sub-pixels among the plurality of channel current sources 151
  • the B-component global current The gain adjuster 15B is electrically coupled to the plurality of channel current sources for carrying blue (B component) sub-pixels among the plurality of channel current sources 151 .
  • the channel current control circuit 19 includes a plurality of channel current gain regulators 191, and the plurality of channel current gain regulators 191 are respectively electrically coupled to the plurality of channel current sources 151, and respectively receive the plurality of currents Gain data control.
  • the R-component global current gain regulator 15R is electrically coupled to the 96 output channels DOUT[95:0]
  • the 32 red output channels such as DOUT2, ..., DOUT95
  • the G component global current gain regulator 15G is electrically coupled to the 32 green output channels in the 96 output channels DOUT[95:0], such as DOUT1, ... , DOUT94
  • the B-component global current gain regulator 15G is electrically coupled to 32 blue output channels such as DOUT0, . . . , DOUT93 in the 96 output channels DOUT[95:0].
  • the three color component global current gain adjusters such as the R component global current gain adjuster 15R, the G component global current gain adjuster 15G, and the B component global current gain adjuster 15B, can be connected to external resistors respectively.
  • the plurality of channel current gain regulators 191 are 96 channel current gain regulators, which are controlled by corresponding current gain data to be respectively responsible for the single-channel current gain adjustment of the 96 output channels DOUT[95:0], and For example, each includes a resistor network controlled by the current gain data and electrically coupled to the corresponding channel current source 151 .
  • the current source circuit 15 can omit the global current gain regulators 15R, 15G and 15B.
  • the data clock signal DCLK at the data clock input terminal transmits the display control data of the R, G and B components in the serial data DIN[2:0] input from the serial data input terminal to the display control data.
  • the display drive circuit 10 collects 3 bits of display control data at the rising edge of each data clock signal DCLK, each of the R, G, and B components is 1 bit.
  • the storage signal LE converts the 3*16bit grayscale data + 3*8bit current contained in the 72bit display control data in the shift temporary storage circuit 111 through a combination command (usually the latch signal includes a rising edge of the data clock signal DCLK).
  • the gain data are respectively transferred to the grayscale data storage area 131 and the current gain data storage area 133 in the buffer circuit 13 .
  • the size of the grayscale data storage area 131 and the current gain data storage area 133 is associated with the number of output channels and the number of scan lines supported by the display driving circuit 10 .
  • a display drive circuit that supports 96 output channels (32 output channels for R, G, and B, respectively) and 64 scanning lines
  • the buffer circuit 13 of the display driving circuit 10 adopts the form of ping-pong operation, that is, when the grayscale data is displayed, the complete grayscale data of the previous frame is used. Buffer input of data is performed, so the size of the grayscale data storage area 131 and the current gain data storage area 133 are 192Kb and 96Kb, respectively, for storing two frames of complete grayscale data and current gain data.
  • the display driving circuit 10 In order to display synchronously with the display data of the front-end video source, the display driving circuit 10 also has corresponding synchronous display processing.
  • the display driving circuit 10 will switch the ping-pong data in the buffer circuit 13, and switch the display control data (including grayscale data and current gain data) completed by the previous frame buffering.
  • switch the storage sub-area of display control data that has been displayed to be coupled to the shift register circuit 111 to receive new display control data, and the Vsync command will clear the frequency multiplier circuit.
  • the grayscale clock signal GCLK generated by 171 is the grayscale clock count value of the counter 172 for pulse counting.
  • the display driving circuit 10 Before actually starting the grayscale display, the display driving circuit 10 needs to perform some working states such as the working mode and the global current gain according to the register data received by the command processing circuit 12 (for example, written into the configuration register via the shift temporary storage circuit 111 ).
  • Configuration At this time, the configuration content includes the grayscale data scattering mode, the grayscale depth to be realized, the global current gain, etc.
  • the register configuration is also distinguished by the combination commands of different data clock signals DCLK and latch signals LE.
  • the display driving circuit 10 starts to realize grayscale. To light up an LED light point, there is already a matching row driving current in the periphery, and the display driving circuit 10 needs to control the on/off of the output channel DOUT[95:0] according to the display control data of different lines to complete the LED light point. Lights up, but to realize the distinction of grayscale data, there are two parts associated, one is the output current size of the output channel, and the other is the opening time of the output channel.
  • the grayscale data of 1000 grayscale value is realized using PWM
  • the implementation method requires 1000 grayscale clock signal cycles.
  • the grayscale clock signal here is GCLK in Figure 1B.
  • the same grayscale data with 2000 grayscale values needs 2000 grayscale clock signal cycles.
  • different The grayscale data is converted to display lighting times of different time lengths; in this embodiment, the switching state of the output channel DOUT[95:0] of the display driving circuit 10 is It is controlled by the grayscale data and the grayscale clock count value, and the actual maximum brightness of the LED light point is controlled by the current gain data.
  • the resistors work together, and the external resistors are fixed after the LED display panel is determined. Therefore, the lighting brightness of the LED light points can be controlled by means of global current gain and current gain data.
  • the grayscale data of 10mA can be selected to light the time of 1000 grayscale clock signal cycles.
  • the current gain data coordinated control method proposed in this embodiment provides a new lighting method.
  • the same benchmark is to achieve
  • the grayscale data display effect of 1000 grayscale values can be achieved by reducing the current and increasing the grayscale data to achieve the same effect as the original 10mA and 1000 grayscale clock signal cycles.
  • the current can be reduced to 5mA, while Increase the number of cycles of the gray clock signal to 2000 cycles of the gray clock signal. This effect is close to the effect achieved by the previous one.
  • the current data can be reduced to 8mA, and the gray clock is lit.
  • the number of cycles of the signal is increased to 1200, and the effect can also be consistent.
  • the accurate realization mode conversion can be realized by collecting the current gain data and the realization relationship between the lighting effect and the grayscale data.
  • the grayscale scattering algorithm is used to display the grayscale data in groups, which can improve the refresh rate during grayscale realization, and can also prevent the grayscale clock signal when the refresh rate is not a grayscale clock signal. Problems such as the inability to achieve low ash caused by the integer multiple of the period.
  • the display driving circuit 10 of the embodiment of the present application is designed so that it can receive display control data including grayscale data and current gain data, and can control the on-time of each channel current source 151 based on the grayscale data. , and control the output current size of each channel current source 151 based on the current gain data, so that the dynamic adjustment of the channel current can be realized; in this way, the grayscale data can be improved by reducing the output current size (the driving current corresponding to the display point), That is, the display bit depth can be increased.
  • the display effect of the LED display device is related to the refresh rate and the driving current of each gray scale
  • the driving current of display points such as LED light points and increasing the gray scale data at low gray scales
  • the low brightness and low brightness can be effectively improved.
  • Grayscale refresh rate under gray the desired brightness value can be accurately obtained, thereby improving the display accuracy of the entire LED display device at low gray levels, so as to solve the problem of low brightness and low gray level transitions. Shun problem.
  • FIG. 2 is a schematic diagram of a specific structure of another display driving circuit 30 according to an embodiment of the present application.
  • the circuit structure of the display driving circuit 30 is basically the same as that of the display driving circuit 10 shown in FIGS. 1A and 1B , and also includes: an interface circuit 11 , a command processing circuit 12 , a buffer circuit 13 , and a current source circuit 15.
  • the channel grayscale control circuit 17 and the channel current control circuit 19; and the channel grayscale control circuit 17 includes a frequency multiplier circuit 171, a counter 172, a grayscale scattering processing circuit 173, an output buffer 174 and a plurality of comparators 175.
  • the interface circuit 11 in the display driving circuit 30 in this embodiment includes a shift temporary storage circuit 111 and is used to access the data clock signal DCLK, the latch signal LE, the serial data DIN[2:0] and different the second clock signal CLK based on the data clock signal DCLK;
  • the shift temporary storage circuit 111 is used for receiving the serial data DIN[2:0] to obtain the plurality of grayscale data and the plurality of current gain data and is controlled by the data clock signal DCLK and the latch signal LE;
  • the command processing circuit 12 is electrically coupled to the shift register circuit 111 and accepts the data clock signal DCLK and the control of the latch signal LE;
  • the buffer circuit 13 is electrically coupled to the shift temporary storage circuit 111 to obtain the plurality of grayscale data and the plurality of current gain data; and the channel grayscale control circuit 17 is controlled by the second clock signal CLK.
  • the frequency multiplier circuit 171 of this embodiment adopts another clock signal CLK not used for the data clock signal DCLK as the input clock signal for generating the grayscale clock signal GCLK, which makes the generation of the grayscale clock signal GCLK no longer limited by the data clock signal DCLK, which improves the flexibility of grayscale clock signal GCLK generation.
  • the clock CLK can be generated by an external crystal oscillator circuit.
  • FIG. 3 is a schematic diagram of a specific structure of still another display driving circuit 50 according to an embodiment of the present application.
  • the internal circuit structure of the display driving circuit 50 is basically the same as the circuit structure of the display driving circuit 10 shown in FIGS. 1A and 1B , and also includes: an interface circuit 11 , a command processing circuit 12 , a buffer circuit 13 , and a current source
  • the circuit 15 , the channel grayscale control circuit 17 and the channel current control circuit 19 for the connection relationship between these circuits and their respective structures and functions, reference may be made to the relevant descriptions in the foregoing first embodiment, which will not be repeated here.
  • the channel grayscale control circuit 17 in the display driving circuit 50 of this embodiment includes a counter 172, a grayscale breakup processing circuit 173, an output buffer 174 and a plurality of comparators 175, that is, the frequency multiplication circuit is omitted. 171.
  • the interface circuit 11 in the driving circuit 50 includes a shift temporary storage circuit 111 and is used to access the data clock signal DCLK, the latch signal LE, the serial data DIN[2:0] and different The grayscale clock signal GCLK of the data clock signal DCLK;
  • the shift temporary storage circuit 111 is used to receive the serial data DIN[2:0] to obtain the multiple grayscale data and the multiple current gains data and is controlled by the data clock signal DCLK and the latch signal LE;
  • the command processing circuit 12 is electrically coupled to the shift register circuit 111 and accepts the data clock signal DCLK and the latch control of the signal LE;
  • the buffer circuit 13 is electrically coupled to the shift register circuit 111 to obtain the plurality of grayscale data and the plurality of current gain data;
  • the channel grayscale control circuit 17 accepts control of the grayscale clock signal GCLK.
  • the channel grayscale control circuit 17 in this embodiment uses an external grayscale clock signal GCLK, so the frequency multiplier circuit 171 can be omitted.
  • FIG. 4 is a schematic diagram of a specific structure of another display driving circuit 70 according to an embodiment of the present application.
  • the circuit structure of the display driving circuit 70 is basically the same as that of the display driving circuit 10 shown in FIGS. 1A and 1B , and also includes: an interface circuit 11 , a command processing circuit 12 , a buffer circuit 13 , and a current source circuit 15.
  • the channel grayscale control circuit 17 and the channel current control circuit 19; and the channel grayscale control circuit 17 includes a frequency multiplier circuit 171, a counter 172, a grayscale scattering processing circuit 173, an output buffer 174 and a plurality of comparators 175.
  • the display driving circuit 70 of this embodiment further includes: a scanning control circuit 59, which is electrically coupled to the gray scale breaking processing circuit 173 in the channel gray scale control circuit 17, and is used to sequentially generate a plurality of For line scan signals, for example, it has 64 output channels LINE[63:0] to sequentially output 64 line scan signals.
  • the scan control circuit 59 is integrated into the display driving circuit 70 , which can effectively improve the integration of the display driving circuit 70 and reduce the complexity of PCB design when designing an LED display panel.
  • the scanning control circuit 59 As for the working principle of the scanning control circuit 59, for example, since the gray scale realization of the display driving circuit 70 is controlled by the gray scale breaking processing circuit 173 and the counter 172, for example, after the gray scale breaking algorithm is turned on, each time To achieve a set number such as 256 grayscale clock signal cycles, the line wrapping will start. At this time, the scan control circuit 59 needs to be notified to perform a line wrapping operation. Of course, since the grayscale data is stored in order in the display driver circuit 70, it is also implemented according to the order. The scanning sequence is implemented. At this time, the scanning control circuit 59 (for example, from the gray scale breaking processing circuit 173 ) receives a simple logic, and can perform the accumulation operation and the clearing operation to complete the output of the scanning signal.
  • FIG. 5 is a schematic diagram of a partial structure of an LED display panel according to an embodiment of the present application.
  • the LED display panel 400 includes: a pixel array PA, a display driving circuit 10 and a scan control chip 420 .
  • the pixel array PA includes 32 columns of pixels P, and each pixel P includes a plurality of different color LEDs such as R, G, B three primary color LED light points, so the pixel array PA has 96 columns of LED light points.
  • the 96 columns of LED light points are respectively electrically coupled to the 96 output channels DOUT0 - DOUT95 of the display driving circuit 10
  • the pixels P in each column are electrically coupled to three adjacent output channels of the display driving circuit 10 .
  • the pixel array PA includes 64 rows of pixels P, and the 64 rows of pixels P are respectively electrically coupled to the 64 output channels LINE0 - LINE63 of the scan control chip 420 .
  • the scan control chip 420 of this embodiment includes, for example, a row decoding chip, which can cooperate with the display driving circuit 10 to sequentially generate 64 row scan signals (or scan drive signals) in each round of 64 scans.
  • the output channels of the scan control chip 420 of the present embodiment are not limited to 64, and can also be other numbers such as 32, etc., and the specific number can be determined according to actual application requirements.
  • the display driving circuit 10 of the present embodiment receives inputs of the data clock signal DCLK, the serial data DIN[2:0], and the latch signal LE.
  • FIG. 6 is a schematic partial structure diagram of another LED display panel according to an embodiment of the present application.
  • the LED display panel 600 includes: a pixel array PA, a display driving circuit 30 and a scan control chip 420 .
  • the pixel array PA includes 32 columns of pixels P, and each pixel P includes a plurality of different color LEDs such as R, G, B three primary color LED light points, so the pixel array PA has 96 columns of LED light points.
  • the 96 columns of LED light points are respectively electrically coupled to the 96 output channels DOUT0 - DOUT95 of the display driving circuit 30 , and the pixels P in each column are electrically coupled to three adjacent output channels of the display driving circuit 30 .
  • the pixel array PA includes 64 rows of pixels P, and the 64 rows of pixels P are respectively electrically coupled to the 64 output channels LINE0 - LINE63 of the scan control chip 420 .
  • the scan control chip 420 in this embodiment includes, for example, a row decoding chip, which can cooperate with the display driving circuit 30 to sequentially generate 64 row scan signals (or scan drive signals) in each round of 64 scans. It should be noted that the output channels of the scan control chip 420 in this embodiment are not limited to 64, and may also be other numbers such as 32, and the specific number may be determined according to actual application requirements.
  • the display driving circuit 30 of the present embodiment receives the input of the data clock signal DCLK, the serial data DIN[2:0], the latch signal LE, and the second clock signal CLK for generating the grayscale clock signal GCLK.
  • FIG. 7 is a schematic partial structure diagram of still another LED display panel according to an embodiment of the present application.
  • the LED display panel 800 includes: a pixel array PA, a display driving circuit 50 and a scan control chip 420 .
  • the pixel array PA includes 32 columns of pixels P, and each pixel P includes a plurality of different color LEDs such as R, G, B three primary color LED light points, so the pixel array PA has 96 columns of LED light points.
  • the 96 columns of LED light points are respectively electrically coupled to the 96 output channels DOUT0 - DOUT95 of the display driving circuit 50 , and the pixels P in each column are electrically coupled to three adjacent output channels of the display driving circuit 50 .
  • the pixel array PA includes 64 rows of pixels P, and the 64 rows of pixels P are respectively electrically coupled to the 64 output channels LINE0 - LINE63 of the scan control chip 420 .
  • the scan control chip 420 of this embodiment includes, for example, a row decoding chip, which can cooperate with the display driving circuit 50 to sequentially generate 64 row scan signals (or scan drive signals) in each round of 64 scans. It should be noted that the output channels of the scan control chip 420 in this embodiment are not limited to 64, and may also be other numbers such as 32, and the specific number may be determined according to actual application requirements.
  • the display driving circuit 50 of the present embodiment receives inputs of the data clock signal DCLK, the serial data DIN[2:0], the latch signal LE, and the grayscale clock signal GCLK.
  • FIG. 8 is a schematic partial structure diagram of another LED display panel provided by an embodiment of the present application.
  • the LED display panel 1000 includes: a pixel array PA and a display driving circuit 70 .
  • the pixel array PA includes 32 rows of pixel points P, and each pixel point P includes a plurality of different color LEDs such as R, G, B three primary color LED light points, so the pixel array PA has 96 columns of LED light points.
  • the 96 columns of LED light points are respectively electrically coupled to the 96 output channels DOUT0 - DOUT95 of the display driving circuit 70 , and the pixel point P in each column is electrically coupled to three adjacent output channels of the display driving circuit 70 .
  • the pixel array PA includes 64 rows of pixels P, and the 64 rows of pixels P are respectively electrically coupled to the 64 output channels LINE0 - LINE63 of the display driving circuit 70 .
  • the display driving circuit 70 of this embodiment integrates a scan control circuit 59 (as shown in FIG. 4 ), which can sequentially generate 64 line scan signals (or scan drive signals) in each round of 64 scans. It should be noted that the output channels of the line scan signal of the display driving circuit 70 in this embodiment are not limited to 64, and may also be other numbers such as 32, and the specific number can be determined according to actual application requirements.
  • FIG. 9 is a schematic structural diagram of a display device according to an embodiment of the present application.
  • the display device 900 includes: a front-end display control card 901 and an LED display panel 903 .
  • the front-end display control card 901 is used for outputting display control data including grayscale data and current gain data
  • display control data including grayscale data and current gain data
  • a hardware structure similar to a receiving card, a scanning card or a module controller that is mature in the field of LED display control technology is used, That is to say, a programmable logic device such as an FPGA (Field Programmable Gate Array, Field Programmable Gate Array) device is used as the image processor; but the image processor of this embodiment can directly output all data including grayscale data and current gain data.
  • the display control data, or an FPGA device or an ASIC (Application Specific Integrated Circuit) device is added at the back end of the image processor to convert the grayscale data output by the image processor into grayscale data. and current gain data for the display control data.
  • the LED display panel 903 may adopt the LED display panel 400 , 600 , 800 or 1000 described in the fifth embodiment, the sixth embodiment, the seventh embodiment or the eighth embodiment, and the display driving circuit included in the display driving circuit is electrically
  • the front-end display control card 901 is coupled to receive the display control data to realize image display.
  • the display device 900 of this embodiment may be an LED display box including a front-end display control card 901 and one or more LED display panels 903 , but this is only an example and is not intended to limit the embodiment of the present application.
  • the display device 900 of this embodiment can realize dynamic adjustment of the channel current, which is beneficial to increase the display bit depth, improve the grayscale refresh rate under low brightness and low gray, and improve the display accuracy of the entire LED display device under low gray to solve the problem of low grayscale.
  • FIG. 10 is a schematic flowchart of a display driving method provided by an embodiment of the present application. As shown in FIG. 10 , the display driving method of this embodiment includes, for example, the following steps:
  • S150 Control the ON durations of the current sources of the multiple channels respectively according to the multiple grayscale data
  • S170 Control the magnitudes of the output currents of the multiple channel current sources respectively according to the multiple current gain data.
  • the display driving method of this embodiment can realize dynamic adjustment of channel current, which is beneficial to increase the display bit depth, improve the grayscale refresh rate in low brightness and low gray, and improve the display accuracy of the entire LED display device in low gray. In order to solve the problem of uneven grayscale transition in low light and low gray.
  • the step S150 includes: (i) receiving a grayscale clock signal, and generating a grayscale clock count value under the control of the grayscale clock signal; (ii) based on a grayscale scattering algorithm Controlling the counting operation of the counter and generating a grayscale grouping control signal; and (iii) respectively acquiring the plurality of grayscale data and generating under the control of the grayscale clock count value and the grayscale grouping control signal
  • a plurality of grayscale display control signals are respectively transmitted to the plurality of channel current sources to control the on-time of the plurality of channel current sources.
  • this embodiment can evenly disperse the high gray part and the low gray part, so that in some scenes where the grayscale is not fully realized, it can also ensure that most of the grayscale can be realized as much as possible. .
  • the step S150 further includes: performing frequency multiplication processing on the input clock signal to generate the grayscale clock signal.
  • the frequency doubling processing in this embodiment is beneficial to increase the elasticity of the generation of the grayscale clock signal.
  • the step S170 includes: respectively controlling the output currents of the multiple channel current sources according to multiple point-by-point current gain data.
  • the use of point-by-point current gain data in this embodiment enables the same channel current source to use the current gain data corresponding to the different display points when driving different display points (such as LED light points), which is beneficial to improve The accuracy of the current dynamic adjustment.
  • the step S130 includes: buffering point-by-point grayscale data frame by frame in a ping-pong storage manner; and buffering point-by-point current gain data frame by frame in a ping-pong storage manner.
  • Both the grayscale data and the current gain data in this embodiment adopt a ping-pong storage method, which is beneficial to improve processing speed and performance.
  • the step S170 includes: respectively controlling the output currents of the multiple channel current sources according to multiple channel-by-channel current gain data.
  • the use of the channel-by-channel current gain data in this embodiment can make the current gain data used by the same channel current source in different display frames different, and at least it can realize frame-by-frame current dynamic adjustment.
  • a single display driving circuit can complete the grayscale realization of multiple color components, but the embodiments of the present application are not limited to this, and a single display driving circuit can also be used as an example.
  • the display driving circuit is designed to only complete the grayscale realization of a single color component, so that the grayscale data of the three color components of R, G, and B can be realized by using three display driving circuits respectively.
  • the disclosed system, apparatus and method may be implemented in other manners.
  • the device embodiments described above are only illustrative.
  • the division of units is only a logical function division. In actual implementation, there may be other division methods.
  • multiple units or components may be combined or integrated. to another system, or some features can be ignored, or not implemented.
  • the shown or discussed mutual coupling or direct coupling or communication connection may be through some interfaces, indirect coupling or communication connection of devices or units, and may be in electrical, mechanical or other forms.
  • Units described as separate components may or may not be physically separated, and components shown as units may or may not be physical units, that is, may be located in one place, or may be distributed over multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution in this embodiment.
  • each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically alone, or two or more units may be integrated into one unit.
  • the above-mentioned integrated units can be implemented in the form of hardware, or can be implemented in the form of hardware plus software functional units.
  • the above-mentioned integrated units implemented in the form of software functional units can be stored in a computer-readable storage medium.
  • the above-mentioned software functional unit is stored in a storage medium, and includes several instructions to cause a computer device (which may be a personal computer, a server, or a network device, etc.) to execute some steps of the methods of various embodiments of the present application.
  • the aforementioned storage medium includes: U disk, mobile hard disk, Read-Only Memory (ROM for short), Random Access Memory (RAM for short), magnetic disk or CD, etc. that can store program codes medium.
  • a display driving circuit in the embodiment of the present application, it can acquire grayscale data and current gain data, and can control the on-time of the current source of each channel based on the grayscale data, and control each channel based on the current gain data
  • the output current of the current source can dynamically adjust the channel current; in this way, the grayscale data can be improved by reducing the output current (corresponding to the driving current of the display point), that is, the display bit depth can be improved.
  • the display effect of the LED display device is related to the refresh rate and the driving current of each gray scale, by reducing the driving current of the display point such as the LED light point and increasing the gray scale data at a low gray scale, the low brightness can be effectively improved. Grayscale refresh rate at low grayscale.
  • the desired brightness value can be accurately obtained, thereby improving the display accuracy of the entire LED display device at low gray levels, so as to solve the problem of uneven grayscale transition in low brightness and low gray levels. The problem.

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Abstract

一种显示驱动电路(10)及方法、以及LED显示板(400)和显示装置(900)。显示驱动电路(10)包括：接口电路(11)，用于获取多个灰度数据和多个电流增益数据；命令处理电路(12)，耦接接口电路(11)；缓存电路(13)，耦接接口电路(11)，用于缓存多个灰度数据和多个电流增益数据；电流源电路(15)，耦接命令处理电路(12)且包括多个通道电流源(151)；通道灰度控制电路(17)，耦接命令处理电路(12)、缓存电路(13)和电流源电路(15)，用于根据多个灰度数据分别控制多个通道电流源(151)的打开时长；以及通道电流控制电路(19)，耦接缓存电路(13)和电流源电路(15)，用于根据多个电流增益数据分别控制多个通道电流源(151)的输出电流大小。因此，可以实现通道电流动态调节以提升显示位深。

Description

显示驱动电路及方法、LED显示板和显示装置 技术领域
本申请涉及显示控制技术领域，尤其涉及一种显示驱动电路，一种LED显示板、一种显示装置以及一种显示驱动方法。
背景技术
目前LED(Light Emitting Diode，发光二极管)显示装置因其成本低、功耗小、可视性高、组装自由等优点被应用到各种领域。同时，随着LED显示装置应用的普及，人们对其显示质量的要求也越来越高，因此如何提升LED显示装置的显示质量已成为该领域的研究热点。
随着LED的应用场景越来越多，LED的亮度可调节性和普适性越来越被关注。LED可以应用于户外的高亮屏，也可以应用于室内的低亮会议屏；越来越多的客户需要LED显示装置能够根据自身的需求来调节亮度。现有的一种基于灰度时钟信号GCLK的十六输出通道PWM(Pulse Width Modulation，脉冲宽度调制)型LED显示驱动芯片，其通道控制电路典型地包括与十六个输出通道分别对应的多个比较器、与所述十六个输出通道分别对应的多个电流源、电性耦接在所述多个比较器与所述多个电流源之间的输出缓存器和电性耦接所述多个电流源的全局电流增益调节器。由于采用PWM驱动控制方式，且其所应用的LED显示装置的亮度在1000-20000nit之间，16bit的灰度数据只能被显示其中的10-14bit，所以单纯依靠PWM驱动控制方式难以实现有效提升显示位深的效果。再者，随着小间距LED显示装置的逐渐普及，室内小间距显示装置的亮度普遍控制在100-1000nit之间，而现有的PWM型LED显示驱动芯片在一些需要调暗LED亮度的场景下，由于其内置的灰度打散算法中低灰数据往往只出现一次较短的显示时间，导致经常会出现低亮低灰下灰阶过渡不顺或者低灰刷新率低等问题。
发明内容
因此，为克服现有技术中存在的至少部分缺陷和不足，本申请实施例提供一种显示驱动电路、一种LED显示板、一种显示装置以及一种显示驱动方法。
具体地，本申请实施例提供的一种显示驱动电路，包括：接口电路，用于获取多个灰度数据和多个电流增益数据；命令处理电路，电性耦接所述接口电路； 缓存电路，电性耦接所述接口电路，用于缓存所述多个灰度数据和所述多个电流增益数据；电流源电路，电性耦接所述命令处理电路且包括多个通道电流源；通道灰度控制电路，电性耦接所述命令处理电路、所述缓存电路和所述电流源电路，用于根据所述多个灰度数据分别控制所述多个通道电流源的打开时长；以及通道电流控制电路，电性耦接所述缓存电路和所述电流源电路，用于根据所述多个电流增益数据分别控制所述多个通道电流源的输出电流大小。
本申请实施例通过对显示驱动电路进行设计，其可以获取灰度数据和电流增益数据，并能够基于所述灰度数据控制各个通道电流源的打开时长、以及基于所述电流增益数据控制各个通道电流源的输出电流大小，从而可以实现通道电流动态调节；如此一来可以通过降低输出电流大小(对应显示点的驱动电流)来提高灰度数据，也即可以提升显示位深。再者，由于LED显示装置的显示效果与刷新率及每个灰阶的驱动电流相关，通过在低灰阶时降低显示点比如LED灯点的驱动电流并提高灰度数据，可以有效提高低亮低灰下的灰度刷新率。此外，通过降低输出电流大小且增大灰度数据，可以准确地得到想要的亮度值，进而提升整个LED显示装置低灰下的显示精准度，以解决低亮低灰下灰阶过渡不顺的问题。
在本申请的一个实施例中，所述接口电路包括移位暂存电路且用于接入数据时钟信号、锁存信号和串行数据；所述移位暂存电路用于接收所述串行数据以获取所述多个灰度数据和所述多个电流增益数据且接受所述数据时钟信号及所述锁存信号的控制；所述命令处理电路电性耦接所述移位暂存电路且接受所述数据时钟信号及所述锁存信号的控制；所述缓存电路电性耦接所述移位暂存电路以获取所述多个灰度数据和所述多个电流增益数据；以及，所述通道灰度控制电路接受所述数据时钟信号的控制。本实施例的接口电路可以实现灰度数据及电流增益数据的串行输入输出，其有利于多个显示驱动电路之间的级联；并且所述通道灰度控制电路接受所述数据时钟信号的控制有利于减少所述接口电路的输入端口数量。
在本申请的一个实施例中，所述通道灰度控制电路包括：计数器，电性耦接所述命令处理电路，用于接收灰度时钟信号、并在所述灰度时钟信号的控制下产生灰度时钟计数值；灰度打散处理电路，电性耦接所述命令处理电路和所述计数器，用于接收所述命令处理电路的控制以控制所述计数器的计数操作以及产生灰度分组控制信号；输出缓冲器，电性耦接所述电流源电路的所述多个通道电流源；以及多个比较器，电性耦接所述缓存电路、所述计数器、所述灰度打散处理电路 和所述输出缓冲器，用于分别从所述缓存电路获取所述多个灰度数据、并在所述灰度时钟计数值和所述灰度分组控制信号的控制下产生多个灰度显示控制信号经由所述输出缓冲器分别传送至所述多个通道电流源。本实施例中灰度打散处理电路的采用有利于将高灰部分与低灰部分进行均匀打散分布，这样在某些灰度实现不完整的场景下，还能尽可能的保证大部分灰度可以得以实现。
在本申请的一个实施例中，所述通道灰度控制电路还包括：倍频电路，电性耦接所述计数器，用于产生所述灰度时钟信号并传送至所述计数器。本实施例中倍频电路的采用有利于增大灰度时钟信号产生的弹性。
在本申请的一个实施例中，所述电流源电路还包括多个颜色分量全局电流增益调节器，且每一个所述颜色分量全局电流增益调节器电性耦接所述多个通道电流源中用于带载相同颜色亚像素的多个通道电流源；所述通道电流控制电路包括多个通道电流增益调节器，且所述多个通道电流增益调节器分别电性耦接所述多个通道电流源、并分别接受所述多个电流增益数据的控制。本实施例中，颜色分量全局电流增益调节器的设置有利于相同颜色亚像素的通道电流源的全局调节。
在本申请的一个实施例中，所述接口电路包括移位暂存电路且用于接入数据时钟信号、锁存信号、串行数据和不同于所述数据时钟信号的第二时钟信号；所述移位暂存电路用于接收所述串行数据以获取所述多个灰度数据和所述多个电流增益数据且接受所述数据时钟信号和所述锁存信号的控制；所述命令处理电路电性耦接所述移位暂存电路且接受所述数据时钟信号及所述锁存信号的控制；所述缓存电路电性耦接所述移位暂存电路以获取所述多个灰度数据和所述多个电流增益数据；以及，所述通道灰度控制电路接受所述第二时钟信号的控制。本实施例的接口电路可以实现灰度数据及电流增益数据的串行输入输出，其有利于多个显示驱动电路之间的级联；并且通道灰度控制电路接受不同于数据时钟信号的第二时钟信号之控制，其可以使得灰度时钟信号的产生不再受限于数据时钟信号，提升了灰度时钟信号产生的灵活性。
在本申请的一个实施例中，所述显示驱动电路还包括：扫描控制电路，电性耦接所述通道灰度控制电路，用于依序产生多个行扫描信号。本实施例中，通过整合扫描控制电路，其能够有效提升显示驱动电路的集成度，在LED显示板设计时可以降低PCB(Printed Circuit Board，印刷电路板)设计的复杂度。
在本申请的一个实施例中，所述缓存电路包括灰度数据存储区和电流增益数 据存储区，所述灰度数据存储区用于缓存所述多个灰度数据，所述电流增益数据存储区用于缓存所述多个电流增益数据。本实施例将灰度数据和电流增益数据分开存储，其有利于简化数据读写操作。
在本申请的一个实施例中，所述灰度数据存储区包含两个存储子区域以用于采用乒乓存储方式逐帧缓存灰度数据，所述电流增益数据存储区包含两个存储子区域以用于采用乒乓存储方式逐帧缓存电流增益数据。本实施例的灰度数据和电流增益数据均采用乒乓存储方式，其有利于提升显示驱动电路的处理速度和性能。
在本申请的一个实施例中，所述接口电路、所述命令处理电路、所述缓存电路、所述电流源电路、所述通道灰度控制电路和所述通道电流控制电路整合于同一个芯片内。本实施例将各个电路整合于同一个芯片中，也即显示驱动电路芯片化，其有利于提升显示驱动电路的集成度。
在本申请的一个实施例中，所述多个电流增益数据为逐点电流增益数据，以使得所述多个通道电流源中同一个所述通道电流源在驱动不同显示点时采用与所述不同显示点分别对应的电流增益数据。本实施例的逐点电流增益数据有利于提升电流动态调节的精细度。
在本申请的一个实施例中，所述多个电流增益数据为逐通道电流增益数据，以使得所述多个通道电流源中同一个所述通道电流源在不同显示帧时采用的电流增益数据不同。本实施例中逐通道电路增益数据的采用，其至少可以实现逐帧电流动态调节。
再者，本申请实施例提供的一种LED显示板，包括：像素阵列，包括多个像素点且每一个所述像素点包括多个不同颜色LED；以及至少一个如前述任意一个实施例所述的显示驱动电路，其中所述显示驱动电路的所述多个通道电流源电性耦接所述像素阵列。
本实施例的LED显示板可以实现通道电流动态调节，其有利于提升显示位深、提高低亮低灰下的灰度刷新率、以及提升整个LED显示装置低灰下的显示精准度以解决低亮低灰下灰阶过渡不顺的问题。
此外，本申请实施例提供的一种显示装置，包括：前端显示控制卡，用于输出多个灰度数据和多个电流增益数据；以及如前所述的LED显示板，其中所述LED显示板的所述显示驱动电路电性耦接所述前端显示控制卡以接收所述多个灰度数据和所述多个电流增益数据。
本实施例的显示装置可以实现通道电流动态调节，其有利于提升显示位深、提高低亮低灰下的灰度刷新率、以及提升整个LED显示装置低灰下的显示精准度以解决低亮低灰下灰阶过渡不顺的问题。
另外，本申请实施例提供的一种显示驱动方法，包括：获取多个灰度数据和多个电流增益数据；缓存所述多个灰度数据和所述多个电流增益数据；根据所述多个灰度数据分别控制多个通道电流源的打开时长；以及根据所述多个电流增益数据分别控制所述多个通道电流源的输出电流大小。
本实施例的显示驱动方法可以实现通道电流动态调节，其有利于提升显示位深、提高低亮低灰下的灰度刷新率、以及提升整个LED显示装置低灰下的显示精准度以解决低亮低灰下灰阶过渡不顺的问题。
在本申请的一个实施例中，所述根据所述多个灰度数据分别控制多个通道电流源的打开时长，包括：接收灰度时钟信号、并在所述灰度时钟信号的控制下产生灰度时钟计数值；基于灰度打散算法控制所述计数器的计数操作以及产生灰度分组控制信号；分别获取所述多个灰度数据、并在所述灰度时钟计数值和所述灰度分组控制信号的控制下产生多个灰度显示控制信号分别传送至所述多个通道电流源，以控制所述多个通道电流源的打开时长。本实施例基于灰度打散算法可以将高灰部分与低灰部分进行均匀打散分布，这样在某些灰度实现不完整的场景下，还能尽可能的保证大部分灰度可以得以实现。
在本申请的一个实施例中，所述根据所述多个灰度数据分别控制多个通道电流源的打开时长，还包括：对输入时钟信号进行倍频处理以产生所述灰度时钟信号。本实施例的倍频处理有利于增大灰度时钟信号产生的弹性。
在本申请的一个实施例中，所述根据所述多个电流增益数据分别控制所述多个通道电流源的输出电流大小，包括：根据多个逐点电流增益数据分别控制所述多个通道电流源的输出电流大小。本实施例中逐点电流增益数据的采用，其可以使得同一个通道电流源在驱动不同显示点(比如LED灯点)时采用与所述不同显示点分别对应的电流增益数据，进而有利于提升电流动态调节的精准度。
在本申请的一个实施例中，所述缓存所述多个灰度数据和所述多个电流增益数据，包括：采用乒乓存储方式逐帧缓存逐点灰度数据；以及采用乒乓存储方式逐帧缓存逐点电流增益数据。本实施例的灰度数据和电流增益数据均采用乒乓存储方式，其有利于提升处理速度和性能。
在本申请的一个实施例中，所述根据所述多个电流增益数据分别控制所述多个通道电流源的输出电流大小，包括：根据多个逐通道电流增益数据分别控制所述多个通道电流源的输出电流大小。本实施例逐通道电流增益数据的采用，其可以使得同一个通道电流源在不同显示帧时采用的电流增益数据不同，其至少可以实现逐帧电流动态调节。
上述技术方案可以具有如下优点或有益效果：通过对显示驱动电路进行设计，其可以获取灰度数据和电流增益数据，并能够基于所述灰度数据控制各个通道电流源的打开时长、以及基于所述电流增益数据控制各个通道电流源的输出电流大小，从而可以实现通道电流动态调节；如此一来可以通过降低输出电流大小(对应显示点的驱动电流)来提高灰度数据，也即可以提升显示位深。再者，由于LED显示装置的显示效果与刷新率及每个灰阶的驱动电流相关，通过在低灰阶时降低显示点比如LED灯点的驱动电流并提高灰度数据，可以有效提高低亮低灰下的灰度刷新率。此外，通过降低输出电流大小且增大灰度数据，可以准确地得到想要的亮度值，进而提升整个LED显示装置低灰下的显示精准度，以解决低亮低灰下灰阶过渡不顺的问题。
附图说明
为了更清楚地说明本申请实施例的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1A为本申请实施例的一种显示驱动电路的结构示意图。
图1B为图1A所示显示驱动电路的一种具体结构示意图。
图1C为相关于图1A所示显示驱动电路中的电流源电路、通道灰度控制电路和通道电流控制电路的一种具体结构示意图。
图2为本申请实施例提供的另一种显示驱动电路的具体结构示意图。
图3为本申请实施例提供的再一种显示驱动电路的具体结构示意图。
图4为本申请实施例的又一种显示驱动电路的具体结构示意图。
图5为本申请实施例的一种LED显示板的部分结构示意图。
图6为本申请实施例的另一种LED显示板的部分结构示意图。
图7为本申请实施例的再一种LED显示板的部分结构示意图。
图8为本申请实施例的又一种LED显示板的部分结构示意图。
图9为本申请实施例的一种显示装置的结构示意图。
图10为本申请实施例的一种显示驱动方法的流程示意图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
【第一实施例】
图1A为本申请实施例提供的一种显示驱动电路10的结构示意图。如图1A所示，所述显示驱动电路10包括：接口电路11、命令处理电路12、缓存电路13、电流源电路15、通道灰度控制电路17和通道电流控制电路19。
其中，所述接口电路11用于获取多个灰度数据和多个电流增益数据。
所述命令处理电路12电性耦接所述接口电路11，其例如包括配置寄存器和用于响应命令的电路逻辑。
所述缓存电路13电性耦接所述接口电路11，用于缓存所述多个灰度数据和所述多个电流增益数据。
所述电流源电路15电性耦接所述命令处理电路12且包括多个通道电流源。
所述通道灰度控制电路17电性耦接所述命令处理电路12、所述缓存电路13和所述电流源电路15，用于根据所述多个灰度数据分别控制所述多个通道电流源的打开时长。
所述通道电流控制电路19电性耦接所述缓存电路13和所述电流源电路15，用于根据所述多个电流增益数据分别控制所述多个通道电流源的输出电流大小。
本实施例通过对显示驱动电路10进行设计，其可以获取灰度数据和电流增益数据，并能够基于所述灰度数据控制各个通道电流源的打开时长、以及基于所述电流增益数据控制各个通道电流源的输出电流大小，从而可以实现通道电流动态调节；如此一来可以通过降低输出电流大小来提高灰度数据，也即可以提升显示位深。再者，由于LED显示装置的显示效果与刷新率及每个灰阶的驱动电流相关，通过在低灰阶时降低显示点比如LED灯点的驱动电流并提高灰度数据，可以有效提高低亮低灰下的灰度刷新率。此外，通过降低输出电流大小且增大灰度数据， 可以准确地得到想要的亮度值，进而提升整个LED显示装置低灰下的显示精准度，以解决低亮低灰下灰阶过渡不顺的问题。另外，在本实施例中，所述接口电路11、所述命令处理电路12、所述缓存电路13、所述电流源电路15、所述通道灰度控制电路17和所述通道电流控制电路19可以整合于同一个芯片内，以提升整个显示驱动电路10的集成度，但本申请并不以此为限。
更具体地，参见图1B及图1C，所述接口电路11例如包括移位暂存电路111且用于接入数据时钟信号DCLK、锁存信号LE和串行数据DIN[2:0]。所述移位暂存电路111用于接收所述串行数据以获取所述多个灰度数据和所述多个电流增益数据且接受所述数据时钟信号DCLK及所述锁存信号LE的控制。举例来说，本实施例的移位暂存电路111包括移位暂存器(Shift Register)和命令响应及数据传输(比如DMA传输)用电路逻辑。此处的DMA为Direct Memory Access的缩写，中文名称为直接存储器存取。
所述命令处理电路12电性耦接所述移位暂存电路111且接受所述数据时钟信号DCLK及所述锁存信号LE的控制。
所述缓存电路13电性耦接所述移位暂存电路111以获取所述多个灰度数据和所述多个电流增益数据。举例来说，本实施例的缓存电路13包括SRAM(Static Random Access Memory，静态随机存取存储器)缓冲存储器以及RAM控制器(RAM Controller)。优选地，所述缓存电路13内配置有灰度数据存储区131和电流增益数据存储区133两个独立的存储区，以用于分别存储所述多个灰度数据和所述多个电流增益数据，此处将灰度数据和电流增益数据分开存储，其有利于简化数据读写操作。进一步地，灰度数据存储区131和电流增益数据存储区133中的每一者还区分为两个存储子区域，这两个存储子区域用于以乒乓存储方式逐帧缓存灰度数据或电流增益数据；这种灰度数据和电流增益数据均采用乒乓存储方式，有利于提升显示驱动电路10的处理速度和性能，当然本领域技术人员可以理解的是，灰度数据和电流增益数据也可以采用其他存储方式进行数据的存取，此处并不以乒乓存储作为限制。
所述通道灰度控制电路17接受所述数据时钟信号DCLK的控制，其例如包括：倍频电路171、计数器172、灰度打散处理电路173、输出缓冲器(Output Buffer)174和多个比较器(Comparator)175。
所述倍频电路171用于对数据时钟信号DCLK进行倍频处理以得到灰度时钟 信号GCLK。举例来说，本实施例的倍频电路171包括PLL(Phase Locked Loop，锁相环)电路或类PLL电路，其例如可以经由倍频处理产生160MHZ的灰度时钟信号GCLK，但本实施例并不以此为限。本实施例的倍频电路171采用数据时钟信号DCLK作为产生灰度时钟信号GCLK的输入时钟信号，其可以减少所述显示驱动电路10的输入端口数量。
所述计数器172电性耦接所述命令处理电路12和所述倍频电路171，用于接收灰度时钟信号GCLK、并在所述灰度时钟信号GCLK的控制下产生灰度时钟计数值。本实施例的计数器172主要用于对灰度时钟信号GCLK进行脉冲计数，其可以为16bit计数器(16-bit Counter)，但本实施例并不以此为限。再者，所述计数器172由所述命令处理电路12进行配置，例如当灰度时钟计数清零值为1024，所述计数器172的灰度时钟计数值达到1024则清零并重新开始计数，又或者当灰度时钟计数清零值为256，所述计数器172的灰度时钟计数值达到256则清零并重新开始计数，当然本实施例的灰度时钟计数清零值并不限于以上所列数值。
所述灰度打散处理电路173电性耦接所述命令处理电路12和所述计数器172，用于接受所述命令处理电路12的控制，进而控制所述计数器172的计数操作以及产生灰度分组控制信号。本实施例中，所述灰度打散处理电路173例如是能够运行灰度打散算法的处理电路，典型地包括存储有灰度打散算法代码的存储器和电性耦接所述存储器并用于执行所述灰度打散算法代码的处理器；所述灰度打散处理电路173可以根据所述命令处理电路12为其配置的灰度数据打散模式和需要实现的灰度深度产生灰度分组显示控制信号；至于灰度打散算法可以采用现有成熟的算法，在此不再赘述。再者，以所述显示驱动电路10应用于驱动控制红绿蓝(RGB)全彩LED像素为例，单个LED像素的显示控制数据包括红色(R)分量显示控制数据、绿色(G)分量显示控制数据和蓝色(B)分量显示控制数据，单颜色分量显示控制数据例如包含16bit灰度数据和8bit电流增益数据；对于16bit灰度数据，其可以根据灰度打散算法将其划分为64个灰度分组、且每一个灰度分组的灰度级为1024，这样通过64个灰度分组可以实现1024*64＝65536＝2 16个灰度级；又或者，若单个灰度分组的灰度级设为256，则16bit灰度数据的显示需要划分为256个灰度分组；当然本实施例的灰度分组数量以及单个灰度分组的灰度级并不限于以上所列数值。
所述输出缓冲器174电性耦接所述电流源电路15的多个通道电流源151。
所述多个比较器175电性耦接所述缓存电路13、所述计数器172、所述灰度打散处理电路173和所述输出缓冲器174，用于分别从所述缓存电路13获取所述多个灰度数据、并在所述灰度时钟计数值和所述灰度分组控制信号的控制下产生多个灰度显示控制信号经由所述输出缓冲器174分别传送至所述多个通道电流源151，以控制各个通道电流源151的打开时长。以所述显示驱动电路10作为一种LED显示驱动芯片为例，其例如具有96个输出通道DOUT[95:0]，从而可以带载/驱动96列LED灯点(显示点)；以RGB三个LED灯点构成一个LED像素为例，则其可以带载32列RGB全彩LED像素，也即96个输出通道DOUT[95:0]区分为32个红色(R)分量输出通道、32个绿色(G)分量输出通道和32个蓝色(B)分量输出通道。
再者，如图1C所示，所述电流源电路15除了包括所述多个通道电流源151之外，例如还包括R分量全局电流增益调节器15R、G分量全局电流增益调节器15G和B分量全局电流增益调节器15B。其中，所述R分量全局电流增益调节器15R电性耦接所述多个通道电流源151中用于带载红色(R分量)亚像素(或称显示点比如LED灯点)的多个通道电流源，所述G分量全局电流增益调节器15G电性耦接所述多个通道电流源151中用于带载绿色(G分量)亚像素的多个通道电流源，所述B分量全局电流增益调节器15B电性耦接所述多个通道电流源151中用于带载蓝色(B分量)亚像素的多个通道电流源。
所述通道电流控制电路19包括多个通道电流增益调节器191，且所述多个通道电流增益调节器191分别电性耦接所述多个通道电流源151、并分别接受所述多个电流增益数据的控制。
以图1C中显示驱动电路10配置有96个输出通道DOUT[95:0]为例，所述R分量全局电流增益调节器15R电性耦接所述96个输出通道DOUT[95:0]中的32个红色输出通道比如DOUT2、…、DOUT95，所述G分量全局电流增益调节器15G电性耦接所述96个输出通道DOUT[95:0]中的32个绿色输出通道比如DOUT1、…、DOUT94，所述B分量全局电流增益调节器15G电性耦接所述96个输出通道DOUT[95:0]中的32个蓝色输出通道比如DOUT0、…、DOUT93。所述R分量全局电流增益调节器15R、G分量全局电流增益调节器15G和B分量全局电流增益调节器15B等三个颜色分量全局电流增益调节器可以分别外接电阻。所述多个通道电流增益调节器191为96个通道电流增益调节器，其接受相对应的 电流增益数据之控制以分别负责96个输出通道DOUT[95:0]的单通道电流增益调节、且例如分别包括一个受控于电流增益数据并电性耦接相对应通道电流源151的电阻网络。当然，可以理解的是，在实际应用中，也可以考虑将R分量全局电流增益调节器15R、G分量全局电流增益调节器15G、B分量全局电流增益调节器15B等三个分量全局电流增益调节器整合为一个全局电流增益调节器，从而由单个全局电流增益调节器负责96个输出通道DOUT[95:0]的全局电流增益调节，也即全局电流增益调节不区分R、G、B分量。甚至，在某些设计方式下，所述电流源电路15也可以省略这些全局电流增益调节器15R、15G及15B。
为便于更清楚地理解本实施例的显示驱动电路10，下面将结合图1A-1C对其工作原理进行举例说明。
当所述显示驱动电路10开始正常上电后，数据时钟输入端的数据时钟信号DCLK将串行数据输入端输入的串行数据DIN[2:0]中的R、G、B分量显示控制数据送至所述移位暂存电路111，所述显示驱动电路10在每一个数据时钟信号DCLK的上升沿采集3bit显示控制数据，R、G、B分量各1bit，当采集到72bit显示控制数据(R、G、B分量各24bit，其中16bit为灰度数据、8bit为电流增益数据，也即灰度数据的比特位(bit)数大于电流增益数据的比特位数)，接着数据时钟信号DCLK和锁存信号LE通过组合命令(一般为锁存信号包含数据时钟信号DCLK的一个上升沿)将所述移位暂存电路111中的72bit显示控制数据包含的3*16bit灰度数据+3*8bit电流增益数据分别传输至所述缓存电路13中的所述灰度数据存储区131和所述电流增益数据存储区133。
所述灰度数据存储区131和所述电流增益数据存储区133的大小与所述显示驱动电路10所支持的输出通道数及扫描行数相关联。例如支持96个输出通道(R、G、B分别各32个输出通道)和64个扫描行数的显示驱动电路，其灰度数据存储区131的大小为96*16bit*64＝96Kb，电流增益数据存储区133的大小为96*8bit*64＝48Kb，同时由于显示驱动电路10的缓存电路13采用乒乓操作的形式，即灰度数据显示时使用上一帧完整的灰度数据，而本帧进行数据的缓冲输入，所以此时灰度数据存储区131和电流增益数据存储区133的大小分别为192Kb及96Kb，用以存放两帧完整灰度数据和电流增益数据。
为了和前端视频源显示数据同步进行显示，显示驱动电路10内部也具有相对应的同步显示处理，当命令处理电路12收到Vsync命令(同样为锁存信号LE包 含数据时钟信号DCLK的上升沿个数的组合命令，一般为2～3个)，所述显示驱动电路10会切换缓存电路13中的乒乓数据，将上一帧缓存完成的显示控制数据(包含灰度数据和电流增益数据)切换至进行读取输出，将已经显示过的显示控制数据的存储子区域切换至耦接移位暂存电路111以用来接收新的显示控制数据，同时Vsync命令会清零对所述倍频电路171产生的灰度时钟信号GCLK进行脉冲计数的计数器172的灰度时钟计数值。
在真正开始灰度显示之前，所述显示驱动电路10需要根据命令处理电路12接收的寄存器数据(例如经由移位暂存电路111写入配置寄存器)进行工作模式及全局电流增益等一些工作状态的配置；此时，需要配置内容包括灰度数据的打散模式、需要实现的灰度深度、全局电流增益等，寄存器配置也是通过不同的数据时钟信号DCLK和锁存信号LE的组合命令进行区分。
待完成配置后，显示驱动电路10开始灰度的实现。要点亮一颗LED灯点，外围已经有配合的行驱动电流，显示驱动电路10需要根据不同行显示控制数据来控制输出通道DOUT[95:0]的开/关就可以完成LED灯点的点亮，但是要实现灰度数据的区分，有两个部分关联，一者为输出通道的输出电流大小，另一者为输出通道的打开时长。比如要实现1000灰度值和2000灰度值的红色分量灰度数据，此时若保证两者的电流大小相同，如均为10mA的情况下，实现1000灰度值的灰度数据使用PWM的实现方式即需要1000个灰度时钟信号周期，这里的灰度时钟信号即为图1B中的GCLK，同样的实现2000灰度值的灰度数据需要2000个灰度时钟信号周期，这样的话，不同的灰度数据就被转换成显示不同时间长度的点亮时间；本实施例通过电流增益数据与灰度数据的共同控制方式，显示驱动电路10的输出通道DOUT[95:0]的开关状态是由灰度数据和灰度时钟计数值来控制，而实际LED灯点的点亮最大亮度是由电流增益数据来控制，显示驱动电路10的各个通道电流源151的控制是由外部电阻和内部配置电阻共同作用，外部电阻在LED显示板确定后就已经固定，因而可以通过全局电流增益和电流增益数据的方式来控制LED灯点的点亮亮度，如上面举例说到的要实现1000灰度值的灰度数据，可以选择使用10mA的电流点亮1000个灰度时钟信号周期的时间，本实施例提出的电流增益数据协同控制的方法提供了新的一种点亮方式，同样基准是要实现1000灰度值的灰度数据显示效果，可以通过降低电流，并提高灰度数据的方式来达到与原有10mA和1000个灰度时钟信号周期一样的效果，比如可以将电流降 低为5mA、同时将灰度时钟信号的周期数增大为2000个灰度时钟信号周期，这样的效果与前一种实现的效果是接近的，同样的也可以将电流数据降低为8mA、点亮的灰度时钟信号的周期数增大为1200，在效果上也可以是一致的，具体可以通过采集电流增益数据点亮效果与灰度数据的实现关系实现精准的实现方式转换。
再者，在使用PWM方式进行灰度实现时，采用灰度打散算法来进行灰度数据的分组显示，可以提高灰度实现时的刷新率，同时也可以防止在刷新率不是灰度时钟信号周期的整数倍率带来的低灰无法实现等问题。
综上所述，本申请实施例的显示驱动电路10通过设计，其可以接收包含灰度数据和电流增益数据的显示控制数据，并能够基于所述灰度数据控制各个通道电流源151的打开时长、以及基于所述电流增益数据控制各个通道电流源151的输出电流大小，从而可以实现通道电流动态调节；如此一来可以通过降低输出电流大小(对应显示点的驱动电流)来提高灰度数据，也即可以提升显示位深。此外，由于LED显示装置的显示效果与刷新率及每个灰阶的驱动电流相关，通过在低灰阶时降低显示点比如LED灯点的驱动电流并提高灰度数据，可以有效提高低亮低灰下的灰度刷新率。再者，通过降低输出电流大小且增大灰度数据，可以准确地得到想要的亮度值，进而提升整个LED显示装置低灰下的显示精准度，以解决低亮低灰下灰阶过渡不顺的问题。
【第二实施例】
图2为本申请实施例提供的另一种显示驱动电路30的具体结构示意图。如图2所示，显示驱动电路30的电路结构与图1A及1B所示的显示驱动电路10的电路结构基本相同，也包括：接口电路11、命令处理电路12、缓存电路13、电流源电路15、通道灰度控制电路17和通道电流控制电路19；以及所述通道灰度控制电路17包括倍频电路171、计数器172、灰度打散处理电路173、输出缓冲器174和多个比较器175。至于这些电路之间的连接关系和各自的结构及功能可参考前述第一实施例中的相关描述，在此不再赘述。
不同之处在于，本实施例显示驱动电路30中的接口电路11包括移位暂存电路111且用于接入数据时钟信号DCLK、锁存信号LE、串行数据DIN[2:0]和不同于所述数据时钟信号DCLK的第二时钟信号CLK；所述移位暂存电路111用于接收所述串行数据DIN[2:0]以获取所述多个灰度数据和所述多个电流增益数据且接受所述数据时钟信号DCLK和所述锁存信号LE的控制；所述命令处理电路12 电性耦接所述移位暂存电路111且接受所述数据时钟信号DCLK及所述锁存信号LE的控制；所述缓存电路13电性耦接所述移位暂存电路111以获取所述多个灰度数据和所述多个电流增益数据；以及所述通道灰度控制电路17接受所述第二时钟信号CLK的控制。本实施例的倍频电路171采用不用于数据时钟信号DCLK的另一时钟信号CLK作为产生灰度时钟信号GCLK的输入时钟信号，其使得灰度时钟信号GCLK的产生不再受限于数据时钟信号DCLK，提升了灰度时钟信号GCLK产生的灵活性。此外，值得一提的是，所述时钟CLK可以由外接晶振电路产生。
【第三实施例】
图3为本申请实施例提供的再一种显示驱动电路50的具体结构示意图。如图3所示，显示驱动电路50的内部电路结构与图1A及1B所示的显示驱动电路10的电路结构基本相同，也包括：接口电路11、命令处理电路12、缓存电路13、电流源电路15、通道灰度控制电路17和通道电流控制电路19；至于这些电路之间的连接关系和各自的结构及功能可参考前述第一实施例中的相关描述，在此不再赘述。
不同之处在于，本实施例显示驱动电路50中的通道灰度控制电路17包括计数器172、灰度打散处理电路173、输出缓冲器174和多个比较器175，也即省略了倍频电路171。再者，本实施例显示驱动电路50中的接口电路11包括移位暂存电路111且用于接入数据时钟信号DCLK、锁存信号LE、串行数据DIN[2:0]和不同于所述数据时钟信号DCLK的灰度时钟信号GCLK；所述移位暂存电路111用于接收所述串行数据DIN[2:0]以获取所述多个灰度数据和所述多个电流增益数据且接受所述数据时钟信号DCLK和所述锁存信号LE的控制；所述命令处理电路12电性耦接所述移位暂存电路111且接受所述数据时钟信号DCLK及所述锁存信号LE的控制；所述缓存电路13电性耦接所述移位暂存电路111以获取所述多个灰度数据和所述多个电流增益数据；以及所述通道灰度控制电路17接受所述灰度时钟信号GCLK的控制。本实施例的通道灰度控制电路17采用外接灰度时钟信号GCLK，因而可以省略倍频电路171。
【第四实施例】
图4为本申请实施例提供的又一种显示驱动电路70的具体结构示意图。如图4所示，显示驱动电路70的电路结构与图1A及1B所示的显示驱动电路10的电 路结构基本相同，也包括：接口电路11、命令处理电路12、缓存电路13、电流源电路15、通道灰度控制电路17和通道电流控制电路19；以及所述通道灰度控制电路17包括倍频电路171、计数器172、灰度打散处理电路173、输出缓冲器174和多个比较器175。至于这些电路之间的连接关系和各自的结构及功能可参考前述第一实施例中的相关描述，在此不再赘述。
不同之处在于，本实施例的显示驱动电路70还包括：扫描控制电路59，电性耦接所述通道灰度控制电路17中的灰度打散处理电路173，用于依序产生多个行扫描信号，例如其具有64个输出通道LINE[63:0]以依序输出64个行扫描信号。本实施例将扫描控制电路59整合于显示驱动电路70中，其能够有效提升显示驱动电路70的集成度，在LED显示板设计时会降低PCB设计的复杂度。至于所述扫描控制电路59的工作原理，其例如是：由于显示驱动电路70的灰度实现是通过灰度打散处理电路173和计数器172协同控制，比如灰度打散算法开启后，每次实现设定数量比如256个灰度时钟信号周期就要开始换行，此时需要通知扫描控制电路59进行换行操作，当然显示驱动电路70内部由于灰度数据是按照顺序存放，所以在实现时也是按照扫描顺序实现，此时扫描控制电路59(例如从灰度打散处理电路173)接收到一个简单逻辑就可以进行累加操作和清零操作即可完成扫描信号的输出。
【第五实施例】
图5为本申请实施例提供的一种LED显示板的部分结构示意图。如图5所示，LED显示板400包括：像素阵列PA、显示驱动电路10和扫描控制芯片420。
其中，所述像素阵列PA包含32列像素P、且每一个像素P包含多个不同颜色LED比如R、G、B三基色LED灯点，从而像素阵列PA具有96列LED灯点。这96列LED灯点分别电性耦接所述显示驱动电路10的96个输出通道DOUT0～DOUT95，每一列中的像素P电性耦接所述显示驱动电路10的相邻三个输出通道。再者，所述像素阵列PA包含64行像素P，且这64行像素P分别电性耦接所述扫描控制芯片420的64个输出通道LINE0～LINE63。
本实施例的扫描控制芯片420例如包括行译码芯片，其可以配合显示驱动电路10在每一轮64扫过程中依序产生64个行扫描信号(或称扫描驱动信号)。需要说明的是，本实施例的扫描控制芯片420的输出通道并不限于64个，也 可以是其他数量比如32个等，具体数量可以根据实际应用需求确定。
此外，本实施例的显示驱动电路10接收数据时钟信号DCLK、串行数据DIN[2:0]和锁存信号LE的输入。
【第六实施例】
图6为本申请实施例提供的另一种LED显示板的部分结构示意图。如图6所示，LED显示板600包括：像素阵列PA、显示驱动电路30和扫描控制芯片420。
其中，所述像素阵列PA包含32列像素P、且每一个像素P包含多个不同颜色LED比如R、G、B三基色LED灯点，从而像素阵列PA具有96列LED灯点。这96列LED灯点分别电性耦接所述显示驱动电路30的96个输出通道DOUT0～DOUT95，每一列中的像素P电性耦接所述显示驱动电路30的相邻三个输出通道。再者，所述像素阵列PA包含64行像素P，且这64行像素P分别电性耦接所述扫描控制芯片420的64个输出通道LINE0～LINE63。
本实施例的扫描控制芯片420例如包括行译码芯片，其可以配合显示驱动电路30在每一轮64扫过程中依序产生64个行扫描信号(或称扫描驱动信号)。需要说明的是，本实施例的扫描控制芯片420的输出通道并不限于64个，也可以是其他数量比如32个等，具体数量可以根据实际应用需求确定。
此外，本实施例的显示驱动电路30接收数据时钟信号DCLK、串行数据DIN[2:0]、锁存信号LE和供灰度时钟信号GCLK产生之用的第二时钟信号CLK的输入。
【第七实施例】
图7为本申请实施例提供的再一种LED显示板的部分结构示意图。如图7所示，LED显示板800包括：像素阵列PA、显示驱动电路50和扫描控制芯片420。
其中，所述像素阵列PA包含32列像素P、且每一个像素P包含多个不同颜色LED比如R、G、B三基色LED灯点，从而像素阵列PA具有96列LED灯点。这96列LED灯点分别电性耦接所述显示驱动电路50的96个输出通道DOUT0～DOUT95，每一列中的像素P电性耦接所述显示驱动电路50的相邻三个输出通道。再者，所述像素阵列PA包含64行像素P，且这64行像素P分别电性耦接所述扫描控制芯片420的64个输出通道LINE0～LINE63。
本实施例的扫描控制芯片420例如包括行译码芯片，其可以配合显示驱动电路50在每一轮64扫过程中依序产生64个行扫描信号(或称扫描驱动信号)。需要说明的是，本实施例的扫描控制芯片420的输出通道并不限于64个，也可以是其他数量比如32个等，具体数量可以根据实际应用需求确定。
此外，本实施例的显示驱动电路50接收数据时钟信号DCLK、串行数据DIN[2:0]、锁存信号LE和灰度时钟信号GCLK的输入。
【第八实施例】
图8为本申请实施例提供的又一种LED显示板的部分结构示意图。如图8所示，LED显示板1000包括：像素阵列PA和显示驱动电路70。
其中，所述像素阵列PA包含32列像素点P、且每一个像素点P包含多个不同颜色LED比如R、G、B三基色LED灯点，从而像素阵列PA具有96列LED灯点。这96列LED灯点分别电性耦接所述显示驱动电路70的96个输出通道DOUT0～DOUT95，每一列中的像素点P电性耦接所述显示驱动电路70的相邻三个输出通道。再者，所述像素阵列PA包含64行像素P，且这64行像素P分别电性耦接所述显示驱动电路70的64个输出通道LINE0～LINE63。
本实施例的显示驱动电路70整合有扫描控制电路59(如图4所示)，其可以在每一轮64扫过程中依序产生64个行扫描信号(或称扫描驱动信号)。需要说明的是，本实施例的显示驱动电路70的行扫描信号的输出通道并不限于64个，也可以是其他数量比如32个等，具体数量可以根据实际应用需求确定。
【第九实施例】
图9为本申请实施例提供的一种显示装置的结构示意图。如图9所示，显示装置900包括：前端显示控制卡901和LED显示板903。
其中，所述前端显示控制卡901用于输出包含灰度数据和电流增益数据的显示控制数据，其例如采用LED显示控制技术领域成熟的接收卡、扫描卡或模组控制器相似的硬件结构，也即采用可编程逻辑器件比如FPGA(Field Programmable Gate Array，现场可编程门阵列)器件作为图像处理器；但本实施例的所述图像处理器可以直接输出包含灰度数据和电流增益数据的所述显示控制数据、或者在所述图像处理器的后端增设有FPGA器件或ASIC(Application Specific Integrated Circuit，专用集成电路)器件以将所述图像处理器输出的灰度数据转换成包含灰度数据和电流增益数据的所述显示控制数据。
所述LED显示板903可以采用前述第五实施例、第六实施例、第七实施例或第八实施例所述的LED显示板400、600、800或1000，其包含的显示驱动电路电性耦接所述前端显示控制卡901以接收所述显示控制数据实现图像显示。
值得说明的是，本实施例的显示装置900可以是包含前端显示控制卡901和一个或多个LED显示板903的LED显示箱体，但其仅为举例，并非用来限制本申请实施例。
本实施例的显示装置900可以实现通道电流动态调节，其有利于提升显示位深、提高低亮低灰下的灰度刷新率、以及提升整个LED显示装置低灰下的显示精准度以解决低亮低灰下灰阶过渡不顺的问题。
【第十实施例】
图10为本申请实施例提供的一种显示驱动方法的流程示意图。如图10所示，本实施例的显示驱动方法例如包括以下步骤：
S110：获取多个灰度数据和多个电流增益数据；
S130：缓存所述多个灰度数据和所述多个电流增益数据；
S150：根据所述多个灰度数据分别控制多个通道电流源的打开时长；
S170：根据所述多个电流增益数据分别控制所述多个通道电流源的输出电流大小。
至于前述步骤S110～S170的具体细节可参考前述第一实施例的显示驱动电路10的相关描述，在此不再赘述。再者，本实施例的显示驱动方法可以实现通道电流动态调节，其有利于提升显示位深、提高低亮低灰下的灰度刷新率、以及提升整个LED显示装置低灰下的显示精准度以解决低亮低灰下灰阶过渡不顺的问题。
作为本申请的一个实施方式，所述步骤S150包括：(i)接收灰度时钟信号、并在所述灰度时钟信号的控制下产生灰度时钟计数值；(ii)基于灰度打散算法控制所述计数器的计数操作以及产生灰度分组控制信号；以及(iii)分别获取所述多个灰度数据、并在所述灰度时钟计数值和所述灰度分组控制信号的控制下产生多个灰度显示控制信号分别传送至所述多个通道电流源，以控制所述多个通道电流源的打开时长。本实施方式基于灰度打散算法可以将高灰部分与低灰部分进行均匀打散分布，这样在某些灰度实现不完整的场景下，还能尽可能的保证大部分灰度可以得以实现。
作为本申请的一个实施方式，所述步骤S150还包括：对输入时钟信号进行 倍频处理以产生所述灰度时钟信号。本实施方式的倍频处理有利于增大灰度时钟信号产生的弹性。
作为本申请的一个实施方式，所述步骤S170包括：根据多个逐点电流增益数据分别控制所述多个通道电流源的输出电流大小。本实施方式中逐点电流增益数据的采用，其可以使得同一个通道电流源在驱动不同显示点(比如LED灯点)时采用与所述不同显示点分别对应的电流增益数据，进而有利于提升电流动态调节的精准度。
作为本申请的一个实施方式，所述步骤S130包括：采用乒乓存储方式逐帧缓存逐点灰度数据；以及采用乒乓存储方式逐帧缓存逐点电流增益数据。本实施方式的灰度数据和电流增益数据均采用乒乓存储方式，其有利于提升处理速度和性能。
作为本申请的一个实施方式，所述步骤S170包括：根据多个逐通道电流增益数据分别控制所述多个通道电流源的输出电流大小。本实施方式逐通道电流增益数据的采用，其可以使得同一个通道电流源在不同显示帧时采用的电流增益数据不同，其至少可以实现逐帧电流动态调节。
另外，可以理解的是，前述各个实施例仅为本申请的示例性说明，在技术特征不冲突、结构不矛盾、不违背本申请的发明创造目的前提下，各个实施例的技术方案可以任意组合、搭配使用。
再者，值得说明的是，本申请前述各个实施例是以单个显示驱动电路能够完成多颜色分量的灰度实现作为举例进行描述，但本申请实施例并不以此为限，也可以将单个显示驱动电路设计成只完成单颜色分量的灰度实现，这样对于R、G、B三种颜色分量的灰度数据可以分别采用三个显示驱动电路来实现。
此外，值得说明的是，在本申请所提供的几个实施例中，应该理解到，所揭露的系统，装置和方法，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多路单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或单元的间接耦合或通信连接，可以是电性，机械或其它的形式。
作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显 示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多路网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
此外，在本申请各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。上述集成的单元既可以采用硬件的形式实现，也可以采用硬件加软件功能单元的形式实现。
上述以软件功能单元的形式实现的集成的单元，可以存储在一个计算机可读取存储介质中。上述软件功能单元存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)执行本申请各个实施例方法的部分步骤。而前述的存储介质包括：U盘、移动硬盘、只读存储器(Read-Only Memory，简称ROM)、随机存取存储器(Random Access Memory，简称RAM)、磁碟或者光盘等各种可以存储程序代码的介质。
最后应说明的是：以上实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的精神和范围。
【工业实用性】
本申请实施例通过对显示驱动电路进行设计，其可以获取灰度数据和电流增益数据，并能够基于所述灰度数据控制各个通道电流源的打开时长、以及基于所述电流增益数据控制各个通道电流源的输出电流大小，从而可以实现通道电流动态调节；如此一来可以通过降低输出电流大小(对应显示点的驱动电流)来提高灰度数据，也即可以提升显示位深。再者，由于LED显示装置的显示效果与刷新率及每个灰阶的驱动电流相关，通过在低灰阶时降低显示点比如LED灯点的驱动电流并提高灰度数据，可以有效提高低亮低灰下的灰度刷新率。此外，通过降低输出电流大小且增大灰度数据，可以准确地得到想要的亮度值，进而提升整个LED显示装置低灰下的显示精准度，以解决低亮低灰下灰阶过渡不顺的问题。

Claims (20)

  1. 一种显示驱动电路，其特征在于，包括：
    接口电路，用于获取多个灰度数据和多个电流增益数据；
    命令处理电路，电性耦接所述接口电路；
    缓存电路，电性耦接所述接口电路，用于缓存所述多个灰度数据和所述多个电流增益数据；
    电流源电路，电性耦接所述命令处理电路且包括多个通道电流源；
    通道灰度控制电路，电性耦接所述命令处理电路、所述缓存电路和所述电流源电路，用于根据所述多个灰度数据分别控制所述多个通道电流源的打开时长；
    通道电流控制电路，电性耦接所述缓存电路和所述电流源电路，用于根据所述多个电流增益数据分别控制所述多个通道电流源的输出电流大小。
  2. 如权利要求1所述的显示驱动电路，其特征在于，所述接口电路包括移位暂存电路且用于接入数据时钟信号、锁存信号和串行数据；所述移位暂存电路用于接收所述串行数据以获取所述多个灰度数据和所述多个电流增益数据且接受所述数据时钟信号及所述锁存信号的控制；所述命令处理电路电性耦接所述移位暂存电路且接受所述数据时钟信号及所述锁存信号的控制；所述缓存电路电性耦接所述移位暂存电路以获取所述多个灰度数据和所述多个电流增益数据；以及，所述通道灰度控制电路接受所述数据时钟信号的控制。
  3. 如权利要求1所述的显示驱动电路，其特征在于，所述通道灰度控制电路包括：
    计数器，电性耦接所述命令处理电路，用于接收灰度时钟信号、并在所述灰度时钟信号的控制下产生灰度时钟计数值；
    灰度打散处理电路，电性耦接所述命令处理电路和所述计数器，用于接受所述命令处理电路的控制以控制所述计数器的计数操作以及产生灰度分组控制信号；
    输出缓冲器，电性耦接所述电流源电路的所述多个通道电流源；
    多个比较器，电性耦接所述缓存电路、所述计数器、所述灰度打散处理电路和所述输出缓冲器，用于分别从所述缓存电路获取所述多个灰度数据、并在所述 灰度时钟计数值和所述灰度分组控制信号的控制下产生多个灰度显示控制信号经由所述输出缓冲器分别传送至所述多个通道电流源。
  4. 如权利要求3所述的显示驱动电路，其特征在于，所述通道灰度控制电路还包括：倍频电路，电性耦接所述计数器，用于产生所述灰度时钟信号并传送至所述计数器。
  5. 如权利要求1所述的显示驱动电路，其特征在于，所述电流源电路还包括多个颜色分量全局电流增益调节器，且每一个所述颜色分量全局电流增益调节器电性耦接所述多个通道电流源中用于带载相同颜色亚像素的多个通道电流源；所述通道电流控制电路包括多个通道电流增益调节器，且所述多个通道电流增益调节器分别电性耦接所述多个通道电流源、并分别接受所述多个电流增益数据的控制。
  6. 如权利要求1所述的显示驱动电路，其特征在于，所述接口电路包括移位暂存电路且用于接入数据时钟信号、锁存信号、串行数据和不同于所述数据时钟信号的第二时钟信号；所述移位暂存电路用于接收所述串行数据以获取所述多个灰度数据和所述多个电流增益数据且接受所述数据时钟信号和所述锁存信号的控制；所述命令处理电路电性耦接所述移位暂存电路且接受所述数据时钟信号及所述锁存信号的控制；所述缓存电路电性耦接所述移位暂存电路以获取所述多个灰度数据和所述多个电流增益数据；以及，所述通道灰度控制电路接受所述第二时钟信号的控制。
  7. 如权利要求1所述的显示驱动电路，其特征在于，所述显示驱动电路还包括：扫描控制电路，电性耦接所述通道灰度控制电路，用于依序产生多个行扫描信号。
  8. 如权利要求1所述的显示驱动电路，其特征在于，所述缓存电路包括灰度数据存储区和电流增益数据存储区，所述灰度数据存储区用于缓存所述多个灰度数据，所述电流增益数据存储区用于缓存所述多个电流增益数据。
  9. 如权利要求8所述的显示驱动电路，其特征在于，所述灰度数据存储区包含两个存储子区域以用于采用乒乓存储方式逐帧缓存灰度数据，所述电流增益数据存储区包含两个存储子区域以用于采用乒乓存储方式逐帧缓存电流增益数据。
  10. 如权利要求1所述的显示驱动电路，其特征在于，所述接口电路、所述命令处理电路、所述缓存电路、所述电流源电路、所述通道灰度控制电路和所述通道电流控制电路整合于同一个芯片内。
  11. 如权利要求1所述的显示驱动电路，其特征在于，所述多个电流增益数据为逐点电流增益数据，以使得所述多个通道电流源中同一个所述通道电流源在驱动不同显示点时采用与所述不同显示点分别对应的电流增益数据。
  12. 如权利要求1所述的显示驱动电路，其特征在于，所述多个电流增益数据为逐通道电流增益数据，以使得所述多个通道电流源中同一个所述通道电流源在不同显示帧时采用的电流增益数据不同。
  13. 一种LED显示板，其特征在于，包括：
    像素阵列，包括多个像素点且每一个所述像素点包括多个不同颜色LED；以及
    至少一个如权利要求1至12任意一项所述的显示驱动电路，其中所述显示驱动电路的所述多个通道电流源电性耦接所述像素阵列。
  14. 一种显示装置，其特征在于，包括：
    前端显示控制卡，用于输出多个灰度数据和多个电流增益数据；以及
    如权利要求13所述的LED显示板，其中所述LED显示板的所述显示驱动电路电性耦接所述前端显示控制卡以接收所述多个灰度数据和所述多个电流增益数据。
  15. 一种显示驱动方法，其特征在于，包括：
    获取多个灰度数据和多个电流增益数据；
    缓存所述多个灰度数据和所述多个电流增益数据；
    根据所述多个灰度数据分别控制多个通道电流源的打开时长；以及
    根据所述多个电流增益数据分别控制所述多个通道电流源的输出电流大小。
  16. 如权利要求15所述的显示驱动方法，其特征在于，所述根据所述多个灰度数据分别控制多个通道电流源的打开时长，包括：
    接收灰度时钟信号、并在所述灰度时钟信号的控制下产生灰度时钟计数值；
    基于灰度打散算法控制所述计数器的计数操作以及产生灰度分组控制信号；
    分别获取所述多个灰度数据、并在所述灰度时钟计数值和所述灰度分组控制信号的控制下产生多个灰度显示控制信号分别传送至所述多个通道电流源，以控制所述多个通道电流源的打开时长。
  17. 如权利要求16所述的显示驱动方法，其特征在于，所述根据所述多个灰度数据分别控制多个通道电流源的打开时长，还包括：
    对输入时钟信号进行倍频处理以产生所述灰度时钟信号。
  18. 如权利要求15所述的显示驱动方法，其特征在于，所述根据所述多个电流增益数据分别控制所述多个通道电流源的输出电流大小，包括：
    根据多个逐点电流增益数据分别控制所述多个通道电流源的输出电流大小。
  19. 如权利要求18所述的显示驱动方法，其特征在于，所述缓存所述多个灰度数据和所述多个电流增益数据，包括：
    采用乒乓存储方式逐帧缓存逐点灰度数据；
    采用乒乓存储方式逐帧缓存逐点电流增益数据。
  20. 如权利要求15所述的显示驱动方法，其特征在于，所述根据所述多个电流增益数据分别控制所述多个通道电流源的输出电流大小，包括：
    根据多个逐通道电流增益数据分别控制所述多个通道电流源的输出电流大小。
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