WO2012022235A1 - 显示控制的倍频方法及装置 - Google Patents

显示控制的倍频方法及装置 Download PDF

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Publication number
WO2012022235A1
WO2012022235A1 PCT/CN2011/078188 CN2011078188W WO2012022235A1 WO 2012022235 A1 WO2012022235 A1 WO 2012022235A1 CN 2011078188 W CN2011078188 W CN 2011078188W WO 2012022235 A1 WO2012022235 A1 WO 2012022235A1
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Prior art keywords
output
data
display control
pulse
counter
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PCT/CN2011/078188
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English (en)
French (fr)
Inventor
石磊
李照华
王乐康
符传汇
陈克勇
尹志刚
Original Assignee
深圳市明微电子股份有限公司
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Priority claimed from CN 201010259673 external-priority patent/CN101901578B/zh
Priority claimed from CN2011100751793A external-priority patent/CN102184709B/zh
Application filed by 深圳市明微电子股份有限公司 filed Critical 深圳市明微电子股份有限公司
Publication of WO2012022235A1 publication Critical patent/WO2012022235A1/zh

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    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2007Display of intermediate tones
    • G09G3/2014Display of intermediate tones by modulation of the duration of a single pulse during which the logic level remains constant
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3275Details of drivers for data electrodes

Definitions

  • the present invention relates to the field of digital control, and in particular, to a method and apparatus for display control. Background technique
  • Analog dimming means that the amount of current flowing through the LED is adjusted by the written data to change the brightness of the LED.
  • Pulse width modulation pulse dimming refers to adjusting the time width of the LED on or off over a period of time. When the LED is turned on, it is driven by a fixed current and can be set by an external resistor. When the LED is turned off, no current flows. Thus, the display effect in a certain period of time is that the brightness of the lamp has changed. And the longer the light is on during this fixed time, the overall effect is that the light is brighter. This can achieve the purpose of adjusting the brightness of the LED within a certain period of time.
  • Pulse width modulation pulse dimming completely avoids the shortcomings of the above analog dimming.
  • the lamp is lit, a constant current flows through, and the wavelength of the light does not change.
  • the basic clock for the pulse width modulation pulse is increased, and the allowable duty ratio is selected more during the original fixed time period; or the original time period is lengthened, and the original basic clock is used. , there will be more duty cycle options.
  • pulse width modulation pulse dimming also has its own drawbacks. Since this dimming method requires the brightness to be averaged over a certain period of time, when the gradation level of the LED is high, the period is long. In this way, when the LED is on or off, or the capture time is too short, so that the ratio of light to extinguish received in the time can not truly reflect the original brightness ratio.
  • capture time is far It is much smaller than the capture time of the human eye to the picture. In this way, when the human eye looks sharper and the picture is taken by the camera or the camera, the picture may cause flickering, or streaking.
  • MSB is the high word bit in the standard period data of pulse width modulation pulse. Although it is slightly distorted, it can better reflect the duty cycle of the standard period of pulse width modulation pulse.
  • LSB is the low word in the standard period data of pulse width modulation pulse. Bit, just to be within a standard period of pulse width modulation pulse (ie, the period before multiplier), the overall display is not distorted. This exists: When capturing the moment near the LSB, it will cause more obvious local display distortion.
  • An object of the present invention is to at least solve one of the above-mentioned technical drawbacks, and in particular to realize a display control of a high refresh rate by generating a pulse width modulated pulse signal at a higher frequency without affecting the accuracy of the original data.
  • an embodiment of the present invention provides, in one aspect, a method of display control, including the following steps:
  • the pulse width modulation pulse PMW signal OUT is output, where:
  • the brightness setting value ⁇ is equal to a high level time of the pulse width modulation pulse PWM signal OUT in a complete counter period, and a high level time of the pulse width modulation pulse PWM signal OUT Dividing into a plurality of brightness control signals, respectively, respectively appearing in a complete counter period, thereby increasing the display refresh rate, 0 ⁇ ⁇ ⁇ , ⁇ is the bit length of the counter, and the high level time is the effective display time;
  • the pulse width modulation pulse PMW signal OUT drives the LEDs for display control.
  • Another aspect of an embodiment of the present invention also provides a computer program for performing the above method of display control.
  • Another aspect of an embodiment of the present invention also provides a computer readable medium having computer executable components for carrying a computer program for performing the method of display control described above.
  • Another embodiment of the present invention further provides a display control apparatus, including a counter, a logic operator, a data strobe, and a logic combiner.
  • the counter is configured to receive a basic clock and output a periodic digital signal
  • the logic operator is configured to receive the periodic digital signal and output the data into the data gate as the gated data;
  • the data strobe is configured to receive and acquire a preset brightness setting value as strobe data, and the data strobe outputs D1 ;
  • the logic combiner is configured to receive a pulse width modulation pulse PMW signal OUT to drive the LED to realize display control, wherein:
  • the brightness setting value ⁇ is equal to a high level time of the pulse width modulation pulse PWM signal OUT in a complete counter period, and a high level time of the pulse width modulation pulse PWM signal OUT
  • the image is divided into a plurality of brightness control signals, and then appears separately in the same time, thereby increasing the display refresh rate, 0 ⁇ Kn, and ⁇ is the bit length of the counter.
  • the pulse width modulation pulse signal is generated at a higher frequency without affecting the accuracy of the original data, thereby realizing display control of high refresh frequency, and appropriately adjusting the pulse width modulation pulse PMW signal
  • the ratio is output mode to ensure the driving effect of the output port.
  • FIG. 2 is a flow chart of a method for displaying control according to an embodiment of the present invention.
  • FIG. 3 is a schematic diagram of implementation of a pulse width modulation pulse according to an embodiment of the present invention.
  • Figure 4 is a schematic diagram of an asynchronous counter
  • Figure 5 is a schematic diagram of a synchronous counter
  • Figure 6 is a schematic diagram of a logic operator
  • Figure 7 is a schematic diagram of a data strobe
  • Figure 8 is a schematic diagram of a logic combiner
  • Figure 9 is a schematic diagram of the generated logic combined waveform and PWM output waveform
  • FIG. 10 is a schematic structural diagram of an apparatus for displaying control according to an embodiment of the present invention.
  • Figure 11 is a schematic diagram of a comparison of pulse width modulation pulse techniques. detailed description
  • the traditional pulse width modulation pulse is implemented as follows:
  • the basic clock (CLK) is input to a counter, and the counter starts counting. From the start data, for example, all 0, - until the end data, for example, all 1s, the cycle is repeated. If the output of the counter is less than the value of data DATA, then the output is high, otherwise the output is low. Thus, the data is output in the form of a duty cycle.
  • CLK basic clock
  • the human eye when the refresh rate of the data reaches 60 Hz or more, the human eye does not have a flickering or streaking feeling on the image; and the shutter of the camera can reach 4000 Hz. That is to say, the human eye allows a pulse width modulation pulse with a standard period of 16.7 milliseconds, while the camera only allows 0.25 milliseconds. For example, the data update period of the universal screen is now 4 milliseconds.
  • the human eye looks very clear, but when shooting with a camera, the entire pulse width modulation pulse standard period cannot be captured for 0.25 milliseconds, and the duty cycle captured within 0.25 milliseconds does not reflect the data that needs to be presented at that time. So the stripes are clear
  • the present invention provides a display control method comprising the steps of: acquiring a preset brightness setting value M l input data strobe as strobe data, and a basic clock entering counter, an output period After the logical digital signal passes through the logic operator, the output data enters the data gate as the gated data, and the data gater outputs D1 ; the output of the data gater enters the logic combiner, and then outputs a pulse width modulation pulse PMW signal OUT, wherein: the brightness setting value ⁇ is equal to a high level time of the pulse width modulation pulse PWM signal OUT in a complete counter period, the number of basic clocks, and the pulse width The high-level time of the modulated pulse PWM signal OUT is divided into a plurality of brightness control signals, and then appears respectively in a complete counter period, thereby increasing the display refresh rate, 0 ⁇ Kn, ⁇ is the bit length of the counter; The pulse width modulation pulse PMW signal OUT drives the LEDs for display control
  • a flowchart of a method for displaying control according to an embodiment of the present invention includes the following steps:
  • step S110 the basic clock input counter, the counter output Q l periodic digital signal after the output logic operator enters the data strobe as being gated data,
  • a schematic diagram of a pulse width modulation pulse is implemented in accordance with an embodiment of the present invention.
  • the base clock (CLK) is input to an n-bit counter, and the counter starts counting, from the start data, for example, n zeros, to the end of the data, for example, n ones, and so on.
  • the counter includes an asynchronous counter or a synchronous counter.
  • the high-level time of the n outputs has an overlapping portion, and the duty ratio is 1/2, and the output high pulse of the high bit contains the number of basic clocks, and the output of the adjacent lower bits contains the basic clock. 2 times the number, the low frequency is 2 times the high frequency, and the output signal is from high to low.
  • a schematic diagram of an asynchronous counter consists of a D flip-flop string.
  • the QB of each level of the D flip-flop is terminated with the D terminal.
  • the Q terminal of the previous stage D flip-flop is connected to the CLKB terminal of the first-stage D flip-flop, and the QB terminal is connected to the CLK terminal of the first-stage D flip-flop.
  • a schematic diagram of the synchronization counter is used. When all low-order outputs are all ones and the high-order output is 0, the state of the high-order bits is changed from 0 to 1, or from 1 to 0.
  • the periodic digital signal output by the counter passes through the logic operator:
  • the periodic digital signal obtains n outputs through logic operation, and the high-level time of the n outputs does not overlap.
  • the high-order output high-pulse includes the number of basic clocks.
  • the output of the adjacent low-order high pulse contains the number of basic clocks. Times, the number of high pulses per output is evenly distributed over the standard period of the pulse width modulation pulse.
  • the output of A l 5 from high to low is ⁇ ( ⁇ _ ⁇ , ⁇ ( ⁇ _ 2 ), ..., ⁇ ., which satisfies the following conditions:
  • k is a positive integer less than 0 or less than n; thus, the originally overlapping high pulses are not overlapped after being operated, and the original duty ratio is fixed to 1/2. After the operation, the high-order duty ratio is twice the low-order duty ratio. .
  • FIG. 6 it is a schematic diagram of the logic operator, corresponding to n inputs and n outputs.
  • the input Qk is taken as the output highest bit A ( ⁇ - ⁇ , , in this embodiment, the BUF buffer is selected to increase the driving capability, and the data is not affected.
  • the next highest bit ⁇ ⁇ 2 ) output is:
  • Qk is low, that is, when the data after the INV inverter is 1, it is output, otherwise it is kept low; similarly, the remaining bits can be
  • the output is simply implemented according to the above equation.
  • step S110 the preset brightness setting value M l is input to the data gate as the strobe data. Thereafter, the data strobe outputs the data signal according to the strobe data and the strobed data.
  • FIG 7 it is a schematic diagram of the data gate.
  • it can also be implemented by a similar circuit such as a transmission gate, but its purpose is usually to make data selection common.
  • the strobed data corresponding to the bit is strobed; when the strobe data is "false", the strobed data corresponding to the bit is masked. For example, if the data bit is 1, the corresponding logical operation bit is gated; if the data bit is 0, the corresponding logical group operation bits are masked and their outputs are logically ORed.
  • the output of the data strobe satisfies the following formula:
  • the output of the strobe data from the high to the low is ⁇ ⁇ .,., ⁇
  • the output of the strobe data from the high to the low is M ⁇ M ⁇ Mo, and the output signal is from high to low.
  • the output is ⁇ ( ⁇ _ ⁇ , ⁇ ( ⁇ _ 2 ), ..., ⁇ .;
  • the output zero of the strobe data is n bits.
  • S120 The data signal output by the data strobe passes through the logic combiner and outputs a pulse width modulated pulse PWM signal.
  • step S120 the logical combiner includes:
  • the output of the data strobe is logically ORed and the pulse width modulated pulse PWM signal is output.
  • Figure 8 it is a schematic diagram of a logical combiner.
  • the logic or gate is implemented, and other circuits can be used to implement the function of the module: that is, if an input is high, the output is high. The high time is the output valid time. If an implementation is used, the low time is the output valid time, then the logical AND gate can be used here.
  • the module summarizes the effective time of n inputs.
  • the pulse width modulation pulse PMW signal OUT satisfies the following formula:
  • the pulse width is cut into a plurality of discrete high pulses.
  • the output signal has the following characteristics: a brightness set value equal to a number of basic clocks of the series of pulse width modulated pulse PWM signals in a complete counter period; and the series of pulse width modulations
  • the pulsed PWM signal is divided into a plurality of brightness control signals at a high level, and is respectively displayed at the same time to form a higher refresh rate.
  • the highest bit of the logic operator output is characterized by the highest refresh rate. 1/2 Duty Cycle
  • the refresh rate is J_ , where T is the basic clock period.
  • FIG. 9 is a schematic diagram of the generated logic combination waveform and the PWM output waveform.
  • the PWM signal drives the LED to perform display control.
  • step S130 the LED signal is driven by the pulse signal obtained in step S120 to realize display control.
  • the output pulse width modulation pulse PMW signal OUT drives the LED.
  • the LED driver circuit is also connected in the middle of the LED to meet the driving current requirements of the LED. In the constant current driving mode, a constant current independent of factors such as circuit supply voltage, temperature, and load voltage is provided; in the constant voltage driving mode, a sufficiently large driving current capability is provided to meet the current demand of the LED path.
  • the present invention also proposes to execute the display control method in the above embodiment by a computer program.
  • the present invention also provides a computer readable medium having computer executable components for carrying a computer program for executing the display control method in the above embodiment.
  • FIG. 10 it is a schematic structural diagram of an apparatus 100 for displaying control according to an embodiment of the present invention.
  • a counter 110 a logic operator 120, a data strobe 130, and a logic combiner 140 are included.
  • the counter 110 is configured to receive a basic clock, and output a periodic digital signal logic operator 120 for receiving a periodic digital signal and outputting the data into the data strobe
  • the counter 110 packs the high-level time of the n outputs with overlapping portions, and the duty ratio is 1/2.
  • the high-order output high pulse includes the number of basic clocks, and the output of the adjacent low-order high pulse contains the number of basic clocks. 2 times, the low frequency is twice the high frequency, and the output signal is ( ⁇ ⁇ _ ⁇ , ( ⁇ ⁇ _ 2 ),..., 0 from the high to the low.
  • the periodic digital signal output by the counter 110 ( ⁇ via the logic operator 120 includes: the periodic digital signal obtains n outputs through a logic operation, the high-level time of the n outputs does not overlap, and the high-order output high pulse includes the basic clock
  • the number is that the output high pulse of the adjacent lower bits contains twice the number of basic clocks, and the number of high pulses per output is evenly distributed within the standard period of the pulse width modulation pulse.
  • the periodic digital signal output by the counter 110 is output through the logic operator 140, from high to low.
  • k is a positive integer less than 0 or less than n; thus, the originally overlapping high pulses are not overlapped after being operated, and the original duty ratio is fixed to 1/2. After the operation, the high-order duty ratio is twice the low-order duty ratio. .
  • the data strobe 130 is configured to receive the ⁇ and obtain a preset brightness setting value ⁇ as the strobe data, and the data strobe 130 outputs I
  • the data strobe 130 includes:
  • the strobed data corresponding to the bit is strobed; when the strobe data is '1", the strobed data corresponding to the bit is masked.
  • the output of the strobe data from the high to the low is ⁇ ⁇ .,., ⁇
  • the output of the strobe data from the high to the low is M ⁇ M ⁇ Mo, and the output signal is from high to low.
  • the output is ⁇ ( ⁇ _ ⁇ , ⁇ ( ⁇ _ 2 ), ..., ⁇ .; when the digit length of the strobe data is less than ⁇ , the output of the strobe data
  • the force is zero and the n is zero.
  • the logic combiner 140 is configured to receive the pulse width modulation pulse PMW signal OUT after receiving 1 ⁇ , and drive the LED to realize display control, wherein:
  • the brightness setting value ⁇ is equal to the number of basic clocks of the pulse width modulation pulse PWM signal OUT in one complete counter 110 period, and the high level time of the pulse width modulation pulse PWM signal OUT is divided into a plurality of brightness
  • the control signals are then respectively present in a complete counter period, thereby increasing the display refresh rate, 0 ⁇ Kn , ⁇ being the bit length of the counter 110.
  • the logical combiner 140 includes:
  • the output of the data strobe 130 is logically ORed and outputs a pulse width modulated pulse PWM signal.
  • the pulse width modulation pulse output by the logic combiner 140 PMW signal OUT satisfies the following formula:
  • the highest bit of the logic operator output is characterized by the highest refresh rate. 1/2 Duty Cycle
  • the refresh rate is J_ , where T is the basic clock period.
  • the output pulse width modulation pulse PMW signal OUT drives the LED.
  • the LED driver circuit is also connected in the middle of the LED to meet the driving current requirements of the LED.
  • a constant current driving mode a constant current independent of factors such as circuit supply voltage, temperature, and load voltage is provided; in the constant voltage driving mode, a sufficiently large driving current capability is provided to meet the current demand of the LED path.
  • the traditional pulse width modulation pulse method is: An 8-bit counter. This counter takes time T For the basic clock cycle, gradually increase from 8'bOOOO OOOO to 8, bllll-1111, and then to 8'b0000-0000. So reciprocating.
  • the duty cycle is 99 ⁇ /256 ⁇ .
  • the refresh rate is: 1/256 ⁇ .
  • the pulse width modulation pulse method proposed by the present invention is: an 8-bit counter. This counter uses the time ⁇ as the basic clock cycle, gradually increasing from 8, b0000 to 0000 to 8, bllll-1111, and then to 8, b0000 0000. So reciprocating.
  • D corpse M 1 *A corpse 1*A corpse * ⁇ i* ⁇ * ⁇ * ⁇ I* ⁇ *26;
  • the PWM output is:
  • OUT is the time when the LED is lit.
  • the LED is lit for:
  • the duty cycle is 99 ⁇ /256 ⁇ .
  • the duty cycle is the same as the conventional pulse width modulation pulse method.
  • the *04 pulse is a high pulse of 16 consecutive basic clocks per 64 basic clocks
  • the * ⁇ i*03 pulse is a high pulse of 8 consecutive basic clocks per 64 basic clocks
  • the pulse of ⁇ i* ⁇ * ⁇ * ⁇ I* ⁇ *26 is a high pulse of two basic clocks independently and uniformly distributed in 256T per 256 basic clocks
  • * ⁇ * ⁇ * ⁇ * ⁇ * ⁇ * ⁇ * ⁇ 7 is a high pulse with one basic clock in the middle of this 256T.
  • the new pulse width modulation pulse method can correctly display the duty ratio, and the refresh rate is improved because of the dispersion of the light-off time. That is, the new pulse width modulation pulse method can improve the refresh rate while ensuring high precision.
  • Figure 11 it is a schematic diagram of the waveforms of various PWMs. If the output frequency is too high, the duty ratio is not true, and the driving capability is insufficient.
  • the solution proposed by the present invention can also be adaptively adjusted, appropriately lowering the refresh rate, increasing the duty ratio, and increasing the refresh rate. The ratio is taken into account (the illustration deliberately reduces the refresh rate for obvious contrast, and the actual situation can increase the output frequency appropriately).
  • the above method or device proposed by the present invention generates a pulse width modulation pulse signal at a higher frequency without affecting the accuracy of the original data, thereby realizing display control of a high refresh frequency, and appropriately adjusting the pulse width modulation pulse PMW Signal duty cycle output mode to ensure the driving effect of the output port.
  • the above method or device proposed by the present invention is realized by logically combining the output of the counter and being gated by data, and the implementation scheme is simple and efficient.
  • each functional unit in each embodiment of the present invention may be integrated into one processing module, or each unit may exist physically separately, or two or more units may be integrated into one module.
  • the above integrated modules can be implemented in the form of hardware or in the form of software functional modules.
  • the integrated modules, if implemented in the form of software functional modules and sold or used as separate products, may also be stored in a computer readable storage medium.
  • the above-mentioned storage medium may be a read only memory, a magnetic disk or an optical disk or the like.

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Description

显示控制的倍频方法及装置 技术领域
本发明涉及数字控制领域, 具体而言, 本发明涉及显示控制的方法及装 置。 背景技术
如何控制 LED的亮度, 技术发展从开始的模拟调光方式到现在的脉宽 调制脉冲调光方式,甚至现在很多应用中可以将模拟调光和脉宽调制脉冲调 光结合使用。 模拟调光是指, 通过写入的数据, 调节流过 LED的电流大小, 使得 LED亮度发生变化。 脉宽调制脉冲调光是指, 通过在一段时间内, 调 节 LED亮或者灭的时间宽度。 LED导通的时候, 是固定电流驱动, 可以通 过外置电阻设定; LED 关断的时候, 没有电流通过。 这样, 在一定的时间 内的显示效果是灯的亮度发生了变化。 并且在这个固定时间内, 灯亮的时间 越长, 总体效果为灯就越亮。 这样可以达到在一定时间内, 对 LED进行亮 度调节的目的。
模拟调光的缺点主要有如下两点: 1、 改变经过 LED 的电流, 会改变 LED的光色,这样会使得像素的色配增加很多不确定性; 2、如果要增加 LED 的灰度等级, 需要高精度的 DAC, 其线性度和精度受到限制。
脉宽调制脉冲调光则完全规避了上述模拟调光的缺点。 灯点亮的时候, 流过的是固定的电流, 光的波长不会变化。 如果需要增加灰度等级, 将用于 脉宽调制脉冲的基本时钟提速, 在原来固定的时间周期内, 容许的占空比选 择会更多; 或者将原来时间周期加长, 用原有的基本时钟, 也会有更多的占 空比选择。
所以, 业内基本都釆用脉宽调制脉冲调光的方式对 LED调光。 不过, 脉宽调制脉冲调光也有自身的缺陷。因为此种调光方法是需要将亮度在一定 时间内平均的, 所以当 LED的灰度等级较高时, 周期较长。 这样, LED亮 或灭的时候, 或者捕捉的时间太短, 以至于该时间内接受到的亮灭比, 不能 很真实的体现原有亮灭比。摄像机等数码摄像产品拍摄画面时, 捕捉时间远 远小于人眼对画面的捕捉时间。 这样, 人眼看起来较清晰的画面, 被摄像机 或者相机拍摄时, 画面可能造成闪烁感, 或者说产生条紋。
在现有的脉宽调制脉冲倍频方法中, 大都存在由 MSB ( Most Significant Bit, 最高有效位) 和 LSB ( Least Significant Bit, 最低有效位) 构成的倍频 小周期。 MSB 是脉宽调制脉冲标准周期数据中的高字位, 虽略有失真, 但 能较好的反映脉宽调制脉冲标准周期的占空比; LSB是脉宽调制脉冲标准周 期数据中的低字位, 仅仅是为了在一个脉宽调制脉冲标准周期内(即倍频之 前的周期) , 整体显示不失真。 这样就存在: 当捕捉到 LSB附近的时刻时, 会造成较为明显的局部显示失真。
因此, 有必要提出一种有效的技术方案, 在不影响原有数据的精度和输 出占空比的前提下, 能有效提高显示的刷新频率, 而且能保持输出端口的驱 动能力。 发明内容
本发明的目的旨在至少解决上述技术缺陷之一,特别通过在不影响原有 数据的精度的前提下, 以更高的频率生成脉宽调制脉冲信号, 实现高刷新频 率的显示控制。
为了达到上述目的, 本发明的实施例一方面提出了一种显示控制的方 法, 包括以下步骤:
获取预设的亮度设定值 Ml 输入数据选通器作为选通数据, 以及基本 时钟进入计数器, 输出周期性数字信号 经过逻辑运算器之后输出 ^进入 所述数据选通器作为被选通数据, 所述数据选通器输出 D1 ;
所述数据选通器输出的 进入经过逻辑组合器后, 输出脉宽调制脉冲 PMW信号 OUT, 其中:
所述亮度设定值^等于在一个完整计数器周期内所述脉宽调制脉冲 PWM信号 OUT 的高电平时间包含基本时钟的个数, 并且所述脉宽调制脉 冲 PWM信号 OUT的高电平时间分割成多个亮度控制信号, 其后在一个完 整计数器周期内分别出现, 从而提高显示刷新率, 0≤Κη , η 为所述计数器 的位数长度, 高电平时间是指有效显示时间; 所述脉宽调制脉冲 PMW信号 OUT驱动发光二极管 LED进行显示控制。 本发明实施例另一方面还提出了一种计算机程序,用于执行上述的显示 控制的方法。
本发明实施例另一方面还提出了一种具有计算机可执行部件的计算机 可读介质, 用于承载执行上述的显示控制的方法的计算机程序。
本发明实施例另一方面还提出了一种显示控制的装置, 包括计数器、逻 辑运算器、 数据选通器以及逻辑组合器,
所述计数器, 用于接收基本时钟, 输出周期性数字信号
所述逻辑运算器,用于接收所述周期性数字信号 后输出 进入所述数 据选通器作为被选通数据;
所述数据选通器, 用于接收 以及获取预设的亮度设定值 作为选通 数据, 所述数据选通器输出 D1 ;
所述逻辑组合器, 用于接收1^后, 输出脉宽调制脉冲 PMW信号 OUT 驱动发光二极管 LED, 实现显示控制, 其中:
所述亮度设定值^等于在一个完整计数器周期内所述脉宽调制脉冲 PWM信号 OUT 的高电平时间包含基本时钟的个数, 并且所述脉宽调制脉 冲 PWM信号 OUT的高电平时间分割成多个亮度控制信号, 其后在相同时 间内分别出现, 从而提高显示刷新率, 0≤Kn , η为所述计数器的位数长度。
本发明提出的上述方案, 通过在不影响原有数据的精度的前提下, 以更 高的频率生成脉宽调制脉冲信号, 实现高刷新频率的显示控制, 同时适当调 节脉宽调制脉冲 PMW信号占空比输出方式, 以保证输出端口的驱动效果。 本发明提出的上述方案, 通过对计数器的输出进行逻辑组合, 并且通过数据 来选通的方式实现, 实现方案简单、 高效。
本发明附加的方面和优点将在下面的描述中部分给出,部分将从下面的 描述中变得明显, 或通过本发明的实践了解到。 围说明
本发明上述的和 /或附加的方面和优点从下面结合附图对实施例的描述 中将变得明显和容易理解, 其中: 图 1为传统脉宽调制脉冲实现示意图;
图 2为根据本发明实施例显示控制的方法流程图;
图 3为根据本发明实施例脉宽调制脉冲实现示意图;
图 4为用异步计数器的示意图;
图 5为用同步计数器的示意图;
图 6为逻辑运算器示意图;
图 7为数据选通器示意图;
图 8为逻辑组合器示意图;
图 9为产生的逻辑组合波形及 PWM输出波形示意图;
图 10为根据本发明实施例显示控制的装置结构示意图;
图 11为脉宽调制脉冲技术对比示意图。 具体实施方式
下面详细描述本发明的实施例, 所述实施例的示例在附图中示出, 其中 自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能 的元件。 下面通过参考附图描述的实施例是示例性的, 仅用于解释本发明, 而不能解释为对本发明的限制。
现在人们要求显示画面越来越清晰, 画面内容越来越复杂。 也就是说, 画面的数据量越来越大, 而同时需要较高的平板显示刷新频率。 因此需要平 板显示芯片能以更高的频率生成脉宽调制脉冲信号,并且不影响原有数据的 精度。 传统脉宽调制脉冲的实现方式是: 基本时钟(CLK )输入到一个计数 器, 计数器开始计数, 从起始数据, 例如全 0 , —直到结束数据, 例如全 1 , 如此周期往复。 如果计数器的输出小于数据 DATA的值, 那么输出就为高 电平, 否则输出就为低电平。 这样, 数据以占空比的形式输出。 结构图如图 1所示。
对画面的清晰度要求越来越高, 意味着需要像素点能够包含更多的信 息, 也就是灰度等级越来越高, 在基本时钟确定的情况下, 脉宽调制脉冲标 准周期会越来越长。对传统的脉宽调制脉冲方式来说, 用摄像机或者照相机 这就需要解决一个问题: 在提高清晰度的同时, 又需要避免让相机等数码产 品捕捉到条紋。
通常, 当数据的刷新频率达到 60Hz以上时, 人眼对图像的感知就不会 有闪烁感或者条紋感; 而相机的快门可以达到 4000Hz。 也就是说, 人眼允 许的脉宽调制脉冲标准周期为 16.7毫秒, 而相机则只允许 0.25毫秒。 譬如 现在通用屏的数据更新周期为 4毫秒。人眼看起来非常清晰, 但是用摄像机 拍摄时, 由于 0.25 毫秒不能捕捉到整个脉宽调制脉冲标准周期, 而且 0.25 毫秒时间内捕捉到的占空比不能体现该时刻需要展现的数据。所以条紋感明
JU
因此, 需要提出一种新的脉冲宽度调制协议, 既能允许摄像机较短的快 门时间内所捕捉的占空比,又能较好的反映整个脉宽调制脉冲标准周期内的 占空比, 同时具有足够的输出驱动能力。
为了实现本发明之目的, 本发明提出了一种显示控制的方法, 包括以下 步骤: 获取预设的亮度设定值 Ml 输入数据选通器作为选通数据, 以及基 本时钟进入计数器, 输出周期性数字信号 经过逻辑运算器之后输出 ^进 入所述数据选通器作为被选通数据, 所述数据选通器输出 D1 ; 所述数据选通 器输出的 A进入经过逻辑组合器后, 输出脉宽调制脉冲 PMW信号 OUT, 其中: 所述亮度设定值^等于在一个完整计数器周期内所述脉宽调制脉冲 PWM信号 OUT 的高电平时间包含基本时钟的个数, 并且所述脉宽调制脉 冲 PWM信号 OUT的高电平时间分割成多个亮度控制信号, 其后在一个完 整计数器周期内分别出现, 从而提高显示刷新率, 0≤Kn , η 为所述计数器 的位数长度; 所述脉宽调制脉冲 PMW信号 OUT驱动发光二极管 LED进行 显示控制。 在本发明的实施例中, 例如高电平时间是指有效显示时间。
如图 2所示, 为根据本发明实施例显示控制的方法流程图, 包括以下步 骤:
S110: 选通数据和被选通数据输入数据选通器后输出数据信号
在步骤 S110中,基本时钟输入计数器,计数器输出周期性数字信号 Ql 经过逻辑运算器之后输出 进入所述数据选通器作为被选通数据,
如图 3所示, 为根据本发明实施例脉宽调制脉冲实现示意图。 具体而言, 基本时钟(CLK )输入到一个 n位的计数器, 计数器开始计 数, 从起始数据, 例如 n个 0 , —直到结束数据, 例如 n个 1 , 如此周期往 复。
具体而言 ,计数器包括异步计数器或同步计数器。作为本发明的实施例 , n个输出的高电平时间具有重叠部分, 且占空比为 1/2 , 高位的输出高脉冲 包含基本时钟的个数是相邻低位的输出高脉冲包含基本时钟的个数的 2倍, 低位频率是高位频率的 2 倍, 所输出信号从高位到低位依次为
Q(n- l ),Q(n_2), + + +,Q。。
如图 4所示, 为用异步计数器的示意图, 由 D触发器串组成。 每一级 的 D触发器的 QB端接 D端。前一级 D触发器的 Q端连接后一级 D触发器 的 CLKB端, QB端连接后一级 D触发器的 CLK端。 如图 5所示, 为用同 步计数器的示意图。 当所有低位的输出为全 1 , 该高位的输出为 0时, 改变 该高位的状态, 从 0变成 1 , 或者从 1变成 0。
计数器输出的周期性数字信号 经过逻辑运算器包括:
周期性数字信号 通过逻辑运算得到 n个输出, n个输出的高电平时 间不重叠,高位的输出高脉冲包含基本时钟的个数是相邻低位的输出高脉冲 包含基本时钟的个数的 2倍,每个输出的高脉冲数量平均分布于脉宽调制脉 冲标准周期内。
进一步而言 ,计数器输出的周期性数字信号 经过所述逻辑运算器输出
Al 5 从高位到低位依次的输出为 Α_υ, Α_2), ..., Α。, 满足以下条件:
Figure imgf000008_0001
其中 k为 0或者小于 n的正整数;从而使得原本交叠的高脉冲被运算后 不交叠, 原本占空比固定为 1/2经运算后高位占空比是低位占空比的 2倍。
如图 6所示, 为逻辑运算器示意图, 对应 n个输入和 n个输出。 根据输 出驱动效果情况, 选定上述公式中的 k之后, 将输入 Qk作为输出最高位 A ( η-ι , , 在本实施例中, 选取用 BUF緩冲器来增大驱动能力, 不影响数据的 传输。 相应的, 次高位 Α ^2 )输出为: 当 Qk为低电平时即 INV反相器之后 的数据为 1时, 作为输出, 否则保持为低电平; 同样的, 其余位都可 用逻辑门电路, 根据上述式子简单实现输出。
同时, 在步骤 S110中, 获取预设的亮度设定值 Ml 输入数据选通器作 为选通数据。 其后, 数据选通器根据选通数据和被选通数据, 输出数据信号
D1
如图 7所示, 为数据选通器示意图。 本实施例釆用了与门的方式进行, 即丫=八*:8 , 如果正常输出 B , 则需要必须 A=l , 否则输出维持为 0。 在实际 应用中, 亦可釆用传输门等类似电路实现, 但其目的通常是做数据选通用。
当选通数据该位是为 "真" , 则选通相应该位的被选通数据; 当选通数 据该位是 "假" , 则屏蔽相应该位的被选通数据。 例如, 如果数据该位是 1 , 就选通相应的逻辑运算位;如果数据该位是 0 ,就屏蔽相应的逻辑组运算位, 然后将它们的输出进行逻辑或。
作为本发明的实施例, 数据选通器的输出满足如下公式:
D =M1*A1 ,
被选通数据从高位到低位依次的输出为 Α^^ Α^^ .,., Αο , 选通数据从高 位到低位依次的输出为 M^^M^^ Mo , 输出信号从高位到低位依次的输 出为 ϋ_υ_2),...,ϋ。; 当所述选通数据的位数长度小于 η时, 选通数据的输 出 零补齐为 n位。
S 120:数据选通器输出的数据信号经过逻辑组合器后输出脉宽调制脉冲 PWM信号。
在步骤 S120中, 逻辑组合器包括:
将数据选通器的输出, 进行逻辑或, 并输出脉宽调制脉冲 PWM信号。 如图 8所示, 为逻辑组合器的示意图。 本实施例釆用了逻辑或门的方式 实现, 亦可釆用其他电路实现该模块之功能: 即如果某一个输入为高电平, 那么输出即为高电平。 其中高电平时间即为输出有效时间。 如果某实施应用 中, 釆用低电平时间为输出有效时间, 那么此处可以釆用逻辑与门的方式。 总之, 该模块是将 n个输入的有效时间进行汇总。
作为本发明的实施例, 脉宽调制脉冲 PMW信号 OUT满足以下公式:
OUT = !=o 。
通过上述方式, 则原本 2"个基本时钟数的完整计数器周期内, 连续的高 脉冲宽度被切割成多个不连续的高脉冲。 输出信号具有如下特征: 亮度设定 值的大小,等于在一个完整计数器周期内所述一系列脉宽调制脉冲 PWM信 号的高电平时间包含基本时钟的个数; 并且所述一系列脉宽调制脉冲 PWM 信号高电平时间分割成多个亮度控制信号, 经由在相同时间内分别显示, 形 成更高的刷新率。
进一步而 当选取 k=0时, 逻辑运算器的输出为:
Figure imgf000010_0001
此时, 逻辑运算器输出的最高位, 以最高的刷新频率来表征 1/2占空比 刷新率为 J_ , 其中 T是基本时钟周期。
27
由于在实际装置应用中, 不同的应用场合对基本时钟的频率要求不同。 如果基本时钟的频率较快, 例如达到了 33 兆赫兹 (即 T=30纳秒) , 这样 如果输出驱动端口的驱动能力有限, 使得占空比发生了畸变, 如图 10所示, 会影响到使用效果。 所以在实际应用中, 需要注意脉宽调制脉冲输出最高频 率与输出端口驱动能力之间的平衡关系。
通过上述步骤, 可以实现脉宽调制脉冲输出倍频和不影响精度的要求, 如图 9所示, 为产生的逻辑组合波形及 PWM输出波形示意图。
S130: PWM信号驱动发光二极管 LED进行显示控制。
在步骤 S130中,利用步骤 S120得到的脉冲信号,驱动发光二极管 LED, 实现显示控制。 通常, 输出脉宽调制脉冲 PMW信号 OUT驱动发光二极管 LED中间还会连接 LED驱动电路, 用于满足 LED的驱动电流要求。 在恒流 驱动方式中,提供与电路供电电压、温度、 负载电压等因素无关的恒定电流; 在恒压驱动方式中, 提供足够大的驱动电流能力, 以满足 LED通路的电流 需要。
基于上述的显示控制方法, 本发明还提出通过一种计算机程序, 用于执 行上述实施例中的显示控制方法。
基于上述的显示控制方法,本发明还提出一种具有计算机可执行部件的 计算机可读介质, 用于承载执行上述实施例中的显示控制方法的计算机程 序。
如图 10所示,为根据本发明实施例显示控制的装置 100的结构示意图, 包括计数器 110、 逻辑运算器 120、 数据选通器 130以及逻辑组合器 140。 其中, 计数器 110 , 用于接收基本时钟, 输出周期性数字信号 逻辑运算器 120 , 用于接收周期性数字信号 后输出 进入数据选通器
130作为被选通数据。
计数器 110包 n个输出的高电平时间具有 重叠部分, 且占空比为 1/2 , 高位的输出高脉冲包含基本时钟的个数是相邻 低位的输出高脉冲包含基本时钟的个数的 2 倍, 低位频率是高位频率的 2 倍, 所输出信号从高位到低位依次为(^η_υ,(^η_2),...,0。。
计数器 110输出的周期性数字信号 (^经过逻辑运算器 120包括: 周期性数字信号 通过逻辑运算得到 n个输出, n个输出的高电平时间 不重叠,高位的输出高脉冲包含基本时钟的个数是相邻低位的输出高脉冲包 含基本时钟的个数的 2倍,每个输出的高脉冲数量平均分布于脉宽调制脉冲 标准周期内。
计数器 110输出的周期性数字信号 经过逻辑运算器 140输出 ,从高 位到低位
Figure imgf000011_0001
其中 k为 0或者小于 n的正整数;从而使得原本交叠的高脉冲被运算后 不交叠, 原本占空比固定为 1/2经运算后高位占空比是低位占空比的 2倍。
数据选通器 130 ,用于接收^以及获取预设的亮度设定值 ^作为选通数 据, 数据选通器 130输出 I
数据选通器 130包括:
当选通数据该位是为 "真" , 则选通相应该位的被选通数据; 当选通数 据该位是 ' 1" , 则屏蔽相应该位的被选通数据。
数据选通器 130的输出满足如下公式:
D =M1*A1 ,
被选通数据从高位到低位依次的输出为 Α^^ Α^^ .,., Αο , 选通数据从高 位到低位依次的输出为 M^^M^^ Mo , 输出信号从高位到低位依次的输 出为 ϋ_υ, ϋ_2), ..., ϋ。; 当选通数据的位数长度小于 η时, 选通数据的输出 力口零补齐为 n位。
逻辑组合器 140 , 用于接收1^后, 输出脉宽调制脉冲 PMW信号 OUT 驱动发光二极管 LED, 实现显示控制, 其中:
亮度设定值 ^等于在一个完整计数器 110周期内脉宽调制脉冲 PWM信 号 OUT的高电平时间包含基本时钟的个数, 并且脉宽调制脉冲 PWM信号 OUT 的高电平时间分割成多个亮度控制信号, 其后在一个完整计数器周期 内分别出现, 从而提升了显示刷新率, 0≤Kn , η为计数器 110的位数长度。
逻辑组合器 140包括:
将数据选通器 130的输出, 进行逻辑或, 并输出脉宽调制脉冲 PWM信 号。
逻辑组合器 140输出的脉宽调制脉冲 PMW信号 OUT满足以下公式:
进一步而 当选取 k=0时, 逻辑运算器的输出为:
Figure imgf000012_0001
此时, 逻辑运算器输出的最高位, 以最高的刷新频率来表征 1/2占空比 刷新率为 J_ , 其中 T是基本时钟周期。
27
由于在实际装置应用中, 不同的应用场合对基本时钟的频率要求不同。 如果基本时钟的频率较快, 例如达到了 33 兆赫兹 (即 T=30纳秒) , 这样 如果输出驱动端口的驱动能力有限, 使得占空比发生了畸变, 如图 10所示, 会影响到使用效果。 所以在实际应用中, 需要注意脉宽调制脉冲输出最高频 率与输出端口驱动能力之间的平衡关系。
通常, 输出脉宽调制脉冲 PMW信号 OUT驱动发光二极管 LED中间还 会连接 LED驱动电路,用于满足 LED的驱动电流要求。在恒流驱动方式中, 提供与电路供电电压、 温度、 负载电压等因素无关的恒定电流; 在恒压驱动 方式中, 提供足够大的驱动电流能力, 以满足 LED通路的电流需要。
为了进一步阐述本发明, 下面结合进一步的实施例, 以一个 8 位数据 ( 8'b0110— 0011 ) 的脉宽调制脉冲信号为例对本发明进行说明。
传统脉宽调制脉冲方法是: 一个 8 位的计数器。 这个计数器以时间 T 为基本时钟周期, 从 8'bOOOO OOOO 逐步加一到 8,bllll— 1111, 然后再到 8'b0000— 0000。 如此往复。 灰度数据更新到数据存储器中, 如果计数器的输 出数值小于 8,b0110— 0011, 那么脉宽调制脉冲输出就是 1 (即让 LED亮) , 否则输出就是 0(即让 LED灭)。那么 LED灯亮的时间为 2° +21 +25 +26 =99Τ , 灭的时间为 256Τ-99Τ=157Τ。 占空比为 99Τ/256Τ。 并且在一个大的脉宽调 制脉冲标准周期内, 仅仅亮一次, 灭一次, 刷新率为: 1/256Τ。
本发明提出的脉宽调制脉冲方法是: 一个 8位的计数器。 这个计数器以 时间 Τ为基本时钟周期, 从 8,b0000— 0000逐步加一到 8,bllll— 1111, 然后 再到 8,b0000 0000。 如此往复。
计数器的 8个输出, Q7, ...... , Q0, 通过逻辑运算器, 那么根据逻辑 运算器公式:
Figure imgf000013_0001
根据刷新率和端口驱动的要求, 选取 k=5, 输出分别为:
4 = Q5;
= 25*24;
= 25*2 *23;
= 25*ρ4*ρ3*ρ2*ρΐ*ρθ;
逻辑运算器的 n 个输出, 经过数据选通器, 选通数据为 M1分别为:
8'b0110— 0011, 被选通数据 A如上所述。 得到输出数据 如下:
D7=M7*A7=0* A7=0;
D6=M6*A6=1*A6=^*24;
D5=M5*A5=1*A5= Q5"Q4"Q3;
D4=M4*A4=0* A4=0;
D3=M3*A3=0* A3=0;
D2=M2*A2=0* A2=0;
D尸M1*A尸 1*A尸 *^i*^*^*^I*^*26; D0=M0 * A0= 1 * A0= 05 * 04 * 03 * 02 * 0 * 00 * 06 * 07 ;
数据选通器的 n个输出, 作为逻辑组合器的 n个输入, 根据逻辑组合器 公式, PWM输出为:
OUT= -o
OUT即为 LED点亮的时间。
LED点亮的时间为:
256Γ + 256Γ + 256Γ + 256Γ = 64Γ + 32Γ + 2Γ + Γ = 99Γ
4 8 128 256
占空比为 99Τ/256Τ。 占空比与传统脉宽调制脉冲方法一样。 但是因为 *04的脉冲是每 64 个基本时钟中有 16 个连续的基本时钟的高脉冲, *^i*03的脉冲是每 64个基本时钟中有 8个连续的基本时钟的高脉冲, *^i*^*^*^I*^*26的脉冲是每 256个基本时钟中有 2个独立且均匀分 布在 256T 中的基本时钟的高脉冲, 而 *^*^*^*^ϊ*^*^*ρ7是在这 256T的正中间有 1个基本时钟的高脉冲。
所以, 新的脉宽调制脉冲方法能够正确显示占空比, 并且由于其亮灭时 间分散, 所以提高了刷新率。 即, 新的脉宽调制脉冲方法能保证高精度的情 况下, 提高刷新率。 如图 11所示, 为各种 PWM的波形示意图。 如果相对 于输出频率过高容易导致占空比不真实、驱动能力输出不足的情况, 本发明 提出的方案也可以进行适应性调整, 适当调低刷新率、 提高占空比, 对刷新 率与占空比都兼顾(图示为了明显对比而故意降低刷新率, 实际情况可以适 当提高输出频率) 。
本发明提出的上述方法或设备, 通过在不影响原有数据的精度的前提 下, 以更高的频率生成脉宽调制脉冲信号, 实现高刷新频率的显示控制, 同 时适当调节脉宽调制脉冲 PMW信号占空比输出方式, 以保证输出端口的驱 动效果。本发明提出的上述方法或设备,通过对计数器的输出进行逻辑组合, 并且通过数据来选通的方式实现, 实现方案简单、 高效。
本领域普通技术人员可以理解实现上述实施例方法携带的全部或部分 步骤是可以通过程序来指令相关的硬件完成,所述的程序可以存储于一种计 算机可读存储介质中, 该程序在执行时, 包括方法实施例的步骤之一或其组 合。
另外, 在本发明各个实施例中的各功能单元可以集成在一个处理模块 中, 也可以是各个单元单独物理存在, 也可以两个或两个以上单元集成在一 个模块中。 上述集成的模块既可以釆用硬件的形式实现, 也可以釆用软件功 能模块的形式实现。所述集成的模块如果以软件功能模块的形式实现并作为 独立的产品销售或使用时, 也可以存储在一个计算机可读取存储介质中。
上述提到的存储介质可以是只读存储器, 磁盘或光盘等。
以上所述仅是本发明的实施方式, 应当指出, 对于本技术领域的普通技 术人员来说, 在不脱离本发明原理的前提下, 还可以做出若干改进和润饰, 这些改进和润饰也应视为本发明的保护范围。

Claims

权 利 要 求 书
1、 一种显示控制的方法, 其特征在于, 包括以下步骤:
获取预设的亮度设定值 Ml 输入数据选通器作为选通数据, 以及基本 时钟进入计数器, 输出周期性数字信号 经过逻辑运算器之后输出 ^进入 所述数据选通器作为被选通数据, 所述数据选通器输出 D1 ;
所述数据选通器输出的 进入经过逻辑组合器后, 输出脉宽调制脉冲 PMW信号 OUT , 其中:
所述亮度设定值^等于在一个完整计数器周期内所述脉宽调制脉冲 PWM信号 OUT 的高电平时间包含基本时钟的个数, 并且所述脉宽调制脉 冲 PWM信号 OUT的高电平时间分割成多个亮度控制信号, 其后在一个完 整计数器周期内分别出现, 从而提高显示刷新率, 0≤i<n , n 为所述计数器 的位数长度;
所述脉宽调制脉冲 PMW信号 OUT驱动发光二极管 LED进行显示控制。
2、 如权利要求 1所述的显示控制的方法, 其特征在于, 所述计数器包 括异步计数器或同步计数器, 所述 n个输出的高电平时间具有重叠部分, 且 占空比为 1/2 , 高位的输出高脉冲包含基本时钟的个数是相邻低位的输出高 脉冲包含基本时钟的个数的 2倍, 低位频率是高位频率的 2倍, 所输出信号 从高位到低位依次为(^η_υ,(^η_2),...,(¾。
3、 如权利要求 2所述的显示控制的方法, 其特征在于, 所述计数器输 出的周期性数字信号 经过所述逻辑运算器包括:
所述周期性数字信号 通过逻辑运算得到 n个输出,所述 n个输出的高 电平时间不重叠,高位的输出高脉冲包含基本时钟的个数是相邻低位的输出 高脉冲包含基本时钟的个数的 2倍 ,每个输出的高脉冲数量平均分布于脉宽 调制脉冲标准周期内。
4、 如权利要求 3所述的显示控制的方法, 其特征在于, 所述计数器输 出的周期性数字信号 经过所述逻辑运算器输出 ,从高位到低位依次的输 出为 ) , A¾_2) , ..., Α。, A1满足以下条件:
Figure imgf000017_0001
其中 k为 0或者小于 n的正整数;从而使得原本交叠的高脉冲被运算后 不交叠, 原本占空比固定为 1/2经运算后高位占空比是低位占空比的 2倍。
5、 如权利要求 4所述的显示控制的方法, 其特征在于, 选取 k=0, 逻 辑运算器的输出为:
Figure imgf000017_0002
此时逻辑运算器输出的最高刷新频率为丄, 其中 T是基本时钟周期。
27
6、 如权利要求 4所述的显示控制的方法, 其特征在于, 所述数据选通 器包括:
当选通数据该位是为 "真" , 则选通相应该位的被选通数据; 当选通数 据该位是 ' 1" , 则屏蔽相应该位的被选通数据。
7、 如权利要求 6所述的显示控制的方法, 其特征在于, 所述数据选通 器的输出满足如下公式:
D =M1*A1 ,
被选通数据从高位到低位依次的输出为 Α^^ Α^^ .,., Αο , 选通数据从高 位到低位依次的输出为
Figure imgf000017_0003
输出信号从高位到低位依次的输 出为 D(n_n,D(n_ , ...,D。; 当所述选通数据的位数长度小于 n时, 所述选通数据 的输出 1^加零补齐为 n位。
8、 如权利要求 7所述的显示控制的方法, 其特征在于, 所述逻辑组合 器包括:
将数据选通器的输出, 进行逻辑或, 并输出脉宽调制脉冲 PWM信号。
9、 如权利要求 8所述的显示控制的方法, 其特征在于, 所述脉宽调制 脉冲 PMW信号 OUT满足以下公式:
OUT = !=o
10、 一种计算机程序, 其特征在于, 用于执行权利要求 1至 9任一项所 述的显示控制的方法。
11、 一种具有计算机可执行部件的计算机可读介质, 其特征在于, 用于 承载执行权利要求 1至 9任一项所述的显示控制的方法的计算机程序。
12、 一种显示控制的装置, 其特征在于, 包括计数器、 逻辑运算器、 数 据选通器以及逻辑组合器,
所述计数器, 用于接收基本时钟, 输出周期性数字信号
所述逻辑运算器,用于接收所述周期性数字信号 后输出 进入所述数 据选通器作为被选通数据;
所述数据选通器, 用于接收 A以及获取预设的亮度设定值 ^作为选通 数据, 所述数据选通器输出 D1 ;
所述逻辑组合器, 用于接收1^后, 输出脉宽调制脉冲 PMW信号 OUT 驱动发光二极管 LED , 实现显示控制, 其中:
所述亮度设定值^等于在一个完整计数器周期内所述脉宽调制脉冲 PWM信号 OUT 的高电平时间包含基本时钟的个数, 并且所述脉宽调制脉 冲 PWM信号 OUT的高电平时间分割成多个亮度控制信号, 其后在相同时 间内分别出现, 从而提高显示刷新率, 0≤i<n , n为所述计数器的位数长度。
13、 如权利要求 12所述的显示控制的装置, 其特征在于, 所述计数器 包括异步计数器或同步计数器, 所述 n个输出的高电平时间具有重叠部分, 且占空比为 1/2 , 高位的输出高脉冲包含基本时钟的个数是相邻低位的输出 高脉冲包含基本时钟的个数的 2倍, 低位频率是高位频率的 2倍, 所输出信 号从高位到低位依次为(^η_υ,(^η_2),...,(¾。
14、 如权利要求 13所述的显示控制的装置, 其特征在于, 所述计数器 输出的周期性数字信号 经过所述逻辑运算器包括:
所述周期性数字信号 通过逻辑运算得到 n个输出,所述 n个输出的高 电平时间不重叠,高位的输出高脉冲包含基本时钟的个数是相邻低位的输出 高脉冲包含基本时钟的个数的 2倍 ,每个输出的高脉冲数量平均分布于脉宽 调制脉冲标准周期内。
15、 如权利要求 14所述的显示控制的装置, 其特征在于, 所述计数器 输出的周期性数字信号 经过所述逻辑运算器输出 Al 从高位到低位依次的 输出为 Α^η, Α^^ .,., Αο , 满足以下条件:
Figure imgf000019_0001
其中 k为 0或者小于 n的正整数;从而使得原本交叠的高脉冲被运算后 不交叠, 原本占空比固定为 1/2经运算后高位占空比是低位占空比的 2倍。
16、 如权利要求 15所述的显示控制的方法, 其特征在于, 选取 k=0 , 逻辑运算器的输出为:
Figure imgf000019_0002
此时逻辑运算器输出的最高刷新频率为丄, 其中 T是基本时钟周期。
27
17、 如权利要求 15所述的显示控制的装置, 其特征在于, 所述数据选 通器包括:
当选通数据该位是为 "真" , 则选通相应该位的被选通数据; 当选通数 据该位是 ' 1" , 则屏蔽相应该位的被选通数据。
18、 如权利要求 17所述的显示控制的装置, 其特征在于, 所述数据选 通器的输出满足如下公式:
D =M1*A1 ,
被选通数据从高位到低位依次的输出为 Α^^ Α^^ .,., Αο , 选通数据从高 位到低位依次的输出为
Figure imgf000019_0003
输出信号从高位到低位依次的输 出为 D(n_n,D(n_ , ...,D。; 当所述选通数据的位数长度小于 n时, 所述选通数据 的输出 1^加零补齐为 n位。
19、 如权利要求 18所述的显示控制的装置, 其特征在于, 所述逻辑组 合器包括:
将数据选通器的输出, 进行逻辑或, 并输出脉宽调制脉冲 PWM信号。
20、 如权利要求 19所述的显示控制的装置, 其特征在于, 所述逻辑组 合器输出的所述脉宽调制脉冲 PMW信号 OUT满足以下公式:
OUT = -0 。
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