WO2022020502A1 - Methods for fabricating a 3-dimensional memory structure of nor memory strings - Google Patents

Methods for fabricating a 3-dimensional memory structure of nor memory strings Download PDF

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Publication number
WO2022020502A1
WO2022020502A1 PCT/US2021/042620 US2021042620W WO2022020502A1 WO 2022020502 A1 WO2022020502 A1 WO 2022020502A1 US 2021042620 W US2021042620 W US 2021042620W WO 2022020502 A1 WO2022020502 A1 WO 2022020502A1
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layer
trench
oxide
semiconductor
shafts
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PCT/US2021/042620
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English (en)
French (fr)
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Vinod Purayath
Yosuke Nosho
Shohei KAMISAKA
Michiru NAKANE
Eli Harari
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Sunrise Memory Corporation
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Priority to JP2023504166A priority Critical patent/JP2023535394A/ja
Publication of WO2022020502A1 publication Critical patent/WO2022020502A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40117—Multistep manufacturing processes for data storage electrodes the electrodes comprising a charge-trapping insulator
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
    • H01L29/513—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures the variation being perpendicular to the channel plane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/518—Insulating materials associated therewith the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
    • H01L29/7926—Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0466—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS]
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/08—Address circuits; Decoders; Word-line control circuits

Definitions

  • the present invention relates to processes for manufacturing memory integrated circuits.
  • the present invention relates to processes for fabricating thin-film storage transistors in a 3 -dimensional memory structure formed on a planar surface of a semiconductor substrate.
  • High density memory arrays e.g., 3-dimensional arrays of NOR memory strings (“3- D NOR memory arrays”)
  • 3- D NOR memory arrays have been disclosed in, for example, U.S. Patent Application Publication 2017/0092371A1 (“Structural Reference I”), entitled “Capacitive-Coupled Non- Volatile Thin-film Transistor Strings in Three-Dimensional Arrays,” and U.S. Patent Application Publication 2018/0366489A1 (“Structural Reference II”), entitled “3- Dimensional NOR Memory Array Architecture and Methods for Fabrication Thereof.”
  • Structural References I and II are hereby incorporated by reference in their entireties.
  • these 3-D NOR memory arrays may be operated to provide memory circuits at highly desirable speeds that rival conventional memory circuits of much lower circuit densities and significantly higher power dissipation, e.g., as dynamic random-access memories (“DRAMs”).
  • DRAMs dynamic random-access memories
  • a 3-D NOR memory array includes numerous stacks of NOR memory strings, with each stack having numerous NOR memory strings stacked one on top of another.
  • NOR memory string includes numerous storage cells that share a common drain region (“common bit line”) and a common source region (“common source line”), the storage cells being provided on one or both sides along the length of the NOR memory string.
  • Each storage cell is controlled by a conductor (“word line” or “local word line”) that runs substantially orthogonal to the memory string.
  • word line may be shared by numerous storage cells in different NOR memory strings along its length and on opposite sides of the word line.
  • Etching conductors e.g., tungsten
  • a high aspect ratio e.g., 50 or greater
  • a process that creates a NOR memory array with word lines that are separated by a very fine pitch include (i) providing over a planar surface of a semiconductor substrate first and second semiconductor structures separated by a trench having a predetermined width along a first direction that is substantially parallel the planar surface, each semiconductor structure may include multi-layer active strips each extending lengthwise along a second direction that is substantially orthogonal to the first direction, and which are stacked one on top of another along a third direction that is substantially normal to the planar surface, adjacent multi-layer active strips being electrically isolated from each other by a layer of an isolation material, wherein each active multi-layer strip may include first and second semiconductor layers of a first conductivity type separated by a dielectric material; (ii) recessing the sidewalls of the trench at the multi-layer strips along the first direction, thereby creating recesses between two layers of isolation material; (iii) providing in the recesses a predetermined material; (iv) filling the trench with a first
  • the first and second semiconductor layers of each multi-layer active strip, the charge trapping layer, the conductive material may provide, respectively, a common bit line, a common source line, a charge storage layer and a gate electrode of a thin-film storage transistor in a NOR memory string.
  • the predetermined material may be a channel polysilicon material that serves as a channel region for a thin-film storage transistor.
  • the predetermined material is replaced after the word lines are formed to the final channel material, which may be sealed with a dielectric liner (e.gt., an atomic layer deposition (ALD) silicon oxide liner).
  • ALD atomic layer deposition
  • the first and second semiconductor layers may include N + -doped amorphous silicon or polysilicon
  • the third semiconductor layer may include P -doped amorphous or polysilicon
  • the isolation material may include silicon oxycarbide (SiOC) or silicon oxide
  • the charge-trapping layer may include (i) a tunneling layer (e.g., any silicon oxide (SiO x ), silicon nitride (SiN), silicon oxynitride (SiON), any aluminum oxide (A10 x ), any hafnium oxide (HfO x ), zirconium oxide (ZrO x ), any hafnium silicon oxide (HfSi x O y ), any hafnium zirconium oxide (HfZrO), or any combination thereof);(ii) a charge storage layer (e.g., silicon nitride (SiN), hafnium oxide (HfCE), or hafnium silicon oxynit
  • the conductive material may include a metal liner (e.g., titanium (Ti), titanium nitride (TiN), tantalum (Ta) or tantalum nitride (TaN)) and a refractory metal (e.g., tungsten (W), tungsten nitride (WN) or molybdenum (Mo)).
  • the first filler material may include silicon oxide.
  • a cap e.g., tungsten
  • the shafts may be lined with a dielectric liner (e.g., silicon nitride) prior to filling by the second filler material (e.g., silicon oxide).
  • a dielectric liner e.g., silicon nitride
  • FIG. 1 is a schematic top view of modular unit (“tile”) 100 in a memory structure that includes 3-D NOR memory arrays, in accordance with one embodiment of the present invention.
  • Figure 2a(i) shows a cross section in the Z-X plane of memory structure 200 after depositions of numerous material layers (discussed below), in accordance with one embodiment of the present invention.
  • Figure 2a(ii) illustrates successive recessing and etching steps to create staircase portion 102a or 102b of Figure 1, in accordance with one embodiment of the present invention.
  • Figure 2b shows resulting memory structure 200 in an X-Z plane cross section, after separation etch of P -doped amorphous silicon layer 250 is carried out, in accordance with one embodiment of the present invention.
  • Figure 2c shows resulting memory structure 200 in an X-Z plane cross section, after silicon oxide 223 is deposited to fill trenches 216 and planarized.
  • Figure 2d shows resulting memory structure 200 in an X-Z plane cross section, after second group of trenches 218 are formed, according to one embodiment of the present invention.
  • Figure 2e shows resulting memory structure 200 in an X-Z plane cross section, after removal of SiN layers 204a and 204e from each active multi-layer 204, according to one embodiment of the present invention.
  • Figure 2f shows resulting memory structure 200 in an X-Z plane cross section, after replacement of SiN layers 204a and 204e from each of active multi-layers 204 by conductive material 229, according to one embodiment of the present invention.
  • Figure 2g shows resulting memory structure 200 in an X-Z cross section, after recessing conductive material 229, N + amorphous semiconductor layers 204b and 204d and oxide layer 203 of each active multi-layer 204, according to one embodiment of the present invention.
  • Figure 2h shows resulting memory structure 200 in an X-Z cross section, after deposition of channel poly silicon 250 into trenches 218, according to one embodiment of the present invention.
  • Figure 2i shows resulting memory structure 200 in an X-Z cross section, after deposition of silicon oxide 223 into trenches 218, according to one embodiment of the present invention.
  • Figures 2j(i) and 2j(ii) show, respectively, a top view and a cross section view (in an X-Z plane along line A- A’ of Figure 2j(i)) of resulting memory structure 200, after shafts 263 are formed, according to one embodiment of the present invention.
  • Figures 2k(i) and 2k(ii) show, respectively, a top view and a cross section view (in an X-Z plane along line A-A’ of Figure 2k(i)) of resulting memory structure 200, after shafts 263 are filled by sacrificial silicon 265, according to one embodiment of the present invention.
  • Figures 21(i) and 21(h) show, respectively, a top view and a cross section view (in an X-Z plane along line A-A’ of Figure 21(i)) of resulting memory structure 200, after silicon oxide 223 is removed from trenches 218, according to one embodiment of the present invention.
  • Figures 2m(i) and 2m(ii) show, respectively, a top view and a cross section view (in an X-Z plane along line A-A’ of Figure 2m(i)) of resulting memory structure 200, after conductive material 272 is deposited into trenches 218, according to one embodiment of the present invention.
  • Figures 2n(i) and 2n(ii) show, respectively, a top view and a cross section view (in an X-Z plane along line A-A’ of Figure 2n(i)) of resulting memory structure 200, after cap 272t has been formed to protect charge-trapping layer 268, according to one embodiment of the present invention.
  • Figures 2o(i) and 2o(ii) show, respectively, a top view and a cross section view (in an X-Z plane along line A-A’ of Figure 2o(i)) of resulting memory structure 200, after sacrificial amorphous silicon 265 is removed, according to one embodiment of the present invention.
  • Figures 2p(i) and 2p(ii) show, respectively, a top view and a cross section view (in an X-Z plane along line A-A’ of Figure 2p(i)) of resulting memory structure 200, after silicon nitride liner 264 is removed, according to an alternative embodiment of the present invention.
  • Figures 2q(i) and 2q(ii) show, respectively, a top view and a cross section view (in an X-Z plane along line A-A’ of Figure 2q(i)) of resulting memory structure 200, after channel polysilicon 250 is removed, according to an alternative embodiment of the present invention.
  • Figures 2r(i) and 2r(ii) show, respectively, a top view and a cross section view (in an X-Z plane along line A-A’ of Figure 2r(i)) of resulting memory structure 200, after channel polysilicon 280 is deposited, according to an alternative embodiment of the present invention.
  • Figures 2s(i) and 2s(ii) show, respectively, a top view and a cross section view (in an X-Z plane along line A-A’ of Figure 2s(i)) of resulting memory structure 200, after channel polysilicon 280 is recessed, according to an alternative embodiment of the present invention.
  • Figures 2t(i) and 2t(ii) show, respectively, a top view and a cross section view (in an X-Z plane along line A-A’ of Figure 2t(i)) of resulting memory structure 200, after ALD oxide liner 285 is deposited, according to an alternative embodiment of the present invention.
  • FIG. 1 is a schematic top view of modular unit (“tile”) 100 in a memory structure that includes 3-D NOR memory arrays, in accordance with one embodiment of the present invention.
  • Tile 100 is typically formed on a planar surface of a semiconductor substrate, such as a monocrystalline epitaxial layer of a silicon wafer.
  • a rectilinear coordinate reference frame is used, which postulates the planar surface on an X-Y plane, and a normal of the planar surface in the Z-direction orthogonal to the X-Y plane.
  • the semiconductor substrate may include support circuitry for the 3-D NOR memory arrays formed therein or thereon underneath the 3-D NOR memory arrays.
  • Such support circuits may include both analog and digital circuits.
  • Some examples of such support circuits include shift registers, latches, sense amplifiers, reference cells, power supply lines, bias and reference voltage generators, inverters, NAND, NOR, Exclusive-Or and other logic gates, input/output drivers, address decoders (e.g., bit line and word line decoders), other memory elements, data encoding and decoding circuits including, for example, error detection and correction circuits), sequencers and state machines.
  • tile 100 includes “array” portion 101, which is provided between “staircase portions” 102a and 102b.
  • the thin-film storage transistors of the NOR memory strings in tile 100 are formed in array portion 101 and staircase portions 102a and 102b allow connections through conductive vias to the common bit lines and, optionally, the common source lines also, of the NOR memory strings.
  • the Structural References disclose a scheme in which the common source lines are pre-charged to serve as virtual voltage reference source during programming, reading and erase operations, thereby obviating the need for a continuous electrical connection with the support circuitry during such operations.
  • array portion 101 and staircase portions 102a and 102b are not drawn to scale. For example, array portion 101 may be much larger in area than either of staircase portions 102a and 102b.
  • Figure 2a(i) shows a cross section in the Z-X plane of memory structure 200 after depositions of numerous material layers (discussed below), in accordance with one embodiment of the present invention.
  • a pad oxide 201 e.g., a silicon oxide
  • Etch stop layer 202 e.g., tungsten (W), tungsten nitride (WN), aluminum oxide (AIO) or aluminum nitride (AIN)
  • SiOC Silicon oxycarbide
  • Active multi-layers 204 are successively deposited.
  • Active multi-layers 204 each include, in order of deposition, (i) silicon nitride (SiN) layer 204a, (ii) N + -doped amorphous silicon (or polysilicon) layer 204b, (iii) sacrificial oxide layer 204c, (iv) N + -doped amorphous silicon (or polysilicon) layer 204d, and (v) SiN layer 204e.
  • SiOC layer indicated in Figure 2a(i) as SiOC layer 203.
  • Isolation SiOC layer 205 is then deposited on top of multi-layers 204.
  • the resulting structure is memory structure 200 of Figure 2.
  • Figure 2a(ii) illustrates successive recessing and etching steps to create staircase portion 102a or 102b of Figure 1, in accordance with one embodiment of the present invention.
  • the surface of memory structure 200 is patterned to form mask layer 210, exposing a first portion of memory structure 211, as shown in Figure 2a(i)(l).
  • the exposed portion of isolation SiOC layer 205 is then removed to expose a portion of active multi-layer 204 underneath. That exposed portion of active multi-layer 204 is then removed, exposing a portion of SiOC layer 203 underneath.
  • the resulting structure is shown in Figure 2a(ii)(2).
  • Mask layer 210 is then recessed to expose a new portion of isolation SiOC layer 205.
  • CMP chemical-mechanical polishing
  • array portion 101 may also be processed prior to formation of staircase structures 102a and 102b.
  • a hard mask layer e.g., carbon hard mask
  • a hard mask layer is deposited and photo-lithographically patterned over memory structure 200.
  • trenches 216 extends through isolation layers 205 and 203, active multi-layers 204 and etch stop layer 202.
  • trenches 216 are each 70 nm wide, with corresponding edges of adjacent trenches separated 190 nm from each other.
  • trenches 216 are etched at an aspect ratio that is less than 50 (and even less than 30).
  • a series of etching steps then recesses SiN layers 204a and 204e, N + doped amorphous silicon layers 204b and 204d and oxide layer 204c of each active layer 204 by, for example, 10 nm.
  • P -doped amorphous silicon (or poly silicon) layer 250 is conformally deposited and etched back (i.e., a separation etch).
  • N + amorphous silicon layers 204b and 204d of each active multi-layer 204 would provide the common bit line and the common source line of the thin-film transistors of a NOR memory string to be formed.
  • P -doped amorphous silicon layer 250 would provide channel regions for the storage transistors of the NOR memory string.
  • the hard mask and excess P -doped amorphous polysilicon layer 250 on top of memory structure 200 are then removed (e.g., by CMP). Resulting memory structure 200 is shown in an X-Z plane cross section in Figure 2b, after separation etch of P -doped amorphous silicon layer 250 is carried out, in accordance with one embodiment of the present invention.
  • silicon oxide 223 is deposited to fill trenches 216, followed by removal of silicon oxide 223 on the top surface of semiconductor structure 200 and planarization (e.g., by CMP), as shown in an X-Z plane cross section in Figure 2c.
  • second group of trenches 218 are etched in substantially the same manner as trenches 216, as discussed above in conjunction with Figure 2b.
  • Second group of trenches 218 are created between adjacent ones of trenches 216. Since trenches 216 are oxide-filled, the material stacks between adjacent trenches have substantially the same pitch as in the etching of first group of trenches 216, thus providing mechanical support during etching of trenches 218.
  • Trenches 218 are performed at substantially the same aspect ratio as etching of trenches 216. In this manner, forming the trenches in multiple groups allow each trench forming etches to be performed within a desirable aspect ratio (e.g., less than 50).
  • Figure 2d shows resulting memory structure 200 in an X-Z plane cross section, after second group of trenches 218 are formed, according to one embodiment of the present invention.
  • SiN layers 204a and 204e of each of active multi-layers 204 may be removed using, for example, a silicon nitride wet etch.
  • Figure 2e shows resulting memory structure 200 in an X-Z plane cross section, after removal of SiN layers 204a and 204e from each of active multi-layers 204, according to one embodiment of the present invention.
  • An atomic layer deposition (ALD) step deposits conductor material 229 (e.g., a liner of one or more of the following material —titanium, titanium nitride (TiN), tantalum (Ta), or tantalum nitride (TaN) - followed by a refractory metal (e.g., tungsten (W), tungsten nitride, or Molybdenum (Mo)) into the cavities resulting from removing SiN layers 204a and 204e from each of active multi-layers 204.
  • a refractory metal e.g., tungsten (W), tungsten nitride, or Molybdenum (Mo)
  • an etch-back step or an anisotropic etch removes conductive material 229 from the bottom of trenches 218, leaving a substantially conformal layer on their sidewalls.
  • Figure 2f shows resulting memory structure 200 in an X- Z plane cross section, after replacement
  • Conductive material 229 form optional conductor layers in contact with N + amorphous silicon layers 204b and 204d. As N + amorphous silicon layers 204b and 204d of each active multi-layer 204 would become, respectively, the common bit line and the common source line of a NOR memory string to be formed, conductive material 229 reduces the resistivities in the common bit line and the common source line.
  • Conductive material 229 may be further etched to remove it from the sidewalls of trenches 218 and to be further recessed. A series of etching steps then recesses first and second N + -doped amorphous silicon layers 204b and 204d, and oxide layer 204c of each active layer 204 by, for example, 10 nm.
  • Figure 2g shows resulting memory structure 200 in an X-Z cross section, after recessing conductive material 229, N + amorphous semiconductor layers 204b and 204d and oxide layer 203 of each active multi-layer 204, according to one embodiment of the present invention.
  • P -doped amorphous silicon layer (“channel polysilicon”) 250 may be conformally deposited on the sidewalls of trenches 218, in substantially the same manner as described above in conjunction with Figure 2b.
  • Figure 2h shows resulting memory structure 200 in an X-Z cross section, after deposition of channel polysilicon 250 into trenches 218, according to one embodiment of the present invention.
  • Trenches 218 may then be filled by silicon oxide 223 and planarized in the same manner as described above in conjunction with the steps for providing silicon oxide 223 of Figure 2c.
  • Figure 2i shows resulting memory structure 200 in an X-Z cross section, after deposition of silicon oxide 223 into trenches 218, according to one embodiment of the present invention.
  • silicon oxide 223 is deposited into trenches 218 and planarized, no further distinction between trenches 216 and 218 is necessary in the detailed description below. Therefore, hereinafter, trenches 216 and 218 are both referred to as trenches 218.
  • the next steps provide the storage layer and the gate electrode (“word line” or “local word line”) for each thin-film storage transistors of the NOR memory strings.
  • Hard mask 260 is provided over memory structure 200, photolithographically patterned and developed.
  • Hard mask 260 includes columns of oval openings 261.
  • a “column” of objects denotes objects aligned along the Y-direction
  • a “row” of objects denotes objects aligned along the X-direction.
  • Figure 2j(i) adjacent columns of openings 261 are staggered relative to each other along the X-direction, such that the closest openings in adjacent columns have a greater separation between them than if such openings are aligned in the X-direction.
  • adjacent openings within each column are located at a 110 nm pitch along the Y-direction, while adjacent columns are also provided at 110 nm pitch along the X-direction.
  • the major and minor axes of each opening may be 100 nm and 60 nm along the X-direction and the Y-direction, respectively, for example.
  • a series of etchings through openings 261 excavates corresponding shaft 263, removing oxide layers 203 and active multi-layers 204 and reaching down to etch step layer 202.
  • FIG. 2j(i) and 2j(ii) A top view and a cross section view (in an X-Z plane along line A-A’ of Figure 2j(i)) of resulting memory structure 200, after shafts 263 are formed, are shown in Figures 2j(i) and 2j(ii), respectively, according to one embodiment of the present invention.
  • the aspect ratio of the etch steps creating shafts 263 have an aspect ratio that is still substantially within the desirable range (e.g., less than 50).
  • silicon nitride liner 264 (e.g., 5 nm thick) is deposited conformally in shafts 263, which are then filled by sacrificial amorphous silicon 265.
  • Hard mask 260 is then removed and the surface of memory structure 200 is planarized (e.g., by CMP).
  • a top view and a cross section view (in an X-Z plane along line A-A’ of Figure 2k(i)) of resulting memory structure 200, after shafts 263 are filled by sacrificial amorphous silicon 265, are shown in Figures 2k(i) and 2k(ii), respectively, according to one embodiment of the present invention.
  • a wet etch then removes silicon oxide 223 from trenches 218.
  • a conformal charge-trapping layer 268 is conformally deposited on the sidewalls of trenches 218.
  • Charge-trapping layer 268 may be a multi-layer that includes:
  • a tunneling layer e.g., any silicon oxide (SiO x ), silicon nitride (SiN), silicon oxynitride (SiON), any aluminum oxide (A10 x ), any hafnium oxide (HfO x ), zirconium oxide (ZrO x ), any hafnium silicon oxide (HfSi x O y ), any hafnium zirconium oxide (HfZrO), or any combination thereof);
  • a tunneling layer e.g., any silicon oxide (SiO x ), silicon nitride (SiN), silicon oxynitride (SiON), any aluminum oxide (A10 x ), any hafnium oxide (HfO x ), zirconium oxide (ZrO x ), any hafnium silicon oxide (HfSi x O y ), any hafnium zirconium oxide (HfZrO), or any combination thereof);
  • a charge storage layer e.g., silicon nitride (SiN), hafnium oxide (HfCk), or hafnium silicon oxynitride (HfSiON)
  • SiN silicon nitride
  • HfCk hafnium oxide
  • HfSiON hafnium silicon oxynitride
  • a blocking layer e.g., any silicon oxide (SiO x ), any aluminum oxide (AlO x ), or both).
  • the conductive material may include a metal liner (e.g., titanium (Ti), titanium nitride (TiN), tantalum (Ta) or tantalum nitride (TaN)) and a refractory metal (e.g., tungsten (W), tungsten nitride (WN) or molybdenum (Mo)).
  • a tunnel dielectric layer e.g., silicon oxide
  • a storage layer e.g., silicon nitride
  • a blocking dielectric layer e.g., silicon oxide, aluminum oxide, or both.
  • Trenches 218 can then be filled by conductive material 272 (e.g., tungsten, with an TiN adhesion layer), which forms a gate electrode (i.e., the “word line” or the “local word line”) for a storage cell in each active multi-layer 240 along the gate electrode’s length.
  • conductive material 272 e.g., tungsten, with an TiN adhesion layer
  • the gate electrode may be 60 nm x 60 nm or less.
  • a planarization step e.g., CMP may be used to remove excess conductive material 272 from the top surface of memory structure 200.
  • FIG. 2m(i) A top view and a cross section view (in an X-Z plane along line A-A’ of Figure 2m(i)) of resulting memory structure 200, after conductive material 272 is deposited into trenches 218 and planarized, are shown in Figures 2m(i) and 2m(ii), respectively, according to one embodiment of the present invention.
  • Cap 272t may be provided to facilitate contact to the underlying word line and to protect charge-trapping layer 268 in subsequent processing steps.
  • the cap may be formed using additional masking, patterning, depositing (consisting of conductive material 272). and planarization steps.
  • a top view and a cross section view (in an X-Z plane along line A-A’ of Figure 2n(i)) of resulting memory structure 200, after cap 272t is formed, are shown in Figures 2n(i) and 2n(ii), respectively, according to one embodiment of the present invention.
  • Sacrificial amorphous silicon 265 may then be removed from shafts 263 and replaced by a silicon oxide to serve as the isolation between thin- film storage transistors. Excess silicon oxide on the top surface of memory structure 200 may be removed by a planarization step (e.g., CMP). Shafts 263 may also be left unfilled, allowing the air gaps to serve as the isolation between thin-film storage transistors.
  • a top view and a cross section view (in an X- Z plane along line A-A’ of Figure 2o(i)) of resulting memory structure 200, after sacrificial amorphous silicon 265 is removed, are shown in Figures 2o(i) and 2o(ii), respectively, according to one embodiment of the present invention.
  • channel polysilicon 250 is formed early in the manufacturing process (e.g., prior to formation of shafts 263, which is described above in conjunction with Figures 2j(i) and 2j(ii).
  • an alternative embodiment replaces channel polysilicon 250 after sacrificial amorphous silicon 265 is removed.
  • silicon nitride liner 264 is also removed.
  • FIG. 2p(i) A top view and a cross section view (in an X-Z plane along line A-A’ of Figure 2p(i)) of resulting memory structure 200, after silicon nitride liner 264 is removed, are shown in Figures 2p(i) and 2p(ii), respectively, according to an alternative embodiment of the present invention.
  • channel polysilicon 250 is removed by, for example, a wet etch.
  • a top view and a cross section view (in an X-Z plane along line A-A’ of Figure 2q(i)) of resulting memory structure 200, after removal of channel polysilicon 250, are shown in Figures 2q(i) and 2q(ii), respectively, according to an alternative embodiment of the present invention.
  • P -doped channel polysilicon 280 is then deposited into the cavities resulting from removing channel polysilicon 250 from underneath charge-trapping layer 268, for example, and up to 10 nm on the sidewalls of shafts 263.
  • a top view and a cross section view (in an X-Z plane along line A-A’ of Figure 2r(i)) of resulting memory structure 200, after deposition of channel polysilicon 280, are shown in Figures 2r(i) and 2r(ii), respectively, according to an alternative embodiment of the present invention.
  • Channel polysilicon 280 may be recessed to provide greater isolation.
  • an ALD silicon oxide liner 285 e.g., 10 nm
  • FIG. 2t(i) A top view and a cross section view (in an X-Z plane along line A-A’ of Figure 2t(i)) of resulting memory structure 200, after deposition of ALD oxide liner 285, are shown in Figures 2t(i) and 2t(ii), respectively, according to an alternative embodiment of the present invention.
  • a silicon oxide may be deposited into shafts 263 to serve as the isolation between thin-film storage transistors. Excess silicon oxide on the top surface of memory structure 200 may be removed by a planarization step (e.g., CMP). Shafts 263 may also be left unfilled, allowing the air gaps to serve as the isolation between thin-film storage transistors.
  • CMP planarization step

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PCT/US2021/042620 2020-07-21 2021-07-21 Methods for fabricating a 3-dimensional memory structure of nor memory strings WO2022020502A1 (en)

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