WO2022016620A1 - 阵列基板、显示面板及电子设备 - Google Patents

阵列基板、显示面板及电子设备 Download PDF

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Publication number
WO2022016620A1
WO2022016620A1 PCT/CN2020/107153 CN2020107153W WO2022016620A1 WO 2022016620 A1 WO2022016620 A1 WO 2022016620A1 CN 2020107153 W CN2020107153 W CN 2020107153W WO 2022016620 A1 WO2022016620 A1 WO 2022016620A1
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WIPO (PCT)
Prior art keywords
electrode
layer
array substrate
pin diode
substrate
Prior art date
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Ceased
Application number
PCT/CN2020/107153
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English (en)
French (fr)
Inventor
艾飞
宋继越
宋德伟
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Wuhan China Star Optoelectronics Technology Co Ltd
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Wuhan China Star Optoelectronics Technology Co Ltd
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Application filed by Wuhan China Star Optoelectronics Technology Co Ltd filed Critical Wuhan China Star Optoelectronics Technology Co Ltd
Priority to US17/051,929 priority Critical patent/US11835808B2/en
Publication of WO2022016620A1 publication Critical patent/WO2022016620A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/13306—Circuit arrangements or driving methods for the control of single liquid crystal cells
    • G02F1/13312—Circuits comprising photodetectors for purposes other than feedback
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/13338—Input devices, e.g. touch panels
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134363—Electrodes characterised by their geometrical arrangement for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0412—Digitisers structurally integrated in a display
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06V—IMAGE OR VIDEO RECOGNITION OR UNDERSTANDING
    • G06V40/00—Recognition of biometric, human-related or animal-related patterns in image or video data
    • G06V40/10—Human or animal bodies, e.g. vehicle occupants or pedestrians; Body parts, e.g. hands
    • G06V40/12—Fingerprints or palmprints
    • G06V40/13—Sensors therefor
    • G06V40/1318—Sensors therefor using electro-optical elements or layers, e.g. electroluminescent sensing
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/044—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means
    • G06F3/0443—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means using a single layer of sensing electrodes

Definitions

  • the present application relates to the field of display technology, and in particular, to an array substrate, a display panel and an electronic device.
  • optical fingerprint technology is one of the main directions at present. Its principle is to use the different strengths of light reflected by the valleys and ridges of the fingerprint to the sensing area of the display panel, thereby converting different optical signals into The electrical signal is extracted by the chip to form a key fingerprint pattern to achieve the purpose of fingerprint identification.
  • the optical fingerprint technology applied to organic light-emitting diodes is widely used, but the optical fingerprint technology used in the liquid crystal display panel is rarely used. Due to the limitation of backlight, aperture ratio and other factors, the integrated optical fingerprint recognition function in the liquid crystal display panel is increased. The difficulty of fingerprint recognition reduces the accuracy of fingerprint recognition.
  • Embodiments of the present application provide an array substrate, a display panel and an electronic device, which can improve the accuracy of fingerprint identification.
  • Embodiments of the present application provide an array substrate, which includes:
  • the substrate including the control element
  • the third metal layer includes a first electrode, and the first electrode is connected to the control element;
  • the PIN diode includes a first semiconductor layer and an intrinsic semiconductor layer; the PIN diode covers at least part of the semiconductor layer of the control element and part of the first electrode;
  • the second conductive layer is disposed on the PIN diode, the second conductive layer includes a second electrode, and the second electrode covers the PIN diode.
  • Embodiments of the present application further provide a display panel, which includes the above-mentioned array substrate.
  • Embodiments of the present application further provide an electronic device including the above-mentioned display panel.
  • the array substrate, display panel, and electronic device of the embodiments of the present application include a substrate, including a control element; a third metal layer, disposed on the substrate; the third metal layer includes a first electrode, and the control element is connected to the control element.
  • the first electrode is connected; a PIN diode is arranged on the first electrode, the PIN diode includes a first semiconductor layer and an intrinsic semiconductor layer; the PIN diode covers at least part of the semiconductor layer and part of the first semiconductor layer of the control element an electrode; a second conductive layer, disposed on the PIN diode, the second conductive layer includes a second electrode; the second electrode covers the PIN diode; since the photosensitive sensor covers at least part of the semiconductor layer of the control element, Therefore, the aperture ratio is improved, thereby improving the accuracy of fingerprint identification.
  • FIG. 1 is a schematic cross-sectional view of an array substrate according to an embodiment of the present application.
  • FIG. 2 is a flow chart of a manufacturing process of the array substrate shown in FIG. 1 .
  • FIG. 3 is a schematic cross-sectional view of an array substrate according to another embodiment of the present application.
  • FIG. 4 is a schematic structural diagram of a display panel according to an embodiment of the present application.
  • FIG. 5 is a schematic structural diagram of an electronic device according to an embodiment of the present application.
  • first and second are only used for descriptive purposes, and should not be construed as indicating or implying relative importance or implying the number of indicated technical features. Thus, features defined as “first”, “second” may expressly or implicitly include one or more of said features. In the description of the present application, “plurality” means two or more, unless otherwise expressly and specifically defined.
  • the terms “installed”, “connected” and “connected” should be understood in a broad sense, for example, it may be a fixed connection or a detachable connection Connection, or integral connection; it can be mechanical connection, electrical connection or can communicate with each other; it can be directly connected or indirectly connected through an intermediate medium, it can be the internal communication of two elements or the interaction of two elements relation.
  • installed should be understood in a broad sense, for example, it may be a fixed connection or a detachable connection Connection, or integral connection; it can be mechanical connection, electrical connection or can communicate with each other; it can be directly connected or indirectly connected through an intermediate medium, it can be the internal communication of two elements or the interaction of two elements relation.
  • a first feature "on” or “under” a second feature may include direct contact between the first and second features, or may include the first and second features Not directly but through additional features between them.
  • the first feature being “above”, “over” and “above” the second feature includes the first feature being directly above and obliquely above the second feature, or simply means that the first feature is level higher than the second feature.
  • the first feature is “below”, “below” and “below” the second feature includes the first feature being directly below and diagonally below the second feature, or simply means that the first feature has a lower level than the second feature.
  • FIG. 1 is a schematic cross-sectional view of an array substrate according to an embodiment of the present application.
  • the array substrate 100 of this embodiment includes a base 10 , a third metal layer 21 , a PIN diode 30 and a second conductive layer 50 .
  • the substrate 10 includes a control element T1; the control element T1 is also a thin film transistor.
  • the base 10 may include: a base substrate 11 , a first semiconductor layer 14 , a first insulating layer 15 , a first metal layer 16 and a second metal layer 18 .
  • the substrate 10 may further include at least one of a light shielding layer 12, a buffer layer 13, a gate insulating layer 17, a planarization layer 19 and a passivation layer 19'.
  • the substrate 11 may be a glass substrate or a flexible substrate.
  • the material of the base substrate 11 includes one or more of glass, silicon dioxide, polyethylene, polypropylene, polystyrene, polylactic acid, polyethylene terephthalate, polyimide or polyurethane.
  • the light shielding layer 12 is disposed on the base substrate 11 , and the material of the light shielding layer 12 can be a metal material.
  • the buffer layer 13 is disposed on the light shielding layer 12, and the material of the buffer layer 13 includes but not limited to silicon nitride or silicon oxide.
  • the first semiconductor layer 14 is disposed on the buffer layer 13; in a preferred embodiment, the material of the first semiconductor layer 14 is polysilicon. Referring to FIG. 2 , the first semiconductor layer 14 may include a first semiconductor part 141 .
  • the first insulating layer 15 is disposed on the first semiconductor layer 14; the material of the first insulating layer 15 may include at least one of silicon nitride, silicon oxide and organic photoresist.
  • the first metal layer 16 is disposed on the first insulating layer 15 ; the first metal layer 16 includes a first gate electrode 161 .
  • the material of the first metal layer 16 may include at least one of copper, aluminum and titanium.
  • the gate insulating layer 17 is disposed on the first metal layer 16, and the material of the gate insulating layer 17 may include at least one of silicon nitride and silicon oxide.
  • the second metal layer 18 is disposed on the gate insulating layer 17, and the second metal layer 18 includes a first source electrode 181 and a first drain electrode 182; the material of the second metal layer 18 can be the same as that of the first metal layer 16 is the same material.
  • the flat layer 19 is disposed on the second metal layer 18, and the material of the flat layer 19 may include at least one of silicon nitride, silicon oxide and organic photoresist. In a preferred embodiment, the material of the planarization layer 19 is organic photoresist.
  • the passivation layer 19' is disposed on the flat layer 19, and the material of the passivation layer 19' may include at least one of silicon nitride, silicon oxide, and organic photoresist.
  • the third metal layer 21 is disposed on the passivation layer 19'; the third metal layer 21 includes the first electrode 211.
  • the first electrode 211 is connected to the control element T1 , specifically, the first electrode 211 is connected to the first drain electrode 182 .
  • the material of the third metal layer 21 may be at least one of Ti/Al/Ti, Mo, Mo/Cu, and Mo/Al/Mo.
  • the material of the third metal layer 21 is not limited to this.
  • the area of the orthographic projection of the first electrode 211 on the substrate 10 is larger than the area of the orthographic projection of the PIN diode 30 on the substrate 10, that is,
  • the PIN diode 30 partially covers the first electrode 211 .
  • the PIN diode 30 covers at least part of the first semiconductor portion 141 .
  • the PIN diode 30 completely covers the first semiconductor portion 141 .
  • the PIN diode 30 is arranged on the first electrode 211 , and the PIN diode 30 includes a first semiconductor layer 31 , an intrinsic semiconductor layer 32 and a second semiconductor layer 33 ; the intrinsic semiconductor layer 32 and the second semiconductor layer 33 are arranged in sequence on the first semiconductor layer 31 .
  • the material of the first semiconductor layer 31 is N-type amorphous silicon (N+a-Si)
  • the material of the intrinsic semiconductor layer 32 is amorphous silicon (a-Si)
  • the material of the second semiconductor layer 33 is The material is P-type amorphous silicon (P+a-Si).
  • the material of the semiconductor layer of the control element T1 is polysilicon
  • the material of the intrinsic semiconductor layer 32 is amorphous silicon. Since the amorphous silicon can be made relatively thick, it is beneficial to the absorption of light. It is convenient to form a high-performance photosensitive sensor, thus improving the accuracy of fingerprint identification.
  • the second conductive layer 50 is disposed on the PIN diode 30 , and the second conductive layer 50 includes a second electrode 51 .
  • the second electrode 51 covers the PIN diode 30 .
  • the material of the second conductive layer 50 includes, but is not limited to, indium tin oxide.
  • the array substrate 100 further includes: a first conductive layer 40 disposed between the PIN diode 30 and the second conductive layer 50 , the first conductive layer 40 includes a first electrode plate 41 , and the first electrode plate 41 is connected to the first electrode 211 .
  • the first conductive layer 40 may not include the first electrode plate.
  • the material of the first conductive layer 40 includes, but is not limited to, indium tin oxide.
  • the second electrode 51 covers the first electrode 211 and the first electrode plate 41 , that is, the area of the orthographic projection of the second electrode 51 on the substrate. It is greater than the sum of the area of the orthographic projection of the first electrode 211 on the substrate and the area of the orthographic projection of the first electrode plate 41 on the substrate.
  • the array substrate 100 may further include a second electrode plate, which is the part of the second electrode 51 corresponding to the position of the first electrode plate 41 (not marked in the figure); the second electrode plate A storage capacitor C1 is formed with the first electrode plate 41 .
  • the third metal layer 21 further includes a first metal part 212 ; the second electrode 51 is connected to the first metal part 212 .
  • the first metal portion 212 can be used as a voltage access point for the second electrode 51, so that the driving chip can input voltage to the second electrode 51 through the first metal portion 212, thereby shortening the connection between the second electrode 51 and the driving chip The length of the wire reduces the loss of voltage, which further improves the sensitivity of the photosensitive sensor.
  • the second electrode 51 may also cover part or all of the first metal portion 212 .
  • the third metal layer 21 further includes a common electrode 213; the first conductive layer 40 further includes touch electrode lines 42; The position of the common electrode 213 corresponds to the position of the touch electrode line 42 , and the common electrode 213 is connected to the touch electrode line 42 .
  • the material of the first conductive layer 30 includes, but is not limited to, indium tin oxide.
  • the touch electrode lines 42 here are also used as access points for the common voltage.
  • the substrate 10 further includes a switching element T2 , and the switching element T2 includes a third drain 183 .
  • the second conductive layer 50 further includes a pixel electrode 53; the pixel electrode 53 is connected to the drain electrode 183 of the switching element T2.
  • the first conductive layer 40 further includes a third electrode plate 43
  • the second conductive layer 50 further includes a fourth electrode plate 52, wherein the fourth electrode plate 52 and the third electrode plate 52
  • the positions of the electrode plates 43 correspond to each other to form the pixel capacitance.
  • the third drain electrode 183 is located in the second metal layer 18 . That is, the drain and source of the switching element T2 are fabricated in the same layer as the source and drain of the control element T1, respectively.
  • the gate of the switching element T2 can be fabricated in the same layer as the gate of the control element T1, and the semiconductor of the switching element T2 can be fabricated in the same layer. The layer may also be fabricated in the same layer as the semiconductor layer of the control element T1.
  • the above-mentioned array substrate 100 may further include a second insulating layer 22 , a third insulating layer 23 and a fourth insulating layer 24 .
  • the second insulating layer 22 is disposed between the third metal layer 21 and the first semiconductor layer 31; the material of the second insulating layer 22 may include at least one of silicon nitride, silicon oxide, and organic photoresist.
  • the third insulating layer 23 is disposed between the PIN diode 30 and the first conductive layer 40; the material of the third insulating layer 23 may also include at least one of silicon nitride, silicon oxide, and organic photoresist.
  • the fourth insulating layer 24 is disposed between the first conductive layer 40 and the second conductive layer 50; the material of the fourth insulating layer 24 may also include at least one of silicon nitride, silicon oxide, and organic photoresist.
  • the photosensitive sensor includes a PIN diode 30, a first electrode and a second electrode. Since the photosensitive sensor is fabricated on the control element T1, and because the PIN diode 30 covers at least part of the semiconductor layer of the control element, the photosensitive sensor also covers at least part of the control element. Therefore, the aperture ratio is increased, thereby improving the accuracy of fingerprint identification; in addition, the light absorption coefficient of the photosensitive layer of amorphous silicon is much better than that of polysilicon, thereby increasing the sensitivity of the photosensitive sensor.
  • the manufacturing method of the array substrate of this embodiment includes:
  • the light shielding layer 12 is patterned by means of exposure etching or the like, so that the light shielding layer 12 shields the first semiconductor portion 141 .
  • the buffer layer 13 and the first semiconductor layer 14 are sequentially prepared on the light shielding layer 12 .
  • the material of the first semiconductor layer 14 is polysilicon, and the first semiconductor layer 14 is exposed and etched to form the first semiconductor part 141 and the second semiconductor part 142 respectively, and the first semiconductor part 141 and the second semiconductor part are respectively formed.
  • 142 is doped with P ions to form N+, so that the first semiconductor part 141 and the second semiconductor part 142 are easy to make ohmic contact.
  • the first gate electrode 161 and the third gate electrode 162 are formed by patterning the first metal layer 16 . Then, N- ions are implanted into the first semiconductor portion 141 and the second semiconductor portion 142 using a self-aligned process, respectively.
  • the gate insulating layer 17 can be a stacked structure of SiNx/SiOx.
  • rapid thermal annealing can be used for hydrogenation and activation, and then the gate insulating layer 17 is exposed and etched, A source and drain connection hole is formed, and the connection hole is connected to the first semiconductor portion 141 or the second semiconductor portion 142 .
  • the second metal layer 18 is patterned to form the first source electrode 181 and the first drain electrode 182 , and the third drain electrode 183 and the third source electrode 184 .
  • the passivation layer 19' is provided with a via hole, the via hole penetrates the passivation layer 19' and the flat layer 19, and the first electrode 211 is connected to the first drain electrode 182 through the via hole.
  • the third metal layer 21 is patterned to form the first electrode 211 , the first metal part 212 and the common electrode 213 .
  • the material of the first semiconductor layer 31 is N-type amorphous silicon (N+a-Si)
  • the material of the intrinsic semiconductor layer 32 is amorphous silicon (a-Si)
  • the material of the second semiconductor layer 33 is The material is P-type amorphous silicon (P+a-Si).
  • a first connection hole between the touch electrode line 42 and the common electrode 213 and a second connection hole between the first electrode plate 41 and the first electrode 211 are formed on the third insulating layer 23 , and the two connection holes are both The third insulating layer 23 and the second insulating layer 22 are penetrated.
  • the fourth insulating layer 24 is provided with a first via hole and a second via hole, and the first via hole is used to connect the second electrode 51 and the first metal part 212 .
  • the second via hole is used to connect the pixel electrode 53 and the third drain electrode 183 .
  • the second conductive layer 50 is patterned to form the second electrode 51 , the pixel electrode 51 and the fourth electrode plate 52 .
  • the manufacturing method of the array substrate in this embodiment includes all the technical solutions of the above-mentioned array substrate, so all the above-mentioned technical effects can be achieved, which will not be repeated here.
  • the PIN diode 30 may also not include the second semiconductor layer 33 , that is, the PIN diode 30 includes the first semiconductor layer 31 and the intrinsic semiconductor layer 32 .
  • FIG. 1 to FIG. 3 only show schematic structural diagrams of one of the embodiments, but do not limit the present invention.
  • the present embodiment further provides a display panel 200 , which includes any one of the array substrates 100 described above.
  • the display panel 200 may further include a second substrate 201 , and the second substrate 201 is disposed opposite to the array substrate 100 .
  • the display panel 200 may be a liquid crystal display panel.
  • a liquid crystal layer (not shown in the figure) is also disposed between the array substrate 100 and the second substrate 201 .
  • a sealant may also be disposed between the array substrate 100 and the second substrate 201 for attaching the array substrate 100 and the second substrate 201 .
  • the second substrate 201 may include a second base substrate 71 and a second electrode 72 .
  • the second substrate 201 may be a color filter substrate, that is, the second substrate 201 may further include a color filter layer. It can be understood that the structure of the second substrate 201 is not limited to this.
  • FIG. 5 is a schematic structural diagram of an electronic device provided by an embodiment of the present application.
  • the electronic device 300 may include a display panel 200 , a control circuit 80 and a housing 90 . It should be noted that the electronic device 300 shown in FIG. 5 is not limited to the above contents, and may also include other devices, such as a camera, an antenna structure, a fingerprint unlocking module, and the like.
  • the display panel 200 is disposed on the casing 90 .
  • the display panel 200 may be fixed to the casing 90 , and the display panel 200 and the casing 90 form a closed space to accommodate devices such as the control circuit 80 .
  • the casing 90 may be made of a flexible material, such as a plastic casing or a silicone casing.
  • control circuit 80 is installed in the casing 90, the control circuit 80 can be the main board of the electronic device 300, and the control circuit 80 can be integrated with a battery, an antenna structure, a microphone, a speaker, a headphone interface, a universal serial bus interface, One, two or more of functional components such as camera, distance sensor, ambient light sensor, receiver, and processor.
  • the display panel 200 is installed in the casing 90 , and at the same time, the display panel 200 is electrically connected to the control circuit 80 to form a display surface of the electronic device 300 .
  • the display panel 200 may include a display area and a non-display area.
  • the display area may be used to display the screen of the electronic device 300 or for the user to perform touch manipulation and the like. This non-display area can be used to set various functional components.
  • the electronic devices include but are not limited to mobile phones, tablet computers, computer monitors, game consoles, televisions, display screens, wearable devices, and other household appliances or household appliances with display functions.
  • the array substrate, display panel, and electronic device of the embodiments of the present application include a substrate, including a control element; a third metal layer, disposed on the substrate; the third metal layer includes a first electrode, the control element and the control element the first electrode is connected; a PIN diode is arranged on the first electrode, the PIN diode includes a first semiconductor layer and an intrinsic semiconductor layer; the PIN diode covers at least part of the semiconductor layer of the control element and part of the first semiconductor layer.
  • a second conductive layer disposed on the PIN diode, the second conductive layer includes a second electrode; the second electrode covers the PIN diode; since the P photosensitive sensor at least covers part of the semiconductor layer of the control element , thus increasing the aperture ratio, thereby improving the accuracy of fingerprint recognition.

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Abstract

一种阵列基板（100）、显示面板及电子设备，该阵列基板（100）包括基底（11），包括控制元件（T1）；第一电极（211）与所述控制元件（T1）连接；PIN二极管（30），设于所述第一电极（211）上，所述PIN二极管（30）至少覆盖部分所述控制元件（T1）的半导体层（14）和部分第一电极（211）；第二导电层（50），设于所述PIN二极管（30）上，所述第二导电层（50）包括第二电极（51）。

Description

阵列基板、显示面板及电子设备 技术领域
本申请涉及显示技术领域，具体涉及一种阵列基板、显示面板及电子设备。
 背景技术
光学指纹技术与显示面板相结合是目前主要的方向之一，它的原理是利用指纹的谷和脊反射到显示面板的传感区域内的光的强弱不同，从而将不同的光信号转换成电信号，通过芯片提取出来，形成关键的指纹图样，达到指纹识别的目的。
 技术问题
目前应用于有机发光二极管的光学指纹技术比较广泛，但运用在液晶显示面板的光学指纹技术很少，由于受到背光、开口率等因素的限制，从而增加了在液晶显示面板内集成光学指纹识别功能的难度，使得指纹识别的准确度降低。
 技术解决方案
本申请实施例提供一种阵列基板、显示面板及电子设备，可以提高指纹识别的准确度。
本申请实施例提供一种阵列基板，其包括：
基底，包括控制元件；
第三金属层，设于所述基底上；所述第三金属层包括第一电极，所述第一电极与所述控制元件连接；
PIN二极管，设于所述第一电极上，所述PIN二极管包括第一半导体层和本征半导体层；所述PIN二极管至少覆盖部分所述控制元件的半导体层和部分第一电极；
第二导电层，设于所述PIN二极管上，所述第二导电层包括第二电极，所述第二电极覆盖所述PIN二极管。
本申请实施例还提供一种显示面板，其包括上述阵列基板。
本申请实施例还提供一种电子设备，其包括上述显示面板。
 有益效果
本申请实施例的阵列基板、显示面板及电子设备，包括基底，包括控制元件；第三金属层，设于所述基底上；所述第三金属层包括第一电极，所述控制元件与所述第一电极连接；PIN二极管，设于所述第一电极上，所述PIN二极管包括第一半导体层和本征半导体层；所述PIN二极管至少覆盖部分所述控制元件的半导体层和部分第一电极；第二导电层，设于所述PIN二极管上，所述第二导电层包括第二电极；所述第二电极覆盖所述PIN二极管；由于感光传感器至少覆盖部分控制元件的半导体层，因此提高了开口率，进而提高指纹识别的准确度。
 附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请一实施例提供的阵列基板的剖面示意图。
图2为图1所示的阵列基板的制备工艺流程图。
图3为本申请另一实施例提供的阵列基板的剖面示意图。
图4为本申请一实施例提供的显示面板的结构示意图。
图5为本申请一实施例提供的电子设备的结构示意图。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
在本申请的描述中，需要理解的是，术语“中心”、“纵向”、“横向”、“长度”、“宽度”、“厚度”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”、“顺时针”、“逆时针”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个所述特征。在本申请的描述中，“多个”的含义是两个或两个以上，除非另有明确具体的限定。
在本申请的描述中，需要说明的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接或可以相互通讯；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通或两个元件的相互作用关系。对于本领域的普通技术人员而言，可以根据具体情况理解上述术语在本申请中的具体含义。
在本申请中，除非另有明确的规定和限定，第一特征在第二特征之“上”或之“下”可以包括第一和第二特征直接接触，也可以包括第一和第二特征不是直接接触而是通过它们之间的另外的特征接触。而且，第一特征在第二特征“之上”、“上方”和“上面”包括第一特征在第二特征正上方和斜上方，或仅仅表示第一特征水平高度高于第二特征。第一特征在第二特征“之下”、“下方”和“下面”包括第一特征在第二特征正下方和斜下方，或仅仅表示第一特征水平高度小于第二特征。
下文的公开提供了许多不同的实施方式或例子用来实现本申请的不同结构。为了简化本申请的公开，下文中对特定例子的部件和设置进行描述。当然，它们仅仅为示例，并且目的不在于限制本申请。此外，本申请可以在不同例子中重复参考数字和/或参考字母，这种重复是为了简化和清楚的目的，其本身不指示所讨论各种实施方式和/或设置之间的关系。此外，本申请提供了的各种特定的工艺和材料的例子，但是本领域普通技术人员可以意识到其他工艺的应用和/或其他材料的使用。
请参阅图1至图3，图1为本申请一实施例提供的阵列基板的剖面示意图。
如图1所示，本实施例的阵列基板100包括基底10、第三金属层21、PIN二极管30以及第二导电层50。
基底10包括控制元件T1；该控制元件T1也即为薄膜晶体管。在一实施方式中，基底10可包括：衬底基板11、第一半导体层14、第一绝缘层15、第一金属层16以及第二金属层18。此外该基底10还可包括遮光层12、缓冲层13、栅绝缘层17、平坦层19以及钝化层19’中的至少一种。
衬底基板11可为玻璃基板或者柔性衬底。衬底基板11的材质包括玻璃、二氧化硅、聚乙烯、聚丙烯、聚苯乙烯、聚乳酸、聚对苯二甲酸乙二醇酯、聚酰亚胺或聚氨酯中的一种或多种。
遮光层12设于衬底基板11上，遮光层12的材料可为金属材料。
缓冲层13设于遮光层12上，所述缓冲层13的材料包括但不限于氮化硅或氧化硅。
第一半导体层14设于所述缓冲层13上；在一优选实施方式中，第一半导体层14的材料为多晶硅。结合图2，第一半导体层14可包括第一半导体部141。
第一绝缘层15设于所述第一半导体层14上；第一绝缘层15的材料可包括氮化硅、氧化硅以及有机光阻中的至少一种。
第一金属层16设于所述第一绝缘层15上；所述第一金属层16包括第一栅极161。第一金属层16的材料可包括铜、铝以及钛中的至少一种。
栅绝缘层17设于第一金属层16上，栅绝缘层17的材料可包括氮化硅、氧化硅中的至少一种。
第二金属层18设于所述栅绝缘层17上，所述第二金属层18包括第一源极181和第一漏极182；所述第二金属层18的材料可与第一金属层16的材料相同。
平坦层19设于第二金属层18上，平坦层19的材料可包括氮化硅、氧化硅以及有机光阻中的至少一种。在一优选实施方式中，平坦层19的材料为有机光阻。
钝化层19’设于平坦层19上，钝化层19’的材料可包括氮化硅、氧化硅、有机光阻中的至少一种。
第三金属层21设于所述钝化层19’上；所述第三金属层21包括第一电极211。所述第一电极211与所述控制元件T1连接，具体地第一电极211与第一漏极182连接。所述第三金属层21的材料可为Ti/Al/Ti、Mo、Mo/Cu、Mo/Al/Mo中的至少一种。所述第三金属层21的材料不限于此。在一实施方式中，为了提高感光传感器的灵敏度，所述第一电极211在所述基底10上的正投影的面积大于所述PIN二极管30在所述基底10上的正投影的面积，也即PIN二极管30部分覆盖第一电极211。所述PIN二极管30至少覆盖部分第一半导体部141，在一优选实施方式中，为了进一步提高开口率，所述PIN二极管30全部覆盖第一半导体部141。
PIN二极管30设于所述第一电极211上，所述PIN二极管30包括第一半导体层31、本征半导体层32以及第二半导体层33；本征半导体层32以及第二半导体层33依次设于第一半导体层31上。在一实施方式中，第一半导体层31的材料为N型非晶硅（N+a-Si）、本征半导体层32的材料为非晶硅（a-Si），第二半导体层33的材料为P型非晶硅（P+a-Si）。在一优选实施方式中，所述控制元件T1的半导体层的材料为多晶硅，所述本征半导体层32的材料为非晶硅,由于非晶硅可以制作的比较厚，因此利于光的吸收，便于形成高性能的感光传感器，因此提高了指纹识别的准确性。
第二导电层50设于所述PIN二极管30上，所述第二导电层50包括第二电极51。所述第二电极51覆盖所述PIN二极管30。在一实施方式中，第二导电层50的材料包括但不限于氧化铟锡。在一实施方式中，为了减小第一电极的阻抗，该阵列基板100还包括：第一导电层40，第一导电层40设于所述PIN二极管30和所述第二导电层50之间，所述第一导电层40包括第一极板41，所述第一极板41与所述第一电极211连接。当然可以理解的，在其他实施方式中，第一导电层40也可不包括第一极板。在一实施方式中，第一导电层40的材料包括但不限于氧化铟锡。
在一实施方式中，为了进一步提高感光传感器的灵敏度，所述第二电极51覆盖所述第一电极211和第一极板41，也即所述第二电极51在基底上的正投影的面积大于所述第一电极211在基底上的正投影的面积和第一极板41在基底上的正投影的面积之和。其中阵列基板100还可包括第二极板，所述第二极板为所述第二电极51中与所述第一极板41位置对应的部分（图中未标出）；第二极板与第一极板41形成存储电容C1。
在一优选实施方式中，为了减小第二电极的电压的损耗，所述第三金属层21还包括第一金属部212；所述第二电极51与所述第一金属部212连接。此外第一金属部212可以作为第二电极51的电压接入点，以使驱动芯片通过第一金属部212向第二电极51输入电压，进而缩短了第二电极51与驱动芯片之间的连接线的长度，降低了电压的损耗，进而进一步提高了感光传感器的灵敏度。此外在一实施方式中，第二电极51还可覆盖部分或者全部第一金属部212。
在另一实施方式中，为了进一步提高阵列基板的集成度，减小整体厚度，所述第三金属层21还包括公共电极213；所述第一导电层40还包括触控电极线42；所述公共电极213的位置与所述触控电极线42的位置对应，且所述公共电极213与所述触控电极线42连接。在一实施方式中，第一导电层30的材料包括但不限于氧化铟锡。此处的触控电极线42还用于向作为公共电压的接入点。
在一实施方式中，为了简化制程工艺，降低生产成本，所述基底10还包括开关元件T2，所述开关元件T2包括第三漏极183。
所述第二导电层50还包括像素电极53；所述像素电极53与所述开关元件T2的漏极183连接。
在一实施方式中，为了简化制程工艺，降低生产成本，第一导电层40还包括第三极板43，第二导电层50还包括第四极板52，其中第四极板52与第三极板43的位置对应，以形成像素电容。
其中在一优选实施方式中，第三漏极183位于第二金属层18。也即开关元件T2的漏极和源极分别与控制元件T1的源极和漏极同层制作，此外开关元件T2的栅极可与控制元件T1的栅极同层制作，开关元件T2的半导体层也可与控制元件T1的半导体层同层制作。
此外在一实施方式中，上述阵列基板100还可包括第二绝缘层22、第三绝缘层23以及第四绝缘层24。
第二绝缘层22设于所述第三金属层21和第一半导体层31之间；第二绝缘层22的材料可包括氮化硅、氧化硅、有机光阻中的至少一种。
第三绝缘层23设于PIN二极管30和第一导电层40之间；第三绝缘层23的材料也可包括氮化硅、氧化硅、有机光阻中的至少一种。
第四绝缘层24设于第一导电层40和第二导电层50之间；第四绝缘层24的材料也可包括氮化硅、氧化硅、有机光阻中的至少一种。
感光传感器包括PIN二极管30和第一电极以及第二电极，由于在控制元件T1上制作感光传感器，且由于PIN二极管30至少覆盖部分所述控制元件的半导体层，使得感光传感器也至少覆盖部分控制元件的半导体层，因此提高了开口率，进而提高指纹识别的准确度；此外由于非晶硅的感光层的吸光系数大大优于多晶硅，从而增大感光传感器的灵敏度。
如图2所示，在一实施方式中，本实施例的阵列基板的制作方法包括：
S101、在衬底基板11上制备遮光层12；
例如，采用曝光蚀刻等方式对遮光层12进行图案化，以使遮光层12遮挡第一半导体部141。
S102、在遮光层12上依次制备缓冲层13和第一半导体层14。
例如，第一半导体层14的材料为多晶硅，对第一半导体层14进行曝光、蚀刻，分别形成第一半导体部141和第二半导体部142，并分别对第一半导体部141和第二半导体部142进行P离子掺杂形成N+，使第一半导体部141和第二半导体部142易于欧姆接触。
S103、在第一半导体部和第二半导体部上依次沉积第一绝缘层15以及第一金属层16。
例如，对第一金属层16进行图案化处理形成第一栅极161和第三栅极162。然后采用自对准工艺分别对第一半导体部141和第二半导体部142进行N-离子注入。
S104、在第一金属层16上沉积一层栅绝缘层17。
例如，在一实施方式中，栅绝缘层17可为SiNx/SiOx的叠层结构，在一实施方式中，可采用快速热退火进行氢化和活化，然后对该栅绝缘层17进行曝光、蚀刻，形成源极和漏极的连接孔，该连接孔与第一半导体部141或者第二半导体部142连接。
S105、在连接孔内以及栅绝缘层17沉积第二金属层。
例如，对第二金属层18进行图案化处理形成第一源极181和第一漏极182、以及第三漏极183和第三源极184。
S106、在第二金属层18上依次制备平坦层19和钝化层19’。
例如，钝化层19’上设置有过孔，该过孔贯穿钝化层19’和平坦层19，第一电极211通过该过孔与第一漏极182连接。
S107、在钝化层19’沉积第三金属层21。
例如，对所述第三金属层21进行图案化处理形成第一电极211、第一金属部212以及公共电极213。
S108、在第三金属层21沉积第二绝缘层22。
S109、在第二绝缘层22上依次沉积第一半导体层31、本征半导体层32以及第二半导体层33，并对其进行图形化处理。在一实施方式中，第一半导体层31的材料为N型非晶硅（N+a-Si）、本征半导体层32的材料为非晶硅（a-Si），第二半导体层33的材料为P型非晶硅（P+a-Si）。
S110、在第二半导体层33上依次制作第三绝缘层23和第一导电层40，对第一导电层40进行图案化处理形成第一极板41和触控电极线42以及第三极板43。
在第三绝缘层23上制作触控电极线42与公共电极213之间的第一连接孔、以及第一极板41与第一电极211之间的第二连接孔，这两个连接孔均贯穿第三绝缘层23和第二绝缘层22。
S111、在第一导电层40上依次沉积第四绝缘层24和第二导电层50。
例如，第四绝缘层24上设置有第一过孔和第二过孔，所述第一过孔用于连接第二电极51和第一金属部212。
该第二过孔用于连接像素电极53和第三漏极183。
对第二导电层50进行图案化处理形成第二电极51、像素电极51以及第四极板52。
本实施例的阵列基板的制作方法包括了上述阵列基板的全部技术方案，因此能实现上述全部技术效果，此处不再赘述。
在其他实施例中，如图3所示，所述PIN二极管30也可不包括第二半导体层33，也即所述PIN二极管30包括第一半导体层31和本征半导体层32。
可以理解的，图1至图3仅示出其中一种实施方式的结构示意图，但是并不能对本发明构成限定。
如图4所示，本实施例还提供一种显示面板200，其包括上述任意一种阵列基板100，此外该显示面板200还可以包括第二基板201，第二基板201与阵列基板100相对设置。该显示面板200可为液晶显示面板。阵列基板100和第二基板201之间还设置有液晶层（图中未示出）。此外阵列基板100和第二基板201之间还可设置有框胶，用于贴合阵列基板100和第二基板201。在一实施方式中，第二基板201可包括第二衬底基板71和第二电极72。在另一实施方式中，第二基板201可为彩膜基板，也即第二基板201还可包括彩膜层。可以理解的，第二基板201的结构不限于此。
请参阅图5，图5为本申请实施例提供的电子设备的结构示意图。
该电子设备300可以包括显示面板200、控制电路80以及壳体90。需要说明的是，图5所示的电子设备300并不限于以上内容，其还可以包括其他器件，比如还可以包括摄像头、天线结构、纹解锁模块等。
其中，显示面板200设置于壳体90上。
在一些实施例中，显示面板200可以固定到壳体90上，显示面板200和壳体90形成密闭空间，以容纳控制电路80等器件。
在一些实施例中，壳体90可以为由柔性材料制成，比如为塑胶壳体或者硅胶壳体等。
其中，该控制电路80安装在壳体90中，该控制电路80可以为电子设备300的主板，控制电路80上可以集成有电池、天线结构、麦克风、扬声器、耳机接口、通用串行总线接口、摄像头、距离传感器、环境光传感器、受话器以及处理器等功能组件中的一个、两个或多个。
其中，该显示面板200安装在壳体90中，同时，该显示面板200电连接至控制电路80上，以形成电子设备300的显示面。该显示面板200可以包括显示区域和非显示区域。该显示区域可以用来显示电子设备300的画面或者供用户进行触摸操控等。该非显示区域可用于设置各种功能组件。
所述电子设备包括但不限定于手机、平板电脑、计算机显示器、游戏机、电视机、显示屏幕、可穿戴设备及其他具有显示功能的生活电器或家用电器等。
本申请实施例的阵列基板、显示面板及电子设备，包括基底，包括控制元件；第三金属层，设于所述基底上；所述第三金属层包括第一电极，所述控制元件和所述第一电极连接；PIN二极管，设于所述第一电极上，所述PIN二极管包括第一半导体层和本征半导体层；所述PIN二极管至少覆盖部分所述控制元件的半导体层和部分第一电极；第二导电层，设于所述PIN二极管上，所述第二导电层包括第二电极；所述第二电极覆盖所述PIN二极管；由于P感光传感器至少覆盖部分控制元件的半导体层，因此提高了开口率，进而提高指纹识别的准确度。
以上对本申请实施例提供的阵列基板、显示面板及电子设备进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请。同时，对于本领域的技术人员，依据本申请的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本申请的限制。

Claims (20)

  1. 一种阵列基板，其包括：
    基底，包括控制元件；
    第三金属层，设于所述基底上；所述第三金属层包括第一电极，所述第一电极与所述控制元件连接；
    PIN二极管，设于所述第一电极上，所述PIN二极管包括第一半导体层和本征半导体层；所述PIN二极管至少覆盖部分所述控制元件的半导体层和部分第一电极；以及
    第二导电层，设于所述PIN二极管上，所述第二导电层包括第二电极，所述第二电极覆盖所述PIN二极管。
  2. 根据权利要求1所述的阵列基板，其中
    所述第三金属层还包括第一金属部；
    所述第二电极与所述第一金属部连接。
  3. 根据权利要求1所述的阵列基板，其中所述阵列基板还包括：
    第一导电层，设于所述PIN二极管和所述第二导电层之间，所述第一导电层包括第一极板，所述第一极板与所述第一电极连接。
  4. 根据权利要求3所述的阵列基板，其中
    所述第二电极覆盖所述第一电极和所述第一极板。
  5. 根据权利要求4所述的阵列基板，其中所述阵列基板还包括：
    第二极板，所述第二极板为所述第二电极中与所述第一极板位置对应的部分。
  6. 根据权利要求3所述的阵列基板，其中
    所述第三金属层还包括公共电极；所述第一导电层还包括触控电极线；所述公共电极的位置与所述触控电极线的位置对应，所述公共电极与所述触控电极线连接。
  7. 根据权利要求1所述的阵列基板，其中所述第一电极在所述基底上的正投影的面积大于所述PIN二极管在所述基底上的正投影的面积。
  8. 根据权利要求1所述的阵列基板，其中
    所述基底还包括开关元件；
    所述第二导电层还包括像素电极；所述像素电极与所述开关元件的漏极连接。
  9. 根据权利要求1所述的阵列基板，其中
    所述控制元件的半导体层的材料为多晶硅，所述本征半导体层的材料为非晶硅。
  10. 根据权利要求1所述的阵列基板，其中
    所述第一导电层还包括第三极板；
    所述第二导电层还包括第四极板，所述第三极板的位置与所述第四极板的位置对应。
  11. 根据权利要求1所述的阵列基板，其中
    所述PIN二极管还包括第二半导体层，第二半导体层设于所述本征半导体层上。
  12. 一种显示面板，其包括阵列基板，其包括：
    基底，包括控制元件；
    第三金属层，设于所述基底上；所述第三金属层包括第一电极，所述第一电极与所述控制元件连接；
    PIN二极管，设于所述第一电极上，所述PIN二极管包括第一半导体层和本征半导体层；所述PIN二极管至少覆盖部分所述控制元件的半导体层和部分第一电极；以及
    第二导电层，设于所述PIN二极管上，所述第二导电层包括第二电极，所述第二电极覆盖所述PIN二极管。
  13. 根据权利要求12所述的显示面板，其中
    所述第三金属层还包括第一金属部；
    所述第二电极与所述第一金属部连接。
  14. 根据权利要求12所述的显示面板，其中所述阵列基板还包括：
    第一导电层，设于所述PIN二极管和所述第二导电层之间，所述第一导电层包括第一极板，所述第一极板与所述第一电极连接。
  15. 根据权利要求14所述的显示面板，其中
    所述第二电极覆盖所述第一电极和所述第一极板。
  16. 根据权利要求15所述的显示面板，其中所述阵列基板还包括：
    第二极板，所述第二极板为所述第二电极中与所述第一极板位置对应的部分。
  17. 根据权利要求14所述的显示面板，其中
    所述第三金属层还包括公共电极；所述第一导电层还包括触控电极线；所述公共电极的位置与所述触控电极线的位置对应，所述公共电极与所述触控电极线连接。
  18. 根据权利要求12所述的显示面板，其中所述第一电极在所述基底上的正投影的面积大于所述PIN二极管在所述基底上的正投影的面积。
  19. 根据权利要求12所述的显示面板，其中
    所述控制元件的半导体层的材料为多晶硅，所述本征半导体层的材料为非晶硅。
  20. 一种电子设备，其中包括如权利要求12所述的显示面板。
PCT/CN2020/107153 2020-07-23 2020-08-05 阵列基板、显示面板及电子设备 Ceased WO2022016620A1 (zh)

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Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112198729B (zh) 2020-10-28 2022-04-26 武汉华星光电技术有限公司 阵列基板、显示面板及电子设备
CN112909066B (zh) * 2021-02-05 2024-02-02 武汉华星光电半导体显示技术有限公司 显示面板、显示面板的制备方法及显示装置
CN113066798B (zh) 2021-03-08 2022-11-08 武汉华星光电技术有限公司 驱动基板、显示面板及驱动基板的制备方法
CN113433741B (zh) * 2021-06-07 2022-08-05 武汉华星光电技术有限公司 阵列基板、阵列基板的制造方法以及显示装置
WO2023245539A1 (zh) * 2022-06-23 2023-12-28 京东方科技集团股份有限公司 显示基板、显示面板及显示装置

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100007632A1 (en) * 2008-07-10 2010-01-14 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
CN106055162A (zh) * 2016-06-30 2016-10-26 京东方科技集团股份有限公司 显示组件和显示装置
CN107342308A (zh) * 2017-06-30 2017-11-10 上海天马微电子有限公司 一种有机发光显示面板和电子设备
CN108710237A (zh) * 2018-04-27 2018-10-26 厦门天马微电子有限公司 显示面板及显示装置
CN111399265A (zh) * 2019-01-03 2020-07-10 群创光电股份有限公司 显示装置

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5298461B2 (ja) * 2007-05-29 2013-09-25 セイコーエプソン株式会社 液晶装置及び電子機器
CN106200168B (zh) * 2016-07-08 2019-11-26 武汉华星光电技术有限公司 阵列基板及其制作方法、以及液晶显示面板
CN107316884B (zh) * 2017-06-19 2020-08-14 武汉天马微电子有限公司 一种显示面板及显示装置
WO2019015588A1 (en) * 2017-07-18 2019-01-24 Boe Technology Group Co., Ltd. SENSOR, NETWORK SUBSTRATE CONTAINING SENSOR, DISPLAY PANEL CONTAINING NETWORK SUBSTRATE
CN107480639B (zh) * 2017-08-16 2020-06-02 上海天马微电子有限公司 一种触控显示面板和显示装置
CN107422560A (zh) * 2017-09-04 2017-12-01 京东方科技集团股份有限公司 一种阵列基板、其检测方法及显示装置
KR20190028194A (ko) * 2017-09-08 2019-03-18 엘지디스플레이 주식회사 엑스레이 검출기용 어레이 기판과 이를 포함하는 엑스레이 검출기 및 그 제조 방법
CN109065582B (zh) * 2018-08-02 2022-02-15 京东方科技集团股份有限公司 一种阵列基板及显示面板、显示装置
CN112349232B (zh) * 2019-08-06 2025-04-08 群创光电股份有限公司 显示设备及电子设备

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100007632A1 (en) * 2008-07-10 2010-01-14 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
CN106055162A (zh) * 2016-06-30 2016-10-26 京东方科技集团股份有限公司 显示组件和显示装置
CN107342308A (zh) * 2017-06-30 2017-11-10 上海天马微电子有限公司 一种有机发光显示面板和电子设备
CN108710237A (zh) * 2018-04-27 2018-10-26 厦门天马微电子有限公司 显示面板及显示装置
CN111399265A (zh) * 2019-01-03 2020-07-10 群创光电股份有限公司 显示装置

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