WO2022011954A1 - 半导体装置 - Google Patents

半导体装置 Download PDF

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Publication number
WO2022011954A1
WO2022011954A1 PCT/CN2020/136388 CN2020136388W WO2022011954A1 WO 2022011954 A1 WO2022011954 A1 WO 2022011954A1 CN 2020136388 W CN2020136388 W CN 2020136388W WO 2022011954 A1 WO2022011954 A1 WO 2022011954A1
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WO
WIPO (PCT)
Prior art keywords
unit
temperature detection
temperature
semiconductor device
memory chip
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Application number
PCT/CN2020/136388
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English (en)
French (fr)
Inventor
寗树梁
Original Assignee
长鑫存储技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 长鑫存储技术有限公司 filed Critical 长鑫存储技术有限公司
Priority to KR1020227031294A priority Critical patent/KR20220130826A/ko
Priority to EP20945120.2A priority patent/EP4095857A4/en
Priority to JP2022553651A priority patent/JP2023517553A/ja
Priority to US17/389,629 priority patent/US11521661B2/en
Publication of WO2022011954A1 publication Critical patent/WO2022011954A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/04—Arrangements for writing information into, or reading information out from, a digital store with means for avoiding disturbances due to temperature effects
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01K—MEASURING TEMPERATURE; MEASURING QUANTITY OF HEAT; THERMALLY-SENSITIVE ELEMENTS NOT OTHERWISE PROVIDED FOR
    • G01K15/00—Testing or calibrating of thermometers
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01K—MEASURING TEMPERATURE; MEASURING QUANTITY OF HEAT; THERMALLY-SENSITIVE ELEMENTS NOT OTHERWISE PROVIDED FOR
    • G01K15/00—Testing or calibrating of thermometers
    • G01K15/005—Calibration
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type

Definitions

  • the present invention relates to the field of memory, and in particular, to a semiconductor device.
  • Dynamic random access memory (Dynamic Random Access Memory, DRAM) is a semiconductor memory device commonly used in computers, and its memory array area is composed of many repeated memory cells. Each memory cell usually includes a capacitor and a transistor. The gate of the transistor is connected to the word line, the drain is connected to the bit line, and the source is connected to the capacitor. The voltage signal on the word line can control the opening or closing of the transistor, and then through the bit line The data information stored in the capacitor is read, or the data information is written into the capacitor through the bit line for storage.
  • DRAM Dynamic Random Access Memory
  • the technical problem to be solved by the present invention is to provide a semiconductor device that can detect the temperature of the memory chip, prevent the memory chip from starting and running at low temperature, shorten the writing time, and improve the writing stability of the memory chip;
  • the temperature detection unit is calibrated to improve the detection accuracy of the temperature detection unit.
  • the present invention provides a semiconductor device, which includes a memory chip and a temperature detection module, the temperature detection module is used to detect the temperature of the memory chip, and the temperature detection module includes: a temperature detection unit, the The temperature detection unit includes a temperature sensitive unit and an adjustable resistance unit, the electrical conductivity of the temperature sensitive unit changes with the change of temperature, and the adjustable resistance unit is connected in parallel with the temperature sensitive unit; wherein the temperature detection unit is connected by It is configured to calibrate the temperature detection unit by adjusting the resistance value of the adjustable resistance unit.
  • the adjustable resistance unit includes a plurality of sub-resistors and a plurality of switches, the sub-resistors are connected in series, and each of the switches is connected in parallel with at least one of the sub-resistors. Change the resistance value of the adjustable resistance unit.
  • the resistance values of the sub-resistors are the same.
  • sub-resistors are polysilicon resistors or N-type diffused resistors or P-type diffused resistors.
  • sub-resistors are electrically connected through a first layer of metal wires
  • sub-resistors and the switch are electrically connected through a second layer of metal wires.
  • the temperature detection unit further includes a fixed-value resistor, the fixed-value resistor is connected in series with the temperature-sensitive unit, the fixed-value resistor includes a first end and a second end, and the first end of the constant-value resistor is connected to The power supply is electrically connected, and the second end of the constant value resistor is electrically connected to the temperature sensitive unit.
  • the temperature sensitive unit is a diode
  • the positive terminal of the diode is electrically connected to the second terminal of the constant-value resistor
  • the negative terminal of the diode is electrically connected to the ground terminal.
  • the adjustable resistance unit includes a first end and a second end, the sub-resistor is arranged between the first end and the second end, and the first end of the adjustable resistance unit and the ground end electrically connected, the second end of the adjustable resistance unit is electrically connected with the second end of the constant value resistor.
  • the temperature detection module also includes an A/D conversion module, which has an input end and an output end, the input end is electrically connected to the second end of the fixed-value resistor, the output end outputs a digital signal, and the A The /D conversion module is used to convert the analog signal at the second end of the fixed-value resistor into a digital signal.
  • the A/D conversion module includes: a resistance unit having a first end and a second end, the first end of the resistance unit is electrically connected to the power supply, the second end of the resistance unit is electrically connected to the ground terminal,
  • the resistance unit has a plurality of lead terminals, and the voltage of each lead end is different; a plurality of comparison units, the signal of the input end of the A/D conversion module is used as the input signal of the comparison unit, and the plurality of lead ends of the resistance unit are used as the input signal of the comparison unit.
  • the signals are respectively used as reference signals of a plurality of the comparison units, and the comparison units output digital signals.
  • the A/D conversion module further includes an encoding unit, and the encoding unit receives and encodes the digital signal of the comparison unit.
  • the A/D conversion module further includes an output unit, the output unit is connected to the comparison unit, and is used for outputting the digital signal.
  • the resistance unit includes a plurality of sub-resistors connected in series, and the number of the sub-resistors spaced between each lead end of the resistance unit and the second end of the resistance unit is different, so that the voltage of each lead end is different. different.
  • the resistance values of the sub-resistors are the same or different.
  • the number of sub-resistors spaced between each lead end of the resistance unit and the second end of the resistance unit is incremented by a preset value.
  • the sub-resistors are at least one of polysilicon resistors, N-type diffused resistors, and P-type diffused resistors.
  • sub-resistors are electrically connected through a first-layer metal wire, and the resistance unit forms the lead-out terminal through a second-layer metal wire.
  • the temperature detection unit and the memory chip are powered by different power sources.
  • the power supply of the temperature detection unit is earlier than the power supply of the memory chip.
  • the semiconductor device further includes a control chip, and the memory chip and the temperature detection module are electrically connected to the control chip.
  • control chip is used to heat the memory chip before the memory chip is started, and determine whether the temperature detected by the temperature detection unit reaches a set threshold, and if it reaches the set threshold, control the memory chip to start.
  • the temperature detection module is used to detect the temperature of the memory chip, and the temperature detected by the temperature detection module provides a reference for the startup and operation of the memory chip, thereby avoiding the startup and operation of the memory chip at low temperature, shortening the writing time, and improving the Stability of memory chip writing.
  • the temperature detection module of the present invention has a simple circuit structure and is easy to implement, the temperature detection module occupies a small area, and the temperature detection unit is calibrated to improve the detection accuracy of the temperature detection unit.
  • FIG. 1 is a schematic structural diagram of a first embodiment of a semiconductor device of the present invention
  • FIG. 2 is a circuit diagram of a temperature detection module in the semiconductor device of the present invention.
  • FIG. 3 is a circuit diagram of a variable resistance unit of the first embodiment of the semiconductor device of the present invention.
  • FIG. 4 is a schematic structural diagram of a second embodiment of the semiconductor device of the present invention.
  • FIG. 5 is a schematic structural diagram of a third embodiment of the semiconductor device of the present invention.
  • FIG. 6 is a schematic structural diagram of a fourth embodiment of the semiconductor device of the present invention.
  • FIG. 7 is a schematic diagram of electrical connection of the first embodiment of the semiconductor device of the present invention.
  • the present invention provides a semiconductor device, which uses a temperature detection module to detect the temperature of the memory chip, so as to provide a reference for the start-up and operation of the memory chip, thereby preventing the memory chip from starting and operating at low temperature, shortening the writing time, and improving the performance of the memory chip. Stability of memory chip writing.
  • the semiconductor device of the present invention can also calibrate the temperature detection unit to improve the accuracy of temperature measurement.
  • FIG. 1 is a schematic structural diagram of a first embodiment of the semiconductor device of the present invention
  • FIG. 2 is a circuit diagram of a temperature detection module in the semiconductor device of the present invention.
  • the semiconductor device of the present invention includes a memory chip 100 and a temperature detection module 110.
  • the semiconductor device further includes a control chip 120 , the memory chip 100 and the temperature detection module 110 are electrically connected to the control chip 120 .
  • the control chip 120 is used to control the startup and operation of the memory chip 100 and the temperature detection module 110 .
  • the startup of the memory chip 100 includes power-on and self-checking, and the operation of the memory chip 100 includes writing data to the memory chip 100 , reading data from the memory chip 100 , and deleting the data accessed in the memory chip 100 . Wait.
  • the memory chip 100 is an existing memory capable of data writing, data reading and/or data deletion, and the memory chip 100 is formed by a semiconductor integrated manufacturing process.
  • the memory chip 100 may include a memory array and peripheral circuits connected to the memory array.
  • the memory array includes a plurality of memory cells and bit lines, word lines, and metal wirings (metal contact lines) connected to the memory cells. part), the storage unit is used for storing data, and the peripheral circuit is a related circuit when operating the storage array.
  • the memory chip 100 is a DRAM memory chip, and the DRAM memory chip includes a plurality of memory cells.
  • the memory cells generally include capacitors and transistors, the gates of the transistors are connected to the word lines, and the drains are connected to the word lines. It is connected to the bit line, and the source is connected to the capacitor.
  • the memory chip 100 may be other types of memory chips.
  • the temperature detection module 110 is used to detect the temperature of the memory chip 100 and provide a signal to the control chip 120 .
  • the control chip 120 controls the memory chip 100 to start up.
  • the specific size of the set threshold may be set according to actual needs or experience.
  • the temperature detection module 110 includes a temperature detection unit 111 .
  • the temperature detection unit 111 includes a temperature sensitive unit 1110 and an adjustable resistance unit 1111 .
  • the temperature sensitive unit 1110 is used to detect the temperature of the memory chip 100 , and the electrical conductivity of the temperature sensitive unit 1110 varies with the temperature.
  • the temperature-sensitive unit 1110 is a diode.
  • the diode is sensitive to temperature, and its current changes with the change of the surrounding temperature. By measuring the voltage of the diode, the corresponding voltage of the diode is obtained. temperature, which in turn can be used to measure the temperature of the surrounding environment.
  • the adjustable resistance unit 1111 is connected in parallel with the temperature sensitive unit 1110 .
  • the temperature detection unit 111 is configured to calibrate the temperature detection unit 111 by adjusting the resistance value of the adjustable resistance unit 1111 .
  • the resistance value of the adjustable resistance unit 1111 is changed through the control of the control chip 120, so that the output voltage of the positive terminal of the diode changes, so that the calibration of the diode can be realized.
  • FIG. 3 is a circuit diagram of an embodiment of the variable resistance unit 1111 .
  • the adjustable resistance unit 1111 includes a plurality of sub-resistors R1n and a plurality of switches S1n.
  • the sub-resistors R1n are connected in series, each switch S1n is connected in parallel with at least one of the sub-resistors R1n, and the resistance value of the adjustable resistance unit 1111 can be changed by changing the on-off of a plurality of the switches S1n .
  • sub-resistors R11-R15 and switches S11-S15 are schematically shown, and each sub-resistor is connected in parallel with a switch.
  • the sub-resistor R11 is connected in parallel with the switch S11
  • the sub-resistor R12 is connected in parallel with the switch S12
  • the sub-resistor R13 is connected in parallel with the switch S13
  • the sub-resistor R14 is connected in parallel with the switch S14
  • the sub-resistor R15 is connected in parallel with the switch S15.
  • two or more sub-resistors may also be connected in series and then connected in parallel with one switch.
  • R13 is connected in series with switch S11 in parallel.
  • the on-off of a plurality of the switches S1n is changed.
  • the switch S1n is turned off, and the sub-resistor connected in parallel with it is connected to the circuit; when the resistance value of the adjustable resistance unit 1111 needs to be decreased, the switch S1n is connected The switch S1n is turned on, the switch S1n is connected to the circuit, and the sub-resistor connected in parallel with it is disconnected.
  • the switch S11 when the resistance value of the adjustable resistance unit 1111 needs to be increased, the switch S11 is turned off, and the sub-resistor R11 connected in parallel with the switch S11 is connected to the circuit; When the resistance value of the resistance unit 1111 is adjusted, the switch S11 is turned on, so that the switch S11 is connected to the circuit, and the sub-resistor R11 connected in parallel with it is short-circuited.
  • the resistance values of the sub-resistors R1n are the same, so as to simplify the difficulty of layout layout, which is simple and easy to implement, and convenient for manufacture.
  • the sub-resistor R1n is a polysilicon resistor or an N-type diffused resistor or a P-type diffused resistor. Further, the sub-resistors R1n are electrically connected through a first layer of metal wires, and the sub-resistors R1n and the switch S1n are electrically connected through a second layer of metal wires. This approach enables further ease of manufacture, improved stability and accuracy.
  • the switch S1n can be a transistor, such as an NMOS transistor or a PMOS transistor, which has a stable structure and is easy to manufacture.
  • adjustable resistance unit 111 provided by the present invention.
  • other circuit structures may also be used to realize the adjustable resistance unit 111 .
  • the temperature detection unit 111 further includes a constant value resistor Ra.
  • the constant value resistor Ra is connected in series with the temperature sensitive unit 1110 .
  • the temperature sensitive unit 1110 is a diode
  • the first end of the constant value resistor Ra is electrically connected to the power supply Vtemp
  • the second end of the constant value resistor Ra is connected to the diode
  • the positive terminal of the diode is connected, and the negative terminal of the diode is electrically connected to the ground terminal VSS.
  • the adjustable resistance unit 1111 includes a first end and a second end, the sub-resistor Rn is disposed between the first end and the second end, and the first end of the adjustable resistance unit 1111 It is electrically connected to the ground terminal VSS, and the second terminal of the adjustable resistance unit 1111 is electrically connected to the second terminal of the fixed-value resistor Ra.
  • the semiconductor device of the present invention calibrates the temperature detection unit 111 by adjusting the resistance value of the adjustable resistance unit 1111, so as to ensure the accuracy of measurement and avoid large measurement errors.
  • the semiconductor device includes one or more memory chips 100 , and the temperature detection module 110 includes one or more temperature detection units 111 .
  • the temperature detection unit 111 can be used to detect the temperature of one or more memory chips 100 .
  • the temperature detection unit 111 and the memory chip 100 may be in a one-to-one relationship or a one-to-many relationship.
  • the temperature detection unit 111 and the memory chip 100 are in a one-to-one relationship, and the temperature detection unit 111 It is only used to detect the temperature of the memory chip 100 .
  • the temperature detection unit 111 and the memory chip 100 are in a one-to-many relationship, and the temperature detection unit 111 has a one-to-many relationship. It is used for detecting the temperature of a plurality of the memory chips 100 .
  • the The temperature detection unit 111 and the memory chip 100 may have a one-to-one relationship and a one-to-many relationship at the same time, or only a one-to-many relationship. That is, there may be a situation in which one temperature detection unit 111 detects the temperature of only one memory chip 100 and one temperature detection unit 100 detects the temperature of a plurality of the memory chips 100 , or only one temperature detection unit 100 detects a plurality of the temperature of the memory chip 100 .
  • the The temperature detection unit 111 is in a one-to-one relationship with the memory chip 100 , and one of the temperature detection units 111 is used to detect the temperature of one of the memory chips 100 .
  • the number of the memory chips 100 is plural, and the number of the temperature detection units 111 is also plural, as shown in FIG. 1 , which is schematically drawn in FIG. 1 .
  • Four memory chips 100 and four temperature detection units 111 are shown, a plurality of the memory chips 100 are stacked and arranged, and the temperature detection units 111 are in one-to-one correspondence with the memory chips 100 .
  • the temperature detection unit 111 may be formed in the memory chip 100 through a semiconductor integrated fabrication process. If the temperature detection unit 111 is only used to detect the temperature of one memory chip 100, it can be formed in the memory chip 100. For example, in this embodiment, as shown in FIG. 1, the temperature detection unit 111 and the memory chip 100 are in one-to-one correspondence, and each memory chip 100 is provided with a temperature detection unit 111 . If the temperature detection unit 111 is used to detect the temperature of a plurality of memory chips 100 , it can be formed in any one of the memory chips 100 of the plurality of memory chips 100 , or formed in the middle or bottommost memory chip 100 . Inside. For example, in the second embodiment of the present invention, please refer to FIG. 4 , which is a schematic structural diagram of the second embodiment of the semiconductor device of the present invention. The temperature detection unit 111 is arranged in the bottommost memory chip 100 and can measure four memory chips. The temperature of the chip 100 .
  • the temperature detection unit 111 is not provided in the memory chip 100 , but is provided in the control chip 120 .
  • FIG. 5 is a schematic structural diagram of a semiconductor device according to a third embodiment of the present invention.
  • the temperature detection unit 111 is disposed in the control chip 120 and can measure the four memory chips 100 stacked on the control chip 120 . temperature.
  • FIG. 6 is a schematic structural diagram of a semiconductor device according to a fourth embodiment of the present invention.
  • the semiconductor device further includes a circuit substrate 130 , and the circuit substrate 130 has connection lines (Fig. (not shown), the memory chip 100 and the control chip 120 are both located on the circuit substrate 130 , and the memory chip 100 and the control chip 120 are electrically connected through the connection lines in the circuit substrate 130 .
  • the temperature detection unit 111 is also disposed on the circuit substrate 130 to measure the ambient temperature, which is close to the temperature of the memory chip 100 , which can be approximated as the temperature of the memory chip 100 .
  • the circuit substrate 130 includes but is not limited to a PCB circuit board.
  • the temperature detection unit 111 may not be provided on the circuit substrate 130 , but is provided in the memory chip 100 as shown in FIG. 1 , FIG. 4 and FIG. 5 . Or in the control chip 120 .
  • control chip 120 in controlling the startup of the memory chip 100 in the embodiment of the present invention can also be realized by setting a control circuit in the memory chip 100.
  • the existence of the control chip 120 is not required, and the art Those skilled in the art should understand that it can be set by themselves as required.
  • FIG. 7 is a schematic diagram of electrical connection of the semiconductor device according to the first embodiment of the present invention. Please refer to FIG. 7 .
  • the temperature detection unit 111 is powered by the power supply Vtemp
  • the memory chip 100 is powered by the VDD.
  • the ground terminal VSS, the power supply VDD and the power supply Vtemp are provided by the control chip 120 . Since the temperature detection unit 111 and the memory chip 100 are powered by different power sources, the power supply of the temperature detection unit 111 and the memory unit 100 can be independently controlled, so that the temperature detection unit 111 and the storage unit 100 can be independently controlled.
  • the memory chip 100 is not activated at the same time.
  • the present invention can control the activation of the temperature detection unit 111 and the memory chip 100 respectively, that is, the activation of the temperature detection unit 111 is not affected by whether the memory chip 100 is activated, so that the temperature detection of the memory chip 100 is not affected by the memory chip 100.
  • the influence of whether the chip 100 is started can provide a reference for the start and operation of the memory chip 100 , thereby preventing the memory chip 100 from starting or running at a low temperature, and improving the stability of the memory chip 100 .
  • temperature has a great influence on the performance of the memory chip 100 , especially when the memory chip 100 is activated. If the memory chip 100 is started at a low temperature, the time for writing data into the memory chip 100 will change (eg, lengthen), which will affect the stability of the memory chip 100 writing. temperature so that the memory chip 100 can be activated within a suitable temperature.
  • the power supply of the temperature detection unit 111 in the present invention is earlier than the power supply of the memory chip 100 , that is, before the memory chip 100 is started, the temperature detection unit 111 has been started, so that the temperature before the start of the memory chip 100 can be obtained.
  • the temperature provides a reference for the startup of the memory chip 100 .
  • the power supply time difference between the temperature detection unit 111 and the memory chip 100 depends on the temperature change rate of the memory chip 100.
  • the temperature change rate of the memory chip 100 is large, the time for the memory chip 100 to reach the preset temperature is short, the power supply time difference between the temperature detection unit 111 and the memory chip 100 is small, and if the temperature change rate of the memory chip 100 is small and the time for the memory chip 100 to reach the preset temperature is long, the temperature detection The power supply time difference between the unit 111 and the memory chip 100 is large.
  • the temperature detection unit 111 and the memory chip 100 share the same ground terminal VSS.
  • the advantage is that, on the one hand, the leakage current of the memory chip 100 in the non-starting stage will not be increased, and on the other hand, the number of pins will be reduced and space will be saved.
  • a plurality of memory chips 100 are stacked on the control chip 120 , and the control chip 120 is bonded to the bottommost memory chip 100 in the stacked structure.
  • the memory chip 100 is disposed on the control chip 120, and the control chip 120 and the memory chip 100 are bonded together.
  • the memory chip 100 is formed with a through silicon via interconnection structure 101 , and the memory chip 100 and the control chip 120 are electrically connected through the through silicon via interconnection structure 101 , and the temperature detection unit 111 is electrically connected with the control chip 120 . That is, the memory chip 100 is electrically connected to the ground terminal VSS and the power supply VDD through the through silicon via interconnection structure 101 , and the temperature detection unit 111 is electrically connected to the power supply Vtemp and the ground terminal VSS.
  • each memory chip 100 when a plurality of memory chips 100 are stacked and arranged, each memory chip 100 can be connected to the control chip 120 through different through-silicon via interconnect structures; when there are multiple temperature detection units 111, There may be a situation where each temperature detection unit 111 is connected to the control chip 120 through different through silicon via interconnect structures, and there may also be a situation where multiple temperature detection units 111 share a through silicon via interconnect structure to be connected to the control chip 120 . It can be understood that the memory chip 100 and the temperature detection unit 111 are connected to the control chip 120 through different through-silicon via interconnect structures, so that the temperature detection unit 111 and the memory chip 100 can use different Power supply. Further, the power supply of a plurality of the temperature detection units 111 may also share the process through-silicon via interconnection structure.
  • the memory chip 100 and the temperature detection unit 111 may also be electrically connected to the control chip 120 through metal wires (formed by a wire bonding process).
  • the A/D conversion module 112 includes a resistance unit and a plurality of comparison units Px.
  • the resistance unit has a first end and a second end.
  • the first end of the resistance unit is electrically connected to a power source.
  • the resistance unit and the temperature detection unit 111 may use the same power source, or may use different power sources.
  • the A/D conversion module 112 is provided in the memory chip 100, the first end of the resistance unit and the temperature detection unit 111 can use the same power supply Vtemp; if the A/D conversion module 112 is provided with the same power supply Vtemp In the control chip 120, the first end of the resistance unit and the temperature detection unit 111 may use different power supplies, and the resistance unit may use the power supply VDD.
  • the second terminal of the resistance unit is electrically connected to the ground terminal VSS.
  • the resistance unit has a plurality of lead-out terminals Ax, and the voltage of each lead-out terminal Ax is different.
  • the resistance unit includes a plurality of sub-resistors Rx connected in series, and the number of the sub-resistors Rx spaced between each lead end Ax of the resistance unit and the second end of the resistance unit is different, So that the voltage of each terminal Ax is different.
  • a sub-resistor R1 is spaced between the lead-out terminal A1 and the second end of the resistance unit, and sub-resistors R1 and R2 are spaced between the lead-out end A2 and the second end of the resistance unit, so the voltages of the lead-out end A1 and the lead-out end A2 are different.
  • the number of sub-resistors Rx spaced between each lead end Ax of the resistance unit and the second end of the resistance unit is incremented by a preset value.
  • the preset value may be a certain value or a variable value.
  • the number of sub-resistors Rx spaced between each lead end Ax of the resistance unit and the second end of the resistance unit is incremented by a constant value of 1.
  • the fixed value can also be incremented by 2 or the like.
  • the preset value When the preset value is a variable value, the preset value has a changing trend.
  • the variation trend is set according to the voltage increase of the lead-out terminal Ax. For example, if the voltage increase of the lead-out terminal Ax is increasing, the change trend of the preset value is increasing; if the voltage increase of the lead-out end Ax is decreasing, the change trend of the preset value is decreasing; If the voltage increase of the lead-out terminal Ax is to increase first and then decrease, the change trend of the preset value is to increase first and then decrease.
  • the resistance values of the sub-resistors Rx are the same or different, so that the voltage increase changes between the lead-out terminals Ax are consistent or inconsistent. Wherein, if the resistance values of the sub-resistors Rx are the same, the difficulty of layout layout can be simplified, which is simple and easy to implement, and convenient for manufacture.
  • the signal at the input end of the A/D conversion module is used as the input signal of the comparison unit Px, that is, the analog signal output by the temperature detection unit is used as the input signal of the comparison unit Px.
  • the signals of the multiple terminals Ax of the resistance unit are respectively used as the reference signals of the multiple comparison units Px.
  • the lead-out terminal Ax corresponds to the comparison unit Px one-to-one.
  • the signal of the lead-out terminal A1 is used as the reference signal of the comparison unit P1
  • the signal of the lead-out terminal A2 is used as the reference signal of the comparison unit P2, and so on, the lead-out terminal Ax and the comparison unit Px are one A correspondence.
  • the comparison unit Px outputs a digital signal. According to the digital signal output by the comparison unit Px, the temperature of the memory chip 100 detected by the temperature detection unit 111 can be obtained.
  • the voltage of the lead end Ax changes unevenly , so that the reference signals of the plurality of comparison units Px change non-uniformly, and in different voltage regions, the reference signals of the comparison units Px have different amplitudes, which can change the measurement accuracy of the voltage region.
  • the preset value is changed in a small range, so that the increase of the reference signal is small, the number of signal sampling points is increased, and the measurement accuracy of the region is improved.
  • the preset value is greatly changed, so that the increase of the reference signal is large, the number of signal sampling points is reduced, and the measurement efficiency is improved.
  • the voltage region that needs to be accurately measured is 1.2V-1.7V
  • the corresponding reference signal range is 1.2V-1.7V
  • the preset The increase of the set value is small.
  • the increase of the preset value is 1, so that the increase of the reference signal is 0.1V, so that the number of sampling points in the voltage region can be increased, and the measurement accuracy can be improved.
  • the A/D conversion module 112 further includes an output unit 1120, the output unit 1120 is connected to the comparison unit Px, and is used for outputting the digital signal. Further, in this embodiment, the A/D conversion module 112 further includes an encoding unit EEC, the encoding unit EEC receives the digital signal output by the comparison unit Px, and performs encoding, and the formed signal is input to the output Unit 1120, the output unit 1120 outputs the encoded digital signal.
  • the semiconductor device of the present invention uses the temperature detection module to detect the temperature of the memory chip.
  • the temperature detected by the temperature detection module reaches the set threshold, or after the temperature of the memory chip 100 reaches the set threshold, the memory chip is activated and the temperature
  • the temperature detected by the detection module provides a reference for the startup and operation of the memory chip, thereby preventing the memory chip from starting and operating at low temperature, shortening the writing time, and improving the writing stability of the memory chip.
  • the control chip 120 of the present invention can also be activated before the memory chip 100 is activated, and the control chip 120 uses the heat generated by itself after activation to heat the memory chip 100 to rapidly increase the temperature of the memory chip 100 .
  • control chip 120 controls the temperature detection unit 111 to be activated to detect the temperature of the memory chip 100 .
  • the temperature detection unit 111 can also transmit the detected temperature to the control chip 120 as data of the control chip 120 .
  • the control chip 120 can determine whether the temperature detected by the temperature detection unit 111 reaches the set threshold, and if the temperature reaches the set threshold, the memory chip 100 is controlled to start up.
  • the control unit 120 determines that the temperature detected by the temperature detection unit 111 reaches the set threshold, Then the control chip 120 controls the memory chip 100 to start up.
  • the control unit 120 determines that the temperature detected by the temperature detection unit 111 reaches the set threshold, then The control unit 120 first controls the memory chip 100 closest to the control chip 120 to start up, and then controls the other memory chips 100 above to start up in sequence.
  • temperature detection units 111 and multiple memory chips 100 there are multiple temperature detection units 111 and multiple memory chips 100, and there may be a temperature detection unit 111 that detects the temperature of only one memory chip 100 and a temperature detection unit 111 that detects the temperature of multiple memory chips 100 situation, or only one temperature detection unit 111 detects the temperature of a plurality of the memory chips 100, when the control unit 120 determines that the temperature detected by a certain temperature detection unit 111 reaches the set threshold, it controls the temperature detection unit 111 corresponding to If the temperature detection unit 111 detects the temperature of multiple memory chips 100, it first controls the memory chip 100 closest to the control chip 120 to start up, and then controls the other memory chips 100 above to start up in sequence.
  • the control unit 110 determines that the temperature detected by a certain temperature detection unit 111 reaches the set threshold
  • the memory chip 100 corresponding to the temperature detection unit 111 is controlled to start up.
  • there are 4 memory chips 100 in the stacked structure shown in FIG. 1 and each memory chip 100 has a corresponding temperature detection unit 111 , so each temperature detection unit 111 can detect the temperature of the corresponding memory chip 100 .
  • the control chip 120 will sequentially determine whether the temperature detected by the four temperature detection units 111 reaches the set threshold value, if the temperature detected by a certain temperature detection unit 111 reaches the set threshold value , then control the memory chip corresponding to the temperature detection unit 111 to start up. For example, when the temperature detected by the temperature detection unit 111 in the bottommost memory chip 100 in the stack structure first reaches the set threshold, the control chip 120 first controls the stack structure. The memory chip 100 at the bottom layer starts up, and then, when the temperature detected by the temperature detection unit 111 corresponding to the memory chip 100 in the penultimate layer in the stack structure also reaches the set threshold, the control unit 301 then controls the temperature detection unit 301 in the stack structure. The memory chip 100 in the penultimate layer is activated, and the memory chips 100 in the upper two layers are activated and so on.
  • the aforementioned control structure and control method can further improve the accuracy of the start-up timing of each memory chip 100, and can further reduce the need for each memory chip 100 in a low temperature environment.
  • the writing time during data writing further improves the stability of writing to each memory chip 100 .
  • the temperature of the memory chip 100 can be increased to a set threshold by controlling the chip 120, thereby preventing the bit lines, word lines, and metal connections (metal contacts) in the memory chip 100 from The resistance increases due to the low ambient temperature, thereby reducing the writing time when writing data to the storage chip in a low temperature environment, and improving the writing stability of the storage chip.
  • the set threshold can be set in the control chip 120, and the specific size of the set threshold can be set according to actual needs or experience.
  • control chip 120 may have an additional heating circuit (not shown in the drawings).
  • the heating circuit is used for heating the memory chip 100 .
  • the control chip 120 determines whether the temperature of the memory chip 100 detected by the temperature detection unit 111 reaches the set threshold, and if it does not reach the set threshold, Then, the heating circuit is controlled to heat the memory chip 100 , and if the set threshold is reached, the heating circuit is controlled to stop heating the memory chip 100 . In this way, precise control of the heating process is achieved, so that the temperature of the memory chip 100 can be kept near the set threshold, preventing the temperature of the memory chip 100 from being too high or too low, so that the writing time to the memory can always be kept short.

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Abstract

本发明提供一种半导体装置，其包括存储芯片及温度检测模块，温度检测模块用于检测所述存储芯片的温度，温度检测模块包括：温度检测单元，温度检测单元包括温度敏感单元及可调电阻单元，温度敏感单元的导电性能随温度的变化而变化，可调电阻单元与温度敏感单元并联；其中温度检测单元被配置为通过调整可调电阻单元的电阻值来对温度检测单元进行校准。本发明利用温度检测模块检测存储芯片的温度，从而避免存储芯片在低温下启动及运行，缩短写入时间，提高存储芯片写入的稳定性。另外，本发明温度检测模块电路结构简单，易于实现，温度检测模块占用面积小，且对温度检测单元进行校准，提高温度检测单元的检测准确度。

Description

半导体装置
相关申请引用说明
本申请要求于2020年07月17日递交的中国专利申请号202010689682.7，申请名为“半导体装置”的优先权，其全部内容以引用的形式附录于此。
技术领域
本发明涉及存储器领域，尤其涉及一种半导体装置。
背景技术
动态随机存取存储器(Dynamic Random Access Memory，DRAM)是计算机中常用的半导体存储器件，其存储阵列区由许多重复的存储单元组成。每个存储单元通常包括电容器和晶体管，晶体管的栅极与字线相连、漏极与位线相连、源极与电容器相连，字线上的电压信号能够控制晶体管的打开或关闭，进而通过位线读取存储在电容器中的数据信息，或者通过位线将数据信息写入到电容器中进行存储。
温度对存储器写入存在较大影响，在低温环境中，对存储器进行写入时，存在写入时间较长，写入的稳定性不高的问题。
发明内容
本发明所要解决的技术问题是，提供一种半导体装置，其能够检测存储芯片的温度，避免存储芯片在低温下启动及运行，缩短写入时间，提高存储芯片写入的稳定性；同时还能够对温度检测单元进行校准，提高温度检测单元的检测准确度。
为了解决上述问题，本发明提供了一种半导体装置，其包括存储芯片及温度检测模块，所述温度检测模块用于检测所述存储芯片的温度，所述温度检测模块包括：温度检测单元，所述温度检测单元包括温度敏感单元及可调电阻单元，所述温度敏感单元的导电性能随温度的变化而变化，所述可调电阻单元与所述温度敏感单元并联；其中所述温度检测单元被配置为通过调整所述可调电阻单元的电阻值来对所述温度检测单元进行校准。
进一步，所述可调电阻单元包括多个子电阻及多个开关，所述子电阻串联连接，每一所述开关至少与一个所述子电阻并联，通过改变多个所述开关的通断，来改变所述可调电阻单元的电阻值。
进一步，所述子电阻的阻值相同。
进一步，所述子电阻为多晶硅电阻或者N型扩散电阻或者P型扩散电阻。
进一步，所述子电阻之间通过第一层金属线电连接，所述子电阻与所述开关之间通过 第二层金属线电连接。
进一步，所述温度检测单元还包括定值电阻，所述定值电阻与所述温度敏感单元串联，所述定值电阻包括第一端及第二端，所述定值电阻的第一端与电源电连接，所述定值电阻的第二端与所述温度敏感单元电连接。
进一步，所述温度敏感单元为二极管，所述二极管的正端与所述定值电阻的第二端电连接，所述二极管的负端与接地端电连接。
进一步，所述可调电阻单元包括第一端及第二端，所述子电阻设置在所述第一端与所述第二端之间，所述可调电阻单元的第一端与接地端电连接，所述可调电阻单元的第二端与所述定值电阻的第二端电连接。
进一步，所述温度检测模块还包括A/D转换模块，具有输入端及输出端，所述输入端与所述定值电阻的第二端电连接，所述输出端输出数字信号，所述A/D转换模块用于将所述定值电阻第二端的模拟信号转换为数字信号。
进一步，所述A/D转换模块包括：电阻单元，具有第一端及第二端，所述电阻单元的第一端与电源电连接，所述电阻单元的第二端与接地端电连接，所述电阻单元具有多个引出端，每一引出端的电压不同；多个比较单元，所述A/D转换模块输入端的信号作为所述比较单元的输入信号，所述电阻单元的多个引出端信号分别作为多个所述比较单元的参考信号，所述比较单元输出数字信号。
进一步，所述A/D转换模块还包括编码单元，所述编码单元接收所述比较单元的数字信号，并进行编码。
进一步，所述A/D转换模块还包括输出单元，所述输出单元与所述比较单元连接，用于将所述数字信号输出。
进一步，所述电阻单元包括多个串联连接的子电阻，所述电阻单元的每一引出端与所述电阻单元的第二端之间间隔的子电阻的数量不同，以使每一引出端的电压不同。
进一步，所述子电阻的电阻值相同或不同。
进一步，所述电阻单元的每一引出端与所述电阻单元的第二端之间间隔的子电阻的数量以预设数值递增。
进一步，所述子电阻为多晶硅电阻、N型扩散电阻、P型扩散电阻中的至少一种。
进一步，所述子电阻之间通过第一层金属线电连接，所述电阻单元通过第二层金属线形成所述引出端。
进一步，所述温度检测单元与所述存储芯片采用不同的电源供电。
进一步，所述温度检测单元的供电早于所述存储芯片的供电。
进一步，所述半导体装置还包括控制芯片，所述存储芯片及所述温度检测模块与所述控制芯片电连接。
进一步，所述控制芯片用于在存储芯片启动之前对存储芯片进行加热，并判断所述温度检测单元检测的温度是否达到设定阈值，若达到设定阈值，则控制所述存储芯片启动。
本发明的优点在于，利用温度检测模块检测存储芯片的温度，，温度检测模块检测的温度为存储芯片的启动及运行提供参考，从而避免存储芯片在低温下启动及运行，缩短写入时间，提高存储芯片写入的稳定性。另外，本发明温度检测模块电路结构简单，易于实现，温度检测模块占用面积小，且对温度检测单元进行校准，提高温度检测单元的检测准确度。
附图说明
图1是本发明半导体装置的第一实施例的结构示意图；
图2是本发明半导体装置中温度检测模块的电路图；
图3是本发明半导体装置第一实施例的可变电阻单元的电路图；
图4是本发明半导体装置第二实施例的结构示意图；
图5是本发明半导体装置第三实施例的结构示意图；
图6是本发明半导体装置第四实施例的结构示意图；
图7是本发明半导体装置的第一实施例的电连接示意图。
具体实施方式
下面结合附图对本发明提供的半导体装置的实施例做详细说明。
如背景技术所言，温度对存储器写入存在较大影响，在低温环境中，对存储器进行写入时，存在写入时间较长，写入的稳定性不高的问题。
研究发现，现有的存储器工作在低温环境中时，由于温度下降会使得存储器中的位线、字线、以及金属连线(金属接触部)等的电阻会增大，电阻的增大，会使得向存储器中写入数据时的时间会变化或加长，影响了存储器写入的稳定性。
因此，本发明提供一种半导体装置，其采用温度检测模块检测所述存储芯片的温度，以为存储芯片的启动及运行提供参考，从而避免存储芯片在低温下启动及运行，缩短写入时间，提高存储芯片写入的稳定性。同时，本发明半导体装置还能够对温度检测单元进行校准，提高温度测量的准确度。
图1是本发明半导体装置的第一实施例的结构示意图，图2是本发明半导体装置中温度检测模块的电路图，请参阅图1及图2，本发明半导体装置包括存储芯片100及温度检测模块110。
所述半导体装置还包括控制芯片120，所述存储芯片100及所述温度检测模块110与所述控制芯片120电连接。所述控制芯片120用于控制所述存储芯片100及所述温度检测模块110的启动及运行。所述存储芯片100的启动包括上电以及自检测，所述存储芯片100的运行包括向存储芯片100中写入数据，从存储芯片100读取数据，以及将存储芯片100中存取的数据删除等。
所述存储芯片100为现有能进行数据写入、数据读取和/或数据删除的存储器，所述存储芯片100通过半导体集成制作工艺形成。具体的说，所述存储芯片100可以包括存储阵列和与存储阵列连接的外围电路，所述存储阵列包括多个存储单元和与存储单元连接的位线、字线、以及金属连线(金属接触部)，所述存储单元用于存储数据，所述外围电路为在对存储阵列进行操作时的相关电路。本实施例中，所述存储芯片100为DRAM存储芯片，所述DRAM存储芯片中包括多个存储单元，所述存储单元通常包括电容器和晶体管，所述晶体管的栅极与字线相连、漏极与位线相连、源极与电容器相连。在其他实施例中所述存储芯片100可以为其他类型的存储芯片。
所述温度检测模块110用于检测所述存储芯片100的温度，并将信号提供给控制芯片120。当所述温度检测模块110检测的温度达到设定阈值时，所述控制芯片120控制所述存储芯片100启动。其中，设定阈值的具体大小可以根据实际需要或者经验进行设定。
所述温度检测模块110包括温度检测单元111。所述温度检测单元111包括温度敏感单元1110及可调电阻单元1111。
所述温度敏感单元1110用于检测所述存储芯片100的温度，所述温度敏感单元1110的导电性能随温度的变化而变化。在本实施例中，所述温度敏感单元1110为二极管，所述二极管对温度敏感，随着其周围环境温度的变化，其电流发生变化，通过测量所述二极管的电压，得到所述电压对应的温度，进而能够用于测量周围环境的温度。
所述可调电阻单元1111与所述温度敏感单元1110并联。其中，所述温度检测单元111被配置为通过调整所述可调电阻单元1111的电阻值来对所述温度检测单元111进行校准。具体地说，通过控制芯片120的控制而改变所述可调电阻单元1111的电阻值，使得二极管正端的输出电压发生变化，从而能够实现对二极管的校准。
本实施例列举了一种可变电阻单元1111的电路结构。请参阅图3，其为所述可变电阻单元1111一实施例的电路图，所述可调电阻单元1111包括多个子电阻R1n及多个开关S1n。其中，所述子电阻R1n串联连接，每一所述开关S1n至少与一个所述子电阻R1n并联，通过改变多个所述开关S1n的通断，来改变所述可调电阻单元1111的电阻值。
在该实施例中，示意性地绘示了子电阻R11～R15，开关S11～S15，每一个子电阻均与一个开关并联。具体地说，子电阻R11与开关S11并联，子电阻R12与开关S12并联，子电阻R13与开关S13并联，子电阻R14与开关S14并联，子电阻R15与开关S15并联。在本发明其他实施例中，也可是两个及以上子电阻串联后与一个开关并联，例如，子电阻R11与子电阻R12串联后与开关S11并联，或子电阻R11、子电阻R12及子电阻R13串联后与开关S11并联。
当需要改变所述可调电阻单元1111的电阻值时，改变多个所述开关S1n的通断。当需要增大所述可调电阻单元1111的电阻值时，断开所述开关S1n，使与其并联的子电阻接入电路；当需要减小所述可调电阻单元1111的电阻值时，接通所述开关S1n，使所述开关S1n接入电路，与其并联的子电阻被断开。例如，在该实施例中，当需要增大所述可调电阻单元1111的电阻值时，断开所述开关S11，使与开关S11并联的子电阻R11接入电路；当需要减小所述可调电阻单元1111的电阻值时，接通所述开关S11，使所述开关S11接入电路，与其并联的子电阻R11被短路。
进一步，在本实施例中，所述子电阻R1n的电阻值相同，以简化版图布局难度，简单易行，便于制造。所述子电阻R1n为多晶硅电阻或者N型扩散电阻或者P型扩散电阻。进一步，所述子电阻R1n之间通过第一层金属线电连接，所述子电阻R1n与所述开关S1n之间通过第二层金属线电连接。这种方式能够进一步易于制造，提高稳定性和精确性。
进一步，所述开关S1n可为晶体管，例如NMOS管或PMOS管，其结构稳定，且易于制造。
上述仅为本发明提供的一种可调电阻单元111的实施例，在本发明其他实施例中，也可采用其他电路结构实现可调电阻单元111。
请继续参阅图2，所述温度检测单元111还包括定值电阻Ra。所述定值电阻Ra与所述温度敏感单元1110串联。具体地说，在该实施例中，所述温度敏感单元1110为二极管，则所述定值电阻Ra的第一端与电源Vtemp电连接，所述定值电阻Ra的第二端与所述二极管的正端连接，所述二极管的负端与接地端VSS电连接。
进一步，所述可调电阻单元1111包括第一端及第二端，所述子电阻Rn设置在所述第一端与所述第二端之间，所述可调电阻单元1111的第一端与接地端VSS电连接，所述可调电阻单元1111的第二端与所述定值电阻Ra的第二端电连接。
本发明半导体装置通过调整所述可调电阻单元1111的电阻值来对所述温度检测单元111进行校准，从而能够保证测量的准确性，避免产生较大的测量误差。
所述半导体装置包括一个或者多个存储芯片100，所述温度检测模块110包括一个或者多个温度检测单元111。所述温度检测单元111可用于检测一个或者多个存储芯片100的温度。其中，所述温度检测单元111与所述存储芯片100可为一对一关系，或者一对多关系。
当所述存储芯片100的个数为一个，所述温度检测单元111的个数也为一个时，所述温度检测单元111与所述存储芯片100为一对一关系，所述温度检测单元111仅用于检测该存储芯片100的温度。
当所述存储芯片100的个数为多个，所述温度检测单元111的个数为一个时，所述温度检测单元111与所述存储芯片100为一对多关系，所述温度检测单元111用于检测多个所述存储芯片100的温度。
当所述存储芯片100的个数为多个，所述温度检测单元111的个数也为多个，但所述温度检测单元111的个数小于所述存储芯片100的个数时，所述温度检测单元111与所述存储芯片100可能同时存在一对一关系及一对多关系，或者仅存在一对多关系。即可能存在一个所述温度检测单元111仅检测一个存储芯片100的温度和一个温度检测单元100检测多个所述存储芯片100的温度的情况，或者仅存在一个温度检测单元100检测多个所述存储芯片100的温度的情况。
当所述存储芯片100的个数为多个，所述温度检测单元111的个数也为多个，且所述温度检测单元100的个数与所述存储芯片100的个数相同时，所述温度检测单元111与所述存储芯片100为一对一关系，一个所述温度检测单元111用于检测一个所述存储芯片100的温度。具体地说，在本实施例中，所述存储芯片100的个数为多个，所述温度检测单元111的个数也为多个，如图1所示，在图1中示意性地绘示四个存储芯片100及四个温度检测单元111，多个所述存储芯片100堆叠设置，所述温度检测单元111与所述存储芯片100一一对应。
进一步，所述温度检测单元111可通过半导体集成制作工艺形成在存储芯片100中。若所述温度检测单元111仅用于检测一个存储芯片100的温度，则其可形成在该存储芯片 100中，例如，在本实施例中，如图1所示，温度检测单元111与存储芯片100一一对应，在每一存储芯片100中均设置一个温度检测单元111。若所述温度检测单元111用于检测多个存储芯片100的温度时，其可形成在该多个存储芯片100中的任意一个存储芯片100内，或者形成在居中的或最底层的存储芯片100内。例如，在本发明第二实施例中，请参阅图4，其为本发明半导体装置第二实施例的结构示意图，温度检测单元111设置在最底层的存储芯片100内，其能够测量四个存储芯片100的温度。
在本发明另一实施例中，所述温度检测单元111并未设置在存储芯片100中，而是设置在控制芯片120中。具体地说，请参阅图5，其为本发明半导体装置第三实施例的结构示意图，温度检测单元111设置在控制芯片120内，其能够测量堆叠设置在控制芯片120上的四个存储芯片100的温度。
在本发明另一实施例中，请参阅图6，其为本发明半导体装置第四实施例的结构示意图，所述半导体装置还包括线路基板130，所述线路基板130中具有连接线路(附图中未绘示)，所述存储芯片100以及控制芯片120均位于所述线路基板130上，所述存储芯片100和控制芯片120通过所述线路基板130中的所述连接线路电连接。在该实施例中，所述温度检测单元111也设置在所述线路基板130上，以测量环境温度，该环境温度与存储芯片100温度接近，其可近似作为存储芯片100的温度。其中，所述线路基板130包括但不限于PCB电路板。可以理解的是，在本发明其他实施例中，所述温度检测单元111也可不设置在所述线路基板130上，而是如图1、图4及图5所示，设置在存储芯片100中或者控制芯片120中。
需要注意的是，本发明实施例中控制芯片120在控制存储芯片100启动等方面的功能，也可通过在存储芯片100设置控制电路来实现，此时，可无需控制芯片120的存在，本领域内技术人员应当理解，可根据需要自行设置。
进一步，所述温度检测单元111与所述存储芯片100采用不同的电源供电。图7是本发明半导体装置的第一实施例的电连接示意图，请参阅图7，所述温度检测单元111采用电源Vtemp供电，所述存储芯片100采用VDD供电。其中，所述接地端VSS、电源VDD及电源Vtemp由所述控制芯片120提供。由于所述温度检测单元111与所述存储芯片100采用不同的电源供电，因此，可独立地控制所述温度检测单元111及所述存储单元100的供电，从而实现所述温度检测单元111与所述存储芯片100的不同时启动。
因此，本发明可分别控制所述温度检测单元111与所述存储芯片100的启动，即温度 检测单元111的启动不受存储芯片100是否启动的影响，使得对存储芯片100温度的检测不受存储芯片100是否启动的影响，从而能够为存储芯片100的启动及运行提供参考，进而能够避免存储芯片100在低温下启动或者运行，提高存储芯片100的稳定性。
如前所述，温度对存储芯片100的性能有很大影响，特别是在存储芯片100启动时。若存储芯片100在低温下启动，会使向存储芯片100中写入数据的时间变化(如加长)，影响了存储芯片100写入的稳定性，则在存储芯片100启动之前需要测量存储芯片的温度，以使存储芯片100能够在合适的温度内启动。
因此，本发明所述温度检测单元111的供电早于所述存储芯片100的供电，即在所述存储芯片100启动之前，所述温度检测单元111已经启动，从而可获得存储芯片100启动之前的温度，为存储芯片100的启动提供参考。所述温度检测单元111与所述存储芯片100的供电时间差取决于所述存储芯片100的温度变化速率，若所述存储芯片100的温度变化速率大，所述存储芯片100达到预设温度的时间短，则所述温度检测单元111与所述存储芯片100的供电时间差小，若所述存储芯片100的温度变化速率小，所述存储芯片100达到预设温度的时间长，则所述温度检测单元111与所述存储芯片100的供电时间差大。
进一步，请参阅图7，所述温度检测单元111与所述存储芯片100共用同一接地端VSS。其优点在于，一方面不会增加存储芯片100未启动阶段的泄露电流，另一方面，会减少引脚的数目，节省空间。
请继续参阅图1，多个存储芯片100堆叠设置在所述控制芯片120上，所述控制芯片120与堆叠结构中最底层的存储芯片100键合在一起。而在本发明另一实施例中，当只有一个存储芯片100时，所述存储芯片100设置在控制芯片120上，所述控制芯片120与该存储芯片100键合在一起。
所述存储芯片100中形成有硅通孔互连结构101，通过硅通孔互连结构101将存储芯片100与控制芯片120进行电连接，将温度检测单元111与控制芯片120电连接。即通过硅通孔互连结构101将存储芯片100与接地端VSS及电源VDD电连接，将温度检测单元111与电源Vtemp及接地端VSS电连接。具体地说，在本实施例中，多个存储芯片100堆叠设置时，每一个存储芯片100可以通过不同的硅通孔互连结构与控制芯片120连接；当具有多个温度检测单元111时，可能存在每一个温度检测单元111通过不同的硅通孔互连结构与控制芯片120连接的情况，也可能存在多个温度检测单元111共用硅通孔互连结构与控制芯片120连接的情况。可以理解的是，所述存储芯片100与所述温度检测单元111通过不 同的硅通孔互连结构与控制芯片120连接，以使所述温度检测单元111及所述存储芯片100能够采用不同的电源供电。进一步，多个所述温度检测单元111的供电也可共用工艺硅通孔互连结构。
在其他实施例中，所述存储芯片100及所述温度检测单元111还可以通过金属引线(通过引线键合工艺形成)与所述控制芯片120电连接。
进一步，所述A/D转换模块112包括电阻单元及多个比较单元Px。
所述电阻单元具有第一端及第二端。所述电阻单元的第一端与电源电连接。所述电阻单元可与所述温度检测单元111采用同一电源，也可采用不同电源。例如，若所述A/D转换模块112设置在存储芯片100中，则所述电阻单元的第一端可与所述温度检测单元111采用同一电源Vtemp；若所述A/D转换模块112设置在控制芯片120中，则所述电阻单元的第一端可与所述温度检测单元111采用不同的电源，所述电阻单元可采用电源VDD。所述电阻单元的第二端与接地端VSS电连接。其中，所述电阻单元具有多个引出端Ax，每一引出端Ax的电压不同。
在本实施例中，所述电阻单元包括多个串联连接的子电阻Rx，所述电阻单元的每一引出端Ax与所述电阻单元的第二端之间间隔的子电阻Rx的数量不同，以使每一引出端Ax的电压不同。例如，引出端A1与电阻单元的第二端之间间隔子电阻R1，引出端A2与电阻单元的第二端之间间隔子电阻R1及R2，则引出端A1与引出端A2的电压不同。
其中，所述电阻单元的每一引出端Ax与所述电阻单元的第二端之间间隔的子电阻Rx的数量以预设数值递增。其中，所述预设数值可为一定值，也可为可变数值。
请参阅图2，在本实施例中，所述电阻单元的每一引出端Ax与所述电阻单元的第二端之间间隔的子电阻Rx的数量以定值1递增。而在本发明其他实施例中，也可以定值2等数量递增。
当所述预设数值为可变数值时，所述预设数值具有一变化趋势。所述变化趋势根据所述引出端Ax的电压增幅设定。例如，若所述引出端Ax的电压增幅为递增，则所述预设数值的变化趋势为递增；若所述引出端Ax的电压增幅为递减，则所述预设数值的变化趋势为递减；若所述引出端Ax的电压增幅为先增加再减小，则所述预设数值的变化趋势为先增加再减小。进一步，所述子电阻Rx的电阻值相同或不同，以使得所述引出端Ax之间的电压增幅变化一致或不一致。其中，若所述子电阻Rx的电阻值相同，则能够简化版图布局难度，简单易行，便于制造。
所述A/D转换模块输入端的信号作为所述比较单元Px的输入信号，即所述温度检测单元输出的模拟信号作为所述比较单元Px的输入信号。所述电阻单元的多个引出端Ax信号分别作为多个所述比较单元Px的参考信号。所述引出端Ax与所述比较单元Px一一对应。例如，所述引出端A1信号作为所述比较单元P1的参考信号，所述引出端A2信号作为所述比较单元P2的参考信号，依此类推，所述引出端Ax与所述比较单元Px一一对应。所述比较单元Px输出数字信号。根据所述比较单元Px输出的数字信号，可获得所述温度检测单元111检测的存储芯片100的温度。
当所述电阻单元的每一引出端Ax与所述电阻单元的第二端之间间隔的子电阻Rx的数量以可变的预设数值递增时，所述引出端Ax的电压非均匀地改变，以使多个所述比较单元Px的参考信号非均匀地改变，则在不同的电压区域，所述比较单元Px的参考信号的增幅不同，进而能够改变该电压区域的测量精度。具体地说，对需要精确测量的电压区域，所述预设数值以小幅度改变，以使参考信号的增幅小，提高信号采样点数，进而提高该区域的测量精度，对不需要精确测量的电压区域，所述预设数值以大幅度改变，以使参考信号的增幅大，减少信号采样点数，进而提高测量效率。例如，在本发明一实施例中，需要精确测量的电压区域为1.2V～1.7V，其对应的参考信号范围即为1.2V～1.7V，则在1.2V～1.7V电压区域，所述预设数值的增幅小，例如，所述预设数值的增幅为1，使得参考信号的增幅为0.1V，从而能够增加该电压区域的采样点数，提高测量精度，而在电压小于1.2V及大于1.7V的电压区域，所述预设数值的增幅大，例如，所述预设数值的增幅为3，使得参考信号的增幅为0.3V，适当减少采样点数，提高测量效率。进一步，所述A/D转换模块112还包括输出单元1120，所述输出单元1120与所述比较单元Px连接，用于将所述数字信号输出。进一步，在本实施例中，所述A/D转换模块112还包括编码单元EEC，所述编码单元EEC接收所述比较单元Px输出的数字信号，并进行编码，其形成的信号输入所述输出单元1120，所述输出单元1120将编码后的数字信号输出。
本发明半导体装置利用温度检测模块检测存储芯片的温度，当所述温度检测模块检测的温度达到设定阈值时，或者所述存储芯片100的温度达到设定阈值之后，所述存储芯片启动，温度检测模块检测的温度为存储芯片的启动及运行提供参考，从而避免存储芯片在低温下启动及运行，缩短写入时间，提高存储芯片写入的稳定性。
当存储芯片100处于低温环境中，若对其进行加热，则能够迅速提高存储芯片100的温度，从而加快存储芯片100的启动。因此，本发明所述控制芯片120还能够在存储芯片 100启动之前先进行启动，控制芯片120利用启动后自身产生的热量对存储芯片100进行加热，以快速提高存储芯片100的温度。
在所述控制芯片120启动后，所述控制芯片120控制所述温度检测单元111启动，以检测所述存储芯片100的温度。所述温度检测单元111还能够将检测的温度传送给控制芯片120，以作为控制芯片120的数据。
所述控制芯片120能够判断所述温度检测单元111检测的温度是否达到设定阈值，若达到设定阈值，则控制所述存储芯片100启动。
若仅有一个温度检测单元111及一个存储芯片100，一个所述温度检测单元111仅用于检测一个存储芯片的温度时，当控制单元120判定该温度检测单元111检测的温度达到设定阈值，则所述控制芯片120控制该存储芯片100启动。
若存在一个温度检测单元111及多个存储芯片100，且一个所述温度检测单元111检测多个存储芯片100的温度，当控制单元120判定该温度检测单元111检测的温度达到设定阈值，则控制单元120先控制离所述控制芯片120最近的存储芯片100启动，然后再控制上面的其他存储芯片100依次启动。
若存在多个温度检测单元111及多个存储芯片100，且可能存在一个所述温度检测单元111仅检测一个存储芯片100的温度和一个温度检测单元111检测多个所述存储芯片100的温度的情况，或者仅存在一个温度检测单元111检测多个所述存储芯片100的温度的情况，当控制单元120判断某一个温度检测单元111检测的温度达到设定阈值，则控制该温度检测单元111对应的存储芯片100启动，若该温度检测单元111检测多个存储芯片100的温度，则先控制离所述控制芯片120最近的存储芯片100启动，然后再控制上面的其他存储芯片100依次启动。
若存在多个温度检测单元111及多个存储芯片100，且所述温度检测单元111与所述存储芯片100一一对应，当控制单元110判断某一个温度检测单元111检测的温度达到设定阈值，则控制该温度检测单元111对应的存储芯片100启动。具体地说，如图1所示的堆叠结构中有4个存储芯片100，每一个存储芯片100中对应具有一个温度检测单元111，因而每一个温度检测单元111会对对应的存储芯片100的温度进行检测，获得四个温度检测值，所述控制芯片120会依次判断4个所述温度检测单元111检测的温度是否达到设定阈值时，若某一个温度检测单元111检测的温度达到设定阈值，则控制该温度检测单元111对应的存储芯片启动，比如堆叠结构中最底层的存储芯片100中的温度检测单元111检测 的温度先达到设定阈值时，则控制芯片120先控制所述堆叠结构最底层的那一个存储芯片100启动，接着，堆叠结构中倒数第二层中那个存储芯片100中对应的温度检测单元111检测的温度也达到设定阈值时，则控制单元301接着控制堆叠结构中倒数第二层的那个存储芯片100启动，上面两层的存储芯片100的启动以此类推。
对于半导体装置存在多个存储芯片100时，前述的这种控制结构和控制方式能使得每一个存储芯片100启动时机的精度进一步提高，并能进一步减小低温环境下的对每一个存储芯片100进行数据写入时的写入时间，进一步提高了对每一个存储芯片100写入的稳定性。
当本发明半导体装置工作在低温环境时，通过控制芯片120可以使得存储芯片100升温到设定阈值，从而可以防止存储芯片100中的位线、字线、以及金属连线(金属接触部)由于环境温度过低带来的电阻的增大，从而减小了低温环境下的对存储芯片进行数据写入时的写入时间，提高了存储芯片写入的稳定性。所述设定阈值可以设定在控制芯片120中，设定阈值的具体大小可以根据实际需要或者经验进行设定。
在另一实施例中，所述控制芯片120中可以具有额外的加热电路(附图中未绘示)。所述加热电路用于对所述存储芯片100进行加热。所述控制芯片120在对所述存储芯片100进行加热之前或之后，所述控制芯片120判断所述温度检测单元111检测的存储芯片100的温度是否达到设定阈值，若未达到设定阈值，则控制所述加热电路对存储芯片100进行加热，如达到设定阈值，则控制所述加热电路停止对存储芯片100进行加热。从而实现对加热过程的精确控制，使得存储芯片100的温度能保持在设定阈值附近，防止存储芯片100的温度过高或过低，从而使得对存储器的写入时间始终能保持较短。
以上所述仅是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员，在不脱离本发明原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本发明的保护范围。

Claims (21)

  1. 一种半导体装置，其特征在于，包括存储芯片及温度检测模块，所述温度检测模块用于检测所述存储芯片的温度，所述温度检测模块包括：
    温度检测单元，所述温度检测单元包括温度敏感单元及可调电阻单元，所述温度敏感单元的导电性能随温度的变化而变化，所述可调电阻单元与所述温度敏感单元并联；
    其中所述温度检测单元被配置为通过调整所述可调电阻单元的电阻值来对所述温度检测单元进行校准。
  2. 根据权利要求1所述的半导体装置，其特征在于，所述可调电阻单元包括多个子电阻及多个开关，所述子电阻串联连接，每一所述开关至少与一个所述子电阻并联，通过改变多个所述开关的通断，来改变所述可调电阻单元的电阻值。
  3. 根据权利要求2所述的半导体装置，其特征在于，所述子电阻的阻值相同。
  4. 根据权利要求2所述的半导体装置，其特征在于，所述子电阻为多晶硅电阻或者N型扩散电阻或者P型扩散电阻。
  5. 根据权利要求2所述的半导体装置，其特征在于，所述子电阻之间通过第一层金属线电连接，所述子电阻与所述开关之间通过第二层金属线电连接。
  6. 根据权利要求2所述的半导体装置，其特征在于，所述温度检测单元还包括定值电阻，所述定值电阻与所述温度敏感单元串联，所述定值电阻包括第一端及第二端，所述定值电阻的第一端与电源电连接，所述定值电阻的第二端与所述温度敏感单元电连接。
  7. 根据权利要求6所述的半导体装置，其特征在于，所述温度敏感单元为二极管，所述二极管的正端与所述定值电阻的第二端电连接，所述二极管的负端与接地端电连接。
  8. 根据权利要求7所述的半导体装置，其特征在于，所述可调电阻单元包括第一端及第二端，所述子电阻设置在所述第一端与所述第二端之间，所述可调电阻单元的第一端与接地端电连接，所述可调电阻单元的第二端与所述定值电阻的第二端电连接。
  9. 根据权利要求6所述的半导体装置，其特征在于，所述温度检测模块还包括A/D转换模块，具有输入端及输出端，所述输入端与所述定值电阻的第二端电连接，所述输出端输出数字信号，所述A/D转换模块用于将所述定值电阻第二端的模拟信号转换为数字信号。
  10. 根据权利要求9所述的半导体装置，其特征在于，所述A/D转换模块包括：
    电阻单元，具有第一端及第二端，所述电阻单元的第一端与电源电连接，所述电阻单元 的第二端与接地端电连接，所述电阻单元具有多个引出端，每一引出端的电压不同；
    多个比较单元，所述A/D转换模块输入端的信号作为所述比较单元的输入信号，所述电阻单元的多个引出端信号分别作为多个所述比较单元的参考信号，所述比较单元输出数字信号。
  11. 根据权利要求10所述的半导体装置，其特征在于，所述A/D转换模块还包括编码单元，所述编码单元接收所述比较单元的数字信号，并进行编码。
  12. 根据权利要求10所述的半导体装置，其特征在于，所述A/D转换模块还包括输出单元，所述输出单元与所述比较单元连接，用于将所述数字信号输出。
  13. 根据权利要求9所述的半导体装置，其特征在于，所述电阻单元包括多个串联连接的子电阻，所述电阻单元的每一引出端与所述电阻单元的第二端之间间隔的子电阻的数量不同，以使每一引出端的电压不同。
  14. 根据权利要求13所述的半导体装置，其特征在于，所述子电阻的电阻值相同或不同。
  15. 根据权利要求13所述的半导体装置，其特征在于，所述电阻单元的每一引出端与所述电阻单元的第二端之间间隔的子电阻的数量以预设数值递增。
  16. 根据权利要求13所述的半导体装置，其特征在于，所述子电阻为多晶硅电阻、N型扩散电阻、P型扩散电阻中的至少一种。
  17. 根据权利要求15所述的半导体装置，其特征在于，所述子电阻之间通过第一层金属线电连接，所述电阻单元通过第二层金属线形成所述引出端。
  18. 根据权利要求1所述的半导体装置，其特征在于，所述温度检测单元与所述存储芯片采用不同的电源供电。
  19. 根据权利要求17所述的半导体装置，其特征在于，所述温度检测单元的供电早于所述存储芯片的供电。
  20. 根据权利要求1所述的半导体装置，其特征在于，所述半导体装置还包括控制芯片，所述存储芯片及所述温度检测模块与所述控制芯片电连接。
  21. 根据权利要求20所述的半导体装置，其特征在于，所述控制芯片用于在存储芯片启动之前对存储芯片进行加热，并判断所述温度检测单元检测的温度是否达到设定阈值，若达到设定阈值，则控制所述存储芯片启动。
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