WO2022011921A1 - 一种薄膜晶体管阵列基板及显示装置 - Google Patents

一种薄膜晶体管阵列基板及显示装置 Download PDF

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WO2022011921A1
WO2022011921A1 PCT/CN2020/130984 CN2020130984W WO2022011921A1 WO 2022011921 A1 WO2022011921 A1 WO 2022011921A1 CN 2020130984 W CN2020130984 W CN 2020130984W WO 2022011921 A1 WO2022011921 A1 WO 2022011921A1
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insulating layer
layer
semiconductor
semiconductor layer
thin film
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French (fr)
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白思航
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Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Priority to US17/264,805 priority Critical patent/US12199109B2/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/301—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements flexible foldable or roll-able electronic displays, e.g. thin LCD, OLED
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0221—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/451—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs characterised by the compositions or shapes of the interlayer dielectrics
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/471—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having different architectures, e.g. having both top-gate and bottom-gate TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H10D86/423—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO

Definitions

  • the present invention relates to the field of display, in particular to a display device, and in particular to a thin film transistor array substrate of the display device.
  • Active-matrix organic light-emitting diodes Active-matrix organic light-emitting diodes
  • AMOLED Organic light emitting diode
  • Low temperature polysilicon (LTPS) thin film transistors are widely welcomed by the market due to their high resolution, high brightness and high aperture ratio.
  • LTPS low temperature polysilicon
  • the mobility of active layer polysilicon is too large, resulting in high leakage current.
  • the power consumption is large under low frequency driving.
  • the channel length in the driving thin film transistor must be made large, so that it is difficult to achieve high PPI (Pixels).
  • PPI Physical Inch
  • using low temperature polysilicon as the active layer still has the problem of high hysteresis, which is easy to cause the problem of image afterimage.
  • Metal oxides emerged as new semiconductor active layer materials. Its advantages are high carrier mobility, low cost, low energy consumption and less heat generation, but its disadvantages are poor TFT threshold voltage stability and oxides.
  • the active layer material is sensitive to the outside world.
  • semiconductor layers of different materials are arranged on the same substrate to form a thin film transistor array substrate and a display device, so that the obtained display device can have the respective advantages of the two thin film transistors.
  • It is a polysilicon material and a metal oxide material, and the display device thus prepared can have high brightness and high resolution while reducing driving power consumption.
  • the process is complicated, especially the manufacturing temperature of low temperature polysilicon components is about 600°C, which is difficult to combine with the metal oxide semiconductor process, and the manufacturing cost remains high.
  • the thickness is relatively large, and it is difficult to meet the current development trend of thinning and flexible bending.
  • the purpose of the present invention is to provide a thin film transistor array substrate and a display device, which can optimize the production process, reduce the manufacturing cost, and have a better thickness of the array substrate.
  • an embodiment of the present application provides a thin film transistor array substrate, including:
  • the intermediate insulating layer includes an oxide insulating layer.
  • the first semiconductor layer includes a polysilicon semiconductor material
  • the second semiconductor layer includes an oxide semiconductor material
  • the intermediate insulating layer is a single oxide insulating layer, and the thickness of the intermediate insulating layer is 1500-4500 ⁇ .
  • the hydrogen content in the second gate insulating layer is greater than or equal to 20%.
  • the intermediate insulating layer further includes a nitride insulating layer, wherein the nitride insulating layer is located under the oxide insulating layer, and the film thickness of the oxide insulating layer is Less than or equal to the film thickness of the nitride insulating layer.
  • the hydrogen content in the nitride insulating layer is greater than or equal to 10% and less than or equal to 15%, and the hydrogen content in the second gate insulating layer is greater than 15%.
  • the oxide insulating layer is a dense oxide film layer.
  • the deposition and etching ratio of the oxide insulating layer is higher than 3:1.
  • the thickness of the intermediate insulating layer is 2-3 times the thickness of the second gate insulating layer.
  • the height difference between the upper surface of the first semiconductor layer and the lower surface of the second semiconductor layer is 3500-7500 ⁇ .
  • an embodiment of the present application further provides a display device, the display device includes the thin film transistor array substrate, and the thin film transistor array substrate includes:
  • the intermediate insulating layer includes an oxide insulating layer.
  • the first semiconductor layer includes a polysilicon semiconductor material
  • the second semiconductor layer includes an oxide semiconductor material
  • the intermediate insulating layer is a single oxide insulating layer, and the thickness of the intermediate insulating layer is 1500-4500 ⁇ .
  • the hydrogen content in the second gate insulating layer is greater than or equal to 20%.
  • the intermediate insulating layer further includes a nitride insulating layer, wherein the nitride insulating layer is located under the oxide insulating layer, and the oxide insulating layer has a film thickness equal to or less than the film thickness of the nitride insulating layer.
  • the hydrogen content of the nitride insulating layer is greater than or equal to 10% and less than or equal to 15%, and the hydrogen content of the second gate insulating layer is greater than 15%.
  • the oxide insulating layer is a dense oxide film layer.
  • the deposition etching ratio of the oxide insulating layer is higher than 3:1.
  • the thickness of the intermediate insulating layer is 2-3 times the thickness of the second gate insulating layer.
  • the height difference between the upper surface of the first semiconductor layer and the lower surface of the second semiconductor layer is 3500-7500 ⁇ .
  • the low temperature polysilicon semiconductor is subjected to a hydrogenation process in advance, so as to avoid the high temperature treatment affecting the metal oxide semiconductor material, and at the same time, the film layer structure and the forming process of the thin film transistor array substrate are optimized, and the process time is shortened, and the process time is shortened.
  • the manufacturing cost is saved, the thickness of the film layer is reduced, and the flexible bending performance of the array substrate is improved.
  • FIG. 1 is a schematic structural diagram of a thin film transistor array substrate provided by an embodiment of the present invention
  • FIG. 2 is another schematic structural diagram of a thin film transistor array substrate provided by an embodiment of the present invention.
  • the present application provides a thin film transistor array substrate and a display device.
  • a thin film transistor array substrate and a display device.
  • the present application will be further described in detail below with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are only used to explain the present application, but not to limit the present application.
  • FIG. 1 is a schematic structural diagram of a first embodiment of a thin film transistor array substrate of the present invention.
  • the present invention provides a thin film transistor array substrate.
  • the thin film transistor array substrate includes: a substrate substrate 100 , which is disposed on the substrate substrate 100 The first semiconductor layer 101 on the top, the first gate insulating layer 102 covering the first semiconductor layer 101, the first gate insulating layer 102 disposed on the first gate insulating layer 102 and overlapping with the first semiconductor layer 101 The gate electrode 103, the second gate insulating layer 104 covering the first gate electrode 103, the conductive layer 105 and the second gate electrode 106 disposed on the second gate insulating layer 104 and arranged in the same layer , the intermediate insulating layer 107 covering the conductive layer 105 and the second gate electrode 106, the second semiconductor layer 108 disposed on the intermediate insulating layer 107, the second semiconductor layer 108 and the second The gate electrode 106 overlaps; the third gate insulating layer 109 covering the second semiconductor layer 108
  • the conductive layer 105 overlaps with the first gate electrode 103, and the conductive layer 105 and the first gate electrode below form 103 the upper and lower electrodes of the storage capacitor in the pixel circuit, and the second gate
  • the electrode 106 serves as the lower gate of the oxide thin film transistor, wherein the second gate electrode 106 does not overlap with the first gate electrode 103 .
  • the first semiconductor layer 101 and the second semiconductor layer 108 are semiconductor layers of different materials.
  • the first semiconductor layer 101 includes a polysilicon semiconductor material, such as low temperature polysilicon (LTPS).
  • Layer 108 includes an oxide semiconductor material, such as indium gallium zinc oxide (IGZO), in other embodiments, the metal oxide semiconductor layer may also be zinc oxide (ZnO), indium oxide (InO), gallium oxide (GaO) at least one of.
  • IGZO indium gallium zinc oxide
  • the metal oxide semiconductor layer may also be zinc oxide (ZnO), indium oxide (InO), gallium oxide (GaO) at least one of.
  • the first semiconductor layer and the second semiconductor layer respectively form the active layers of the first thin film transistor and the second thin film transistor
  • the thin film transistor array substrate further includes a fourth gate insulation disposed on the third gate electrode 110 layer 111, and a first source-drain and a second source-drain provided on the fourth gate insulating layer 111, the first source-drain is connected to the first semiconductor layer, and the second source The drain is connected to the second semiconductor layer.
  • the polysilicon active layer is often subjected to hydrogenation treatment.
  • the hydrogenation treatment is to use hydrogen ions to fill the unbonded bonds of polysilicon atoms to reduce dangling bonds, thereby improving the stability of P-Si. It improves electron mobility, conductivity and threshold voltage uniformity, while reducing leakage current (Ioff).
  • the hydrogenation treatment needs to be carried out under high temperature conditions, which will cause hydrogen ions (H+) to diffuse in all directions, which will cause free H+ to act on the active layer of the oxide thin film transistor, robbing the oxygen in the metal oxide, resulting in oxide A large number of oxygen vacancies appear, which makes the oxide semiconductor layer conductive, and further causes a short circuit of the source and drain of the oxide transistor.
  • H+ hydrogen ions
  • the hydrogenation of the polysilicon and the heat treatment of the oxide semiconductor layer are often carried out at the same time.
  • it In order to prevent the hydrogen ions from affecting the oxide semiconductor material during the high-temperature hydrogenation process, it needs to be located in the middle between the two semiconductor layers.
  • the insulating layer has good hydrogen resistance, so that the intermediate insulating layer often needs a sufficient thickness to achieve the above purpose, which results in a large thickness of the prepared array substrate, which cannot meet the requirements of flexible bending.
  • the high-temperature hydrogenation treatment of the polysilicon in the thin film transistor array substrate is advanced, that is, the first semiconductor layer 101 is subjected to the high-temperature hydrogenation treatment after the formation of the second gate insulating layer 104 . It can only migrate in the direction of the underlying polysilicon semiconductor material, and after complete hydrogenation, the subsequent fabrication of the conductive layer 104 , the second gate electrode 106 and the intermediate insulating layer 107 is performed. Since the hydrogenation treatment has been completed at this time, the hydrogen ions provided by the intermediate insulating layer for hydrogenation are not needed, so the intermediate insulating layer 107 can be a single oxide insulating layer, which can reduce the forming process of the film layer and simplify the process.
  • the thickness of the intermediate insulating layer is preferably 1500-4500 ⁇ , which can not only ensure a good hydrogen blocking effect, prevent the oxide semiconductor layer from being conductorized, but also take into account the flexible bending of the thin film transistor array substrate. Folding performance.
  • the intermediate insulating layer 107 is preferably an inorganic insulating layer of SiO x material, and its formation method includes chemical vapor deposition (CVD) fabrication, physical vapor deposition (PVD) fabrication, or spin coating.
  • CVD chemical vapor deposition
  • PVD physical vapor deposition
  • the hydrogen content of the first gate insulating layer 102 and the second gate insulating layer 104 can be adjusted to provide sufficient hydrogen ions to the first semiconductor layer 101 during the hydrogenation process.
  • the hydrogen content in the film layer can be adjusted by adjusting the process parameters, such as adjusting the film formation rate and gas ratio.
  • the content of SH and NH in the film can be measured by spectral analysis (FTIR) to test the H+ in each film layer. concentration.
  • the hydrogen content in the second gate insulating layer 104 is greater than or equal to 20%, and more preferably, the hydrogen content in the second gate insulating layer 104 is between 20% and 30% to ensure Sufficient hydrogen ions are provided during the hydrogenation process to achieve complete hydrogenation of polysilicon.
  • the hydrogenation treatment process may also be performed after the conductive layer 105 and the metal layer where the second gate electrode 106 is located are formed. At this time, the metal layer has not been etched and can completely cover the second gate electrode 106 . In the gate insulating layer 104, during the hydrogenation process, the metal layer can also block the upward migration of hydrogen ions, so as to improve the utilization rate of hydrogen ions and the effect of hydrogenation.
  • the metal layer is patterned to form a patterned conductive layer 105 and a second gate electrode 106.
  • the conductive layer 105 is the same layer as the second gate electrode 106 of the second thin film transistor.
  • the process flow is simplified, the production of one film layer is reduced, and the overall thickness of the array substrate is reduced.
  • the intermediate insulating layer remanufactured at this time does not need to participate in the hydrogenation treatment, it is beneficial to further optimize and reduce the thickness of the intermediate insulating layer 107 .
  • the process of simultaneously performing the hydrogenation treatment and the heat treatment of the oxide semiconductor can also be used.
  • the intermediate insulating layer needs to be improved. Referring to FIG. 2 , the intermediate insulating layer 107 includes an oxide insulating layer 107A and a nitride insulating layer 107B, and the nitride insulating layer 107B is located under the oxide insulating layer 107A.
  • the nitride insulating layer 107B in the intermediate insulating layer 107 is attached to the second gate insulating layer 104, wherein nitrogen element can inhibit the migration of hydrogen ions and prevent the hydrogen ions from moving to the oxide semiconductor.
  • nitrogen element can inhibit the migration of hydrogen ions and prevent the hydrogen ions from moving to the oxide semiconductor.
  • Directional diffusion improves the utilization rate of hydrogen ions, and at the same time, the nitride insulating layer 107B also contains hydrogen, which can also supplement the hydrogen ions during the hydrogenation process to ensure complete hydrogenation of polysilicon.
  • the oxide insulating layer 107A in the intermediate insulating layer 107 does not contain hydrogen ions, it can effectively block the migration of hydrogen ions, and can effectively avoid the influence of hydrogen ions on the oxide semiconductor material.
  • the process combination of the transistor and the oxide semiconductor thin film transistor is realized, and the yield of the product is improved.
  • the content of hydrogen ions in the nitride insulating layer 107B is further limited to be only slightly lower than the content of hydrogen ions in the second gate insulating layer 104, so that the nitride
  • the concentration difference of the hydrogen content in the insulating layer 107B and the adjacent second gate insulating layer 104 is much smaller than the concentration difference of the hydrogen content in the second gate insulating layer 104 and the first semiconductor layer 101, so hydrogen During diffusion, the ions will migrate to the direction of the first semiconductor layer 101 with a larger concentration difference, which is equivalent to forming a migration barrier switch in the nitride insulating layer, which can have a better effect of inhibiting migration.
  • the hydrogen content of the nitride insulating layer 107B is greater than or equal to 10% and less than or equal to 15%, and the hydrogen content of the second gate insulating layer 104 is greater than 15%. In this way, a sufficient supply of hydrogen ions can be ensured to achieve complete hydrogenation of polysilicon, and a better effect of inhibiting the migration of hydrogen ions to the second semiconductor layer 108 can be achieved.
  • the hydrogen blocking effect can also be improved by increasing the film density.
  • the oxide insulating layer 107A is a dense oxide film layer.
  • the oxide insulating layer of SiO x 107A preferably prepared by adjusting the deposition rate of the oxide insulating layer, a layer of a coupling agent or modifying heat treatment, etc., can be obtained at 200 °C -500 °C Dense oxide insulating layer with higher density.
  • the deposition and etching ratio of the oxide film is used to characterize the density of the oxide film layer, wherein a higher deposition and etching ratio means a higher film density.
  • the dense oxide film layer makes it have better hydrogen barrier properties.
  • the intermediate insulating layer 107 By improving the hydrogen barrier capability of the nitride insulating layer 107B or the oxide insulating layer 107A in the intermediate insulating layer 107, the intermediate insulating layer 107, especially the oxide insulating layer 107A, avoids using a larger thickness to obtain better performance.
  • a good hydrogen blocking effect makes reducing the thickness of the oxide insulating layer 107A a feasible and beneficial improvement direction.
  • the film thickness of the oxide insulating layer 107A is preferably less than or equal to the nitride.
  • the film thickness of the insulating layer 107B can not only shorten the time for film deposition or coating, improve the mass production efficiency, but also help to reduce the thickness of the thin film transistor array substrate.
  • the thicknesses of the first gate insulating layer 102 and the second gate insulating layer 104 are both 1000-1500 ⁇
  • the thickness of the intermediate insulating layer 107 is the thickness of the second gate insulating layer 2-3 times the thickness of 104, and further preferably, the thickness of the intermediate insulating layer 107 is 1500-4500 ⁇ .
  • the height difference between the upper surface of the first semiconductor layer and the lower surface of the second semiconductor layer in the thin film transistor array substrate is preferably 3500-7500 ⁇ , more preferably, the height difference between the upper surface of the first semiconductor layer and the lower surface of the second semiconductor layer is 4500-6500 ⁇ , so that both the functional characteristics and flexibility of the thin film transistor array substrate are taken into account, and the process is The process is also conducive to reducing costs and improving production efficiency.
  • An embodiment of the present invention further provides a display device, the display device includes the above-mentioned thin film transistor array substrate.

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  • General Physics & Mathematics (AREA)
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Abstract

一种薄膜晶体管阵列基板及显示装置，所述薄膜晶体管阵列基板包括两种不同的半导体材料形成的第一半导体层（101）和第二半导体层（108），与第一半导体层（101）重叠设置的第一栅极电极（103）和导电层（105），与第二半导体层（108）重叠设置的第二栅极电极（106）和第三栅极电极（110），以及设置在第二半导体层（108）与第二栅极电极（106）之间的中间绝缘层（107）。

Description

一种薄膜晶体管阵列基板及显示装置 技术领域
本发明涉及显示领域，尤其是涉及一种显示装置，具体涉及一种显示装置的薄膜晶体管阵列基板。
 背景技术
随着显示技术的发展和用户对显示设备的外观、性能等各方面的要求越来越高，有源矩阵有机发光二极体(Active-matrix organic light emitting diode，AMOLED)柔性显示器的应用越来越广泛，而随着显示器性能提升的同时，显示装置能否保持低消耗功率的特性愈发成为关注重点。
低温多晶硅(LTPS)薄膜晶体管以其高分辨率、高亮度、高开口率等优点广受市场欢迎，但低温多晶硅(LTPS)工艺中有源层多晶硅迁移率过大，导致漏电流较高，在低频驱动下功耗较大，为了更好的展开灰阶，必须将驱动薄膜晶体管中沟道长度做的很大，这样就难以实现高PPI(Pixels Per Inch)，同时以低温多晶硅作为有源层还存在迟滞较高，容易导致画面残像的问题。金属氧化物作为新的半导体有源层材料应运而生，其优点是载流子迁移率较高、成本较低、能耗低发热少，但其缺点是TFT阈值电压稳定性欠佳，氧化物有源层材料对外界比较敏感。
现有技术中已有在同一基板上布置不同材料的半导体层制成薄膜晶体管阵列基板和显示装置，以使制得的显示装置能够兼具两种薄膜晶体管各自的优点，例如两种半导体层分别为多晶硅材料和金属氧化物材料，如此制得的显示装置能够具备高亮度、高分辨率的同时降低驱动功耗。但是工艺制程复杂，特别是低温多晶硅元件的制作工艺温度约在600℃，与金属氧化物半导体工艺难以结合，制造成本居高不下，同时，由于同时存在两种不同的有源层，导致阵列基板的厚度较大，难以满足目前轻薄化、可柔性弯折的发展趋势。
 技术问题
本发明目的在于提供一种薄膜晶体管阵列基板及显示装置，以优化生产工艺、降低制造成本，并具有较优的阵列基板厚度。
 技术解决方案
第一方面，本申请实施例提供一种薄膜晶体管阵列基板，包括：
第一半导体层；覆盖所述第一半导体层的第一栅极绝缘层；设置在所述第一栅极绝缘层上并与所述第一半导体层重叠的第一栅极电极；覆盖所述第一栅极电极的第二栅极绝缘层；设置在所述第二栅极绝缘层上并同层布置的导电层和第二栅极电极；中间绝缘层，覆盖所述导电层和所述第二栅极电极；设置在所述中间绝缘层上的第二半导体层，所述第二半导体层与所述第二栅极电极重叠；覆盖所述第二半导体层的第三栅极绝缘层，设置在所述第三栅极绝缘层上并与所述第二半导体层重叠的第三栅极电极；其中，所述第一半导体层与所述第二半导体层为不同材料的半导体层，所述中间绝缘层包括氧化物绝缘层。
在所述薄膜晶体管阵列基板中，所述第一半导体层包括多晶硅半导体材料，所述第二半导体层包括氧化物半导体材料。
在所述薄膜晶体管阵列基板中，所述中间绝缘层为单一的氧化物绝缘层，所述中间绝缘层的厚度为1500-4500Å。
在所述薄膜晶体管阵列基板中，所述第二栅极绝缘层中氢含量大于或等于20%。
在所述薄膜晶体管阵列基板中，所述中间绝缘层还包括氮化物绝缘层，其中，所述氮化物绝缘层位于所述氧化物绝缘层下方，并且，所述氧化物绝缘层的膜层厚度小于或等于氮化物绝缘层的膜层厚度。
在所述薄膜晶体管阵列基板中，所述氮化物绝缘层中氢含量≥10%且≤15%，所述第二栅极绝缘层中氢含量大于15%。
在所述薄膜晶体管阵列基板中，所述氧化物绝缘层为致密氧化物膜层。
所述的薄膜晶体管阵列基板中，所述氧化物绝缘层的沉积蚀刻比高于3:1。
在所述薄膜晶体管阵列基板中，所述中间绝缘层的厚度为所述第二栅极绝缘层的厚度的2-3倍。
在所述薄膜晶体管阵列基板中，所述第一半导体层的上表面与所述第二半导体层的下表面之间的高度差为3500-7500Å。
第二方面，本申请实施例还提供一种显示装置，所述显示装置包括所述薄膜晶体管阵列基板，所述薄膜晶体管阵列基板包括：
第一半导体层；覆盖所述第一半导体层的第一栅极绝缘层；设置在所述第一栅极绝缘层上并与所述第一半导体层重叠的第一栅极电极；覆盖所述第一栅极电极的第二栅极绝缘层；设置在所述第二栅极绝缘层上并同层布置的导电层和第二栅极电极；中间绝缘层，覆盖所述导电层和所述第二栅极电极；设置在所述中间绝缘层上的第二半导体层，所述第二半导体层与所述第二栅极电极重叠；覆盖所述第二半导体层的第三栅极绝缘层，设置在所述第三栅极绝缘层上并与所述第二半导体层重叠的第三栅极电极；其中，所述第一半导体层与所述第二半导体层为不同材料的半导体层，所述中间绝缘层包括氧化物绝缘层。
在所述显示装置中，所述第一半导体层包括多晶硅半导体材料，所述第二半导体层包括氧化物半导体材料。
在所述显示装置中，所述中间绝缘层为单一的氧化物绝缘层，所述中间绝缘层的厚度为1500-4500Å。
在所述显示装置中，所述第二栅极绝缘层中氢含量大于或等于20%。
在所述显示装置中，所述中间绝缘层还包括氮化物绝缘层，其中，所述氮化物绝缘层位于所述氧化物绝缘层下方，并且，所述氧化物绝缘层的膜层厚度等于或小于氮化物绝缘层的膜层厚度。
在所述显示装置中，所述氮化物绝缘层中氢含量≥10%且≤15%，所述第二栅极绝缘层中氢含量大于15%。
在所述显示装置中，所述氧化物绝缘层为致密氧化物膜层。
在所述显示装置中，所述氧化物绝缘层的沉积蚀刻比高于3:1。
在所述显示装置中，所述中间绝缘层的厚度为所述第二栅极绝缘层的厚度的2-3倍。
在所述显示装置中，所述第一半导体层的上表面与所述第二半导体层的下表面之间的高度差为3500-7500Å。
 有益效果
相较于现有技术，本发明通过对低温多晶硅半导体提前进行氢化工艺处理，避免高温处理影响金属氧化物半导体材料，同时对薄膜晶体管阵列基板的膜层结构和成型工艺进行优化，制程时间缩短、节约了制造成本，并降低了膜层厚度，提高阵列基板的柔性弯折性能。
 附图说明
图1为本发明实施例提供的薄膜晶体管阵列基板的结构示意图；
图2为本发明实施例提供的薄膜晶体管阵列基板的又一结构示意图。
 本发明的实施方式
本申请提供一种薄膜晶体管阵列基板及显示装置，为使本申请的目的、技术方案及效果更加清楚、明确，以下参照附图并举实施例对本申请进一步详细说明。应当理解，此处所描述的具体实施例仅用以解释本申请，并不用于限定本申请。
请参阅图1，为本发明薄膜晶体管阵列基板的第一实施例的结构示意图，本发明提供一种薄膜晶体管阵列基板，所述薄膜晶体管阵列基板包括：基板衬底100，设在基板衬底100上的第一半导体层101，覆盖所述第一半导体层101的第一栅极绝缘层102，设置在所述第一栅极绝缘层102上并与所述第一半导体层101重叠的第一栅极电极103，覆盖所述第一栅极电极103的第二栅极绝缘层104，设置在所述第二栅极绝缘层104上并同层布置的导电层105和第二栅极电极106，覆盖所述导电层105和所述第二栅极电极106的中间绝缘层107，设置在所述中间绝缘层107上的第二半导体层108，所述第二半导体层108与所述第二栅极电极106重叠；覆盖所述第二半导体层108的第三栅极绝缘层109，设置在所述第三栅极绝缘层109上并与所述第二半导体108层重叠的第三栅极电极110。所述导电层105与所述第一栅极电极103重叠，所述导电层105与下方的所述第一栅极电极形成103构成像素电路中存储电容的上、下电极，所述第二栅极电极106作为氧化物薄膜晶体管的下栅极，其中，第二栅极电极106与第一栅极电极103不重叠。
所述第一半导体层101与所述第二半导体层108为不同材料的半导体层，本实施例优选所述第一半导体层101包括多晶硅半导体材料，例如低温多晶硅(LTPS)，所述第二半导体层108包括氧化物半导体材料，例如氧化铟镓锌(IGZO)，在其他实施方式中，该金属氧化物半导体层也可以为氧化锌(ZnO)，氧化铟(InO)，氧化镓(GaO)中的至少一种。所述第一半导体层和所述第二半导体层分别形成第一薄膜晶体管和第二薄膜晶体管的有源层，薄膜晶体管阵列基板还包括设置在第三栅极电极110上的第四栅极绝缘层111、以及设置在所述第四栅极绝缘层111上的第一源漏极和第二源漏极，所述第一源漏极与所述第一半导体层连接，所述第二源漏极与所述第二半导体层连接。
由于多晶硅晶粒间存在粒界态，多晶硅与栅极绝缘层间存在界面态，影响多晶硅薄膜晶体管的电性。因此在低温多晶硅薄膜晶体管的制造工艺中，往往采用对多晶硅有源层进行氢化处理，所述氢化处理就是利用氢离子填补多晶硅原子的未结合键、来减少悬挂键，从而提高P-Si的稳定性，提升电子迁移率、导电特性及阈值电压均匀性，同时降低漏电流(Ioff)。但氢化处理需要在高温条件下进行，这会导致氢离子(H+)向各个方向扩散，会导致游离的H+作用在氧化物薄膜晶体管的有源层，抢夺金属氧化物中的氧，导致氧化物出现大量的氧缺陷，使得氧化物半导体层导体化，进而造成氧化物晶体管源漏极的短路。
现有技术中为了节约工序，往往会将多晶硅的氢化与氧化物半导体层的热处理同时进行，为避免高温氢化过程中氢离子影响到氧化物半导体材料，就需要位于两种半导体层之间的中间绝缘层具有较好的阻氢能力，使得所述中间绝缘层往往需要足够的厚度来达到上述目的，这就导致制得的阵列基板的厚度较大，无法满足柔性弯折的要求。
本发明实施例中，将薄膜晶体管阵列基板中多晶硅的高温氢化处理提前，即在所述第二栅极绝缘层104形成后即对所述第一半导体层101进行高温氢化处理，此时氢离子仅能向下方的多晶硅半导体材料的方向迁移，待完全氢化后，再进行后续的导电层104和第二栅极电极106以及中间绝缘层107的制作。由于此时氢化处理已经完成，无需所述中间绝缘层为氢化补充提供的氢离子，故所述中间绝缘层107可以为单一的氧化物绝缘层，这样能够减少膜层的成型工序，简化工艺制程，降低制造成本，并且由于中间绝缘层107不用参与高温氢化过程，对其阻氢的要求也会降低，使得单一的氧化物绝缘层膜层厚度具有进一步优化的空间，更有利于实现柔性弯折，具体地，所述中间绝缘层的厚度优选为1500-4500Å，此厚度范围既能够保证较好的阻氢效果，防止氧化物半导体层被导体化，同时又能兼顾薄膜晶体管阵列基板的柔性弯折性能。
所述中间绝缘层107优选SiO x材料的无机绝缘层，其形成方法包括进行化学气相沉积(CVD)制作工艺、物理气相沉积(PVD)制作工艺或旋转涂布法(spin coating)等等。
为了保证氢化充分，可通过调整所述第一栅极绝缘层102和所述第二栅极绝缘层104的氢含量，以在氢化过程中向所述第一半导体层101提供足够的氢离子。膜层中氢含量可以通过调整制程参数，例如调整成膜速率以及气体比例的方式进行调节，成膜后可以通过光谱分析(FTIR)测试薄膜中S-H和N-H的含量的方法测试各膜层中H+浓度。在本实施例中，优选所述第二栅极绝缘层104中氢含量大于或等于20%，更优选所述第二栅极绝缘层104中氢含量在20% - 30%之间，以保证氢化过程中提供足够的氢离子，实现多晶硅的完全氢化。
在另一些实施例中，所述氢化处理工艺还可以在导电层105和第二栅极电极106所在的金属层形成后进行，此时所述金属层尚未进行蚀刻，能够完全覆盖所述第二栅极绝缘层104，在氢化处理时，所述金属层也能够阻挡氢离子向上迁移，提高氢离子利用率和氢化效果。在氢化完成后再对所述金属层进行图案化，形成图案化的导电层105和第二栅极电极106，所述导电层105与第二薄膜晶体管的所述第二栅极电极106同层设置，这样既简化了工艺流程，减少了一道膜层制作，也有利于阵列基板整体厚度的减薄。同样，此时再制作的所述中间绝缘层由于不用参与氢化处理，有利于所述中间绝缘层107厚度的进一步优化减薄。
在另一些实施例中，为了缩短热处理的时间，也可沿用将氢化处理与氧化物半导体的热处理同时进行的工艺制程，此时为了实现优化膜层厚度，需要对所述中间绝缘层进行改进。请参阅图2所示，所述中间绝缘层107包括氧化物绝缘层107A和氮化物绝缘层107B，所述氮化物绝缘层107B位于所述氧化物绝缘层107A下方。
在对多晶硅半导体层氢化过程中，影响氢离子迁移的因素主要有两方面：第一，是否有阻隔氢扩散的物质影响H的正常扩散；第二，氢离子的扩散会从高浓度向低浓度扩散。由此，本实施例中所述中间绝缘层107中的氮化物绝缘层107B贴合所述第二栅极绝缘层104，其中氮元素能够抑制氢离子的迁移，并避免氢离子向氧化物半导体方向扩散，提高氢离子的利用率，同时氮化物绝缘层107B中同样含有氢，在氢化处理过程中，也能够起到补足氢离子的作用，保证多晶硅的完全氢化。所述中间绝缘层107中的氧化物绝缘层107A中由于不含氢离子，对氢离子的迁移能够起到较好的阻隔作用，能有效避免氢离子对氧化物半导体材料的影响，使得多晶硅薄膜晶体管与氧化物半导体薄膜晶体管的工艺结合得到实现，提高产品的良率。
为控制氢离子的迁移方向，在本实施例中，进一步限定所述氮化物绝缘层107B中氢离子含量仅仅稍低于所述第二栅极绝缘层104中氢离子含量，使得所述氮化物绝缘层107B与相邻的第二栅极绝缘层104中的氢含量的浓度差远小于所述第二栅极绝缘层104与所述第一半导体层101中的氢含量的浓度差，故而氢离子在扩散时会向浓度差较大的所述第一半导体层101的方向迁移，这相当于在氮化物绝缘层中形成了一个迁移阻挡开关，能够起到较好的抑制迁移效果。本实施例中优选所述氮化物绝缘层107B中氢含量≥10%且≤15%，所述第二栅极绝缘层104中氢含量大于15%。这样既能够保证足够的氢离子供应实现多晶硅的完全氢化，又能够实现较好的抑制氢离子向所述第二半导体层108迁移的作用。
另外，通过提高膜层密度也可提高其阻氢效果，在另一些实施例中，所述氧化物绝缘层107A为致密氧化物膜层。具体的，所述氧化物绝缘层107A优选由SiO x制备，通过调节氧化物绝缘层的堆积速度、采用偶联剂改性或在200℃-500℃条件下对膜层热处理等方式，能够得到密度更高的致密氧化物绝缘层。
通常采用氧化物膜的沉积蚀刻比来表征氧化物膜层的密度，其中沉积蚀刻比越高意味着膜层密度越高，本实施例优选沉积蚀刻比高于3:1的氧化物膜层作为致密氧化物膜层，使其具备更优的阻氢性能。
上述通过提高中间绝缘层107中氮化物绝缘层107B或氧化物绝缘层107A的阻氢能力，使得所述中间绝缘层107，特别是所述氧化物绝缘层107A避免采用较大的厚度来获取更好的阻氢效果，进而使得降低所述氧化物绝缘层107A膜层的厚度成为可行且有益的改进方向，本实施例优选所述氧化物绝缘层107A的膜层厚度小于或等于所述氮化物绝缘层107B的膜层厚度，这样既能够缩短膜层沉积或涂布的时间，提高量产效率，同时有利于降低薄膜晶体管阵列基板的厚度。
在一些实施例中，所述第一栅极绝缘层102和所述第二栅极绝缘层104的厚度均为1000-1500Å，所述中间绝缘层107的厚度为所述第二栅极绝缘层104的厚度的2-3倍，进一步优选所述中间绝缘层107的厚度为1500-4500Å为佳。另一方面，通过对阵列基板的膜层结构及制造工艺进行优化，所述薄膜晶体管阵列基板中所述第一半导体层上表面与所述第二半导体层的下表面之间的高度差优选为3500-7500Å，更优选所述第一半导体层上表面与所述第二半导体层的下表面之间的高度差为4500-6500Å，如此既兼顾了薄膜晶体管阵列基板的功能特性和柔性，在工艺制程上也有利于降低成本、提高生产效率。
本发明实施例还提供一种显示装置，所述显示装置包括上述薄膜晶体管阵列基板。
可以理解的是，对本领域普通技术人员来说，可以根据本申请的技术方案及其发明构思加以等同替换或改变，而所有这些改变或替换都应属于本申请所附的权利要求的保护范围。

Claims (20)

  1. 一种薄膜晶体管阵列基板，包括：
    第一半导体层；
    覆盖所述第一半导体层的第一栅极绝缘层；
    设置在所述第一栅极绝缘层上并与所述第一半导体层重叠的第一栅极电极；
    覆盖所述第一栅极电极的第二栅极绝缘层；
    设置在所述第二栅极绝缘层上并同层布置的导电层和第二栅极电极；
    中间绝缘层，覆盖所述导电层和所述第二栅极电极；
    设置在所述中间绝缘层上的第二半导体层，所述第二半导体层与所述第二栅极电极重叠；
    覆盖所述第二半导体层的第三栅极绝缘层，
    设置在所述第三栅极绝缘层上并与所述第二半导体层重叠的第三栅极电极；
    其中，所述第一半导体层与所述第二半导体层为不同材料的半导体层，所述中间绝缘层包括氧化物绝缘层。
  2. 如权利要求1所述的薄膜晶体管阵列基板，所述第一半导体层包括多晶硅半导体材料，所述第二半导体层包括氧化物半导体材料。
  3. 如权利要求2所述的薄膜晶体管阵列基板，所述中间绝缘层为单一的氧化物绝缘层，所述中间绝缘层的厚度为1500-4500Å。
  4. 如权利要求3所述的薄膜晶体管阵列基板，所述第二栅极绝缘层中氢含量大于或等于20%。
  5. 如权利要求2所述的薄膜晶体管阵列基板，所述中间绝缘层还包括氮化物绝缘层，其中，所述氮化物绝缘层位于所述氧化物绝缘层下方，并且，所述氧化物绝缘层的膜层厚度等于或小于氮化物绝缘层的膜层厚度。
  6. 如权利要求5所述的薄膜晶体管阵列基板，所述氮化物绝缘层中氢含量≥10%且≤15%，所述第二栅极绝缘层中氢含量大于15%。
  7. 如权利要求1所述的薄膜晶体管阵列基板，所述氧化物绝缘层为致密氧化物膜层。
  8. 如权利要求1所述的薄膜晶体管阵列基板，所述氧化物绝缘层的沉积蚀刻比高于3:1。
  9. 如权利要求1所述的薄膜晶体管阵列基板，所述中间绝缘层的厚度为所述第二栅极绝缘层的厚度的2-3倍。
  10. 如权利要求1所述的薄膜晶体管阵列基板，所述第一半导体层的上表面与所述第二半导体层的下表面之间的高度差为3500-7500Å。
  11. 一种显示装置，所述显示装置包括薄膜晶体管阵列基板，所述薄膜晶体管阵列基板包括：
    第一半导体层；
    覆盖所述第一半导体层的第一栅极绝缘层；
    设置在所述第一栅极绝缘层上并与所述第一半导体层重叠的第一栅极电极；
    覆盖所述第一栅极电极的第二栅极绝缘层；
    设置在所述第二栅极绝缘层上并同层布置的导电层和第二栅极电极；
    中间绝缘层，覆盖所述导电层和所述第二栅极电极；
    设置在所述中间绝缘层上的第二半导体层，所述第二半导体层与所述第二栅极电极重叠；
    覆盖所述第二半导体层的第三栅极绝缘层，
    设置在所述第三栅极绝缘层上并与所述第二半导体层重叠的第三栅极电极；
    其中，所述第一半导体层与所述第二半导体层为不同材料的半导体层，所述中间绝缘层包括氧化物绝缘层。
  12. 如权利要求11所述的显示装置，所述第一半导体层包括多晶硅半导体材料，所述第二半导体层包括氧化物半导体材料。
  13. 如权利要求12所述的显示装置，所述中间绝缘层为单一的氧化物绝缘层，所述中间绝缘层的厚度为1500-4500Å。
  14. 如权利要求13所述的显示装置，所述第二栅极绝缘层中氢含量大于或等于20%。
  15. 如权利要求12所述的显示装置，所述中间绝缘层还包括氮化物绝缘层，其中，所述氮化物绝缘层位于所述氧化物绝缘层下方，并且，所述氧化物绝缘层的膜层厚度等于或小于氮化物绝缘层的膜层厚度。
  16. 如权利要求15所述的显示装置，所述氮化物绝缘层中氢含量≥10%且≤15%，所述第二栅极绝缘层中氢含量大于15%。
  17. 如权利要求11所述的显示装置，所述氧化物绝缘层为致密氧化物膜层。
  18. 如权利要求17所述的显示装置，所述氧化物绝缘层的沉积蚀刻比高于3:1。
  19. 如权利要求11所述的显示装置，所述中间绝缘层的厚度为所述第二栅极绝缘层的厚度的2-3倍。
  20. 如权利要求11所述的显示装置，所述第一半导体层的上表面与所述第二半导体层的下表面之间的高度差为3500-7500Å。
PCT/CN2020/130984 2020-07-17 2020-11-24 一种薄膜晶体管阵列基板及显示装置 Ceased WO2022011921A1 (zh)

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