CN111785740A - 一种薄膜晶体管阵列基板及显示装置 - Google Patents
一种薄膜晶体管阵列基板及显示装置 Download PDFInfo
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Abstract
本发明公开了一种薄膜晶体管阵列基板及显示装置,所述薄膜晶体管阵列基板包括两种不同的半导体材料形成的第一半导体层和第二半导体层,与第一半导体层重叠设置的第一栅极电极和导电性层,与第二半导体层重叠设置的第二栅极电极和第三栅极电极,以及设置在第二半导体层与第二栅极电极之间的中间绝缘层。通过对薄膜晶体管阵列基板的膜层结构和成型工艺进行优化,使得制程时间缩短,节约了制造成本,并降低了膜层厚度,提高阵列基板的柔性弯折性能。
Description
技术领域
本发明涉及显示技术领域,尤其涉及显示装置,具体涉及一种显示装置的薄膜晶体管阵列基板。
背景技术
随着显示技术的发展和用户对显示设备的外观、性能等各方面的要求越来越高,有源矩阵有机发光二极体(Active-matrix organic light emitting diode,AMOLED)柔性显示器的应用越来越广泛,而随着显示器性能提升的同时,显示装置能否保持低消耗功率的特性愈发成为关注重点。
低温多晶硅(LTPS)薄膜晶体管以其高分辨率、高亮度、高开口率等优点广受市场欢迎,但低温多晶硅(LTPS)工艺中有源层多晶硅迁移率过大,导致漏电流较高,在低频驱动下功耗较大,为了更好的展开灰阶,必须将驱动薄膜晶体管中沟道长度做的很大,这样就难以实现高PPI(Pixels Per Inch),同时以低温多晶硅作为有源层还存在迟滞较高,容易导致画面残像的问题。金属氧化物作为新的半导体有源层材料应运而生,其优点是载流子迁移率较高、成本较低、能耗低发热少,但其缺点是TFT阈值电压稳定性欠佳,氧化物有源层材料对外界比较敏感。
现有技术中已有在同一基板上布置不同材料的半导体层制成薄膜晶体管阵列基板和显示装置,以使制得的显示装置能够兼具两种薄膜晶体管各自的优点,例如两种半导体层分别为多晶硅材料和金属氧化物材料,如此制得的显示装置能够具备高亮度、高分辨率的同时降低驱动功耗。但是工艺制程复杂,特别是低温多晶硅元件的制作工艺温度约在600℃,与金属氧化物半导体工艺难以结合,制造成本居高不下,同时,由于同时存在两种不同的有源层,导致阵列基板的厚度较大,难以满足目前轻薄化、可柔性弯折的发展趋势。
因此,现有技术存在缺陷,亟需解决。
发明内容
本发明目的在于提供一种薄膜晶体管阵列基板及显示装置,以优化生产工艺、降低制造成本,并具有较优的阵列基板厚度。
为实现上述目的,本发明提供一种薄膜晶体管阵列基板,包括:
第一半导体层;
覆盖所述第一半导体层的第一栅极绝缘层;
设置在所述第一栅极绝缘层上并与所述第一半导体层重叠的第一栅极电极;
覆盖所述第一栅极电极的第二栅极绝缘层;
设置在所述第二栅极绝缘层上并同层布置的导电层和第二栅极电极;
中间绝缘层,覆盖所述导电层和所述第二栅极电极;
设置在所述中间绝缘层上的第二半导体层,所述第二半导体层与所述第二栅极电极重叠;
覆盖所述第二半导体层的第三栅极绝缘层,
设置在所述第三栅极绝缘层上并与所述第二半导体层重叠的第三栅极电极;
其中,所述第一半导体层与所述第二半导体层为不同材料的半导体层,所述中间绝缘层包括氧化物绝缘层。
特别地,所述第一半导体层包括多晶硅半导体材料,所述第二半导体层包括氧化物半导体材料。
特别地,所述中间绝缘层为单一的氧化物绝缘层,所述中间绝缘层的厚度为1500-4500A。
特别地,所述第二栅极绝缘层中氢含量大于或等于20%。
特别地,所述中间绝缘层还包括氮化物绝缘层,其中,所述氮化物绝缘层位于所述氧化物绝缘层下方,并且,所述氧化物绝缘层的膜层厚度等于或小于氮化物绝缘层的膜层厚度。
特别地,所述氮化物绝缘层中氢含量≥10%且≤15%,所述第二栅极绝缘层中氢含量大于15%。
特别地,所述氧化物绝缘层为致密氧化物膜层。
特别地,所述中间绝缘层的厚度为所述第二栅极绝缘层的厚度的2-3倍。
特别地,所述第一半导体层的上表面与所述第二半导体层的下表面之间的高度差为3500-7500A。
本发明还提供一种显示装置,所述显示装置包括薄膜晶体管阵列基板,所述薄膜晶体管阵列基板为上述任一项所述的薄膜晶体管阵列基板。
本发明的有益效果:本发明通过对低温多晶硅半导体提前进行氢化工艺处理,避免高温处理影响金属氧化物半导体材料,同时对薄膜晶体管阵列基板的膜层结构和成型工艺进行优化,制程时间缩短、节约了制造成本,并降低了膜层厚度,提高阵列基板的柔性弯折性能。
附图说明
为了更清楚地说明本发明实施例中的技术方案,下面将对实施例描述中所需要使用的附图作简单地介绍,显而易见地,下面描述中的附图仅仅是本发明的一些实施例,对于本领域技术人员来讲,在不付出创造性劳动的前提下,还可以根据这些附图获得其他的附图。
图1为本发明实施例提供的薄膜晶体管阵列基板的结构示意图。
图2为本发明实施例提供的薄膜晶体管阵列基板的又一结构示意图。
具体实施方式
下面将结合本发明实施例中的附图,对本发明实施例中的技术方案进行清楚、完整地描述。显然,所描述的实施例仅仅是本发明一部分实施例,而不是全部的实施例。基于本发明中的实施例,本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例,都属于本发明保护的范围。
在本发明的描述中,需要理解的是,术语“中心”、“纵向”、“横向”、“长度”、“宽度”、“厚度”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”、“顺时针”、“逆时针”等指示的方位或位置关系为基于附图所示的方位或位置关系,仅是为了便于描述本发明和简化描述,而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作,因此不能理解为对本发明的限制。此外,术语“第一”、“第二”仅用于描述目的,而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此,限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个所述特征。在本发明的描述中,“多个”的含义是两个或两个以上,除非另有明确具体的限定。
在本发明的描述中,需要说明的是,除非另有明确的规定和限定,术语“安装”、“相连”、“连接”应做广义理解,例如,可以是固定连接,也可以是可拆卸连接,或一体地连接;可以是机械连接,也可以是电连接或可以相互通讯;可以是直接相连,也可以通过中间媒介间接相连,可以是两个元件内部的连通或两个元件的相互作用关系。对于本领域的普通技术人员而言,可以根据具体情况理解上述术语在本发明中的具体含义。
在本发明中,除非另有明确的规定和限定,第一特征在第二特征之“上”或之“下”可以包括第一和第二特征直接接触,也可以包括第一和第二特征不是直接接触而是通过它们之间的另外的特征接触。而且,第一特征在第二特征“之上”、“上方”和“上面”包括第一特征在第二特征正上方和斜上方,或仅仅表示第一特征水平高度高于第二特征。第一特征在第二特征“之下”、“下方”和“下面”包括第一特征在第二特征正下方和斜下方,或仅仅表示第一特征水平高度小于第二特征。
下文的公开提供了许多不同的实施方式或例子用来实现本发明的不同结构。为了简化本发明的公开,下文中对特定例子的部件和设置进行描述。当然,它们仅仅为示例,并且目的不在于限制本发明。此外,本发明可以在不同例子中重复参考数字和/或参考字母,这种重复是为了简化和清楚的目的,其本身不指示所讨论各种实施方式和/或设置之间的关系。此外,本发明提供了的各种特定的工艺和材料的例子,但是本领域普通技术人员可以意识到其他工艺的应用和/或其他材料的使用。
请参阅图1,为本发明薄膜晶体管阵列基板的第一实施例的结构示意图,本发明提供一种薄膜晶体管阵列基板,所述薄膜晶体管阵列基板包括:基板衬底100,设在基板衬底100上的第一半导体层101,覆盖所述第一半导体层101的第一栅极绝缘层102,设置在所述第一栅极绝缘层102上并与所述第一半导体层101重叠的第一栅极电极103,覆盖所述第一栅极电极103的第二栅极绝缘层104,设置在所述第二栅极绝缘层104上并同层布置的导电层105和第二栅极电极106,覆盖所述导电层105和所述第二栅极电极106的中间绝缘层107,设置在所述中间绝缘层107上的第二半导体层108,所述第二半导体层108与所述第二栅极电极106重叠;覆盖所述第二半导体层108的第三栅极绝缘层109,设置在所述第三栅极绝缘层109上并与所述第二半导体108层重叠的第三栅极电极110。所述导电层105与所述第一栅极电极103重叠,所述导电层105与下方的所述第一栅极电极形成103构成像素电路中存储电容的上、下电极,所述第二栅极电极106作为氧化物薄膜晶体管的下栅极,其中,第二栅极电极106与第一栅极电极103不重叠。
所述第一半导体层101与所述第二半导体层108为不同材料的半导体层,本实施例优选所述第一半导体层101包括多晶硅半导体材料,例如低温多晶硅(LTPS),所述第二半导体层108包括氧化物半导体材料,例如氧化铟镓锌(IGZO),在其他实施方式中,该金属氧化物半导体层也可以为氧化锌(ZnO),氧化铟(InO),氧化镓(GaO)中的至少一种。所述第一半导体层和所述第二半导体层分别形成第一薄膜晶体管和第二薄膜晶体管的有源层,薄膜晶体管阵列基板还包括设置在第三栅极电极110上的第四栅极绝缘层111、以及设置在所述第四栅极绝缘层111上的第一源漏极和第二源漏极,所述第一源漏极与所述第一半导体层连接,所述第二源漏极与所述第二半导体层连接。
由于多晶硅晶粒间存在粒界态,多晶硅与栅极绝缘层间存在界面态,影响多晶硅薄膜晶体管的电性。因此在低温多晶硅薄膜晶体管的制造工艺中,往往采用对多晶硅有源层进行氢化处理,所述氢化处理就是利用氢离子填补多晶硅原子的未结合键、来减少悬挂键,从而提高P-Si的稳定性,提升电子迁移率、导电特性及阈值电压均匀性,同时降低漏电流(Ioff)。但氢化处理需要在高温条件下进行,这会导致氢离子(H+)向各个方向扩散,会导致游离的H+作用在氧化物薄膜晶体管的有源层,抢夺金属氧化物中的氧,导致氧化物出现大量的氧缺陷,使得氧化物半导体层导体化,进而造成氧化物晶体管源漏极的短路。
现有技术中为了节约工序,往往会将多晶硅的氢化与氧化物半导体层的热处理同时进行,为避免高温氢化过程中氢离子影响到氧化物半导体材料,就需要位于两种半导体层之间的中间绝缘层具有较好的阻氢能力,使得所述中间绝缘层往往需要足够的厚度来达到上述目的,这就导致制得的阵列基板的厚度较大,无法满足柔性弯折的要求。
本发明实施例中,将薄膜晶体管阵列基板中多晶硅的高温氢化处理提前,即在所述第二栅极绝缘层104形成后即对所述第一半导体层101进行高温氢化处理,此时氢离子仅能向下方的多晶硅半导体材料的方向迁移,待完全氢化后,再进行后续的导电层104和第二栅极电极106以及中间绝缘层107的制作。由于此时氢化处理已经完成,无需所述中间绝缘层为氢化补充提供的氢离子,故所述中间绝缘层107可以为单一的氧化物绝缘层,这样能够减少膜层的成型工序,简化工艺制程,降低制造成本,并且由于中间绝缘层107不用参与高温氢化过程,对其阻氢的要求也会降低,使得单一的氧化物绝缘层膜层厚度具有进一步优化的空间,更有利于实现柔性弯折,具体地,所述中间绝缘层的厚度优选为1500-4500A,此厚度范围既能够保证较好的阻氢效果,防止氧化物半导体层被导体化,同时又能兼顾薄膜晶体管阵列基板的柔性弯折性能。
所述中间绝缘层107优选SiOx材料的无机绝缘层,其形成方法包括进行化学气相沉积(CVD)制作工艺、物理气相沉积(PVD)制作工艺或旋转涂布法(spin coating)等等。
为了保证氢化充分,可通过调整所述第一栅极绝缘层102和所述第二栅极绝缘层104的氢含量,以在氢化过程中向所述第一半导体层101提供足够的氢离子。膜层中氢含量可以通过调整制程参数,例如调整成膜速率以及气体比例的方式进行调节,成膜后可以通过光谱分析(FTIR)测试薄膜中S-H和N-H的含量的方法测试各膜层中H+浓度。在本实施例中,优选所述第二栅极绝缘层104中氢含量大于或等于20%,更优选所述第二栅极绝缘层104中氢含量在20%-30%之间,以保证氢化过程中提供足够的氢离子,实现多晶硅的完全氢化。
在另一些实施例中,所述氢化处理工艺还可以在导电层105和第二栅极电极106所在的金属层形成后进行,此时所述金属层尚未进行蚀刻,能够完全覆盖所述第二栅极绝缘层104,在氢化处理时,所述金属层也能够阻挡氢离子向上迁移,提高氢离子利用率和氢化效果。在氢化完成后再对所述金属层进行图案化,形成图案化的导电层105和第二栅极电极106,所述导电层105与第二薄膜晶体管的所述第二栅极电极106同层设置,这样既简化了工艺流程,减少了一道膜层制作,也有利于阵列基板整体厚度的减薄。同样,此时再制作的所述中间绝缘层由于不用参与氢化处理,有利于所述中间绝缘层107厚度的进一步优化减薄。
在另一些实施例中,为了缩短热处理的时间,也可沿用将氢化处理与氧化物半导体的热处理同时进行的工艺制程,此时为了实现优化膜层厚度,需要对所述中间绝缘层进行改进。请参阅图2所示,所述中间绝缘层107包括氧化物绝缘层107A和氮化物绝缘层107B,所述氮化物绝缘层107B位于所述氧化物绝缘层107A下方。
在对多晶硅半导体层氢化过程中,影响氢离子迁移的因素主要有两方面:第一,是否有阻隔氢扩散的物质影响H的正常扩散;第二,氢离子的扩散会从高浓度向低浓度扩散。由此,本实施例中所述中间绝缘层107中的氮化物绝缘层107B贴合所述第二栅极绝缘层104,其中氮元素能够抑制氢离子的迁移,并避免氢离子向氧化物半导体方向扩散,提高氢离子的利用率,同时氮化物绝缘层107B中同样含有氢,在氢化处理过程中,也能够起到补足氢离子的作用,保证多晶硅的完全氢化。所述中间绝缘层107中的氧化物绝缘层107A中由于不含氢离子,对氢离子的迁移能够起到较好的阻隔作用,能有效避免氢离子对氧化物半导体材料的影响,使得多晶硅薄膜晶体管与氧化物半导体薄膜晶体管的工艺结合得到实现,提高产品的良率。
为控制氢离子的迁移方向,在本实施例中,进一步限定所述氮化物绝缘层107B中氢离子含量仅仅稍低于所述第二栅极绝缘层104中氢离子含量,使得所述氮化物绝缘层107B与相邻的第二栅极绝缘层104中的氢含量的浓度差远小于所述第二栅极绝缘层104与所述第一半导体层101中的氢含量的浓度差,故而氢离子在扩散时会向浓度差较大的所述第一半导体层101的方向迁移,这相当于在氮化物绝缘层中形成了一个迁移阻挡开关,能够起到较好的抑制迁移效果。本实施例中优选所述氮化物绝缘层107B中氢含量≥10%且≤15%,所述第二栅极绝缘层104中氢含量大于15%。这样既能够保证足够的氢离子供应实现多晶硅的完全氢化,又能够实现较好的抑制氢离子向所述第二半导体层108迁移的作用。
另外,通过提高膜层密度也可提高其阻氢效果,在另一些实施例中,所述氧化物绝缘层107A为致密氧化物膜层。具体的,所述氧化物绝缘层107A优选由SiOx制备,通过调节氧化物绝缘层的堆积速度、采用偶联剂改性或在200℃-500℃条件下对膜层热处理等方式,能够得到密度更高的致密氧化物绝缘层。
通常采用氧化物膜的沉积蚀刻比来表征氧化物膜层的密度,其中沉积蚀刻比越高意味着膜层密度越高,本实施例优选沉积蚀刻比高于3:1的氧化物膜层作为致密氧化物膜层,使其具备更优的阻氢性能。
上述通过提高中间绝缘层107中氮化物绝缘层107B或氧化物绝缘层107A的阻氢能力,使得所述中间绝缘层107,特别是所述氧化物绝缘层107A避免采用较大的厚度来获取更好的阻氢效果,进而使得降低所述氧化物绝缘层107A膜层的厚度成为可行且有益的改进方向,本实施例优选所述氧化物绝缘层107A的膜层厚度小于或等于所述氮化物绝缘层107B的膜层厚度,这样既能够缩短膜层沉积或涂布的时间,提高量产效率,同时有利于降低薄膜晶体管阵列基板的厚度。
在一些实施例中,所述第一栅极绝缘层102和所述第二栅极绝缘层104的厚度均为1000-1500A,所述中间绝缘层107的厚度为所述第二栅极绝缘层104的厚度的2-3倍,进一步优选所述中间绝缘层107的厚度为1500-4500A为佳。另一方面,通过对阵列基板的膜层结构及制造工艺进行优化,所述薄膜晶体管阵列基板中所述第一半导体层上表面与所述第二半导体层的下表面之间的高度差优选为3500-7500A,更优选所述第一半导体层上表面与所述第二半导体层的下表面之间的高度差为4500-6500A,如此既兼顾了薄膜晶体管阵列基板的功能特性和柔性,在工艺制程上也有利于降低成本、提高生产效率。
本发明实施例还包括提供一种显示装置,所述显示装置包括薄膜晶体管阵列基板,所述薄膜晶体管阵列基板为上述任一所述的薄膜晶体管阵列基板。
在上述实施例中,对各个实施例的描述都各有侧重,某个实施例中没有详述的部分,可以参见其他实施例的相关描述。
以上对本发明实施例进行了详细介绍,本文中应用了具体个例对本发明的原理及实施方式进行了阐述,以上实施例的说明只是用于帮助理解本发明的技术方案及其核心思想;本领域的普通技术人员应当理解:其依然可以对前述各实施例所记载的技术方案进行修改,或者对其中部分技术特征进行等同替换;而这些修改或者替换,并不使相应技术方案的本质脱离本发明各实施例的技术方案的范围。
Claims (10)
1.一种薄膜晶体管阵列基板,其特征在于,包括:
第一半导体层;
覆盖所述第一半导体层的第一栅极绝缘层;
设置在所述第一栅极绝缘层上并与所述第一半导体层重叠的第一栅极电极;
覆盖所述第一栅极电极的第二栅极绝缘层;
设置在所述第二栅极绝缘层上并同层布置的导电层和第二栅极电极;
中间绝缘层,覆盖所述导电层和所述第二栅极电极;
设置在所述中间绝缘层上的第二半导体层,所述第二半导体层与所述第二栅极电极重叠;
覆盖所述第二半导体层的第三栅极绝缘层,
设置在所述第三栅极绝缘层上并与所述第二半导体层重叠的第三栅极电极;
其中,所述第一半导体层与所述第二半导体层为不同材料的半导体层,所述中间绝缘层包括氧化物绝缘层。
2.如权利要求1所述的薄膜晶体管阵列基板,其特征在于,所述第一半导体层包括多晶硅半导体材料,所述第二半导体层包括氧化物半导体材料。
3.如权利要求2所述的薄膜晶体管阵列基板,其特征在于,所述中间绝缘层为单一的氧化物绝缘层,所述中间绝缘层的厚度为1500-4500A。
4.如权利要求3所述的薄膜晶体管阵列基板,其特征在于,所述第二栅极绝缘层中氢含量大于或等于20%。
5.如权利要求2所述的薄膜晶体管阵列基板,其特征在于,所述中间绝缘层还包括氮化物绝缘层,其中,所述氮化物绝缘层位于所述氧化物绝缘层下方,并且,所述氧化物绝缘层的膜层厚度等于或小于氮化物绝缘层的膜层厚度。
6.如权利要求5所述的薄膜晶体管阵列基板,其特征在于,所述氮化物绝缘层中氢含量≥10%且≤15%,所述第二栅极绝缘层中氢含量大于15%。
7.如权利要求1所述的薄膜晶体管阵列基板,其特征在于,所述氧化物绝缘层为致密氧化物膜层。
8.如权利要求1所述的薄膜晶体管阵列基板,其特征在于,所述中间绝缘层的厚度为所述第二栅极绝缘层的厚度的2-3倍。
9.如权利要求1所述的薄膜晶体管阵列基板,其特征在于,所述第一半导体层的上表面与所述第二半导体层的下表面之间的高度差为3500-7500A。
10.一种显示装置,所述显示装置包括薄膜晶体管阵列基板,所述薄膜晶体管阵列基板为如权利要求1-9中任一项所述的薄膜晶体管阵列基板。
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PCT/CN2020/130984 WO2022011921A1 (zh) | 2020-07-17 | 2020-11-24 | 一种薄膜晶体管阵列基板及显示装置 |
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CN112599571A (zh) * | 2020-12-08 | 2021-04-02 | 武汉华星光电半导体显示技术有限公司 | 显示面板 |
WO2022011921A1 (zh) * | 2020-07-17 | 2022-01-20 | 武汉华星光电半导体显示技术有限公司 | 一种薄膜晶体管阵列基板及显示装置 |
CN114023765A (zh) * | 2021-10-21 | 2022-02-08 | 武汉华星光电半导体显示技术有限公司 | 阵列基板及其制备方法、显示面板 |
WO2023216315A1 (zh) * | 2022-05-11 | 2023-11-16 | 武汉华星光电技术有限公司 | 阵列基板、显示面板及显示终端 |
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JP2990046B2 (ja) * | 1995-08-16 | 1999-12-13 | 日本電気株式会社 | 反射型液晶表示装置及びその製造方法 |
JP5906571B2 (ja) * | 2010-04-06 | 2016-04-20 | ソニー株式会社 | 液晶表示装置、液晶表示装置の製造方法 |
JP2016134388A (ja) * | 2015-01-15 | 2016-07-25 | 株式会社ジャパンディスプレイ | 表示装置 |
US9985082B2 (en) * | 2016-07-06 | 2018-05-29 | Lg Display Co., Ltd. | Organic light emitting display device comprising multi-type thin film transistor and method of manufacturing the same |
KR102530003B1 (ko) * | 2016-12-15 | 2023-05-08 | 삼성디스플레이 주식회사 | 트랜지스터 표시판 및 이를 포함하는 표시 장치 |
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CN111081723B (zh) * | 2019-12-31 | 2022-04-29 | 厦门天马微电子有限公司 | 阵列基板、阵列基板的制作方法、显示面板以及显示装置 |
CN111785740A (zh) * | 2020-07-17 | 2020-10-16 | 武汉华星光电半导体显示技术有限公司 | 一种薄膜晶体管阵列基板及显示装置 |
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WO2022011921A1 (zh) * | 2020-07-17 | 2022-01-20 | 武汉华星光电半导体显示技术有限公司 | 一种薄膜晶体管阵列基板及显示装置 |
CN112599571A (zh) * | 2020-12-08 | 2021-04-02 | 武汉华星光电半导体显示技术有限公司 | 显示面板 |
CN114023765A (zh) * | 2021-10-21 | 2022-02-08 | 武汉华星光电半导体显示技术有限公司 | 阵列基板及其制备方法、显示面板 |
CN114023765B (zh) * | 2021-10-21 | 2023-07-25 | 武汉华星光电半导体显示技术有限公司 | 阵列基板及其制备方法、显示面板 |
WO2023216315A1 (zh) * | 2022-05-11 | 2023-11-16 | 武汉华星光电技术有限公司 | 阵列基板、显示面板及显示终端 |
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