WO2022011835A1 - Semiconductor power device and manufacturing method thereof - Google Patents

Semiconductor power device and manufacturing method thereof Download PDF

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WO2022011835A1
WO2022011835A1 PCT/CN2020/117288 CN2020117288W WO2022011835A1 WO 2022011835 A1 WO2022011835 A1 WO 2022011835A1 CN 2020117288 W CN2020117288 W CN 2020117288W WO 2022011835 A1 WO2022011835 A1 WO 2022011835A1
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epitaxial layer
type epitaxial
region
type
trench
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Chinese (zh)
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刘磊
毛振东
徐真逸
龚轶
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苏州东微半导体有限公司
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Abstract

The present invention relates to the technical field of semiconductor power devices. Disclosed are a semiconductor power device and a manufacturing method thereof. The semiconductor power device comprises: an n-type epitaxial layer; a plurality of cell region trenches and a plurality of termination region trenches recessed into the n-type epitaxial layer, the depth of the termination region trench being less than the depth of the cell region trench; and p-type doped regions located within the n-type epitaxial layer under the termination region trenches, wherein each termination region trench has the p-type doped region disposed thereunder.

Description

半导体功率器件及其制造方法Semiconductor power device and method of manufacturing the same
本申请要求在2020年7月13日提交中国专利局、申请号为202010671084.7的中国专利申请的优先权，该申请的全部内容通过引用结合在本申请中。This application claims the priority of the Chinese Patent Application No. 202010671084.7 filed with the China Patent Office on July 13, 2020, the entire contents of which are incorporated herein by reference.
技术领域technical field
本申请属于半导体功率器件技术领域，例如一种半导体功率器件及其制造方法。The present application belongs to the technical field of semiconductor power devices, such as a semiconductor power device and a manufacturing method thereof.
背景技术Background technique
半导体功率器件的设计中，元胞区的设计决定器件的电阻、电容以及击穿电压等特性，但它受限于终端区保护设计的有效性和面积。好的终端区设计中，为保证器件可靠性，电压击穿点应落在元胞区，而不是终端区，同时终端区占用面积会直接影响元胞区的导通电阻。相关技术中的半导体功率器件为了降低特征导通电阻，需要提高n型外延层的掺杂浓度，这使得终端区在横向上难以耗尽，导致终端区耐压低于元胞区耐压，从而影响了半导体功率器件的耐压。In the design of semiconductor power devices, the design of the cell region determines the resistance, capacitance and breakdown voltage of the device, but it is limited by the effectiveness and area of the termination region protection design. In a good terminal area design, in order to ensure the reliability of the device, the voltage breakdown point should be located in the cell area, not the terminal area, and the area occupied by the terminal area will directly affect the on-resistance of the cell area. In order to reduce the characteristic on-resistance of semiconductor power devices in the related art, it is necessary to increase the doping concentration of the n-type epitaxial layer, which makes it difficult for the terminal region to be depleted in the lateral direction, resulting in the withstand voltage of the terminal region being lower than that of the cell region, so It affects the withstand voltage of semiconductor power devices.
发明内容SUMMARY OF THE INVENTION
本申请提供一种半导体功率器件及其制造方法，以避免相关技术中的半导体功率器件的耐压难以调整的情况。The present application provides a semiconductor power device and a manufacturing method thereof, so as to avoid the situation that the withstand voltage of the semiconductor power device in the related art is difficult to adjust.
本申请提供了一种半导体功率器件，包括：The present application provides a semiconductor power device, including:
n型外延层；n-type epitaxial layer;
凹陷在所述n型外延层内的若干个元胞区沟槽和若干个终端区沟槽，所述终端区沟槽的深度小于所述元胞区沟槽的深度；several cell region trenches and several terminal region trenches recessed in the n-type epitaxial layer, the depth of the termination region trenches is less than the depth of the cell region trenches;
位于所述n型外延层内且位于所述终端区沟槽下方的p型掺杂区，每个所述终端区沟槽的下方均设置有所述p型掺杂区。Each of the p-type doped regions located in the n-type epitaxial layer and below the termination region trenches is provided with the p-type doped region under each of the termination region trenches.
本申请还提出了上述半导体功率器件的制造方法，包括：The present application also proposes a method for manufacturing the above-mentioned semiconductor power device, including:
在n型外延层上形成硬掩膜层；forming a hard mask layer on the n-type epitaxial layer;
通过光刻工艺和刻蚀工艺形成凹陷在所述n型外延层内的元胞区沟槽和终端区沟槽；forming cell region trenches and terminal region trenches recessed in the n-type epitaxial layer by a photolithography process and an etching process;
进行p型离子注入，在所述元胞区沟槽和所述终端区沟槽下方的所述n型外延层内形成p型注入区；performing p-type ion implantation to form a p-type implantation region in the n-type epitaxial layer below the cell region trench and the termination region trench;
通过光刻工艺暴露出所述元胞区沟槽，对所述n型外延层进行刻蚀以刻蚀掉位于所述元胞区沟槽下方的所述p型注入区，保留位于所述终端区沟槽下方的所述p型注入区，所述终端区沟槽的深度小于所述元胞区沟槽的深度。The cell region trench is exposed through a photolithography process, and the n-type epitaxial layer is etched to etch away the p-type implantation region under the cell region trench, leaving the terminal In the p-type implantation region below the region trench, the depth of the termination region trench is smaller than the depth of the cell region trench.
附图说明Description of drawings
图1是本申请提供的半导体功率器件的第一个实施例的剖面结构示意图；1 is a schematic cross-sectional structure diagram of a first embodiment of a semiconductor power device provided by the present application;
图2是本申请提供的半导体功率器件的第二个实施例的剖面结构示意图；2 is a schematic cross-sectional structure diagram of a second embodiment of the semiconductor power device provided by the present application;
图3是本申请提供的半导体功率器件的第三个实施例的剖面结构示意图；3 is a schematic cross-sectional structure diagram of a third embodiment of the semiconductor power device provided by the present application;
图4-图5是本申请提供的半导体功率器件的制造方法的一个实施例的制造工艺中的主要结构的剖面结构示意图。4-5 are schematic cross-sectional structural diagrams of main structures in a manufacturing process of an embodiment of the manufacturing method of a semiconductor power device provided by the present application.
具体实施方式detailed description
以下将结合本申请实施例中的附图，通过具体方式，完整地描述本申请的技术方案。显然，所描述的实施例是本申请的一部分实施例，而不是全部的实施例。应当理解，本申请所使用的诸如“具有”、“包含”以及“包括”等术语并不配出一个或多个其它元件或其组合的存在或添加。同时，为清楚地说明本申请的具体实施方式，说明书附图中所列示意图，放大了本申请所述的层和区域的厚度，且所列图形大小并不代表实际尺寸。The technical solutions of the present application will be completely described below in specific manners with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are some, but not all, embodiments of the present application. It should be understood that terms such as "having", "comprising" and "including" used herein do not assign the presence or addition of one or more other elements or combinations thereof. Meanwhile, in order to clearly illustrate the specific embodiments of the present application, the schematic diagrams listed in the accompanying drawings of the specification have enlarged the thicknesses of the layers and regions described in the present application, and the sizes of the listed figures do not represent actual sizes.
图1是本申请提供的半导体功率器件的第一个实施例的剖面结构示意图，如图1所示，本申请提供的半导体功率器件包括n型衬底20，位于n型衬底20之上的n型外延层21，凹陷在n型外延层21内的若干个元胞区沟槽201和若干 个终端区沟槽202，终端区沟槽202的深度小于元胞区沟槽201的深度，在图1的实施例中，仅示例性的示出了两个元胞区沟槽201和三个终端区沟槽202。在半导体功率器件中，元胞区沟槽201位于元胞区100内，终端区沟槽位于终端区200内，且在俯视结构上，终端区200环绕包围元胞区100。FIG. 1 is a schematic cross-sectional structure diagram of a first embodiment of a semiconductor power device provided by the present application. As shown in FIG. 1 , the semiconductor power device provided by the present application includes an n-type substrate 20 . The n-type epitaxial layer 21, several cell region trenches 201 and several terminal region trenches 202 recessed in the n-type epitaxial layer 21, the depth of the termination region trench 202 is less than the depth of the cell region trench 201, In the embodiment of FIG. 1 , only two cell region trenches 201 and three termination region trenches 202 are exemplarily shown. In the semiconductor power device, the cell region trench 201 is located in the cell region 100 , the termination region trench is located in the termination region 200 , and the termination region 200 surrounds the cell region 100 in a top view.
位于n型外延层21内且位于终端区沟槽202下方的p型掺杂区24，每个终端区沟槽202的下方均设置有p型掺杂区24。位于终端区沟槽202内的场氧化层22和导电多晶硅23，至少有一个终端区沟槽202内的导电多晶硅23外接源极电压。Each of the p-type doped regions 24 located in the n-type epitaxial layer 21 and below the termination region trenches 202 is provided with a p-type doped region 24 under each termination region trench 202 . The field oxide layer 22 and the conductive polysilicon 23 located in the trenches 202 in the termination region, at least one of the conductive polysilicon 23 in the trenches 202 in the termination region is connected to a source voltage.
本申请的半导体功率器件的终端区包括终端区沟槽结构和位于终端区沟槽下方的p型掺杂区，其中终端区沟槽结构作为沟槽终端结构，p型掺杂区作为场环终端结构，由此，终端区的耐压由沟槽终端结构和场环终端结构共同决定，这可以提高终端区的耐压，进而提高半导体功率器件的耐压和可靠性。The termination region of the semiconductor power device of the present application includes a termination region trench structure and a p-type doped region located under the termination region trench, wherein the termination region trench structure serves as the trench termination structure, and the p-type doped region serves as a field ring termination Therefore, the withstand voltage of the termination region is jointly determined by the trench termination structure and the field ring termination structure, which can improve the withstand voltage of the termination region, thereby improving the withstand voltage and reliability of the semiconductor power device.
图2是本申请提供的半导体功率器件的第二个实施例的剖面结构示意图，如图2所示，本申请的半导体功率器件中的n型外延层可以包括第一n型外延层41和位于第一n型外延层41之上的第二n型外延层42，第一n型外延层41和第二n型外延层42的掺杂浓度不同。可选的，第二n型外延层42的掺杂浓度大于第一n型外延层41的掺杂浓度，由此，低掺杂浓度的第一n型外延层41设置为提高半导体功率器件的耐压，高掺杂浓度的第二n型外延层设置为降低半导体功率器件的导通电阻。当n型外延层包括第一n型外延层41和第二n型外延层42时，终端区沟槽202的底部可以位于第二n型外延层42内，也可以是终端区沟槽202的底部位于第一n型外延层41内，在图2中，示例性的示出了终端区沟槽202的底部位于第一n型外延层41内的结构。FIG. 2 is a schematic cross-sectional structure diagram of a second embodiment of the semiconductor power device provided by the present application. As shown in FIG. 2 , the n-type epitaxial layer in the semiconductor power device of the present application may include a first n-type epitaxial layer 41 and a The doping concentration of the second n-type epitaxial layer 42 on the first n-type epitaxial layer 41 is different from that of the first n-type epitaxial layer 41 and the second n-type epitaxial layer 42 . Optionally, the doping concentration of the second n-type epitaxial layer 42 is greater than the doping concentration of the first n-type epitaxial layer 41 . Therefore, the first n-type epitaxial layer 41 with a low doping concentration is set to improve the performance of the semiconductor power device. Withstanding voltage, the second n-type epitaxial layer with high doping concentration is provided to reduce the on-resistance of the semiconductor power device. When the n-type epitaxial layer includes the first n-type epitaxial layer 41 and the second n-type epitaxial layer 42 , the bottom of the termination region trench 202 may be located in the second n-type epitaxial layer 42 , or may be the bottom of the termination region trench 202 . The bottom is located in the first n-type epitaxial layer 41 . In FIG. 2 , a structure in which the bottom of the termination region trench 202 is located in the first n-type epitaxial layer 41 is exemplarily shown.
图3是本申请提供的半导体功率器件的第三个实施例的剖面结构示意图，结合图1和图3所示，本申请的半导体功率器件，终端区沟槽202与p型掺杂区24一一对应，如图1所示；或者如图3所示，本申请的半导体功率器件，位 于每个终端区沟槽202的下方的p型掺杂区相连接形成一个p型扩散掺杂区25。FIG. 3 is a schematic cross-sectional structural diagram of a third embodiment of the semiconductor power device provided by the present application. As shown in FIG. 1 and FIG. 3 , in the semiconductor power device of the present application, the termination region trench 202 and the p-type doped region 24 are one One correspondence, as shown in FIG. 1 ; or as shown in FIG. 3 , in the semiconductor power device of the present application, the p-type doped regions located under each terminal region trench 202 are connected to form a p-type diffusion doped region 25 .
图4-图5是本申请提供的半导体功率器件的制造方法的一个实施例的制造工艺中的主要结构的剖面结构示意图，首先如图4所示，在n型衬底20上形成n型外延层21，并在n型外延层21上形成硬掩膜层31，硬掩膜层31通常包括氧化硅层和氮化硅层；之后通过光刻工艺和刻蚀工艺形成凹陷在n型外延层21内的元胞区沟槽201和终端区沟槽202，图4中仅示例性的示出了两个元胞区沟槽201和三个终端区沟槽202，然后进行p型离子注入，在元胞区沟槽201和终端区沟槽202下方的n型外延层21内形成p型注入区32。4-5 are schematic cross-sectional structural diagrams of main structures in the manufacturing process of an embodiment of the manufacturing method of a semiconductor power device provided by the present application. First, as shown in FIG. 4 , an n-type epitaxy is formed on the n-type substrate 20 layer 21, and a hard mask layer 31 is formed on the n-type epitaxial layer 21. The hard mask layer 31 usually includes a silicon oxide layer and a silicon nitride layer; then a recess is formed on the n-type epitaxial layer through a photolithography process and an etching process. The cell region trenches 201 and the termination region trenches 202 in 21, only two cell region trenches 201 and three termination region trenches 202 are exemplarily shown in FIG. 4, and then p-type ion implantation is performed, A p-type implantation region 32 is formed in the n-type epitaxial layer 21 under the cell region trench 201 and the termination region trench 202 .
接下来，如图5所示，通过光刻工艺暴露出元胞区沟槽201，然后继续对n型外延层21进行刻蚀以刻蚀掉位于元胞区沟槽21下方的p型注入区32，保留位于终端区沟槽202下方的所述p型注入区32，在该步刻蚀后，元胞区沟槽201的深度会增加，从而使得元胞区沟槽201的深度大于终端区沟槽202的深度。Next, as shown in FIG. 5 , the cell region trench 201 is exposed by a photolithography process, and then the n-type epitaxial layer 21 is etched to etch away the p-type implantation region located under the cell region trench 21 32. Retain the p-type implantation region 32 under the trench 202 in the termination region. After this step of etching, the depth of the trench 201 in the cell region will increase, so that the depth of the trench 201 in the cell region is greater than that in the termination region Depth of trench 202 .
最后，通过常规工艺即可制备得到本申请的半导体功率器件，需要说明的是，通过控制终端区沟槽202之间的间距以及p型注入区32的注入浓度，在后续制备工艺中，可以使p型注入区32在扩散后，在每个终端区沟槽202的下方均形成一个p型掺杂区；也可以是使p型注入区32在扩散后相连接形成一个p型扩散掺杂区，即在每个终端区沟槽202的下方的p型掺杂区相连接形成一个p型扩散掺杂区。Finally, the semiconductor power device of the present application can be prepared by a conventional process. It should be noted that by controlling the spacing between the trenches 202 in the terminal region and the implantation concentration of the p-type implantation region 32, in the subsequent preparation process, the After the p-type implanted regions 32 are diffused, a p-type doped region is formed under each termination region trench 202; it is also possible to connect the p-type implanted regions 32 after diffusion to form a p-type diffused doped region , that is, the p-type doped regions below each termination region trench 202 are connected to form a p-type diffusion doped region.
本申请的半导体功率器件的元胞区沟槽可以适用于不同的栅极结构，如栅极结构和源极多晶硅为上下位置关系，或者栅极结构和源极多晶硅为左右位置关系，同时为了匹配元胞区沟槽内的栅极结构，在终端区沟槽内也可以形成与之相对应的栅极结构，终端区沟槽内的栅极结构应浮空设置或外接源极电压。The cell region trench of the semiconductor power device of the present application can be applied to different gate structures, for example, the gate structure and the source polysilicon are in an up and down positional relationship, or the gate structure and the source polysilicon are in a left and right positional relationship. For the gate structure in the cell region trench, a corresponding gate structure can also be formed in the termination region trench, and the gate structure in the termination region trench should be floating or externally connected to a source voltage.

Claims (9)

  1. 半导体功率器件，包括：Semiconductor power devices, including:
    n型外延层；n-type epitaxial layer;
    凹陷在所述n型外延层内的若干个元胞区沟槽和若干个终端区沟槽，所述终端区沟槽的深度小于所述元胞区沟槽的深度；several cell region trenches and several terminal region trenches recessed in the n-type epitaxial layer, the depth of the termination region trenches is less than the depth of the cell region trenches;
    位于所述n型外延层内且位于所述终端区沟槽下方的p型掺杂区，每个所述终端区沟槽的下方均设置有所述p型掺杂区。Each of the p-type doped regions located in the n-type epitaxial layer and below the termination region trenches is provided with the p-type doped region under each of the termination region trenches.
  2. 如权利要求1所述的器件，其中，所述n型外延层包括第一n型外延层和位于所述第一n型外延层之上的第二n型外延层，所述第一n型外延层和所述第二n型外延层的掺杂浓度不同。The device of claim 1, wherein the n-type epitaxial layer comprises a first n-type epitaxial layer and a second n-type epitaxial layer overlying the first n-type epitaxial layer, the first n-type epitaxial layer The doping concentrations of the epitaxial layer and the second n-type epitaxial layer are different.
  3. 如权利要求2所述的器件，其中，所述第二n型外延层的掺杂浓度大于所述第一n型外延层的掺杂浓度。The device of claim 2, wherein the doping concentration of the second n-type epitaxial layer is greater than the doping concentration of the first n-type epitaxial layer.
  4. 如权利要求2所述的器件，其中，所述终端区沟槽的底部位于所述第二n型外延层内。3. The device of claim 2, wherein a bottom of the termination region trench is within the second n-type epitaxial layer.
  5. 如权利要求2所述的器件，其中，所述终端区沟槽的底部位于所述第一n型外延层内。3. The device of claim 2, wherein a bottom of the termination region trench is within the first n-type epitaxial layer.
  6. 如权利要求1所述的器件，还包括位于所述终端区沟槽内的场氧化层和导电多晶硅，至少有一个所述终端区沟槽内的导电多晶硅外接源极电压。The device of claim 1, further comprising a field oxide layer and conductive polysilicon in the termination region trenches, at least one of the conductive polysilicon in the termination region trenches being connected to a source voltage.
  7. 根据权利要求1所述的器件，其中，所述终端区沟槽与所述p型掺杂区一一对应。The device of claim 1 , wherein the termination region trenches correspond one-to-one with the p-type doped regions.
  8. 如权利要求1所述的器件，其中，位于每个所述终端区沟槽下方的所述p型掺杂区相连接形成一个p型扩散掺杂区。The device of claim 1 wherein said p-type doped regions under each of said termination region trenches are connected to form a p-type diffused doped region.
  9. 半导体功率器件的制造方法，包括：A method of manufacturing a semiconductor power device, including:
    在n型外延层上形成硬掩膜层；forming a hard mask layer on the n-type epitaxial layer;
    通过光刻工艺和刻蚀工艺形成凹陷在所述n型外延层内的元胞区沟槽和终端区沟槽；forming cell region trenches and terminal region trenches recessed in the n-type epitaxial layer by a photolithography process and an etching process;
    进行p型离子注入，在所述元胞区沟槽和所述终端区沟槽下方的n型外延 层内形成p型注入区；performing p-type ion implantation to form a p-type implantation region in the n-type epitaxial layer below the cell region trench and the termination region trench;
    通过光刻工艺暴露出所述元胞区沟槽，对所述n型外延层进行刻蚀以刻蚀掉位于所述元胞区沟槽下方的所述p型注入区，保留位于所述终端区沟槽下方的所述p型注入区，所述终端区沟槽的深度小于所述元胞区沟槽的深度。The cell region trench is exposed through a photolithography process, and the n-type epitaxial layer is etched to etch away the p-type implantation region under the cell region trench, leaving the terminal In the p-type implantation region below the region trench, the depth of the termination region trench is smaller than the depth of the cell region trench.
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120326207A1 (en) * 2011-06-08 2012-12-27 Rohm Co., Ltd. Semiconductor device and manufacturing method
JP2013069866A (en) * 2011-09-22 2013-04-18 Toshiba Corp Semiconductor device
JP2016189369A (en) * 2015-03-30 2016-11-04 サンケン電気株式会社 Semiconductor device
CN107403839A (en) * 2017-07-25 2017-11-28 无锡新洁能股份有限公司 Suitable for the power semiconductor device structure and manufacture method of deep trench
CN207217547U (en) * 2017-09-28 2018-04-10 无锡紫光微电子有限公司 It is a kind of to improve pressure-resistant shield grid MOSFET terminal structures

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102006036347B4 (en) * 2006-08-03 2012-01-12 Infineon Technologies Austria Ag Semiconductor device with a space-saving edge structure
CN102318045B (en) * 2008-02-14 2014-08-06 马克斯半导体股份有限公司 Edge termination with improved breakdown voltage
US8575685B2 (en) * 2011-08-25 2013-11-05 Alpha And Omega Semiconductor Incorporated Buried field ring field effect transistor (BUF-FET) integrated with cells implanted with hole supply path
US11101346B2 (en) * 2016-03-21 2021-08-24 Huntech Semiconductor (Shanghai) Co. Ltd Edge termination designs for semiconductor power devices
US10439075B1 (en) * 2018-06-27 2019-10-08 Semiconductor Components Industries, Llc Termination structure for insulated gate semiconductor device and method
CN110400836A (en) * 2019-08-29 2019-11-01 无锡新洁能股份有限公司 A kind of power semiconductor and preparation method thereof

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120326207A1 (en) * 2011-06-08 2012-12-27 Rohm Co., Ltd. Semiconductor device and manufacturing method
JP2013069866A (en) * 2011-09-22 2013-04-18 Toshiba Corp Semiconductor device
JP2016189369A (en) * 2015-03-30 2016-11-04 サンケン電気株式会社 Semiconductor device
CN107403839A (en) * 2017-07-25 2017-11-28 无锡新洁能股份有限公司 Suitable for the power semiconductor device structure and manufacture method of deep trench
CN207217547U (en) * 2017-09-28 2018-04-10 无锡紫光微电子有限公司 It is a kind of to improve pressure-resistant shield grid MOSFET terminal structures

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