WO2022007460A1 - 降压型直流-直流转换器 - Google Patents

降压型直流-直流转换器 Download PDF

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Publication number
WO2022007460A1
WO2022007460A1 PCT/CN2021/087523 CN2021087523W WO2022007460A1 WO 2022007460 A1 WO2022007460 A1 WO 2022007460A1 CN 2021087523 W CN2021087523 W CN 2021087523W WO 2022007460 A1 WO2022007460 A1 WO 2022007460A1
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Prior art keywords
voltage
power transistor
circuit
current
discharge
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PCT/CN2021/087523
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English (en)
French (fr)
Inventor
谢凌寒
巩令风
黄星星
王国鹏
汪东
Original Assignee
无锡力芯微电子股份有限公司
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Priority to KR1020227030253A priority Critical patent/KR102641551B1/ko
Publication of WO2022007460A1 publication Critical patent/WO2022007460A1/zh

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0003—Details of control, feedback or regulation circuits
    • H02M1/0025—Arrangements for modifying reference values, feedback values or error values in the control loop of a converter
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H02M1/083—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the ignition at the zero crossing of the voltage or the current
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/32—Means for protecting converters other than automatic disconnection
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
    • H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
    • H02M3/072—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps adapted to generate an output voltage whose value is lower than the input voltage
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H02M3/158—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0048—Circuits or arrangements for reducing losses
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Definitions

  • the invention relates to the technical field of power conversion, in particular to a step-down DC-DC converter.
  • Constant on-time (COT, constant on-time) step-down direct current (DC-DC) converter has the advantages of good transient response, simple internal circuit, and fewer peripheral devices.
  • the output voltage accuracy is not high enough.
  • An important reason that affects the output voltage accuracy is the error caused by slope compensation.
  • Figure 1 is a circuit schematic diagram of a conventional COT step-down DC-DC converter.
  • HSD_FET first power transistor
  • the compensation ramp voltage generated by the ramp voltage generating circuit is set to zero.
  • FIG. 2 at very light load, after the first power transistor is turned on, it remains off for a very long period of time, and at this time, the compensation slope voltage Vslope continues to increase until its maximum voltage limit value Vslope_max.
  • the first power transistor HSD_FET will only be turned on when the following equation is satisfied.
  • the purpose of the present invention is to provide a step-down DC-DC converter, which can solve the error caused by slope compensation and improve the output voltage accuracy.
  • the present invention provides a step-down DC-DC converter, which further includes: an output circuit, which is used for converting an input voltage into an output voltage, which includes a circuit connected in series to the input terminal a first power transistor and a second power transistor between the ground and the ground; a voltage feedback circuit for obtaining a feedback voltage based on the output voltage; a ripple generating circuit for generating a ripple voltage related to the current of the inductor; current The zero point detection circuit is used to detect the zero point of the current of the inductor and generate the current zero point signal; the ramp voltage generation circuit, when the first power transistor is switched from on to off, it generates a ramp voltage whose voltage gradually increases from the initial voltage, When the current zero point detection circuit detects that the current of the inductor reaches the zero point, the ramp voltage is gradually reduced to the initial voltage; the first comparator includes a first comparison input terminal and a second comparison input terminal, the first comparison The input terminal receives the first voltage
  • the comparison result of a comparator controls the turn-on and turn-off of the first power transistor and the second power transistor, the first power transistor and the second power transistor will not be turned on at the same time, and the current zero point detection circuit detects the current of the inductor When reaching the zero point, the second power transistor is controlled to be turned off.
  • the ramp voltage in the present invention no longer increases when the inductor current reaches zero, but gradually decreases to zero, so that under light load conditions, when the first power transistor is turned on, the ramp voltage Vslope It has been reduced to zero, which can eliminate the error caused by slope compensation and improve the output voltage accuracy.
  • Figure 1 is a circuit schematic diagram of a traditional COT step-down DC-DC converter
  • FIG. 2 is a timing diagram of some signals of the COT step-down DC-DC converter in FIG. 1;
  • FIG. 3 is a schematic circuit diagram of the COT step-down DC-DC converter in one embodiment of the present invention.
  • FIG. 4 is a circuit diagram of the ramp voltage generating circuit in FIG. 3 in one embodiment
  • Fig. 5 is a timing diagram of the COT step-down DC-DC converter in Fig. 3 and a part of signals of the ramp voltage generating circuit in Fig. 4;
  • FIG. 7 is the output voltage and load current waveforms of the conventional COT step-down DC-DC converter in FIG. 1;
  • FIG. 8 is a circuit diagram of the discharge control logic circuit in FIG. 3 in one embodiment
  • FIG. 10 is the output voltage overshoot and recovery waveforms of the conventional COT step-down DC-DC converter in FIG. 1 .
  • references herein to "one embodiment” or “an embodiment” refers to a particular feature, structure, or characteristic that may be included in at least one implementation of the present invention.
  • the appearances of "in one embodiment” in various places in this specification are not all referring to the same embodiment, nor are they separate or selectively mutually exclusive from other embodiments.
  • the terms connected, connected, and connected herein mean electrically connected, all mean direct or indirect electrical connection.
  • the present invention proposes a step-down DC-DC converter, which can solve the problem of long duration of overshoot in transient response of large current.
  • FIG. 3 is a schematic circuit diagram of a step-down DC-DC converter 300 in an embodiment of the present invention.
  • the step-down DC-DC converter 300 includes an output circuit 310, a voltage feedback circuit 320, a discharge path 330, a discharge control circuit 340, a ripple generation circuit 350, a current zero point detection circuit 360, a first A comparator (or PWM comparator) 370 , an on-time signal generating circuit 380 , a logic circuit 390 , a ramp voltage generating circuit 410 , a first driving circuit 420 and a second driving circuit 430 .
  • the output circuit 310 is used to convert the input voltage VIN into the output voltage Vout.
  • the output voltage Vout is lower than the input voltage VIN, so it can be called a step-down DC-DC converter.
  • the output circuit 310 includes a first power transistor HSD_FET and a second power transistor LSD_FET connected in series between the input terminal and the ground terminal, the first power transistor HSD_FET and the second power transistor The node between the LSD_FETs is called an intermediate node SW.
  • the output circuit 310 includes an input terminal that receives an input voltage VIN and an output terminal that provides an output voltage Vout, the input terminal may also be labeled VIN, and the output terminal may also be labeled Vout.
  • the output circuit 310 may further include an inductor L and an output capacitor Co, and the first power transistor HSD_FET and the second power transistor LSD_FET are controlled to be turned on alternately to achieve voltage conversion.
  • the first power transistor HSD_FET and the second power transistor LSD_FET will not be turned on at the same time, that is, when the first power transistor HSD_FET is turned on, the second power transistor LSD_FET is turned off, and when the second power transistor LSD_FET is turned on, the first power transistor LSD_FET is turned on.
  • the power transistor HSD_FET is turned off.
  • the inductor L can be provided outside the chip, and other circuit parts can be integrated in the chip.
  • the voltage feedback circuit 320 is configured to obtain a feedback voltage VFB based on the output voltage Vout. As shown in FIG. 3 , in one embodiment, the voltage feedback circuit 320 includes two voltage dividing resistors Rf1 and Rf2 connected in series between the output voltage Vout and ground, and the voltage at the intermediate node of the two voltage dividing resistors is is the feedback voltage VFB.
  • the feedback voltage VFB can reflect the magnitude of the output voltage Vout.
  • the discharge path 330 is coupled between the output circuit and the ground terminal and can be controlled to discharge. As shown in FIG. 3 , in one embodiment, the discharge path 330 includes a first resistor R1 and a discharge switch S1 connected in series between the intermediate node SW of the output circuit and the ground GND. In another embodiment, the discharge path 330 can also be coupled to the output terminal Vout, which can achieve the same effect. Since the inductor L1 is located outside the chip, the discharge path 330 is usually coupled to the intermediate node. It should be noted that the coupling here includes direct and indirect connections.
  • the discharge control circuit 340 controls the discharge path 330 to discharge when the feedback voltage VFB obtained by the voltage feedback circuit 320 is greater than the second reference voltage VREF_2 and the first power transistor HSD_FET is turned off.
  • the discharge path 330 is controlled to prohibit discharging.
  • the discharge control circuit 340 controls the discharge path 330 to discharge by controlling the discharge switch S1 to be turned on, and the discharge control circuit 340 controls the discharge by controlling the discharge switch S1 to be turned off Via 330 inhibits discharge.
  • the second reference voltage VREF_2 is greater than the first reference voltage VREF_1, for example, equal to VREF_1*104%, where VREF_1 is the first reference voltage, which will be described in detail later.
  • the discharge control circuit 340 includes a second comparator 341 and a discharge control logic circuit 342 .
  • the second comparator 341 is used to compare the feedback voltage VFB with the second reference voltage VREF_2, and provide the comparison result to the discharge control logic circuit 342, and the discharge control logic circuit 342 is based on the first
  • the discharge path 330 is controlled by the control signal (signal PWM and signal HSD_ON) of the power transistor HSD_FET and the comparison result of the second comparator 341 .
  • the ripple generating circuit 350 is used for generating a ripple voltage Vrip reflecting the magnitude of the current IL of the inductor L in the output circuit 310 .
  • the ripple generating circuit 350 obtains the ripple voltage Vrip by detecting the current of the intermediate node SW.
  • the waveform of the ripple voltage Vrip is consistent with the waveform of the current IL of the inductor L.
  • the current zero point detection circuit 360 is used to detect the current zero point of the intermediate node SW and generate a current zero point signal ZERO_CURT.
  • the ramp voltage generation circuit 410 generates a ramp voltage Vslople whose voltage gradually increases from the initial voltage when the first power transistor HSD_FET is switched from on to off, and when the current zero point detection circuit 360 detects that the current of the intermediate node SW reaches the zero point , the ramp voltage Vslople gradually decreases to the initial voltage.
  • the ramp voltage Vslople generated by the existing ramp voltage generating circuit in FIG. 1 will continue to gradually increase until the maximum value Vslople_max (the dotted line part in FIG. 5 ) when the current of the intermediate node SW reaches zero.
  • the slope voltage Vslople in the present invention will gradually drop to the initial voltage when the current of the intermediate node SW reaches the zero point.
  • the initial voltage may be 0.
  • the first comparator (or PWM comparator) 370 includes a first comparison input terminal and a second comparison input terminal.
  • the first comparison input terminal receives the first voltage sum Vslople+VREF_1 obtained by adding the ramp voltage Vslople and the first reference voltage VREF_1, and the second comparison input terminal receives the ripple voltage Vrip and the feedback voltage VFB added together
  • the second voltage and Vrip+VFB are obtained later.
  • PWM PWM
  • the second power transistor LSD_FET is controlled to be turned off until the first power transistor in the next cycle After the turn-on time expires, the second power transistor LSD_FET is turned on again.
  • the on-time signal generating circuit 380 generates a predetermined on-time control signal Ton according to the comparison result of the first comparator 370, wherein when the comparison result PWM of the first comparator 370 transitions from inactive to active, the predetermined The on-duration control signal Ton becomes active after a jump, and becomes inactive after a predetermined on-duration.
  • the predetermined on-time duration can be obtained through a timer.
  • the on-time signal generating circuit 380 may also be referred to as a on-time one-shot (T ON One-Shot) circuit.
  • valid and invalid refer to two logic level states, usually valid logic level refers to the logic level that causes the first power transistor to be turned on, and invalid logic level refers to the logic level that causes the first power transistor to be turned off .
  • the logic circuit 390 generates a first control signal HSD_ON for controlling the first power transistor and a second control signal for controlling the second power transistor according to the predetermined on-time duration control signal Ton, the PWM control signal and the current zero signal ZERO_CURT of the on-time signal generating circuit LSD_ON.
  • Ton the predetermined on-time control signal
  • the first control signal HSD_ON is output to control the first power transistor HSD_FET to be turned on
  • the second control signal is output to control the second power transistor LSD_FET to be turned off.
  • the first control signal HSD_ON is output to control the first power transistor HSD_FET to turn off, and when the predetermined on-time control signal Ton is invalid and the current of the intermediate node SW does not reach zero, the second power transistor HSD_ON is output.
  • the control signal controls the second power transistor LSD_FET to be turned on, and when the predetermined turn-on time control signal is invalid and the current of the intermediate node SW reaches zero, the second control signal is output to control the second power transistor LSD_FET to be turned off.
  • the first driving circuit 420 drives the first power transistor HSD_FET to be turned on and off based on the first control signal.
  • the second driving circuit 430 drives the second power transistor LSD_FET to be turned on and off based on the second control signal.
  • the discharge control logic circuit 342 controls the discharge path 330 based on the comparison result PWM of the first comparator, the comparison result VFB_H of the second comparator and the first control signal HSD_ON output from the logic circuit 390 . Specifically, the discharge control logic circuit 342 determines whether the first power transistor starts to be turned on based on the inactive-to-active edge of the comparison result PWM of the first comparator, and based on the active of the first control signal HSD_ON output from the logic circuit 390 It is determined whether the first power transistor starts to be turned off until the invalid transition edge, thereby controlling the turning on or off of the discharge switch S1. In principle, the discharge switch S1 should be turned off before the first power transistor is turned on, and can be turned on after the first power transistor is turned off.
  • FIG. 8 is a circuit diagram of the discharge control logic circuit 342 of FIG. 3 in one embodiment.
  • the discharge control logic circuit 342 includes NOT gates NOT1 and NOT2, AND gates AND1 and AND2, and D flip-flops, whose connection relationship is shown in FIG. 8 .
  • FIG. 4 is a circuit diagram of the ramp voltage generating circuit 410 in FIG. 3 in one embodiment.
  • the ramp voltage generating circuit 410 includes: a capacitor C41 , a charging current source I 1 , a ramp voltage output circuit 411 , a release path 412 connected in parallel with the capacitor C41 , and a charging control circuit 413 .
  • the ramp voltage output circuit 411 obtains and outputs the ramp voltage Vslople based on the stored voltage of the capacitor C41.
  • the charging control circuit 413 controls the third switch S3 when the first power transistor HSD_FET switches from on to off (that is, when the first control signal HSD_ON transitions from active to inactive, such as from high level to low level). and S4 are turned off, the charging current source I 1 to the capacitor C41 charging, beginning from the time T1, Vslople gradually increased according to FIG. 5, the inductor current I L at this time gradually decreases, the current When the zero point detection circuit 360 detects that the current of the intermediate node SW reaches the zero point, that is, time T2, the release path 412 is turned on to discharge the capacitor C41 and gradually reaches zero.
  • the release passage 412 includes a first release branch and a second release branch.
  • the first release branch includes a series-connected first discharge current source I 2 and a first release switch S 41
  • the second release branch includes a series-connected second discharge current source I 3 and a second release switch S 2 .
  • the first release switch S 41 is controlled by the current zero point signal ZERO_CURT
  • the second release switch S 2 is controlled by the current zero point signal ZERO_CURT after passing through the delay unit.
  • the charging control circuit 413 controls the third switch S3 when the first power transistor HSD_FET is switched from off to on (that is, when the first control signal HSD_ON transitions from inactive to active, such as from low level to high level).
  • S4 is turned on, and the voltage of the capacitor C41 is completely released to 0.
  • the ramp voltage output circuit 411 includes: NMOS transistors MN1 and MN2, PMOS transistors MP1 and MP2, and resistors R41 and R42.
  • MN1 is connected to the source electrode of the capacitor C41, the gate of MN2 whose gate and drain connected to the MN1, MN1 is connected to the drain of the charging current source I 1.
  • the source of MN2 is grounded through resistor R41, the drain of MN2 is connected to the drain and gate of MP1, the gate of MP1 is connected to the gate of MP2, the sources of MP1 and MP2 are connected to the power supply, and the drain of MP2 is connected to the drain through resistor R42 Ground, the non-ground terminal of R42 is the output terminal.
  • FIG. 5 is a timing diagram of the COT step-down DC-DC converter in FIG. 3 and the partial signals of the ramp voltage generating circuit in FIG. 4 .
  • the first control signal HSD_ON when the first control signal HSD_ON is at a high level, the first power transistor is turned on, and the second power transistor is turned off.
  • the voltage of the intermediate node SW is high, and the current IL of the inductor L , that is, the intermediate node
  • the current of the SW gradually increases, and the switches S3 and S4 in FIG. 4 are turned on at this time, and the Vslope is 0.
  • the first control signal HSD_ON jumps to a low level, the first power transistor is turned off, and the second power transistor is turned on.
  • the ramp amount when the first power transistor is turned off, when the current of the inductor L decreases to zero, the ramp amount is kept substantially constant, and the ramp amount is gradually reduced until zero after about 0.5us.
  • the slope voltage Vslope under a light load condition, when the first power transistor is turned on, the slope voltage Vslope has dropped to zero. So when the following equation is satisfied,
  • the VFB is lower than the traditional scheme, that is, the output voltage under light load is lower than the traditional scheme, which can also improve the output voltage accuracy.
  • FIG. 6 shows the output voltage and load current waveforms of the COT step-down DC-DC converter in the present invention. As can be seen from the figure, when the load current changes from 0 to 3A, the output voltage changes approximately to 1.02V-1.01V.
  • Figure 7 shows the output voltage and load current waveforms of the conventional COT step-down DC-DC converter in Figure 1. It can be seen from the figure that when the load current changes from 0 to 3A, the output voltage changes about 1.038V to 1.01V. Obviously, the present invention obviously improves the output load regulation rate and improves the output voltage precision.
  • the discharge path of the output terminal Vout is opened, as shown in Fig. Switch S1 in 3.
  • the PWM signal becomes low, it means that the first power transistor is to be turned on, that is, the switch S1 in FIG. 3 is turned off,
  • R1 resistor in Figure 3 can be set to its value as required.
  • R1 in FIG. 3 can be about 110ohm, when the overshoot is about 200mV, the output capacitor Co is 40uF, the discharge current is about 9.1mA, and when the output returns to the set value of 1V, the required time is:
  • the method of the present invention can only be discharged through the feedback resistors Rf1 and Rf2 in FIG. 3 .
  • the resistors Rf1 and Rf2 should not be too small, and their currents are usually controlled at 70uA or even lower.
  • FIG. 10 is the output voltage overshoot and recovery waveform of the conventional COT step-down DC-DC converter in FIG. 1 . After about 8ms, the output voltage is still maintained at 1.186V.
  • words such as “connected”, “connected”, “connected”, “connected”, “coupled” and the like refer to electrical connection, and unless otherwise specified, refer to direct or indirect electrical connection.
  • Indirect connection includes connection through electronic components or units such as resistors, capacitors, inductors, transistors, filters, etc.

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  • Power Engineering (AREA)
  • Dc-Dc Converters (AREA)

Abstract

本发明提供一种降压型直流-直流转换器，其还包括：输出电路，其用于将输入电压转换成输出电压，其包括串联于输入端和接地端之间的第一功率晶体管和第二功率晶体管；电压反馈电路，用于基于所述输出电压得到反馈电压；斜坡电压产生电路，其在第一功率晶体管从导通切换至截止时，产生电压从初始电压逐渐增大的斜坡电压，在检测到电感的电流到达零点时，使得所述斜坡电压逐渐减小至初始电压；第一比较器，其第一比较输入端接收所述斜坡电压与第一参考电压相加后得到的第一电压和，其第二比较输入端接收纹波电压与所述反馈电压相加后得到的第二电压和。这样，可以消除斜坡补偿带来的误差，也就能提高输出电压精度。

Description

降压型直流-直流转换器 技术领域
本发明涉及电源转换技术领域，尤其涉及一种降压型直流-直流转换器。
背景技术
传统结构的Constant on-time(COT，恒导通时间)降压型直流-直流(DC-DC)转换器虽具有瞬态响应好、内部电路简洁、所需外围器件少等优点，但是也具有输出电压精度不够高的不足。而影响输出电压精度的一个重要原因是斜坡补偿带来的误差。
图1为传统的COT降压型直流-直流转换器的电路原理图。如图1，当第一功率晶体管(HSD_FET，有时也被称为高位功率晶体管)导通时，才将斜坡电压产生电路产生的补偿斜坡电压设为零。如图2所示，在极轻载时，第一功率晶体管导通结束后，有非常长的一段时间保持关断状态，而此时补偿斜坡电压Vslope不断增加，直至其最大限压值Vslope_max。
根据传统COT降压型直流-直流转换器的原理，当满足下面方程时，第一功率晶体管HSD_FET才会开启。
VFB+Vrip<VREF_1+Vslope
显而易见，补偿斜坡电压Vslope的增加势必造成反馈电压VFB增加，从而造成轻载时输出电压Vout高出设定值。
此外不管是电压模直流-直流转换器、电流模直流-直流转换器，还是COT直流-直流转换器，它们在电流负载由重载瞬间跳变为轻载时，输出电压都不可避免的有较大的过冲电压。由于COT直流-直流转换器的瞬态响应性能要优于电压模直流-直流转换器和电流模直流-直流转换器，因此它的输出过冲电压要低于电压模和电流模直流-直流转换器。即使是COT直流-直流转换器，当负载由重载突然变为轻载甚至零时，电感储存的能量会释放到输出电容上，从而使得输出电压远高于设定值。为了减少过冲电压的持续时间，会使用较低阻值的反馈电阻。反馈电阻的阻值越小，其电流越大。这样可以通过较低阻值的反馈电阻将输出电压慢慢降到设定值。即使这样，也需要很长时间输出电压才能恢复到设定值。同时，由于使用了较低阻值的反馈电阻，也增加了系统的静态功耗。
因此，有必要提出一种改进的方案来克服上述问题。
发明内容
本发明的目的在于提供一种降压型直流-直流转换器，其可以解决斜坡补偿带来的误差，提高输出电压精度。
为实现发明目的，根据本发明的一个方面，本发明提供一种降压型直流-直流转换器，其还包括：输出电路，其用于将输入电压转换成输出电压，其包括串联于输入端和接地端之间的第一功率晶体管和第二功率晶体管；电压反馈电路，用于基于所述输出电压得到反馈电压；纹波产生电路，用于产生与电感的电流有关的纹波电压；电流零点检测电路，其用于检测电感的电流的零点并产生电流零点信号；斜坡电压产生电路，其在第一功率晶体管从导通切换至截止时，产生电压从初始电压逐渐增大的斜坡电压，在所述电流零点检测电路检测到电感的电流到达零点时，使得所述斜坡电压逐渐减小至初始电压；第一比较器，其包括第一比较输入端和第二比较输入端，第一比较输入端接收所述斜坡电压与第一参考电压相加后得到的第一电压和，第二比较输入端接收所述纹波电压与所述反馈电压相加后得到的第二电压和，基于第一比较器的比较结果控制第一功率晶体管和第二功率晶体管的导通和截止，第一功率晶体管和第二功率晶体管不会同时导通，另外在所述电流零点检测电路检测到电感的电流到达零点时，控制所述第二功率晶体管截止。
与现有技术相比，本发明中的斜坡电压在电感的电流到达零点时不再升高，而是逐渐降低至零，这样在轻载条件下，第一功率晶体管导通时，斜坡电压Vslope已经降为零，可以消除斜坡补偿带来的误差，也就能提高输出电压精度。
附图说明
图1为传统的COT降压型直流-直流转换器的电路原理图；
图2为图1中的COT降压型直流-直流转换器的部分信号的时序图；
图3为本发明中的COT降压型直流-直流转换器在一个实施例中的电路原理图；
图4为图3中的斜坡电压产生电路在一个实施例中的电路图；
图5为图3中的COT降压型直流-直流转换器和和图4中的斜坡电压产生 电路的部分信号的时序图；
图6为本发明中的COT降压型直流-直流转换器的输出电压和负载电流波形；
图7为图1中的传统的COT降压型直流-直流转换器的输出电压和负载电流波形；
图8为图3中的放电控制逻辑电路在一个实施例中的电路图；
图9为本发明中的COT降压型直流-直流转换器的输出电压过冲及恢复波形；
图10为图1中的传统的COT降压型直流-直流转换器的输出电压过冲及恢复波形。
具体实施方式
为使本发明的上述目的、特征和优点能够更加明显易懂，下面结合附图和具体实施方式对本发明作进一步详细的说明。
此处所称的“一个实施例”或“实施例”是指可包含于本发明至少一个实现方式中的特定特征、结构或特性。在本说明书中不同地方出现的“在一个实施例中”并非均指同一个实施例，也不是单独的或选择性的与其他实施例互相排斥的实施例。除非特别说明，本文中的连接、相连、相接的表示电性连接的词均表示直接或间接电性相连。
本发明提出一种降压型直流-直流转换器，其可以解决大电流瞬态响应过冲持续时间长的问题。
图3为本发明中的降压型直流-直流转换器300在一个实施例中的电路原理图。如图3所示的，所述降压型直流-直流转换器300包括输出电路310、电压反馈电路320、放电通路330、放电控制电路340、纹波产生电路350、电流零点检测电路360、第一比较器(或称PWM比较器)370、导通时间信号发生电路380、逻辑电路390、斜坡电压产生电路410、第一驱动电路420和第二驱动电路430。
所述输出电路310用于将输入电压VIN转换成输出电压Vout。在一个实施例中，所述输出电压Vout低于所述输入电压VIN，因此可以将其称之为降压型直流-直流转换器。如图3所示，在一个实施例中，所述输出电路310包括串联 于输入端和接地端之间的第一功率晶体管HSD_FET和第二功率晶体管LSD_FET，第一功率晶体管HSD_FET和第二功率晶体管LSD_FET之间的节点被称为中间节点SW。所述输出电路310包括输入端和输出端，所述输入端接收输入电压VIN，所述输出端提供输出电压Vout，输入端也可以被标记为VIN，输出端也可以被标记为Vout。所述输出电路310还可以包括电感L和输出电容Co，第一功率晶体管HSD_FET和第二功率晶体管LSD_FET被控制的交替的导通以实现电压转换。作为一个基本原则，第一功率晶体管HSD_FET和第二功率晶体管LSD_FET不会同时导通，即第一功率晶体管HSD_FET导通时，第二功率晶体管LSD_FET截止，第二功率晶体管LSD_FET导通时，第一功率晶体管HSD_FET截止。优选的，所述电感L可以被设置于芯片外，而其他电路部分可以被集成于芯片内。
所述电压反馈电路320用于基于所述输出电压Vout得到反馈电压VFB。如图3所示，在一个实施例中，所述电压反馈电路320包括串联于所述输出电压Vout和地之间的两个分压电阻Rf1和Rf2，两个分压电阻的中间节点的电压为所述反馈电压VFB。所述反馈电压VFB能够反应所述输出电压Vout的大小。
所述放电通路330耦接于输出电路和接地端之间且可以受控放电。如图3所示，在一个实施例中，所述放电通路330包括串联于输出电路的中间节点SW和地GND之间的第一电阻R1和放电开关S1。在另一个实施例中，所述放电通路330也可以耦接于输出端Vout，可以起到同样的效果。由于电感L1位于芯片外，因此所述放电通路330通常耦接于所述中间节点，需要注意的是，这里的耦接包括直接和间接相连。
所述放电控制电路340在所述电压反馈电路320得到的反馈电压VFB大于第二参考电压VREF_2且第一功率晶体管HSD_FET截止时控制所述放电通路330放电，在所述电压反馈电路320得到的反馈电压VFB小于第二参考电压VREF_2或第一功率晶体管HSD_FET导通时控制所述放电通路330禁止放电。在一个实施例中，所述放电控制电路340通过控制所述放电开关S1导通来控制所述放电通路330放电，所述放电控制电路340通过控制所述放电开关S1断开来控制所述放电通路330禁止放电。第二参考电压VREF_2大于第一参考电压VREF_1，比如等于VREF_1*104％，其中VREF_1为第一参考电压，其在后文会被详细介绍。
如图3所示的，所述放电控制电路340包括第二比较器341和放电控制逻辑电路342。所述第二比较器341用于比较所述反馈电压VFB和所述第二参考电压VREF_2，并将比较结果提供给所述放电控制逻辑电路342，所述放电控制逻辑电路342基于所述第一功率晶体管HSD_FET的控制信号(信号PWM和信号HSD_ON)和第二比较器341的比较结果控制所述放电通路330。
所述纹波产生电路350用于产生反映所述输出电路310中的电感L的电流I L的大小的纹波电压Vrip。所述中间节点SW的电流与电感L的电流I L的大小一致，因此优选的可以利用所述中间节点SW的电流来表征电感L的电流I L，在本文中的有时也用中间节点SW的电流来替代电感L的电流I L来进行说明。具体的，所述纹波产生电路350通过检测所述中间节点SW的电流得到所述纹波电压Vrip。所述纹波电压Vrip的波形与所述电感L的电流I L的波形一致。所述电流零点检测电路360用于检测中间节点SW的电流的零点并产生电流零点信号ZERO_CURT。
斜坡电压产生电路410在第一功率晶体管HSD_FET从导通切换至截止时，产生电压从初始电压逐渐增大的斜坡电压Vslople，在所述电流零点检测电路360检测到中间节点SW的电流到达零点时，所述斜坡电压Vslople逐渐减小至初始电压。如图5所示的，图1中的现有斜坡电压产生电路产生的斜坡电压Vslople在中间节点SW的电流到达零点时还会继续逐渐升高直到最大值Vslople_max(如图5的虚线部分)，而本发明中的斜坡电压Vslople在中间节点SW的电流到达零点时则会逐渐下降至初始电压。具体的，所述初始电压可以是0。
第一比较器(或称PWM比较器)370包括第一比较输入端和第二比较输入端。第一比较输入端接收所述斜坡电压Vslople与第一参考电压VREF_1相加后得到的第一电压和Vslople+VREF_1，第二比较输入端接收所述纹波电压Vrip与所述反馈电压VFB相加后得到的第二电压和Vrip+VFB。基于第一比较器370的比较结果PWM(也可以被称为PWM控制信号)控制第一功率晶体管HSD_FET和第二功率晶体管LSD_FET的导通和截止。另外，在所述电流零点检测电路360检测到中间节点SW的电流I L(或称电感的电流)到达零点时，所述第二功率晶体管LSD_FET被控制的截止，直到下一个周期第一功率晶体管导通时间结束后，第二功率晶体管LSD_FET才重新导通。
所述导通时间信号发生电路380根据第一比较器370的比较结果产生预定导通时长控制信号Ton，其中在第一比较器370的比较结果PWM为从无效跳变为有效时，所述预定导通时长控制信号Ton跳变为有效，持续预定导通时长后跳变为无效。预定导通时长可以通过计时器计时得到。所述导通时间信号发生电路380也可以被称为导通时间单触发(T ON One-Shot)电路。这里有效和无效是指两个逻辑电平状态，通常有效的逻辑电平是指导致第一功率晶体管导通的逻辑电平，无效的逻辑电平是指导致第一功率晶体管截止的逻辑电平。
逻辑电路390根据导通时间信号发生电路的预定导通时长控制信号Ton、PWM控制信号和电流零点信号ZERO_CURT产生控制第一功率晶体管的第一控制信号HSD_ON和控制第二功率晶体管的第二控制信号LSD_ON。其中，在预定导通时长控制信号Ton为有效时，输出第一控制信号HSD_ON控制第一功率晶体管HSD_FET导通，输出第二控制信号控制第二功率晶体管LSD_FET截止。在预定导通时长控制信号Ton为无效时，输出第一控制信号HSD_ON控制第一功率晶体管HSD_FET截止，在预定导通时长控制信号Ton为无效且中间节点SW的电流未到零点时，输出第二控制信号控制第二功率晶体管LSD_FET导通，在预定导通时长控制信号为无效且中间节点SW的电流达到零点时，输出第二控制信号控制第二功率晶体管LSD_FET截止。
第一驱动电路420基于第一控制信号驱动第一功率晶体管HSD_FET的导通和截止。第二驱动电路430基于第二控制信号驱动第二功率晶体管LSD_FET的导通和截止。
如图3所示，所述放电控制逻辑电路342基于第一比较器的比较结果PWM、第二比较器的比较结果VFB_H和逻辑电路输390出的第一控制信号HSD_ON控制所述放电通路330。具体的，所述放电控制逻辑电路342基于第一比较器的比较结果PWM的无效至有效的跳边沿确定第一功率晶体管是否开始导通，基于逻辑电路输390出的第一控制信号HSD_ON的有效至无效的跳变沿确定第一功率晶体管是否开始截止，进而控制所述放电开关S1的导通或断开。原则上，所述放电开关S1应该在第一功率晶体管导通之前被断开，在第一功率晶体管截止之后才能导通。
图8为图3中的放电控制逻辑电路342在一个实施例中的电路图。所述放电控制逻辑电路342包括非门NOT1和NOT2、与门AND1和AND2，以及D 触发器，其连接关系如图8。
图4为图3中的斜坡电压产生电路410在一个实施例中的电路图。如图4所示的，所述斜坡电压产生电路410包括：电容C41、充电电流源I 1、斜坡电压输出电路411、与所述电容C41并联的释放通路412以及充电控制电路413。
所述斜坡电压输出电路411基于所述电容C41的储能电压得到并输出斜坡电压Vslople。充电控制电路413在第一功率晶体管HSD_FET从导通切换至截止(即第一控制信号HSD_ON从有效跳变至无效时，比如从高电平跳变为低电平)时，控制第三开关S3和S4断开，所述充电电流源I 1给所述电容C41充电，如图5所述的，从T1时刻开始，Vslople逐渐升高，而此时电感电流I L逐渐降低，在所述电流零点检测电路360检测到中间节点SW的电流到达零点时，即T2时刻，所述释放通路412导通给所述电容C41放电逐渐到达0。所述释放通路412包括第一释放支路和第二释放支路。第一释放支路包括串联的第一放电电流源I 2和第一释放开关S 41，第二释放支路包括串联的第二放电电流源I 3和第二释放开关S 2。第一释放开关S 41由电流零点信号ZERO_CURT控制，第二释放开关S 2由电流零点信号ZERO_CURT经过延迟单元后控制。充电控制电路413在第一功率晶体管HSD_FET从截止切换至导通(即第一控制信号HSD_ON从无效跳变至有效时，比如从低电平跳变为高电平)时，控制第三开关S3和S4导通，将所述电容C41的电压彻底释放到0。
所述斜坡电压输出电路411包括：NMOS晶体管MN1、MN2，PMOS晶体管MP1，MP2，电阻R41和R42。MN1的源级与电容C41相连，其栅级与MN2的栅极和MN1的漏级相连，MN1的漏级与充电电流源I 1相连。MN2的源级通过电阻R41接地，MN2的漏级与MP1的漏级和栅极相连，MP1的栅极与MP2的栅极相连，MP1和MP2的源级接电源，MP2的漏级通过电阻R42接地，R42的非接地端为输出端。
图5为图3中的COT降压型直流-直流转换器和和图4中的斜坡电压产生电路的部分信号的时序图。如图5所示的，第一控制信号HSD_ON为高电平时，第一功率晶体管导通，第二功率晶体管截止，此时中间节点SW的电压为高，电感L的电流I L，即中间节点SW的电流逐渐增大，此时图4中的开关S3和S4导通，Vslope为0。第一控制信号HSD_ON跳变为低电平时，第一功率晶体管截止，第二功率晶体管导通，此时中间节点SW的电压为0，电感L的电 流I L逐渐减小直到0，此时图4中的开关S3和S4断开，Vslope逐渐增大。电感L的电流I L到达0时，在电流零点信号ZERO_CURT跳变为高电平，此时开关S41和S2先后导通，所述释放通路412导通给所述电容C41放电逐渐到达0。
在本发明中，在第一功率晶体管处于关断的相位，当电感L的电流减到零时，即保持斜坡量基本恒定，经过大约0.5us即将斜坡量慢慢降低，直至零。在本发明中，在轻载条件下，第一功率晶体管导通时，斜坡电压Vslope已经降为零。因此当满足以下方程时，
VFB+Vrip<VREF_1
即
VFB<VREF_1-Vrip
显然，在轻载下，VFB要低于传统的方案，也即轻载下输出电压要低于传统方案，这样也就能提高输出电压精度。
图6为本发明中的COT降压型直流-直流转换器的输出电压和负载电流波形，从图可知，当负载电流从0变化至3A时，输出电压大约变化为1.02V～1.01V。
图7为图1中的传统的COT降压型直流-直流转换器的输出电压和负载电流波形，从图可知当负载电流从0变化至3A时，输出电压大约变化为1.038V～1.01V。显然，本发明明显改善了输出的负载调整率，提高了输出电压的精度。
当负载大电流突然降为零时，输出电压Vout会有很大过冲，而且电荷没有释放路径，这样输出端的高电压会维持很长一段时间。
而在本发明中，当输出电压Vout超出额定电压的4％(第一参考电压对应于输出电压为额定电压)之后，且信号HSD_ON为低时，即会开启输出端Vout的放电通路，即图3中的开关S1。当PWM信号变低时，意味着要开启第一功率晶体管时，即关断图3中的开关S1，
通常图3中的R1电阻可以根据需要而设定其取值。本发明中图3的R1可以约为110ohm，当过冲约为200mV,输出电容Co为40uF，泄放电流约为9.1mA，输出恢复到设定值1V时，所需时间为：
Figure PCTCN2021087523-appb-000001
如果不采取本发明的方式，只能通过图3中的反馈电阻Rf1和Rf2放电。为了减少系统的静态功耗，电阻Rf1和Rf2不会太小，其电流通常控制在70uA，甚至更低。
Figure PCTCN2021087523-appb-000002
图10为图1中的传统的COT降压型直流-直流转换器的输出电压过冲及恢复波形，在经历约8ms后，输出电压仍维持在1.186V。
本发明具有如下优势中的一个或多个：
1)针对传统COT降压型直流-直流转换器的输出电压精度较差的问题，找出其原因，即斜波补偿在轻载时过大，导致输出电压偏高。本发明在低位功率管(第二功率晶体管)为零时，逐步降低斜波补偿量直至零。这样就消除了斜波补偿量在轻载时造成输出电压往上漂的影响，改善了系统的负载调整率。
2)通常大电流降压型直流-直流转换器，负载由重载瞬间跳变为轻载或空载时，输出电压都会有较大过冲，而且过冲持续的时间比较长。在本发明中，当输出电压超出设定值4％，且高位功率管(第一功率晶体管)时关断状态时，即开启电流泄放通路(即放电通路330)。当输出电压恢复到设定值，高位功率管即将开启时，则关断电流泄放通路(即放电通路330)。这样就极大的减少了输出电压的过冲持续时间。这样就可以不依赖于较小的输出反馈电阻来泄放电流。可以使用较大的输出反馈电阻，以减小系统的静态电流。
在本发明中，“连接”、“相连”、“连”、“接”、“耦接”等表示电性连接的词语，如无特别说明，则表示直接或间接的电性连接，所述间接连接包括通过电阻、电容、电感、晶体管、滤波器等电子元器件或单元连接。
以上所述仅为本发明的较佳实施方式，本发明的保护范围并不以上述实施方式为限，但凡本领域普通技术人员根据本发明揭示内容所作的等效修饰或变化，皆应纳入权利要求书中记载的保护范围内。

Claims (10)

  1. 一种降压型直流-直流转换器，其特征在于，其还包括：
    输出电路，其用于将输入电压转换成输出电压，其包括串联于输入端和接地端之间的第一功率晶体管和第二功率晶体管；
    电压反馈电路，用于基于所述输出电压得到反馈电压；
    纹波产生电路，用于产生与电感的电流有关的纹波电压；
    电流零点检测电路，其用于检测电感的电流的零点并产生电流零点信号；
    斜坡电压产生电路，其在第一功率晶体管从导通切换至截止时，产生电压从初始电压逐渐增大的斜坡电压，在所述电流零点检测电路检测到电感的电流到达零点时，使得所述斜坡电压逐渐减小至初始电压；
    第一比较器，其包括第一比较输入端和第二比较输入端，第一比较输入端接收所述斜坡电压与第一参考电压相加后得到的第一电压和，第二比较输入端接收所述纹波电压与所述反馈电压相加后得到的第二电压和，
    基于第一比较器的比较结果控制第一功率晶体管和第二功率晶体管的导通和截止，第一功率晶体管和第二功率晶体管不会同时导通，另外在所述电流零点检测电路检测到电感的电流到达零点时，控制所述第二功率晶体管截止。
  2. 如权利要求1所述的降压型直流-直流转换器，其特征在于，其还包括：
    耦接于输出电路和接地端之间的放电受控的放电通路；
    放电控制电路，其在所述电压反馈电路得到的反馈电压大于第二参考电压且第一功率晶体管截止时控制所述放电通路对所述输出电路进行放电，在所述电压反馈电路得到的反馈电压小于第二参考电压或第一功率晶体管导通时控制所述放电通路禁止放电
  3. 如权利要求2所述的降压型直流-直流转换器，其特征在于，
    所述放电通路包括串联于输出电路和接地端之间的第一电阻和放电开关，所述放电控制电路通过控制所述放电开关导通来控制所述放电通路放电，所述放电控制电路通过控制所述放电开关断开来控制所述放电通路禁止放电。
  4. 如权利要求2所述的降压型直流-直流转换器，其特征在于，所述放电控制电路包括第二比较器和放电控制逻辑电路，所述第二比较器用于比较所述反馈电压和所述第二参考电压，并将比较结果提供给所述放电控制逻辑电路，所述放电控制逻辑电路基于所述第一功率晶体管的控制信号和第二比较器的比较 结果控制所述放电通路。
  5. 如权利要求2所述的降压型直流-直流转换器，其特征在于，第一功率晶体管和第二功率晶体管之间的节点被称为中间节点，所述放电通路耦接于中间节点和接地端之间。
  6. 如权利要求1所述的降压型直流-直流转换器，其特征在于，其还包括：
    导通时间信号发生电路，其根据第一比较器的比较结果以及预定导通时长产生预定导通时长控制信号，其中在第一比较器的比较结果为从无效跳变为有效时，所述预定导通时长控制信号跳变为有效，持续预定导通时长后跳变为无效；
    逻辑电路，其根据导通时间信号发生电路的预定导通时长控制信号和所述电流零点信号产生控制第一功率晶体管的第一控制信号和控制第二功率晶体管的第二控制信号，其中在预定导通时长控制信号为有效时控制第一功率晶体管导通，第二功率晶体管截止，在预定导通时长控制信号为无效时控制第一功率晶体管截止，在预定导通时长控制信号为无效且电感的电流未到零点时控制第二功率晶体管导通，在预定导通时长控制信号为无效且电感的电流达到零点时控制第二功率晶体管截止；
    第一驱动电路，其基于第一控制信号驱动第一功率晶体管的导通和截止；
    第二驱动电路，其基于第二控制信号驱动第二功率晶体管的导通和截止。
  7. 如权利要求1所述的降压型直流-直流转换器，其特征在于，所述斜坡电压产生电路包括：电容C41、充电电流源、斜坡电压输出电路、与所述电容C41并联的释放通路和充电控制电路，
    充电控制电路，其在第一功率晶体管从导通切换至截止时，使得所述充电电流源给所述电容C41充电，在所述电流零点检测电路检测到电感的电流到达零点时，所述释放通路导通给所述电容C41放电，
    所述斜坡电压输出电路基于所述电容C41的储能电压得到并输出斜坡电压。
  8. 如权利要求7所述的降压型直流-直流转换器，其特征在于，所述释放通路包括：第一释放支路和第二释放支路，
    第一释放支路包括串联的第一放电电流源和第一释放开关，
    第二释放支路包括串联的第二放电电流源和第二释放开关，
    第一释放开关由电流零点信号控制，第一释放开关由电流零点信号经过延迟单元后控制。
  9. 如权利要求7所述的降压型直流-直流转换器，其特征在于，所述斜坡电压输出电路包括：NMOS晶体管MN1、MN2，PMOS晶体管MP1，MP2，电阻R41和R42，MN1的源级与电容C41相连，其栅级与MN2的栅极和MN1的漏级相连，MN1的漏级与充电电流源I 1相连，MN2的源级通过电阻R41接地，MN2的漏级与MP1的漏级和栅极相连，MP1的栅极与MP2的栅极相连，MP1和MP2的源级接电源，MP2的漏级通过电阻R42接地，R42的非接地端为输出端输出所述斜坡电压。
  10. 如权利要求1所述的降压型直流-直流转换器，其特征在于，第一功率晶体管和第二功率晶体管之间的节点被称为中间节点SW，所述输出电路还包括连接于中间节点SW和输出端之间的电感L，所述电流零点检测电路通过检测中间节点SW的电流得到电感的电流，并进而检测电感的电流的零点。
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115313830A (zh) * 2022-08-16 2022-11-08 圣邦微电子（北京）股份有限公司 Dc-dc变换器
CN117394661A (zh) * 2023-12-07 2024-01-12 杰华特微电子股份有限公司 导通时间产生电路及开关转换器

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111817562B (zh) * 2020-07-08 2021-06-22 无锡力芯微电子股份有限公司 降压型直流-直流转换器
CN112653333B (zh) * 2020-12-18 2021-10-08 电子科技大学 一种dc-dc变换器的数模混合控制电路和控制方法
CN113067476B (zh) * 2021-03-08 2022-04-15 无锡力芯微电子股份有限公司 一种acot降压型转换器
CN115378258B (zh) * 2022-10-26 2023-03-24 苏州浪潮智能科技有限公司 一种服务器及其直流降压电路的补偿电路

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103683935A (zh) * 2013-12-03 2014-03-26 成都芯源系统有限公司 一种开关模式电源及其控制电路和控制方法
CN104319998A (zh) * 2014-09-29 2015-01-28 矽力杰半导体技术(杭州)有限公司 一种开关电源控制电路、开关电源及控制方法
CN105262329A (zh) * 2014-11-19 2016-01-20 成都芯源系统有限公司 恒定导通时间控制的开关变换器及其控制器和控制方法
US20170346396A1 (en) * 2014-05-14 2017-11-30 Cirel Systems Private Limited Accurate zero current detector circuit in switching regulators
CN111817563A (zh) * 2020-07-08 2020-10-23 无锡力芯微电子股份有限公司 降压型直流-直流转换器
CN111817562A (zh) * 2020-07-08 2020-10-23 无锡力芯微电子股份有限公司 降压型直流-直流转换器

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4902390B2 (ja) * 2007-02-17 2012-03-21 セイコーインスツル株式会社 カレント検出回路及び電流モード型スイッチングレギュレータ
CN102377342B (zh) * 2011-08-12 2015-08-26 成都芯源系统有限公司 直流到直流变换电路的控制电路和控制方法
TWI496402B (zh) * 2013-07-29 2015-08-11 Anpec Electronics Corp 電流式降壓轉換器及使用其之電子系統
CN203632550U (zh) * 2013-12-03 2014-06-04 成都芯源系统有限公司 一种开关模式电源及其控制电路
CN203674982U (zh) * 2013-12-30 2014-06-25 成都芯源系统有限公司 恒定导通时长控制的开关电源及其控制电路
CN104079167A (zh) * 2014-07-07 2014-10-01 矽力杰半导体技术(杭州)有限公司 控制电路、开关电源和控制方法
US10374514B2 (en) * 2014-11-05 2019-08-06 Qualcomm Incorporated Boost converters having self-adaptive maximum duty-cycle-limit control
CN105356734B (zh) * 2015-11-18 2017-12-22 浙江大学 一种基于COT控制含纹波补偿的Buck电路电源管理芯片
JP6832697B2 (ja) * 2016-01-22 2021-02-24 ローム株式会社 スイッチング電源回路、負荷駆動装置、液晶表示装置
US9806617B1 (en) * 2016-09-09 2017-10-31 Dialog Semiconductor (Uk) Limited Switch mode power converter with overshoot and undershoot transient control circuits
US10418907B1 (en) * 2018-06-18 2019-09-17 M3 Technology Inc. Control circuit and method for switching power converters
US10581325B1 (en) * 2018-11-07 2020-03-03 Texas Instruments Incorporated Power converter with slope compensation

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103683935A (zh) * 2013-12-03 2014-03-26 成都芯源系统有限公司 一种开关模式电源及其控制电路和控制方法
US20170346396A1 (en) * 2014-05-14 2017-11-30 Cirel Systems Private Limited Accurate zero current detector circuit in switching regulators
CN104319998A (zh) * 2014-09-29 2015-01-28 矽力杰半导体技术(杭州)有限公司 一种开关电源控制电路、开关电源及控制方法
CN105262329A (zh) * 2014-11-19 2016-01-20 成都芯源系统有限公司 恒定导通时间控制的开关变换器及其控制器和控制方法
CN111817563A (zh) * 2020-07-08 2020-10-23 无锡力芯微电子股份有限公司 降压型直流-直流转换器
CN111817562A (zh) * 2020-07-08 2020-10-23 无锡力芯微电子股份有限公司 降压型直流-直流转换器

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
NIE WEIDONG;LIU YINGYING;HAN HAIQING;DONG HUAIPENG;WU JIN;YU ZONGGUANG: "A Synchronous Buck DC-DC Converter with Automatic Switching of Zero-Crossing Current", MICROELECTRONICS, vol. 43, no. 6, 20 December 2013 (2013-12-20), pages 782 - 787, XP055886517, ISSN: 1004-3365 *

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115313830A (zh) * 2022-08-16 2022-11-08 圣邦微电子（北京）股份有限公司 Dc-dc变换器
CN115313830B (zh) * 2022-08-16 2024-05-14 圣邦微电子（北京）股份有限公司 Dc-dc变换器
CN117394661A (zh) * 2023-12-07 2024-01-12 杰华特微电子股份有限公司 导通时间产生电路及开关转换器
CN117394661B (zh) * 2023-12-07 2024-03-22 杰华特微电子股份有限公司 导通时间产生电路及开关转换器

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