WO2022002269A1 - 一种数据传输方法及装置 - Google Patents

一种数据传输方法及装置 Download PDF

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Publication number
WO2022002269A1
WO2022002269A1 PCT/CN2021/104375 CN2021104375W WO2022002269A1 WO 2022002269 A1 WO2022002269 A1 WO 2022002269A1 CN 2021104375 W CN2021104375 W CN 2021104375W WO 2022002269 A1 WO2022002269 A1 WO 2022002269A1
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Prior art keywords
different
equalizer
differential transmission
binary bit
bit streams
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PCT/CN2021/104375
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English (en)
French (fr)
Inventor
陆玉春
黄志雷
臧大军
莫道春
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华为技术有限公司
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Publication of WO2022002269A1 publication Critical patent/WO2022002269A1/zh

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/0264—Arrangements for coupling to transmission lines
    • H04L25/0272—Arrangements for coupling to multiple lines, e.g. for differential transmission
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
    • H04B10/40—Transceivers
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks

Definitions

  • the present application relates to the field of communication technologies, and in particular, to a data transmission method and apparatus.
  • differential signals In high-speed electrical interconnection systems, data streams are generally transmitted in the form of differential signals.
  • the differential signal refers to the signal with the same amplitude and opposite phase, it can be called a positive signal and a negative signal respectively.
  • the sending system A can send a signal to the system B through a differential transmission line, wherein the signal transmitted in the differential transmission line is a differential signal.
  • the positive signal and the negative signal are subtracted to obtain the signal sent by the transmitting system.
  • transmission line 1 and transmission line 2 shown in FIG. 1 carry exactly the same information, resulting in low utilization of the transmission line.
  • the present application provides a data transmission method and device, which can effectively improve the efficiency of system transmission of information.
  • an embodiment of the present application provides a data transmission method, and the method can be executed by a communication device, and the communication device can be a wired device, such as a router, a switch, or an optical transport network (optical transport network, OTN) transmission device.
  • the communication device may also be a device including any type of interface, such as a general computer interface, an OTN interface, a peripheral component interconnect express (PCIE) interface, an Ethernet interface, or a serializer/deserializer (serializer/deserializer) deserializer, SerDes) interface, etc.
  • PCIE peripheral component interconnect express
  • SerDes serializer/deserializer
  • the communication device may also be any type of chip (or may also be referred to as a circuit system, a chip system, etc.), such as a mobile phone chip, a central processing unit (CPU) chip, or any chip that requires a high-speed communication interface, etc. .
  • a mobile phone chip a central processing unit (CPU) chip
  • CPU central processing unit
  • the communication device as the transmitting end as an example, and the method includes:
  • the differential transmission line transmits the two different analog signals, one of the differential transmission lines corresponds to one analog signal, and the differential transmission lines share one ground line.
  • the above-mentioned obtaining two different binary bit streams includes: obtaining two different binary bit streams through a two-channel distributor.
  • the sending end may split the original binary data stream (or may also be referred to as an original binary bit stream, etc.) through a two-channel distributor to obtain two different binary bit streams. That is, the above-mentioned two different binary bit streams may be part of the original binary data stream. It is understandable that the embodiment of the present application does not limit whether the above-mentioned two different binary bit streams are half of the original binary data stream. However, in order to improve the data transmission efficiency, the above two different binary bit streams may be half of the original binary data stream. As for how the two-way distributor splits the original binary data stream, the embodiment of the present application does not limit it.
  • the method further includes: performing equalization processing on the result output by the modulator through a butterfly equalizer; processing the result output by the modulator through a digital-to-analog converter to obtain two different analog signals includes: using a digital-to-analog converter Process the output of the butterfly equalizer to obtain two different analog signals.
  • the transmitting end performs equalization processing on the result output by the modulator through the butterfly equalizer, and can perform mutually coupled pre-emphasis on the result output by the modulator. To a certain extent, it compensates for the undesired situations such as signal broadening and mutual interference between two signals in the differential transmission line, so that the quality of the signal equalized by the butterfly equalizer at the receiving end is better.
  • the two different binary bit streams come from the same data packet or control packet. It can also be understood as: the original binary data stream is the binary data stream of the data message; or the binary data stream of the control message, etc.
  • an embodiment of the present application provides a data transmission method, which can be executed by a communication device.
  • the following description will be given by taking the communication device as the receiving end as an example, and the method includes:
  • Two different analog signals are received through a differential transmission line, one of the differential transmission lines corresponds to one analog signal, and the differential transmission line shares a ground wire; then the analog-to-digital converter is used to process the two different analog signals to obtain two channels.
  • different digital signals equalize the two different digital signals through a butterfly equalizer; and demodulate the output result of the butterfly equalizer through a demodulator to obtain two different binary bit streams.
  • the method further includes: combining two different binary bit streams through a dual-channel combiner to obtain a binary data stream.
  • an original binary data stream can be obtained.
  • a butterfly equalizer is used to reduce interference between two different digital signals.
  • the butterfly equalizer can use to reduce this interference.
  • the above-mentioned receiving two channels of different analog signals through the differential transmission line includes: when the operating mode of the butterfly equalizer is the first mode, receiving two channels of different mode signals through the differential transmission line.
  • the operating mode of the butterfly equalizer is the second mode
  • the same information can be transmitted on the differential transmission line.
  • differential signals with the same amplitude and opposite phases may be transmitted on the differential transmission line.
  • the embodiments of the present application can change the working mode of the butterfly equalizer under the condition that the differential transmission line remains unchanged, so as to realize the switching of the same information or different information transmitted by the differential transmission line, so as to ensure the compatibility of the system.
  • the method further includes: inputting the result outputted by the butterfly equalizer to the decider; feeding back the result outputted by the decider to the butterfly equalizer; the above-mentioned outputting the butterfly equalizer through the demodulator
  • Demodulating the result of the determinator to obtain two different binary bit streams includes: processing the result output by the decider through the demodulator to obtain two different binary bit streams.
  • the method further includes: performing equalization processing on the result output by the butterfly equalizer again through the equalizer; and demodulating the result output by the butterfly equalizer through the demodulator to obtain two different binary bit streams
  • the method includes: demodulating the output result of the equalizer through a demodulator to obtain two different binary bit streams.
  • the equalizer may include one or more of DFE, MLSE, PR, or decider, and the like.
  • the method further includes: The result output by the equalizer is processed; the above-mentioned demodulating the result output by the butterfly equalizer by the demodulator to obtain two different binary bit streams includes: demodulating the result output by the decider by the demodulator , to obtain two different binary bit streams.
  • the above-mentioned decider may also be replaced with any one or more of the following: a decision feedback equalizer DFE, a partial response PR, or a maximum likelihood sequence estimation MLSE.
  • a decision feedback equalizer DFE a partial response PR
  • a maximum likelihood sequence estimation MLSE a maximum likelihood sequence estimation MLSE.
  • the demodulator can demodulate the result output by the MLSE.
  • the decider is replaced with a PR
  • the demodulator can demodulate the result output by the PR.
  • the result output by the butterfly equalizer can be input to the DFE and MLSE in sequence, and in this case, the demodulator can demodulate the result output by the MLSE.
  • any one or more of the decision feedback equalizer DFE, the partial response PR, or the maximum likelihood sequence estimation MLSE can also be used for
  • the results output by the butterfly equalizer are processed, which will not be described in detail here.
  • the result output by the decider may also be fed back to the butterfly equalizer.
  • an embodiment of the present application provides a communication device, where the communication device includes:
  • a two-way distributor is used to obtain two different binary bit streams; a modulator is used to modulate the two different binary bit streams; a digital-to-analog converter is used to process the results output by the modulator to obtain Two different analog signals; differential transmission interface, used to send the two different analog signals, the two different analog signals are transmitted through differential transmission lines, one transmission line in the differential transmission line corresponds to one analog signal, and the differential transmission line share a ground wire.
  • the communication device further includes: a butterfly equalizer, for performing equalization processing on the result output by the modulator; and a digital-to-analog converter, specifically for performing equalization on the result output by the butterfly equalizer processing to obtain two different analog signals.
  • an embodiment of the present application provides a communication device, where the communication device includes:
  • the differential transmission interface is used to receive two different analog signals transmitted through the differential transmission line.
  • One transmission line in the differential transmission line corresponds to one analog signal, and the differential transmission line shares one ground wire; the analog-to-digital converter is used for the two channels.
  • Different analog signals are processed to obtain two different digital signals; a butterfly equalizer is used to equalize the two different digital signals; a demodulator is used to perform equalization on the output result of the butterfly equalizer. demodulate to obtain two different binary bit streams.
  • the communication device further includes: a dual-channel combiner, configured to combine two different binary bit streams to obtain a binary data stream.
  • the butterfly equalizer is used to reduce the interference between the two different digital signals.
  • the differential transmission interface is specifically used to receive two different mode signals when the operating mode of the butterfly equalizer is the first mode.
  • the communication device further includes: a decider, configured to process a result output by the butterfly equalizer, and feed back the result output by the decider to the butterfly equalizer; a demodulator, specifically It is used to process the result output by the judger to obtain two different binary bit streams.
  • the above-mentioned communication device may further include an equalizer, a processor, a memory, and the like, and other components included in the communication device are not limited in this embodiment of the present application.
  • the equalizer here may be used to perform equalization processing again on the result output by the butterfly equalizer, and the embodiment of the present application does not limit the specific type of the equalizer.
  • an embodiment of the present application provides a communication apparatus, configured to execute the method in the first aspect or any possible implementation manner of the first aspect.
  • the communication apparatus includes corresponding means for performing the method of the first aspect or any possible implementation of the first aspect.
  • the communication device includes corresponding means for performing the method of the second aspect or any possible implementation of the second aspect.
  • the communication device may include a transceiving unit and a processing unit.
  • the present application provides a computer-readable storage medium, where the computer-readable storage medium is used to store a computer program, and when the computer program is executed, the above-mentioned first aspect or any possible implementation manner of the first aspect can be The method shown is implemented. Alternatively, when the computer program is executed, the method shown in the above-mentioned second aspect or any possible implementation manner of the second aspect is realized.
  • the present application provides a computer program product, the computer program product includes a computer program or computer code, when the computer program or computer code is executed, the above-mentioned first aspect or any possible implementation manner of the first aspect is achieved.
  • the method shown is implemented.
  • the method shown in the above-mentioned second aspect or any possible implementation manner of the second aspect is realized.
  • the present application provides a computer program for implementing the method shown in the first aspect or any possible implementation manner of the first aspect. Alternatively, it is used to implement the method shown in the second aspect or any possible implementation manner of the second aspect.
  • the present application provides a communication system, the communication system includes a sending end and a receiving end, the sending end is configured to execute the method shown in the first aspect or any possible implementation manner of the first aspect, the receiving end For performing the method shown in the second aspect or any possible implementation manner of the second aspect.
  • FIG. 1 is a schematic diagram of transmission of a differential signal provided by an embodiment of the present application
  • 2a is a schematic structural diagram of a differential transmission line provided by an embodiment of the present application.
  • 2b is a schematic structural diagram of a differential transmission line provided by an embodiment of the present application.
  • 3a to 3e are schematic structural diagrams of five types of butterfly equalizers provided by embodiments of the present application.
  • 4a is a schematic flowchart of a data transmission method provided by an embodiment of the present application.
  • 4b is a schematic diagram of a communication system provided by an embodiment of the present application.
  • Figure 4c is a schematic diagram of signals at a, b and c in Figure 4b;
  • 4d is a schematic diagram of a data transmission system provided by an embodiment of the present application.
  • 5a to 5e are schematic structural diagrams of five communication systems provided by embodiments of the present application.
  • 6a is a schematic structural diagram of a communication system provided by an embodiment of the present application.
  • 6b is a schematic diagram of a data transmission system provided by an embodiment of the present application.
  • FIG. 7 is a schematic structural diagram of a communication device provided by an embodiment of the present application.
  • FIG. 8 is a schematic structural diagram of a communication device provided by an embodiment of the present application.
  • FIG. 9 is a schematic structural diagram of a communication apparatus provided by an embodiment of the present application.
  • At least one (item) means one or more
  • plural means two or more
  • at least two (item) means two or three and three
  • “and/or” is used to describe the relationship of related objects, indicating that there can be three kinds of relationships, for example, "A and/or B” can mean: only A exists, only B exists, and both A and B exist three a situation.
  • the character “/” generally indicates that the associated objects are an “or” relationship.
  • At least one of the following” or similar expressions refers to any combination of these items. For example, at least one (a) of a, b or c, can mean: a, b, c, "a and b", “a and c", “b and c", or "a and b and c" ".
  • Differential transmission line A transmission line composed of two transmission lines sharing a ground wire.
  • Differential transmission lines can exist in the form of cables, connectors, or printed circuit board (PCB) wiring.
  • the two transmission lines in a differential transmission line can be two lines of equal length, equal width, close proximity, and on the same level.
  • FIG. 2a and FIG. 2b are respectively schematic structural diagrams of a differential transmission line provided by the present application.
  • the conductor S1 and the conductor S2 shown in FIG. 2a are transmission lines in the differential transmission line, respectively. It can also be seen from FIG. 2a that the two transmission lines share a ground line.
  • FIG. 2b shows a modified differential transmission line, the differential transmission line includes four transmission lines, and the four transmission lines share a ground line. It can be understood that what is shown in FIG.
  • the combined diameter of the conductor and the insulating medium of one transmission line may be 0.05 mm to 20 mm.
  • the diameter of the ground wire may be 0.01mm to 10mm, and the distance between the centers of the two transmission lines may be 0.05mm to 20mm.
  • the distance between the center of the transmission line and the center of the ground line can be 0.05mm to 15mm.
  • the diameter of the entire differential transmission line may be 0.1 mm ⁇ 50 mm. It can be understood that the specific structure of the differential transmission line shown here is only an example, and in a specific implementation, there may be other sizes or types of differential transmission lines, which are not limited in this application.
  • two signals can be transmitted on the differential transmission line, and the voltage difference between the two signals and the reference ground has the same amplitude and opposite phase.
  • the signals transmitted on the differential transmission lines may be differential signals, and the information carried on the differential transmission lines may be the same.
  • the communication device obtains one signal in the differential signal, the other signal can be obtained by inversion.
  • double-speed transmission can be a signal transmission technology. Different from the traditional one signal line and one ground line, double-speed transmission can transmit signals on both transmission lines of the differential transmission line, but the two signals The amplitudes may not have the same relationship, and the phases may not have the opposite relationship. It can be understood that since the information carried in the differential transmission line is not used in this application, the method of transmitting two different analog signals through the differential transmission line may also be called double-speed transmission.
  • the communication device after acquiring the two different analog signals transmitted through the differential transmission line, the communication device can perform equalization processing through the butterfly equalizer shown in FIG. 3a, FIG. 3b or FIG. interference caused by different analog signals.
  • the transmitting end can send two different analog signals to the receiving end through a differential transmission line, and correspondingly, the receiving end can receive two different analog signals transmitted through the differential transmission line.
  • the transmitter can send two different analog signals through the differential transmission line shown in Figure 2a, and correspondingly, receive The terminal can receive two different analog signals through the differential transmission line shown in Figure 2a.
  • the transmitting end can send four different analog signals through the differential transmission line shown in Fig. 2b, and correspondingly, the receiving end can receive four different analog signals through the differential transmission line shown in Fig. 2b. different analog signals. It can be understood that, for the specific description of the four different analog signals, reference may be made to the above description of the two different analog signals, which will not be described in detail here.
  • the communication device cannot obtain another channel of analog signal by translating and/or linearly transforming one channel of analog signal. That is, after one analog signal is shifted and/or linearly transformed, another analog signal cannot be obtained.
  • the communication device acquires one analog signal among the two different analog signals, the other analog signal cannot be obtained by delaying the one analog signal; or, the one analog signal cannot be multiplied by a multiple.
  • the two different analog signals may not be symmetrical signals with equal voltages and opposite phases.
  • the two different analog signals may not be symmetrical signals with the same voltage and opposite phases at the same time.
  • the differential transmission line may include two transmission lines. It can be understood that a differential transmission line can also be called a differential signal line, and the differential signal line includes two signal lines. Alternatively, the differential transmission line may also be referred to as including two signal lines, or the like, or the differential transmission lines shown in this application may also be collectively referred to as channels, etc. The application does not limit the specific names of the differential transmission lines. It can be understood that the signal transmitted on the differential transmission line may specifically be an analog signal.
  • Butterfly equalizer It is a digital equalization system with multiple inputs and multiple outputs, and each output of the butterfly equalizer can be obtained by equalizing the signals of the multiple inputs.
  • the present application provides five types of butterfly equalizers respectively.
  • port 1 and port 3 are input ports, respectively, and ports 2 and 4 are output ports, respectively.
  • the butterfly equalizer includes four feed forward equalizers (FFE), which are respectively denoted as FFE 12 , FFE 14 , FFE 32 and FFE 34 .
  • FFE feed forward equalizers
  • the signal (such as digital signal) obtained by port 1 passes through FFE 12
  • the signal obtained by port 3 passes through FFE 32
  • the signals output by FFE 12 and FFE 32 are added by the adder, that is, the output signal of port 2 (or called for the output).
  • the signal obtained by port 1 passes through FFE 14 , the signal obtained at port 3 passes through FFE 34 , and the signals output by FFE 14 and FFE 34 are added by the adder, that is, the output signal of port 4 is obtained.
  • the second diagram in FIG. 4c is a schematic diagram of the signal before processing by the butterfly equalizer. It can be seen from Fig. 4c that after the signals are equalized by the butterfly equalizer, the digital signals output by the butterfly equalizer have almost no overlap, and are restored to almost independent signals.
  • the two outputs of the butterfly equalizer are also ideal four-level signals respectively.
  • the output result of the butterfly equalizer is still two different digital signals, but the two different digital signals can be respectively expressed as four-level signals.
  • the signal recovered by the butterfly equalizer can be determined by the output of the modulator in the transmitting end.
  • the multiplexed output of the butterfly equalizer can be similar to the output of the modulator in the transmitting end.
  • the butterfly equalizer can restore the acquired two-channel digital signals into two-level signals.
  • the butterfly equalizer can restore the acquired two-channel digital signals into 8-level signals.
  • the butterfly equalizer in FIG. 3b and FIG. 3c includes a selector (eg, the trapezoid in FIG. 3b and FIG. 3c ), and the selector can be used to control the working mode of the butterfly equalizer.
  • the selector can make the operation mode of the butterfly equalizer similar to that of FIG. 3a.
  • the working mode of the butterfly equalizer may be as shown in FIG. 3c.
  • the butterfly equalizer can be equivalent to an FFE.
  • the operation mode of the butterfly equalizer can be divided into a first mode and a second mode.
  • the output of the butterfly equalizer can be two different digital signals, because the information bit rate carried by the two different digital signals is a single channel.
  • the signal carries twice the bit rate of information, so this first mode may also be referred to as a double-speed operating mode.
  • the working mode of the butterfly equalizer is the second mode
  • the second mode may also be called the single-speed working mode.
  • the input signal of port 3 of the butterfly equalizer can be converted into a signal whose phase is opposite to that of the input signal, and then added to the signal input at port 1.
  • the input signal of port 3 of the butterfly equalizer is inverted and added to the input signal of port 1.
  • DFE decision feedback equalizer
  • DFE 4 delays the input signal and outputs it, and adds it with the outputs of FFE 12 and FFE 32 to obtain the output signal of port 2.
  • the processing capability of signal interference can be enhanced, the equalization capability of the butterfly equalizer can be improved, and the quality of the equalized signal can be improved.
  • the butterfly equalizer shown in FIG. 3e includes x inputs and x outputs. Wherein, after the x input passes through the x FFE equalizers respectively, the output results of the x FFE equalizers are added to obtain the output signal of output 1.
  • the other output principles are the same as the output principles at port 1, and are not repeated here.
  • High-speed data communication systems such as electrical interconnections on PCBs, equipment backplanes, between equipment frames, within equipment racks and between equipment core racks, are mostly differential transmission lines.
  • a differential transmission line can be used to transmit two signals with the same amplitude and opposite phases, and the information carried on the two transmission lines of the differential transmission line is the same.
  • the above data transmission method often leads to low utilization efficiency of the differential transmission line and low data transmission rate of the system.
  • the present application provides a data transmission method and device, which can transmit different information by using a differential transmission line, improve the utilization rate of the differential transmission line, and improve the rate of system data transmission.
  • the method provided by the present application can improve the transmission rate of the system on the premise that the density of the differential transmission lines and the frequency of the transmission signal on each transmission line in the differential transmission lines remain unchanged. Compared with the data transmission method shown in Figure 1, the transmission rate can be more than doubled.
  • Fig. 4a is a schematic flowchart of a data transmission method provided by an embodiment of the present application
  • Fig. 4b is a schematic diagram of a communication system corresponding to Fig. 4a
  • Fig. 4c is a schematic diagram of signals at a, b and c in Fig. 4b.
  • the method shown in FIG. 4a may be applied to a communication apparatus, and the communication apparatus may include wired equipment and the like.
  • the communication device may include a router, a switch, or an optical transport network (optical transport network, OTN) transmission device or the like.
  • OTN optical transport network
  • the communication device can also include any type of interface, such as the interface can include a general computer interface, an OTN interface, a peripheral component interconnect express (PCIE) interface, an Ethernet interface or a serialization deserializer. (serializer/deserializer, SerDes) interface, etc.
  • the communication device may also include any type of chip, for example, the chip may include a mobile phone chip, a central processing unit (CPU) chip, or any chip that requires a high-speed communication interface.
  • the data transmission method can be applied to a scenario of high-speed electrical interconnection.
  • the scenario of high-speed electrical interconnection can be understood as a higher rate of data transmission between two communication devices.
  • the data transmission method may be applied to at least two communication apparatuses, and FIG. 4a uses the transmitting end and the receiving end as examples to illustrate the method shown in the embodiment of the present application.
  • the transmitting end and the receiving end may be two communication devices connected by a differential transmission line, or may be two chips or interfaces connected by a differential transmission line, etc., which are not limited in the embodiment of the present application.
  • the data transmission method includes:
  • the sender obtains two different binary bit streams.
  • the two different binary bit streams may come from the same data or signaling.
  • the two different binary bit streams may come from the same data packet; or, from the same control packet or the like.
  • the sending end may obtain two different binary bit streams through a two-way distributor.
  • the two different binary bit streams obtained by the sender may be parts of the original binary data stream (also referred to as the original binary bit stream, etc.).
  • the sending end since the sending end needs to exchange data and/or signaling with other devices when communicating with other devices, the data and/or signaling obtained by the sending end can also be referred to as the original binary data stream (of course also may be called a raw binary bit stream).
  • the sending end may generate data and/or signaling, etc., and this embodiment of the present application does not limit how the sending end obtains the original binary data stream.
  • the two different binary bit streams obtained by the sender may be half of the original binary data stream.
  • the sender may divide the original binary data stream into two paths in turn through a demultiplexer (DeMux), for example, the first data (which may be data in binary form) of the original binary data stream is distributed to the second One binary bit stream, the second data is assigned to the second binary bit stream, the third data is assigned to the first binary bit stream, and so on.
  • DeMux demultiplexer
  • the binary bit stream shown in the embodiment of the present application may also be called a signal stream or the like, and the embodiment of the present application does not limit the specific name of the binary bit stream.
  • FIG. 5a to FIG. 5c provided by the embodiments of the present application.
  • the two different binary bit streams may also come from different data and/or signaling, such as different data packets or control packets.
  • the source of the binary bit stream is not limited. For this implementation, reference may also be made to FIG. 5d provided in the embodiment of the present application.
  • the transmitting end modulates the two different binary bit streams through the modulator.
  • the modulation mode may include pulse amplitude modulation (pulse amplitude modulation, PAM), quadrature amplitude modulation (quadrature amplitude modulation, QAM), and the like.
  • the level number of the modulated signal is the same as the level number of the signal recovered by the butterfly equalizer.
  • the transmitting end may perform symbol mapping on two different binary bit streams. For example, for PAM-4 modulation mode, the transmitting end can use Gray code to perform symbol mapping, for example, 0,0 is mapped to -3; 0,1 is mapped to -1; 1,1 is mapped to +1; 1,0 is mapped to +3.
  • the transmitting end may map the first two bits of every four bits to the real part symbols using the Gray code, and the last two bits use the Gray code to map the imaginary part symbols. For example, 0,0,0,0 is mapped to -3,-3j; 0,0,0,1 is mapped to -3,-1j; 0,0,1,1 is mapped to -3,+1j; 0,0 ,1,0 maps to -3,+3j; 0,1,0,0 maps to -1,-3j, and so on.
  • the transmitting end processes the result output by the modulator through a digital-to-analog converter (DAC) to obtain two different analog signals.
  • DAC digital-to-analog converter
  • the method shown in FIG. 4a may further include: the transmitting end performs equalization processing on the result output by the modulator through a butterfly equalizer.
  • the transmitting end can perform mutual coupling pre-emphasis on the acquired two binary bit streams, thereby effectively compensating for the signal broadening introduced in the differential transmission line to a certain extent. , mutual interference of two signals and other undesirable effects, improve the accuracy of the original binary data stream restored by the receiver from the butterfly equalizer, and make the signal quality of the receiver after equalization better. It can be understood that reference may also be made to FIG. 5b for this implementation.
  • step 403 can also be replaced with: the transmitting end processes the result output by the butterfly equalizer through the digital-to-analog converter, and obtains two different analog signals.
  • the transmitting end sends two different analog signals through a differential transmission line, one of the differential transmission lines corresponds to one analog signal, and the differential transmission lines share one ground line.
  • the receiving end receives two different analog signals through the differential transmission line.
  • the two binary bit streams obtained by the transmitting end are different binary bit streams respectively, so that the differential transmission line can carry different information and improve the data transmission rate.
  • the transmitting end adopts the PAM-4 modulation mode, and the baud rate of one binary bit stream is 56 Gbd. Since one symbol corresponds to 2 bits, the signal bit rate is 112 Gbps, and the bit rate of the entire system transmission data is 224 Gbps.
  • the receiving end processes the two different analog signals through an analog-to-digital converter (analog-to-digital converter, ADC) to obtain two different digital signals.
  • ADC analog-to-digital converter
  • the receiving end performs equalization processing on the two different digital signals through a butterfly equalizer.
  • interference may exist between the two different analog signals transmitted by the differential transmission line, so the butterfly equalizer can be used to reduce the interference between the two different digital signals.
  • the type of butterfly equalizer included in the receiving end may be as shown in FIG. 3a, or may also be as shown in FIG. 3b, and the specific description of the butterfly equalizer will not be described in detail here.
  • the equalizer can also perform equalization processing on the output result of the butterfly equalizer again, and then use the demodulator to perform equalization processing on the output result of the butterfly equalizer.
  • the result of the equalizer output is demodulated.
  • the receiving end demodulates the result output by the butterfly equalizer through the demodulator to obtain two different binary bit streams.
  • the receiving end may obtain two binary bit streams through symbol inverse mapping.
  • the method shown in FIG. 4a may further include:
  • the receiving end combines the two different binary bit streams through a multiplexer (Mux) to obtain a binary data stream.
  • Mcux multiplexer
  • the binary data stream here can be understood as the original binary data stream obtained by the sender.
  • the transmitter may include a modulator and a DAC
  • the receiver may include an ADC, a butterfly equalizer, and a demodulator.
  • the analog signal output at a in Fig. 4b can be respectively as shown in the first picture in Fig. 4c. Since the two transmission lines of the differential transmission line interfere with each other, after the analog signal output from a is transmitted through the differential transmission line, the two analog signals will be coupled together, as shown in the second diagram in Figure 4c. In the second diagram of Figure 4c, the two analog signals obtained by the receiving end are superimposed on each other, and due to the loss of the channel, the two analog signals obtained by the receiving end may be chaotic.
  • the signal output from the butterfly equalizer appears as a four-level signal as understood, similar to the first plot of Figure 4c. It can be understood that the signal diagram shown in FIG. 4c is shown by taking the butterfly equalizer as an example of FIG. 3a, FIG. 3b or FIG. 3d.
  • the two dotted lines in the differential transmission lines in FIG. 4b indicate that when a signal is transmitted by one of the differential transmission lines, the signal will be affected by the other transmission line. In other words, each of the differential transmission lines interferes with each other.
  • the method shown in FIG. 4a may further include: the receiving end inputs the result output by the butterfly equalizer to the decider, and the result output by the decider is fed back to the butterfly equalizer.
  • the above step 407 can also be replaced with: the demodulator is used to process the result output by the decider to obtain two different binary bit streams. It can be understood that, for the above implementation manner, reference may be made to FIG. 5c.
  • the transmitter can perform symbol mapping, modulation, pre-emphasis, and conversion into analog signals on the obtained binary data stream.
  • the receiving end can also convert the acquired signal into a digital signal, equalize, demodulate, and de-map symbols. It can be understood that, for the data transmission method shown in FIG. 4d, reference may also be made to FIG. 4a to FIG. 4c, which will not be described in detail here.
  • the efficiency of data transmission can be effectively improved.
  • the method provided by the embodiment of the present application can increase the output data rate by two times (compared to the rate shown in FIG. ). For example, for PAM-4 modulation with a baud rate of 56GBd, if differential signals are used, the data transmission bit rate of the entire system is 112 Gbps; however, the data transmission bit rate of the system according to the embodiment of the present application can be increased to 224 Gbps.
  • the transmitting end may include a dual splitter, a symbol mapping and a DAC.
  • the receiving end can include continuous time linear equalizer (CTLE), ADC, butterfly equalizer, decider/DFE/partial response (PR)/maximum likelihood sequence estimation (maximum likelihood sequence estimation, MLSE), symbol de-mapping, and two-way combiner.
  • CTLE continuous time linear equalizer
  • ADC ADC
  • butterfly equalizer decider/DFE/partial response (PR)/maximum likelihood sequence estimation (maximum likelihood sequence estimation, MLSE), symbol de-mapping, and two-way combiner.
  • the result output from the butterfly equalizer may sequentially pass through one or more of the decider, DFE, PR, and MLSE.
  • the result output from the butterfly equalizer can be arbitrarily passed through one or more of the decider, DFE, PR, and MLSE.
  • the embodiments of the present application do not limit the specific positions of the decider, the DFE, the PR, and the MLSE in the receiving end or the post-signal sequence that the signals pass through.
  • DFE can be used to further eliminate residual interference.
  • the decider can be used to decide the symbol corresponding to the level.
  • PR and MLSE can also determine the symbol corresponding to the level.
  • the DFE, PR, MLSE, or decider may be collectively referred to as an equalizer, so as to perform equalization processing on the result output by the butterfly equalizer again.
  • the transmitting end may process the obtained binary data stream (or may also be referred to as the original binary data stream) through a dual distributor to obtain two different binary bit streams. Then the two different binary bit streams are converted into two different analog signals through symbol mapping and DAC respectively.
  • the transmitting end sends two different analog signals through the differential transmission line, for example, the interface between the transmitting end and the differential transmission line may be port 1 and port 3 in FIG. 5a.
  • the interface between the receiving end and the differential transmission line is port 2 and port 4 in Fig. 5a.
  • the receiving end After the receiving end obtains the two different analog signals through the differential transmission line, the receiving end can filter the obtained analog signals through CTLE to reduce the attenuation of the high-frequency part of the signal introduced by the link, so that the signal in the time domain is attenuated. The spread becomes smaller, and it is closer to the original signal sent by the sender.
  • the analog signal is then converted into a digital signal by an ADC.
  • the butterfly equalizer equalizes the digital signal output by the ADC, it passes through one or more of the determinator, DFE, PR or MLSE to obtain the output result, that is, two different binary bit streams. After the two different binary bit streams pass through the dual-channel combiner, the receiving end can recover the binary data stream.
  • the symbol mapping may be equivalent to the modulator shown in FIG. 4a and/or FIG. 4b, and the symbol inverse mapping may be equivalent to the demodulator shown in FIG. 4a and/or FIG. 4b.
  • the sending end splits the original binary data stream through a dual-channel distributor, so that different information is transmitted on the differential transmission line, the utilization rate of the differential transmission line is improved, and the rate of system data transmission is increased.
  • a butterfly equalizer may also be included in the transmitting end.
  • the difference from FIG. 5a is that after the transmitting end processes the two binary bit streams respectively through symbol mapping, the output result of the symbol mapping is used as the input of the butterfly equalizer in the transmitting end.
  • the transmitting end pre-emphasizes the output result of symbol mapping through a butterfly equalizer, and then converts it into an analog signal through a DAC.
  • the signal is pre-emphasized by the butterfly equalizer, which can improve the quality of the signal after the signal is equalized by the butterfly equalizer in the receiving end.
  • FIG. 5b It can be understood that for other descriptions in FIG. 5b, reference may be made to FIG. 5a, which will not be described in detail here.
  • the receiver includes a decider, and the decider can be used to feed back its output result to the butterfly equalizer.
  • a butterfly equalizer with a cross-DFE equalizer is used, which can make the system more capable of handling mutual interference between two signals.
  • FIG. 5c For the components included in the transmitting end of FIG. 5c, reference may be made to FIG. 5a and/or FIG. 5b, etc., which will not be described in detail here.
  • the type of butterfly equalizer in Embodiments 1 to 3 may include the butterfly equalizer shown in 3a; or, as shown in FIG. 3b, when the working mode of the butterfly equalizer is dual Butterfly equalizer in double speed mode.
  • the two binary bit streams obtained by the sending end through the dual-channel distributor come from the same binary data stream.
  • the sender can obtain different binary data streams, denoted as binary data stream 1 (or referred to as original binary data stream 1) and binary data stream 2 (or referred to as original binary data stream 2).
  • the different binary data streams are respectively transmitted through the differential transmission line after symbol mapping and DAC.
  • the different binary data streams are respectively transmitted through a differential transmission line after symbol mapping, butterfly equalizer, and DAC.
  • the receiving end can also recover two different binary data streams through ADC, butterfly equalizer, symbol de-mapping, etc. It can be understood that, for the components included in the transmitting end and the receiving end of FIG. 5d, reference may be made to FIG. 5a, FIG. 5b, or FIG. 5c, etc., which will not be described in detail here.
  • the receiver when the transmitter needs to send a differential signal, the receiver can change the working mode of the butterfly equalizer. In other words, by changing the operating mode of the butterfly equalizer, differential signals can be transmitted on the differential transmission line.
  • the butterfly equalizer shown in FIG. 5e reference may be made to the butterfly equalizer shown in FIG. 3c, which will not be described in detail here.
  • the input signal of port 3 of the butterfly equalizer can be inverted and output to the selector. middle. Then the signal output through the selector is added to the signal input at port 1. Then the inverted and summed signals of port 1 and port 3 will be equalized by an FFE equalizer and output through port 2 of the butterfly equalizer. After the output signal is processed by one or more of the decider, DFE, PR, and MLSE, and after symbol de-mapping, the receiving end can restore the original binary data stream.
  • the result output by the butterfly equalizer may also be input to the DFE and the decider in sequence, and then the result output by the DFE and the decider is fed back to the butterfly equalizer, etc., which will not be described in detail here.
  • each of the above-mentioned embodiments is shown by taking the differential transmission line transmitting two signals as an example.
  • more signals can be transmitted, as shown in Figures 6a and 6a. shown in Figure 6b.
  • the number of signals sent by the transmitting end, the number of transmission lines, and the number of signals received by the receiving end are all changed from 2 to x.
  • the original binary data stream is processed by the demultiplexer.
  • the demultiplexer maps the binary data stream to x-way binary bit stream.
  • the bit rate of each channel of x binary bit streams is 1/x of the bit rate of the original binary data stream.
  • the x outputs of the demultiplexer are respectively input to the x modulators.
  • the modulator modulates the input signal, such as the PAM-N modulation shown in Figures 6a and 6b. Therefore, after a modulator (eg, symbol mapping), the transmitter can obtain x channels of PAM-N signals, and each channel of signals is different, that is, each transmission line carries different information.
  • the x PAM-N signals i.e. the outputs of the x modulators
  • the outputs of the x modulators can also be pre-emphasized, and then converted into analog signals and sent through multiplex transmission lines.
  • the x-channel analog signals obtained by the receiving end may be signals after mutual interference.
  • the x-channel signals are taken as a whole to be equalized, and the equalized x-channel outputs are then input to the x-channel demodulators.
  • "taking the x-channel signals as a whole” means that each output channel of the equalization uses the multi-channel input signal.
  • the x-channel demodulators respectively demodulate the input signals of each of the x-channel demodulators to obtain x-channel binary bit streams.
  • the bit rate of each binary bit stream obtained by the receiving end may be consistent with the bit rate of each binary bit stream output by the transmitting end through the demultiplexer.
  • different information is transmitted on the x transmission lines, so the data transmission rate of the system is x times the data transmission rate of each transmission line.
  • the data transmission rate of the system is x times the data transmission rate of each transmission line.
  • the bit rate of the x DAC output signals is 112 Gbps, and the x DAC outputs are different information, so the entire system data
  • the transmitted bit rate is x*112Gbps.
  • FIG. 7 is a schematic structural diagram of a communication apparatus provided by an embodiment of the present application, and the communication apparatus can be used to execute the method shown in FIG. 4a.
  • the communication device includes a processing unit 701 and a transceiver unit 702 .
  • the communication device may be the transmitting end in the above-mentioned embodiments, wherein,
  • a processing unit 701 for acquiring two different binary bit streams
  • processing unit 701 can also obtain the two different binary bit streams through the transceiver unit 702;
  • the processing unit 701 is also used to modulate two different binary bit streams; and convert the result after the modulation into two different analog signals;
  • the transceiver unit 702 is used for outputting the two different analog signals.
  • the transceiver unit can output the two different analog signals through differential transmission lines, one of the differential transmission lines corresponds to one analog signal, and the differential transmission lines share one ground line.
  • the processing unit 701 may also be configured to perform equalization processing on the result after the modulation, and convert the result after the equalization processing into two different analog signals.
  • the processing unit 701 may be one or more processors, and the transceiver unit 702 may be a transceiver, or a transceiver unit 702 may also be a sending unit and a receiving unit, the sending unit may be a transmitter, and the receiving unit may be a receiver, and the sending unit and the receiving unit are integrated into one device, such as a transceiver.
  • the processing unit 701 may be one or more processing circuits, and the transceiver unit 702 may be an input and output interface, also called a communication interface, or an interface circuit, or an interface such as a differential transmission interface, etc. Wait.
  • the communication device may be the receiving end in the above-mentioned embodiment, wherein,
  • a transceiver unit 702 used for acquiring two different analog signals
  • the transceiver unit can specifically acquire two different analog signals transmitted through a differential transmission line.
  • One transmission line of the differential transmission line corresponds to one analog signal, and the differential transmission lines share one ground line.
  • the processing unit 701 is used for processing two different analog signals to obtain two different digital signals;
  • the processing unit 701 is further configured to perform equalization processing on the two different digital signals, and demodulate the result after the equalization processing to obtain two different binary bit streams.
  • the processing unit 701 is further configured to combine the two different binary bit streams to obtain a binary data stream.
  • the processing unit 701 is further configured to perform decision processing on the result after the equalization processing, and demodulate the result after the decision processing to obtain two different binary bit streams.
  • the processing unit 701 may also be configured to perform equalization processing again on the result after equalization processing, and then perform demodulation to obtain two different binary bit streams.
  • the processing unit 701 may be one or more processors, and the transceiver unit 702 may be a transceiver, or a transceiver unit 702 may also be a sending unit and a receiving unit, the sending unit may be a transmitter, and the receiving unit may be a receiver, and the sending unit and the receiving unit are integrated into one device, such as a transceiver.
  • the processing unit 701 may be one or more processing circuits, and the transceiver unit 702 may be an input/output interface, also called a communication interface, or an interface circuit, or an interface such as a differential transmission interface, etc. Wait.
  • FIG. 8 is a schematic structural diagram of a communication device provided by an embodiment of the present application.
  • the communication device may be the transmitting end in the above-mentioned embodiment. As shown in FIG. 8 , the transmitting end includes:
  • a two-way distributor 801 is used to obtain two different binary bit streams
  • a modulator 802 for modulating the two different binary bit streams
  • the digital-to-analog converter 803 is used to process the result output by the modulator to obtain two different analog signals;
  • the differential transmission interface 804 is used for sending the two different analog signals, the two different analog signals can be transmitted through differential transmission lines, one of the differential transmission lines corresponds to one analog signal, and the differential transmission lines share a ground wire. That is, the differential transmission interface can be used to connect differential transmission lines.
  • the transmitting end may further include: a butterfly equalizer 805, configured to perform equalization processing on the result output by the modulator;
  • the embodiments of the present application do not limit the specific connection manner between the dual-channel distributor, the modulator, the digital-to-analog converter, and the butterfly equalizer.
  • the specific type of the differential transmission interface is also not limited. It can be understood that, for the specific description of the relationship between the output results of various devices, the binary bit stream, the analog signal, etc., reference may be made to the foregoing embodiments. That is, for the specific description of the transmitting end shown in FIG. 8 , reference may be made to the foregoing embodiments, which will not be described in detail here.
  • the transmitting end shown in the embodiments of the present application may also have more components and the like than those shown in FIG. 8 , which are not limited in the embodiments of the present application.
  • the connection manner shown in FIG. 8 is only an example, which should not be construed as a limitation on the embodiments of the present application.
  • FIG. 9 is a schematic structural diagram of a communication device provided by an embodiment of the present application.
  • the communication device may be the receiving end in the above-mentioned embodiment. As shown in FIG. 9 , the receiving end includes:
  • the differential transmission interface 901 is used to receive two different analog signals transmitted through a differential transmission line.
  • the differential transmission interface can be used to connect a differential transmission line.
  • One transmission line in the differential transmission line corresponds to one analog signal, and the differential transmission line shares a ground wire. ;
  • the analog-to-digital converter 902 is used for processing the two different analog signals to obtain two different digital signals;
  • butterfly equalizer 903 for performing equalization processing on the two different digital signals
  • the demodulator 904 is used for demodulating the output result of the butterfly equalizer to obtain two different binary bit streams.
  • the receiving end may further include:
  • the dual-channel combiner 905 is used for combining two different binary bit streams to obtain a binary data stream.
  • the differential transmission interface 901 is specifically configured to receive two different mode signals when the operating mode of the butterfly equalizer is the first mode.
  • the receiving end may further include: a decider 906, configured to process the result output by the butterfly equalizer, and feed back the result output by the decider to the butterfly equalizer;
  • the demodulator 904 is specifically configured to process the result output by the decider to obtain two different binary bit streams.
  • the receiving end may further include an equalizer (not shown in FIG. 9 ), for performing equalization processing on the result output by the butterfly equalizer again.
  • the demodulator can be used to demodulate the result output by the equalizer to obtain two different binary bit streams.
  • the embodiments of the present application do not limit the specific connection manner between the analog-to-digital converter, the butterfly equalizer, the demodulator, and the two-way combiner.
  • the specific type of the differential transmission interface is also not limited. It can be understood that, for the specific description of the relationship between the output results of various devices, the binary bit stream, the analog signal, etc., reference may be made to the foregoing embodiments. That is, for the specific description of the receiving end shown in FIG. 9 , reference may be made to the foregoing embodiments, which will not be described in detail here.
  • the transmitting end shown in the embodiments of the present application may also have more components and the like than those shown in FIG. 9 , which are not limited in the embodiments of the present application.
  • Embodiments of the present application further provide a communication system, where the communication system includes a transmitter and a receiver.
  • the communication system includes a transmitter and a receiver.
  • the specific description of the transmitter and the receiver such as the steps or functions performed by the receiver and the transmitter, and the specific description of the receiver and the receiver.
  • the specific components and the like included in the terminal and the transmitting terminal reference may be made to the foregoing embodiments, which will not be described in detail here.
  • the disclosed system, apparatus and method may be implemented in other manners.
  • the apparatus embodiments described above are only illustrative.
  • the division of the units is only a logical function division. In actual implementation, there may be other division methods.
  • multiple units or components may be combined or Can be integrated into another system, or some features can be ignored, or not implemented.
  • the shown or discussed mutual coupling or direct coupling or communication connection may be indirect coupling or communication connection through some interfaces, devices or units, and may also be electrical, mechanical or other forms of connection.
  • the units described as separate components may or may not be physically separated, and components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the technical effects of the solutions provided by the embodiments of the present application.
  • each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically alone, or two or more units may be integrated into one unit.
  • the above-mentioned integrated units may be implemented in the form of hardware, or may be implemented in the form of software functional units.
  • the integrated unit if implemented in the form of a software functional unit and sold or used as an independent product, may be stored in a computer-readable storage medium.
  • a computer-readable storage medium includes several instructions to cause a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present application.
  • the aforementioned readable storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), magnetic disk or optical disk, etc. that can store program codes medium.
  • the present application also provides a computer program for implementing the operations and/or processing performed by the sender in the data transmission method provided by the present application.
  • the present application also provides a computer program for implementing the operations and/or processing performed by the receiving end in the data transmission method provided by the present application.
  • the present application also provides a computer-readable storage medium, where computer codes are stored in the computer-readable storage medium, and when the computer codes are executed on the computer, the computer executes the operations performed by the sender in the data transmission method provided by the present application. and/or processing.
  • the present application also provides a computer-readable storage medium, where computer codes are stored in the computer-readable storage medium, and when the computer codes are run on the computer, the computer executes the operations performed by the receiving end in the data transmission method provided by the present application and/or processing.
  • the present application also provides a computer program product, the computer program product includes computer code or computer program, when the computer code or computer program runs on a computer, the operations performed by the sender in the data transmission method provided by the present application and / or processing is implemented.
  • the present application also provides a computer program product, the computer program product includes computer code or computer program, when the computer code or computer program runs on a computer, the operations performed by the receiving end in the data transmission method provided by the present application and / or processing is implemented.

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Abstract

本申请提供一种数据传输方法及装置，该方法包括：发送端获取两路不同的二进制比特流，通过调制器和数模转换器对该两路不同的二进制比特流进行处理，获得两路不同的模拟信号。然后通过差分传输线发送该两路不同的模拟信号，该差分传输线中的一条传输线对应一个模拟信号，且该差分传输线共用一条地线。接收端通过该差分传输线接收该两路不同的模拟信号，通过模数转换器对该两路不同的模拟信号进行处理，获得两路不同的数字信号。然后通过蝶形均衡器和解调器对该两路不同的模拟信号进行处理，获得两路不同的二进制比特流。通过本申请提供的方案，差分传输线上可以传输不同的信息，提高系统的数据传输效率。

Description

一种数据传输方法及装置
本申请要求于2020年07月03日提交中国专利局、申请号为202010632131.7、申请名称为“一种数据传输方法及装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及通信技术领域，尤其涉及一种数据传输方法及装置。
背景技术
在高速电互联系统中，一般会采用差分信号的方式传输数据流。差分信号只要是指振幅相同、相位相反的信号，如可以分别称为正信号和负信号。
如图1所示，发送系统A可以通过差分传输线向系统B发送信号，其中，差分传输线中传输的信号即为差分信号。由此，接收系统B接收到差分信号后，正信号和负信号相减得到发送系统所发出的信号。
然而，图1所示的传输线1和传输线2承载的信息完全一样，导致传输线的利用率低下。
发明内容
本申请提供一种数据传输方法及装置，可有效提高系统传输信息的效率。
第一方面，本申请实施例提供一种数据传输方法，该方法可以由通信装置执行，该通信装置可以是有线设备，如路由器、交换机或光传送网(optical transport network，OTN)传输设备。或者，该通信装置还可以是包括任意类型的接口的装置，如通用计算机接口、OTN接口、快速外围组件互连(peripheral component interconnect express，PCIE)接口、以太网接口或串化解串器(serializer/deserializer，SerDes)接口等。或者，该通信装置还可以是任意类型的芯片(或也可以称为电路系统、芯片系统等)，如手机芯片、中央处理器(central processing unit，CPU)芯片或任何需要高速通信接口的芯片中等。以下将以通信装置为发送端为例进行描述，该方法包括：
获取两路不同的二进制比特流，通过调制器对该两路不同的二进制比特流进行调制；然后通过数模转换器对该调制器输出的结果进行处理，获得两路不同的模拟信号；最后通过差分传输线发送该两路不同的模拟信号，该差分传输线中的一条传输线对应一路模拟信号，且该差分传输线共用一条地线。
本申请实施例提供的技术方案，差分传输线的两条传输线上传输的是不同的信息，相对于差分传输线的两条传输线上传输相同的信息，有效提高了系统的数据传输效率。
在一种可能的实现方式中，两路不同的模拟信号中的一路模拟信号被平移和/或线性变换后，无法得到另一路模拟信号。
在一种可能的实现方式中，上述获取两路不同的二进制比特流包括：通过双路分配器 获取两路不同的二进制比特流。
本申请实施例中，发送端可以将原始的二进制数据流(或者也可以称为原始的二进制比特流等)通过双路分配器进行拆分，获得两路不同的二进制比特流。即上述两路不同的二进制比特流可以为原始的二进制数据流的部分。可理解，本申请实施例对于上述两路不同的二进制比特流是否均为原始的二进制数据流的一半不作限定。但是，为提高数据传输效率，上述两路不同的二进制比特流可以均为原始的二进制数据流的一半。至于双路分配器如何对原始的二进制数据流进行拆分，本申请实施例不作限定。
在一种可能的实现方式中，上述通过调制器对两路不同的二进制比特流进行调制之后，以及上述通过数模转换器对调制器输出的结果进行处理，获得两路不同的模拟信号之前，所述方法还包括：通过蝶形均衡器对调制器输出的结果进行均衡处理；上述通过数模转换器对调制器输出的结果进行处理，获得两路不同的模拟信号包括：通过数模转换器对蝶形均衡器输出的结果进行处理，获得两路不同的模拟信号。
本申请实施例中，发送端通过蝶形均衡器对调制器输出的结果进行均衡处理，可对调制器输出的结果进行相互耦合的预加重。在一定程度上补偿差分传输线中引入信号展宽、两路信号相互干扰等不理想的情况，使得接收端通过蝶形均衡器均衡后的信号的质量更好。
在一种可能的实现方式中，两路不同的二进制比特流来自于同一个数据报文或控制报文。也可以理解为：原始的二进制数据流为数据报文的二进制数据流；或者为控制报文的二进制数据流等。
第二方面，本申请实施例提供一种数据传输方法，该方法可以由通信装置执行，以下将以通信装置为接收端为例进行描述，该方法包括：
通过差分传输线接收两路不同的模拟信号，该差分传输线中的一条传输线对应一路模拟信号，且差分传输线共用一条地线；然后通过模数转换器对两路不同的模拟信号进行处理，获得两路不同的数字信号；通过蝶形均衡器对该两路不同的数字信号进行均衡处理；以及通过解调器对该蝶形均衡器输出的结果进行解调，获得两路不同的二进制比特流。
本申请实施例提供的技术方案，差分传输线的两条传输线上传输的是不同的信息，相对于差分传输线的两条传输线上传输相同的信息，有效提高了系统的数据传输效率。且通过蝶形均衡器对获取到的两路不同的数字信号进行均衡处理，还可以有效降低该两路不同的数字信号之间的干扰。
在一种可能的实现方式中，两路不同的模拟信号中的一路模拟信号被平移和/或线性变换后，无法得到另一路模拟信号。
在一种可能的实现方式中，所述方法还包括：通过双路合并器合并两路不同的二进制比特流，获得二进制数据流。
本申请实施例中，通过对两路不同的二进制比特流进行合并，可以获得原始的二进制数据流。
在一种可能的实现方式中，蝶形均衡器用于减少两路不同的数字信号之间的干扰。
本申请实施例中，差分传输线传输的两路不同的模拟信号之间存在干扰，导致输入至蝶形均衡器中的两路不同的数字信号之间也存在干扰，因此该蝶形均衡器可以用于减少该干扰。
在一种可能的实现方式中，上述通过差分传输线接收两路不同的模拟信号包括：在蝶形均衡器的工作模式为第一模式时，通过差分传输线接收两路不同的模式信号。
可理解，如果蝶形均衡器的工作模式为第二模式，则该差分传输线上可以传输相同的信息。示例性的，差分传输线上可以传输振幅相同、相位相反的差分信号。
本申请实施例可以在差分传输线保持不变的情况下，通过更改蝶形均衡器的工作模式，实现差分传输线传输相同的信息或不同的信息的切换，保证系统的兼容性。
在一种可能的实现方式中，上述通过蝶形均衡器对两路不同的数字信号进行均衡处理之后，以及上述通过解调器对蝶形均衡器输出的结果进行解调，获得两路不同的二进制比特流之前，所述方法还包括：将蝶形均衡器输出的结果输入至判决器；将该判决器输出的结果反馈至该蝶形均衡器；上述通过解调器对蝶形均衡器输出的结果进行解调，获得两路不同的二进制比特流包括：通过解调器对判决器输出的结果进行处理，获得两路不同的二进制比特流。
本申请实施例中，通过采用具有交叉DFE的蝶形均衡器，可增强接收端对信号之间干扰的处理能力。
在一种可能的实现方式中，上述通过蝶形均衡器对两路不同的数字信号进行均衡处理之后，以及上述通过解调器对蝶形均衡器输出的结果进行解调，获得两路不同的二进制比特流之前，方法还包括：通过均衡器对蝶形均衡器输出的结果再次进行均衡处理；上述通过解调器对蝶形均衡器输出的结果进行解调，获得两路不同的二进制比特流包括：通过解调器对均衡器输出的结果进行解调，获得两路不同的二进制比特流。
本申请实施例中，均衡器可以包括DFE、MLSE、PR或判决器中的一个或多个等。
在一种可能的实现方式中，上述通过解调器对所述蝶形均衡器输出的结果进行解调，获得两路不同的二进制比特流之前，所述方法还包括：通过判决器对蝶形均衡器输出的结果进行处理；上述通过解调器对所述蝶形均衡器输出的结果进行解调，获得两路不同的二进制比特流包括：通过解调器对判决器输出的结果进行解调，获得两路不同的二进制比特流。
本申请实施例中，上述判决器还可以替换为以下任一项或多项：判决反馈均衡器DFE、部分响应PR或最大似然序列估算MLSE。示例性的，判决器替换为MLSE时，解调器则可以对该MLSE输出的结果进行解调。示例性的，判决器替换为PR时，解调器则可以为该PR输出的结果进行解调。示例性的，判决器替换为DFE和MLSE时，蝶形均衡器输出的结果可以依次输入至该DFE和MLSE，该情况下，解调器则可以对该MLSE输出的结果进行解调。
本申请实施例中，除了判决器可以对蝶形均衡器输出的结果进行处理之外，判决反馈均衡器DFE、部分响应PR或最大似然序列估算MLSE中的任一项或多项也可以对蝶形均衡器输出的结果进行处理，这里不再一一详述。可选的，当判决器对蝶形均衡器输出的结果进行处理之后，该判决器输出的结果还可以反馈至该蝶形均衡器。
第三方面，本申请实施例提供一种通信装置，该通信装置包括：
双路分配器，用于获取两路不同的二进制比特流；调制器，用于对该两路不同的二进制比特流进行调制；数模转换器，用于对调制器输出的结果进行处理，获得两路不同的模 拟信号；差分传输接口，用于发送该两路不同的模拟信号，该两路不同的模拟信号通过差分传输线传输，该差分传输线中的一条传输线对应一路模拟信号，且该差分传输线共用一条地线。
在一种可能的实现方式中，两路不同的模拟信号中的一路模拟信号被平移和/或线性变换后，无法得到另一路模拟信号。
在一种可能的实现方式中，通信装置还包括：蝶形均衡器，用于对调制器输出的结果进行均衡处理；以及数模转换器，具体用于对该蝶形均衡器输出的结果进行处理，获得两路不同的模拟信号。
第四方面，本申请实施例提供一种通信装置，通信装置包括：
差分传输接口，用于接收通过差分传输线传输的两路不同的模拟信号，该差分传输线中的一条传输线对应一路模拟信号，且差分传输线共用一条地线；模数转换器，用于对该两路不同的模拟信号进行处理，获得两路不同的数字信号；蝶形均衡器，用于对该两路不同的数字信号进行均衡处理；解调器，用于对该蝶形均衡器输出的结果进行解调，获得两路不同的二进制比特流。
在一种可能的实现方式中，两路不同的模拟信号中的一路模拟信号被平移和/或线性变换后，无法得到另一路模拟信号。
在一种可能的实现方式中，通信装置还包括：双路合并器，用于合并两路不同的二进制比特流，获得二进制数据流。
在一种可能的实现方式中，差分传输线传输的两路不同的模拟信号之间存在干扰，因此该蝶形均衡器用于减少两路不同的数字信号之间的干扰。
在一种可能的实现方式中，差分传输接口，具体用于在蝶形均衡器的工作模式为第一模式时，接收两路不同的模式信号。
在一种可能的实现方式中，通信装置还包括：判决器，用于对蝶形均衡器输出的结果进行处理，以及将该判决器输出的结果反馈至蝶形均衡器；解调器，具体用于对该判决器输出的结果进行处理，获得两路不同的二进制比特流。
可理解，在具体实现中，上述通信装置还可能包括均衡器、处理器、存储器等，本申请实施例对于通信装置包括的其他元器件不作限定。这里的均衡器可以用于对蝶形均衡器输出的结果再次进行均衡处理等，本申请实施例对于均衡器的具体类型不作限定。
第五方面，本申请实施例提供一种通信装置，用于执行第一方面或第一方面的任意可能的实现方式中的方法。该通信装置包括具有执行第一方面或第一方面的任意可能的实现方式中的方法的相应单元。或者，用于执行第二方面或第二方面的任意可能的实现方式中的方法。该通信装置包括具有执行第二方面或第二方面的任意可能的实现方式中的方法的相应单元。
例如，该通信装置可以包括收发单元和处理单元。
第六方面，本申请提供一种计算机可读存储介质，该计算机可读存储介质用于存储计算机程序，当计算机程序被执行时，使得上述第一方面或第一方面的任意可能的实现方式所示的方法被实现。或者，当计算机程序被执行时，使得上述第二方面或第二方面的任意可能的实现方式所示的方法被实现。
第七方面，本申请提供一种计算机程序产品，该计算机程序产品包括计算机程序或计算机代码，当计算机程序或计算机代码被执行时，使得上述第一方面或第一方面的任意可能的实现方式所示的方法被实现。或者，当计算机程序或计算机代码被执行时，使得上述第二方面或第二方面的任意可能的实现方式所示的方法被实现。
第八方面，本申请提供一种计算机程序，用于实现上述第一方面或第一方面的任意可能的实现方式所示的方法。或者，用于实现上述第二方面或第二方面的任意可能的实现方式所示的方法。
第九方面，本申请提供一种通信系统，该通信系统包括发送端和接收端，该发送端用于执行上述第一方面或第一方面的任意可能的实现方式所示的方法，该接收端用于执行上述第二方面或第二方面的任意可能的实现方式所示的方法。
附图说明
图1是本申请实施例提供的一种差分信号的传输示意图；
图2a是本申请实施例提供的一种差分传输线的结构示意图；
图2b是本申请实施例提供的一种差分传输线的结构示意图；
图3a至图3e是本申请实施例提供的五种蝶形均衡器的结构示意图；
图4a是本申请实施例提供的一种数据传输方法的流程示意图；
图4b是本申请实施例提供的一种通信系统示意图；
图4c是图4b中的a、b和c处的信号示意图；
图4d是本申请实施例提供的一种数据传输系统示意图；
图5a至图5e是本申请实施例提供的五种通信系统的结构示意图；
图6a是本申请实施例提供的一种通信系统的结构示意图；
图6b是本申请实施例提供的一种数据传输系统示意图；
图7是本申请实施例提供的一种通信装置的结构示意图；
图8是本申请实施例提供的一种通信装置的结构示意图；
图9是本申请实施例提供的一种通信装置的结构示意图。
具体实施方式
为了使本申请的目的、技术方案和优点更加清楚，下面将结合附图对本申请作进一步地描述。
本申请的说明书、权利要求书及附图中的术语“第一”和“第二”等仅用于区别不同对象，而不是用于描述特定顺序。此外，术语“包括”和“具有”以及它们的任何变形，意图在于覆盖不排他的包含。例如包含了一系列步骤或单元的过程、方法、系统、产品或设备等，没有限定于已列出的步骤或单元，而是可选地还包括没有列出的步骤或单元等，或可选地还包括对于这些过程、方法、产品或设备等固有的其它步骤或单元。
在本文中提及的“实施例”意味着，结合实施例描述的特定特征、结构或特性可以包含在本申请的至少一个实施例中。在说明书中的各个位置出现该短语并不一定均是指相同的 实施例，也不是与其它实施例互斥的独立的或备选的实施例。本领域技术人员可以显式地和隐式地理解的是，本文所描述的实施例可以与其它实施例相结合。
在本申请中，“至少一个(项)”是指一个或者多个，“多个”是指两个或两个以上，“至少两个(项)”是指两个或三个及三个以上，“和/或”，用于描述关联对象的关联关系，表示可以存在三种关系，例如，“A和/或B”可以表示：只存在A，只存在B以及同时存在A和B三种情况。字符“/”一般表示前后关联对象是一种“或”的关系。“以下至少一项(个)”或其类似表达，是指这些项中的任意组合。例如，a，b或c中的至少一项(个)，可以表示：a，b，c，“a和b”，“a和c”，“b和c”，或“a和b和c”。
以下详细介绍本申请涉及的术语。
1、差分传输线：两个传输线共用一个地线所组成的传输线。
差分传输线可以以线缆、连接器或印刷电路板(printed circuit board，PCB)布线等形式存在。在电路板上，差分传输线中的两个传输线可以是等长、等宽、紧密靠近，且在同一层面的两根线。示例性的，图2a和图2b分别是本申请提供的一种差分传输线的结构示意图。图2a示出的导体S1和导体S2分别为差分传输线中的传输线，从图2a也可以看出，两条传输线共用一条地线。图2b示出的是一种变形的差分传输线，该差分传输线中包括四条传输线，且该四条传输线共用一条地线。可理解，图2b示出的仅仅是一种变形，对于差分传输线中具体包括的传输线的个数，本申请不作限定。示例性的，差分传输线中，一个传输线的导体和绝缘介质组合的直径可以为0.05mm～20mm。地线的直径可以为0.01mm～10mm，两个传输线中心间距可以为0.05mm～20mm。传输线中心和地线中心间距可以为0.05mm～15mm。整个差分传输线的直径可以为0.1mm～50mm。可理解，这里所示的差分传输线的具体结构仅为一种示例，在具体实现中，可能还存在其他尺寸或类型的差分传输线，本申请对此不作限定。
一般的，差分传输线上可以传输两个信号，该两个信号与参考地之间的电压差的振幅相同，相位相反。换句话说，在差分传输线上传输的信号可以为差分信号，该差分传输线上承载的信息可以相同。通信装置在获取到差分信号中的一路信号时，通过取反可以得到另一路信号。
然而，在本申请中，差分传输线上可以传输两路不同的模拟信号，即该差分传输线上承载的信息可以不同。可选的，双倍速传输可以为一种信号传输的技术，区别于传统的一根信号线和一根地线，双倍速传输可以在差分传输线的两根传输线上都传输信号，但是两个信号的振幅可以没有相同的关系，相位也可以没有相反的关系。可理解，本申请中由于差分传输线中承载的信息不用，通过差分传输线传输两路不同的模拟信号的方式也可以称为双倍速传输。
本申请中，通信装置在获取到通过差分传输线传输的两路不同的模拟信号之后，可以通过图3a、图3b或图3d所示的蝶形均衡器进行均衡处理，从而减少通过差分传输线传输两路不同的模拟信号带来的干扰。本申请提供的通信系统如图5a至图5d中，发送端可以通过差分传输线向接收端发送两路不同的模拟信号，对应的，接收端可以接收通过差分传输线传输的两路不同的模拟信号。结合图2a和图2b所示的差分传输线，图5a至图5d所示的通信系统的结构示意图中，发送端可以通过图2a所示的差分传输线发送两路不同的模 拟信号，对应的，接收端可以通过图2a所示的差分传输线接收两路不同的模拟信号。图6a和图6b所示的通信系统的结构示意图中，发送端可以通过图2b所示的差分传输线发送四路不同的模拟信号，对应的，接收端可以通过图2b所示的差分传输线接收四路不同的模拟信号。可理解，对于四路不同的模拟信号的具体描述，可参考上述两路不同的模拟信号的描述，这里不再详述。
本申请中，通信装置无法通过将一路模拟信号进行平移和/或线性变换得到另一路模拟信号。即一路模拟信号被平移和/或线性变换后，无法得到另一路模拟信号。示例性的，通信装置在获取到该两路不同的模拟信号中的一路模拟信号时，无法通过将该一路模拟信号时延得到另一路模拟信号；或者，无法通过将该一路模拟信号乘以倍数(包括取反，也就是乘以-1)得到另一路模拟信号；或者，无法通过将该一路模拟信号增加固定值或减少固定值，得到另一路模拟信号；或者，无法通过将该一路模拟信号与某一序列卷积，得到另一路信号；或者，无法通过将该一路模拟信号通过以上处理方法的组合，得到另一路信号。
示例性的，该两路不同的模拟信号可以不为电压相等，相位相反的对称信号。如该两路不同的模拟信号在同一时刻可以不为电压相等，相位相反的对称信号。
本申请中，差分传输线可以包括两条传输线。可理解，差分传输线也可以称为差分信号线，该差分信号线包括两条信号线。或者，也可以称为差分传输线包括两条信号线等，或者，本申请示出的差分传输线还可以统称为信道等，本申请对于差分传输线的具体名称不作限定。可理解，差分传输线上传输的信号具体可以为模拟信号。
2、蝶形均衡器：为多路输入、多路输出的数字均衡系统，且该蝶形均衡器的每路输出均可以由该多路输入的信号均衡处理后得到。
如图3a至图3e，本申请分别提供了五种蝶形均衡器的类型。
如图3a至图3d所示，端口1和端口3分别为输入端口，端口2和端口4分别为输出端口。蝶形均衡器中包括四个前馈均衡器(feed forward equalizer，FFE)，分别记为FFE 12、FFE 14、FFE 32和FFE 34。端口1获取到的信号(如数字信号)经过FFE 12，端口3获取到的信号经过FFE 32，且FFE 12和FFE 32输出的信号经过加法器相加，即得到端口2的输出信号(或者称为输出结果)。端口1获取到的信号经过FFE 14，端口3获取到的信号经过FFE 34，且FFE 14和FFE 34输出的信号经过加法器相加，即得到4端口的输出信号。对于端口2和端口4输出信号的电平可参考图4c中的第三个图，图4c的第二个图是蝶形均衡器处理之前的信号示意图。从图4c可以看出信号经过蝶形均衡器均衡之后，该蝶形均衡器输出的数字信号之间几乎没有交叠，恢复成几乎各自独立的信号。由于该示例中发送端中调制器发送的为PAM-4调制的信号，为四电平信号，因此蝶形均衡器的两路输出，也各自分别为较为理想的四电平信号。但是，该蝶形均衡器输出的结果仍为两路不同的数字信号，只是该两路不同的数字信号可以分别表示为四电平信号。
可理解，蝶形均衡器恢复出的信号可以由发送端中调制器的输出决定，换句话说，该蝶形均衡器的多路输出可以与发送端中的调制器输出类似。示例性的，如发送端采用PAM-2调制方式，则蝶形均衡器可以将获取到两路数字信号恢复为两个电平信号。示例性的，如发送端采用PAM-8调制方式，则蝶形均衡器可以将获取到的两路数字信号恢复为8个电平信号。
可选的，图3b和图3c中的蝶形均衡器中包括选择器(如图3b和图3c中的梯形)，该选择器可以用于控制蝶形均衡器的工作模式。示例性的，当控制信号为1时，该选择器可以使得蝶形均衡器的工作模式与图3a类似。示例性的，当控制信号为0时，蝶形均衡器的工作模式可如图3c所示。该情况下，蝶形均衡器可以相当于是一个FFE。换句话说，通过选择器，蝶形均衡器的工作模式可以分为第一模式和第二模式。示例性的，当蝶形均衡器的工作模式为第一模式时，该蝶形均衡器的输出可以为两路不同的数字信号，由于该两路不同的数字信号承载的信息比特率为单路信号承载的信息比特率的两倍，因此该第一模式也可以被称为双倍速工作模式。同样的，当蝶形均衡器的工作模式为第二模式时，该第二模式也可以被称为单倍速工作模式。通信装置中通过设置图3b和图3c所示的蝶形均衡器，可以使得该通信装置在双倍速工作模式和单倍速工作模式之间切换，实现了差分传输线传输相同信息(如差分信号)或不同信息的切换。换句话说，图3b所示的蝶形均衡器可提高差分传输线的利用率。
可理解，当控制信号为0时，蝶形均衡器的端口3的输入信号可以先转换为与输入信号相位相反的信号，然后与端口1输入的信号相加。换句话说，蝶形均衡器的端口3的输入信号被取反后与端口1的输入信号相加。
可选的，图3d示出的蝶形均衡器中增加了两个判决反馈均衡器(decision feedback equalizer，DFE)，分别记为DFE 2和DFE 4。由此，从端口2输出的信号(如数字信号)经过端口2’被反馈给DFE 2，从而作为DFE 2的输入信号。DFE 2将该输入信号延迟后输出，以及与FFE 14和FFE 34的输出相加后得到端口4的输出信号(或者称为输出结果)。类似的，端口4输出的信号经过端口4’被反馈给DFE 4，作为DFE 4的输入信号。DFE 4将该输入信号延迟后输出，以及与FFE 12和FFE 32的输出相加后得到端口2的输出信号。通信装置中通过采用图3d所示的蝶形均衡器，可以增强信号干扰的处理能力，提高蝶形均衡器的均衡能力，改善均衡后信号的质量。
可选的，图3e所示的蝶形均衡器中包括x个输入和x个输出。其中，x路输入分别经过x个FFE均衡器后，该x个FFE均衡器的输出结果相加即得到输出1的输出信号。其余输出原理与端口1处的输出原理相同，此处不再赘述。
可理解，以上是本申请示出的几种蝶形均衡器的类型，但是对于其他类型的蝶形均衡器本申请所示的方法中同样适用。
高速数据通信系统如PCB上、设备背板、设备框间、设备机架内和设备核机架间的电互联采用的多为差分传输线。一般的，差分传输线可以用来传输振幅相同、相位相反的两个信号，且该差分传输线的两个传输线上承载的信息相同。但是，上述传输数据的方法，往往会导致差分传输线的利用效率低下，以及系统传输数据的速率低下。
鉴于此，本申请提供一种数据传输方法及装置，该数据传输方法可以利用差分传输线传输不同的信息，提高差分传输线的利用率，提高系统传输数据的速率。换句话说，本申请提供的方法可以在差分传输线的密度和差分传输线中每条传输线上传输信号的频率不变的前提下，提高系统的传输速率。对比图1所示的数据传输方法，传输速率可以提高一倍以上。
图4a是本申请实施例提供的一种数据传输方法的流程示意图，图4b是与图4a对应的通信系统示意图，图4c是图4b中的a、b和c处的信号示意图。图4a所示的方法可以应用于通信装置，该通信装置可以包括有线设备等。可选的，该通信装置可以包括路由器、交换机或光传送网(optical transport network，OTN)传输设备等。可选的，该通信装置还可以包括任意类型的接口，如该接口可以包括通用计算机接口、OTN接口、快速外围组件互连(peripheral component interconnect express，PCIE)接口、以太网接口或串化解串器(serializer/deserializer，SerDes)接口等。可选的，该通信装置还可以包括任意类型的芯片，如该芯片可以包括手机芯片、中央处理器(central processing unit，CPU)芯片或任何需要高速通信接口的芯片中等。可选的，该数据传输方法可以应用于高速电互联的场景。该高速电互联的场景可以理解为两个通信装置之间传输数据的速率较高。
进一步的，该数据传输方法可以应用于至少两个通信装置，如图4a是以发送端和接收端为例说明本申请实施例所示的方法。本申请实施例中，发送端和接收端可以为通过差分传输线连接的两个通信装置，或者，也可以为通过差分传输线连接的两个芯片或接口等，本申请实施例对此不作限定。如图4a所示，该数据传输方法包括：
401、发送端获取两路不同的二进制比特流。
在一些实现方式中，该两路不同的二进制比特流(也可以称为二进制数据流等)可以来自于同一个数据或信令。示例性的，该两路不同的二进制比特流可以来自于同一个数据报文；或者，来自于同一个控制报文等。示例性的，发送端可以通过双路分配器获取两路不同的二进制比特流。换句话说，发送端获取到的两路不同的二进制比特流可以为原始的二进制数据流(也可以称为原始的二进制比特流等)的部分。这里，由于发送端与其他装置进行通信时，需要向其他装置交互数据和/或信令等，因此，发送端所获取的数据和/或信令也可以称为原始的二进制数据流(当然也可以称为原始的二进制比特流)。或者，发送端可以生成数据和/或信令等，本申请实施例对于发送端如何获取原始的二进制数据流不作限定。
可选的，发送端获取到的两路不同的二进制比特流可以为原始的二进制数据流的一半，该情况下，可以保证该两路不同的二进制比特流能够被同时传输完，提高数据传输的效率。作为示例，发送端可以通过双路分配器(demultiplexer，DeMux)依次将原始的二进制数据流分为两路，如原始的二进制数据流的第一个数据(可能是二进制形式的数据)分配到第一路二进制比特流，第二个数据分配到第二路二进制比特流，第三个数据分配到第一路二进制比特流等，以此类推。例如，原始的二进制数据流为1,0,1,1,0,1,0,0，则第一路二进制比特流为1,1,0,0，第二路二进制比特流为0,1,1,0。或者，本申请实施例示出的二进制比特流还可以称为信号流等，本申请实施例对于二进制比特流的具体名称不作限定。对于上述实现方式的具体描述，还可以参考本申请实施例提供的图5a至图5c。
在另一些实现方式中，该两路不同的二进制比特流还可以来自于不同的数据和/或信令，如不同的数据报文或控制报文等，本申请实施例对于该两路不同的二进制比特流的来源不作限定。对于该种实现方式，还可以参考本申请实施例提供的图5d。
402、发送端通过调制器对两路不同的二进制比特流进行调制。
本申请实施例中，调制方式可以包括脉冲幅度调制(pulse amplitude modulation，PAM)、 正交幅度调制(quadrature amplitude modulation，QAM)等。一般的，调制信号的电平数与蝶形均衡器恢复出的信号的电平数相同。示例性，发送端可以对两路不同的二进制比特流进行符号映射。例如，对于PAM-4调制方式，发送端可以使用格雷码进行符号映射，如将0,0映射为-3；0,1映射为-1；1,1映射为+1；1,0映射为+3。又例如，对于QAM-16调制方式，发送端可以将每四个比特的前两个比特使用格雷码映射为实部符号，后两个比特使用格雷码映射为虚部符号。如将0,0,0,0映射为-3,-3j；0,0,0,1映射为-3,-1j；0,0,1,1映射为-3,+1j；0,0,1,0映射为-3,+3j；0,1,0,0映射为-1,-3j，以此类推。
403、发送端通过数模转换器(digital-to-analog converter，DAC)对调制器输出的结果进行处理，获得两路不同的模拟信号。
本申请实施例中，该两路不同的模拟信号中的一路模拟信号被平移和/或线性变换后，无法获得另一路模拟信号。可理解，对于该两路不同的模拟信号的具体描述，可参考上文描述，这里不再详述。
在一种可能的实现方式中，步骤402之后，以及步骤403之前，图4a所示的方法还可以包括：发送端通过蝶形均衡器对调制器输出的结果进行均衡处理。
本申请实施例中，发送端中通过包括蝶形均衡器，可使得发送端对获取到的两路二进制比特流进行相互耦合的预加重，由此在一定程度上有效补偿差分传输线中引入信号展宽、两路信号相互干扰等不理想效应，提高接收端从蝶形均衡器中还原出原始的二进制数据流的准确性，使得接收端均衡后信号的质量更好。可理解，对于该实现方式还可以参考图5b。
该情况下，上述步骤403还可以替换为：发送端通过数模转换器对蝶形均衡器输出的结果进行处理，获得两路不同的模拟信号。
404、发送端通过差分传输线发送两路不同的模拟信号，差分传输线中的一条传输线对应一路模拟信号，且差分传输线共用一条地线。相应的，接收端通过该差分传输线接收两路不同的模拟信号。
可理解，图4a中示出的是通过差分传输线传输两路不同的模拟信号。
本申请实施例中，发送端获取到的两路二进制比特流分别为不同的二进制比特流，由此差分传输线上可以承载不同的信息，提高数据传输的速率。示例性的，发送端采用PAM-4调制方式，一路二进制比特流的波特率为56Gbd，则由于一个符号对应2个比特，因此信号比特率为112Gbps，整个系统传输数据的比特率为224Gbps。
可理解，对于差分传输线的具体说明，可参考图2a至图2b，这里不再详述。
405、接收端通过模数转换器(analog-to-digital converter，ADC)对两路不同的模拟信号进行处理，获得两路不同的数字信号。
可理解，本申请实施例对于DAC和ADC的具体类型不作限定。
406、接收端通过蝶形均衡器对两路不同的数字信号进行均衡处理。
本申请实施例中，差分传输线传输的两路不同的模拟信号之间可能存在干扰，因此蝶形均衡器可以用于减少两路不同的数字信号之间的干扰。接收端中包括的蝶形均衡器的类型可以如图3a所示，或者，还可以如图3b所示，对于该蝶形均衡器的具体说明，这里不再详述。
可选的，在接收端通过蝶形均衡器对两路不同的数字信号进行均衡处理之后，还可以 通过均衡器对该蝶形均衡器输出的结果再次进行均衡处理，然后通过解调器对该均衡器输出的结果进行解调。对于该均衡器的具体描述，可参考下文示出的实施例，这里先不详述。
407、接收端通过解调器对蝶形均衡器输出的结果进行解调，获得两路不同的二进制比特流。
示例性的，接收端可以通过符号反映射得到两路二进制比特流。
在一种可能的实现方式中，图4a所示的方法还可以包括：
408、接收端通过双路合并器(multiplexer，Mux)合并该两路不同的二进制比特流，获得二进制数据流。
这里的二进制数据流可以理解为发送端所获取的原始的二进制数据流。
示例性的，如图4b所示，发送端中可以包括调制器和DAC，接收端中可以包括ADC、蝶形均衡器和解调器。例如，发送端采用PAM-4进行调制时，图4b中的a处输出的模拟信号可以分别如图4c的第一个图所示。由于差分传输线的两条传输线之间相互有干扰，因此从a处输出的模拟信号经过差分传输线传输后，该两路模拟信号会耦合在一起，如图4c中的第二个图所示。图4c的第二个图中，接收端获取到的两路模拟信号相互叠加，且由于信道具有损耗，因此接收端获取到的两路模拟信号均可能是杂乱无章的。然而，接收端通过蝶形均衡器对两个ADC输出的数字信号进行均衡处理之后，两路数字信号可能就不会存在交叠现象。如图4c的第三图所示，从蝶形均衡器输出的信号表现为理解的四电平信号，与图4c的第一个图类似。可理解，图4c中示出的信号图是以蝶形均衡器为图3a、图3b或图3d为例示出的。
可理解，图4b的差分传输线中的两条虚线表示：在利用差分传输线中的一条传输线传输信号时，该信号会被另一条传输线造成影响。换句话说，差分传输线中的每个传输线之间相互有干扰。
在一种可能的实现方式中，步骤406之后，以及步骤407之前，图4a所示的方法还可以包括：接收端将蝶形均衡器输出的结果输入至判决器，该判决器输出的结果反馈至蝶形均衡器。该情况下，上述步骤407还可以替换为：通过解调器对判决器输出的结果进行处理，获得两路不同的二进制比特流。可理解，对于上述实现方式，可参考图5c。
可理解，对于本申请实施例提供的方法还可以参考图4d。如图4d所示，发送端可以对获取到的二进制数据流进行符号映射、调制、预加重以及转换为模拟信号等。接收端还可以将获取到的信号进行转换为数字信号、均衡、解调和符号反映射等。可理解，对于图4d所示的数据传输方法还可以参考图4a至图4c，这里不再一一详述。
本申请实施例中，通过在差分传输线上传输不同的信息，可有效提高数据传输的效率。具体的，本申请实施例提供的方法可以在保持调制方式不变、信号波特率不变、差分传输线不变的情况下，将输出数据的速率提升两倍(相对于图1所示的速率)。比如对于波特率为56GBd的PAM-4调制，如果使用差分信号，则整个系统的数据传输比特率为112Gbps；但是通过本申请实施例系统的数据传输比特率可以提高为224Gbps。
为更形象的理解图4a和图4b所示的数据传输方法，以下示出了几个具体的实施例。
实施例一、
如图5a所示，发送端可以包括双路分配器、符号映射和DAC。接收端可以包括连续 时间线性均衡器(continuous time linear equalizer，CTLE)、ADC、蝶形均衡器、判决器/DFE/部分响应(partial response，PR)/最大似然序列估算(maximum likelihood sequence estimation，MLSE)、符号反映射和双路合并器。
可选的，从蝶形均衡器输出的结果可以依次经过判决器、DFE、PR、MLSE中的一个或多个。或者，从蝶形均衡器输出的结果可以任意经过判决器、DFE、PR、MLSE中的一个或多个。换句话说，本申请实施例对于判决器、DFE、PR、MLSE在接收端中的具体位置或信号所经过的信后顺序不作限定。其中，DFE可用于进一步消除残余的干扰。判决器可用于判决电平所对应的符号。同样的，PR和MLSE也可以判决电平对应的符号。为便于理解，本申请实施例可以将该DFE、PR、MLSE或判决器等统称为均衡器，以便于对蝶形均衡器输出的结果再次进行均衡处理。
如图5a中，发送端可以通过双路分配器对获得的二进制数据流(或者也可以称为原始二进制数据流)进行处理，得到两路不同的二进制比特流。然后该两路不同的二进制比特流分别经过符号映射和DAC转换为两路不同的模拟信号。发送端通过差分传输线发送两路不同的模拟信号，如发送端与差分传输线之间的接口可以为图5a中的端口1和端口3。接收端与差分传输线之间的接口为图5a中的端口2和端口4。接收端通过差分传输线获取到该两路不同的模拟信号之后，接收端可以通过CTLE对获得的模拟信号进行滤波处理，降低由链路引入的信号高频部分的衰减，使得在时域上信号的展宽变小，更接近发送端原始发送的信号。之后通过ADC将模拟信号转换为数字信号。蝶形均衡器对ADC输出的数字信号进行均衡处理之后，经过判决器、DFE、PR或MLSE中的一个或多个，得到输出结果即两路不同的二进制比特流。该两路不同的二进制比特流经过双路合并器之后，接收端便可以恢复出二进制数据流。
本申请实施例中，符号映射可以相当于图4a和/或图4b示出的调制器，符号反映射可以相当于图4a和/或图4b示出的解调器。
可理解，为便于描述，下文示出的实施例中，与实施例一示出的发送端和接收端中相同的元器件不再一一详述。
本申请实施例中，发送端通过双路分配器拆分原始的二进制数据流，从而使得差分传输线上传输不同的信息，提高差分传输线的利用率，提高了系统传输数据的速率。
实施例二、
如图5b所示，发送端中还可以包括蝶形均衡器。与图5a的不同之处在于：发送端通过符号映射分别对两路二进制比特流进行处理之后，该符号映射的输出结果作为发送端中的蝶形均衡器的输入。发送端通过蝶形均衡器对符号映射的输出结果进行预加重之后，再通过DAC转换为模拟信号。
本申请实施例中，通过蝶形均衡器对信号进行预加重处理，可提高接收端中蝶形均衡器均衡信号后信号的质量。
可理解，对于图5b中的其他描述可参考图5a，这里不再详述。
实施例三、
如图5c所示，接收端中包括判决器，该判决器可以用于将其输出结果反馈至蝶形均衡器。本申请实施例中，采用具有交叉DFE均衡器的蝶形均衡器，可以使得系统对两路信号 间相互干扰的处理能力更强。
可理解，对于图5c发送端中包括的元器件可以参考图5a和/或图5b等，这里不再详述。
可理解，实施例一至实施例三中蝶形均衡器的类型可以包括如3a所示的蝶形均衡器；或者，还可以包括如图3b所示的，当蝶形均衡器的工作模式为双倍速工作模式时的蝶形均衡器。
实施例四、
可理解，图5a至图5c中，发送端通过双路分配器获取到的两路二进制比特流来自于同一个二进制数据流。然而，图5d中，发送端可以获取不同的二进制数据流，记为二进制数据流1(或者称为原始的二进制数据流1)和二进制数据流2(或者称为原始的二进制数据流2)。该不同的二进制数据流分别经过符号映射、DAC后通过差分传输线传输。或者，该不同的二进制数据流分别经过符号映射、蝶形均衡器、DAC后通过差分传输线传输。类似的，接收端也可以通过ADC、蝶形均衡器、符号反映射等恢复出两路不同的二进制数据流。可理解，对于图5d发送端和接收端中包括的元器件可以参考图5a、图5b或图5c等，这里不再详述。
实施例五、
如图5e所示，当发送端需要发送差分信号时，接收端可以更改蝶形均衡器的工作模式。换句话说，通过更改蝶形均衡器的工作模式，差分传输线上可以传输差分信号。对于图5e所示的蝶形均衡器的具体结构可参考图3c所示的蝶形均衡器，这里不再详述。
示例性的，为使得蝶形均衡器能对差分信号进行处理，因此，在蝶形均衡器处理第二模式时，蝶形均衡器的端口3的输入信号可以进行取反操作后输出至选择器中。然后经过选择器输出的信号与端口1输入的信号相加。然后端口1和端口3取反相加后的信号会通过一个FFE均衡器均衡，并通过蝶形均衡器的端口2输出。输出的信号再经过判决器、DFE、PR、MLSE中的一个或多个处理后，经过符号反映射后，接收端便可以恢复出原始的二进制数据流。
可选的，蝶形均衡器输出的结果还可以依次输入至DFE和判决器，然后经过该DFE和判决器输出的结果反馈至蝶形均衡器等，这里不再详述。
可理解，对于图5e的其他描述，还可以对应参考前述实施例，这里不再详述。
实施例六、
以上示出的各个实施例均是以差分传输线传输两路信号为例示出的，然而，本申请实施例中，对于变形的差分传输线来说，还可以传输更多路的信号，如图6a和图6b所示。本申请实施例相对于前述各个实施例，发送端中发送的信号的个数、传输线的个数以及接收端接收到的信号的个数均由2变为x。
如图6a和图6b所示，原始的二进制数据流被多路分配器处理。如多路分配器将二进制数据流映射为x路二进制比特流。x路二进制比特流每路的比特速率为原始的二进制数据流的比特速率的1/x。多路分配器的x路输出分别被输入到x个调制器。调制器对输入信号进行调制，比如图6a和图6b中所示的PAM-N调制。由此，经过调制器(如符号映射)后，发送端便可以获得x路PAM-N信号，且每一路信号不同，即每条传输线上承载不同的信息。然后，该x路PAM-N信号(即x个调制器的输出)可以被转换为模拟信号，通过多 路传输线发送，该多个传输线共用一条地线。或者，该x个调制器的输出也可以经过预加重处理后，再被转成模拟信号，通过多路传输线发送。
这里的多路传输线之间相互之间会产生干扰，因此，接收端获取到的x路模拟信号可能是经过相互干扰后的信号。
接收端获取到x路模拟信号之后，将x路信号作为整体，进行均衡，均衡后的x路输出再输入至x路解调器。这里“将x路信号作为整体”，是指均衡的每一路输出，均用到了多路输入的信号。x路解调器分别对x路解调器中的每路解调器的输入信号进行解调，得到x路二进制比特流。接收端获取到的每路二进制比特流的比特速率可以与发送端经过多路分配器输出每路二进制比特流的比特速率一致。
可理解，对于图6a和图6b所示的数据传输方法的具体描述可以参考前述各个实施例，这里不再一一详述。
本申请实施例中，x条传输线上传输的是不同的信息，因此系统的数据传输速率是每条传输线上数据传输速率的x倍。示例性的，对于PAM-4调制方式来说，如果信号的波特率是56Gbd，那么x个DAC输出信号的比特率均为112Gbps，且x个DAC输出的是不同的信息，因此整个系统数据传输的比特率为x*112Gbps。
可理解，以上所示的各个实施例中，同一种类型的器件的内部结构是否相同，本申请实施例不作限定。示例性的，本申请实施例对于图6a中的x个调制器的具体内部结构是否相同，不作限定。示例性的，本申请实施例对于发送端中蝶形均衡器的类型与接收端中蝶形均衡器的类型是否相同，不作限定。
可理解，以上所示的各个实施例各有侧重，其中一个实施例中未详细描述的实现方式可参考其他实施例，这里不再一一赘述。进一步的，本文中描述的各个实施例可以为独立的方案，也可以根据内在逻辑进行组合，这些方案都落入本申请的保护范围中。
以下详细说明本申请实施例提供的通信装置。
图7是本申请实施例提供的一种通信装置的结构示意图，该通信装置可以用于执行图4a所示的方法。如图7所示，该通信装置包括处理单元701和收发单元702。
在一些实现方式中，该通信装置可以为上述实施例中的发送端，其中，
处理单元701，用于获取两路不同的二进制比特流；
或者，处理单元701还可以通过收发单元702获取该两路不同的二进制比特流；
处理单元701，还用于对两路不同的二进制比特流进行调制；以及将调制之后的结果转换为两路不同的模拟信号；
收发单元702，用于输出该两路不同的模拟信号。
其中，该收发单元，具体可通过差分传输线输出该两路不同的模拟信号，该差分传输线中的一条传输线对应一路模拟信号，且所述差分传输线共用一条地线。
可选的，处理单元701，还可以用于对调制之后的结果进行均衡处理，以及将均衡处理之后的结果转换为两路不同的模拟信号。
需要理解的是，当图7所示的通信装置是发送端或发送端中实现上述功能的部件时，处理单元701可以是一个或多个处理器，收发单元702可以是收发器，或者收发单元702 还可以是发送单元和接收单元，发送单元可以是发送器，接收单元可以是接收器，该发送单元和接收单元集成于一个器件，例如收发器。
当上述发送端是电路系统如芯片时，处理单元701可以是一个或多个处理电路，收发单元702可以是输入输出接口，又或者称为通信接口，或者接口电路，或接口如差分传输接口等等。
可理解，对于上述发送端的具体描述，可参考前述各个实施例，这里不再详述。
复用图7，在另一些实现方式中，该通信装置可以为上述实施例中的接收端，其中，
收发单元702，用于获取两路不同的模拟信号；
例如，收发单元，具体可获取通过差分传输线传输的两路不同的模拟信号，该差分传输线的一条传输线对应一路模拟信号，且所述差分传输线共用一条地线。
处理单元701，用于对两路不同的模拟信号进行处理，获得两路不同的数字信号；
处理单元701，还用于对两路不同的数字信号进行均衡处理，以及对均衡处理之后的结果进行解调，获得两路不同的二进制比特流。
可选的，处理单元701，还用于合并该两路不同的二进制比特流，获得二进制数据流。
可选的，处理单元701，还用于将均衡处理之后的结果进行判决处理，以及将判决处理之后的结果进行解调，获得两路不同的二进制比特流。
可选的，处理单元701，还可以用于对均衡处理之后的结果再次进行均衡处理，然后进行解调，获得两路不同的二进制比特流。
需要理解的是，当图7所示的通信装置是接收端或接收端中实现上述功能的部件时，处理单元701可以是一个或多个处理器，收发单元702可以是收发器，或者收发单元702还可以是发送单元和接收单元，发送单元可以是发送器，接收单元可以是接收器，该发送单元和接收单元集成于一个器件，例如收发器。
当上述接收端是电路系统如芯片时，处理单元701可以是一个或多个处理电路，收发单元702可以是输入输出接口，又或者称为通信接口，或者接口电路，或接口如差分传输接口等等。
可理解，对于上述接收端的具体描述，可参考前述各个实施例，这里不再详述。
图8是本申请实施例提供的一种通信装置的结构示意图，该通信装置可以为上述实施例中的发送端，如图8所示，该发送端包括：
双路分配器801，用于获取两路不同的二进制比特流；
调制器802，用于对该两路不同的二进制比特流进行调制；
数模转换器803，用于对调制器输出的结果进行处理，获得两路不同的模拟信号；
差分传输接口804，用于发送该两路不同的模拟信号，该两路不同的模拟信号可通过差分传输线传输，该差分传输线中的一条传输线对应一路模拟信号，且该差分传输线共用一条地线。即该差分传输接口可以用于连接差分传输线。
在一种可能的实现方式中，发送端还可以包括：蝶形均衡器805，用于对调制器输出的结果进行均衡处理；
以及数模转换器803，具体用于对该蝶形均衡器输出的结果进行处理，获得两路不同的模拟信号。
可理解，本申请实施例对于双路分配器、调制器、数模转换器和蝶形均衡器之间的具体连接方式不作限定。以及对于差分传输接口的具体类型也不作限定。可理解，对于各个器件输出结果之间的关系、二进制比特流、模拟信号等等具体描述，可参考前述实施例。即对于图8所示的发送端的具体描述，可参考前述实施例，这里不再详述。
可理解，本申请实施例示出的发送端还可以具有比图8更多的元器件等，本申请实施例对此不作限定。以及图8所示的连接方式仅为一种示例，不应将其理解为对本申请实施例的限定。
图9是本申请实施例提供的一种通信装置的结构示意图，该通信装置可以为上述实施例中的接收端，如图9所示，该接收端包括：
差分传输接口901，用于接收通过差分传输线传输的两路不同的模拟信号，该差分传输接口可以用于连接差分传输线，该差分传输线中的一条传输线对应一路模拟信号，且差分传输线共用一条地线；
模数转换器902，用于对该两路不同的模拟信号进行处理，获得两路不同的数字信号；
蝶形均衡器903，用于对该两路不同的数字信号进行均衡处理；
解调器904，用于对该蝶形均衡器输出的结果进行解调，获得两路不同的二进制比特流。
在一种可能的实现方式中，接收端还可以包括：
双路合并器905，用于合并两路不同的二进制比特流，获得二进制数据流。
在一种可能的实现方式中，差分传输接口901，具体用于在蝶形均衡器的工作模式为第一模式时，接收两路不同的模式信号。
在一种可能的实现方式中，接收端还可以包括：判决器906，用于对蝶形均衡器输出的结果进行处理，以及将该判决器输出的结果反馈至蝶形均衡器；
解调器904，具体用于对该判决器输出的结果进行处理，获得两路不同的二进制比特流。
在一种可能的实现方式中，接收端还可以包括均衡器(图9中未示出)，用于对蝶形均衡器输出的结果再次进行均衡处理。该情况下，解调器，可用于对该均衡器输出的结果进行解调，获得两路不同的二进制比特流。
可理解，本申请实施例对于模数转换器、蝶形均衡器、解调器和双路合并器之间的具体连接方式不作限定。以及对于差分传输接口的具体类型也不作限定。可理解，对于各个器件输出结果之间的关系、二进制比特流、模拟信号等等具体描述，可参考前述实施例。即对于图9所示的接收端的具体描述，可参考前述实施例，这里不再详述。
可理解，本申请实施例示出的发送端还可以具有比图9更多的元器件等，本申请实施例对此不作限定。
本申请实施例还提供了一种通信系统，该通信系统包括发送端和接收端，对于该发送端和该接收端的具体描述，如对于接收端和发送端执行的步骤或功能，又如对于接收端和发送端包括的具体元器件等，可参考前述各个实施例，这里不再详述。
在本申请所提供的几个实施例中，应该理解到，所揭露的系统、装置和方法，可以通过其它的方式实现。例如，以上所描述的装置实施例仅是示意性的，例如，所述单元的划 分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另外，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口、装置或单元的间接耦合或通信连接，也可以是电的，机械的或其它的形式连接。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本申请实施例提供的方案的技术效果。
另外，在本申请各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以是两个或两个以上单元集成在一个单元中。上述集成的单元既可以采用硬件的形式实现，也可以采用软件功能单元的形式实现。
所述集成的单元如果以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读取存储介质中。基于这样的理解，本申请的技术方案本质上或者说对现有技术做出贡献的部分，或者该技术方案的全部或部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个可读存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)执行本申请各个实施例所述方法的全部或部分步骤。而前述的可读存储介质包括：U盘、移动硬盘、只读存储器(read-only memory,ROM)、随机存取存储器(random access memory,RAM)、磁碟或者光盘等各种可以存储程序代码的介质。
此外，本申请还提供一种计算机程序，该计算机程序用于实现本申请提供的数据传输方法中由发送端执行的操作和/或处理。
本申请还提供一种计算机程序，该计算机程序用于实现本申请提供的数据传输方法中由接收端执行的操作和/或处理。
本申请还提供一种计算机可读存储介质，该计算机可读存储介质中存储有计算机代码，当计算机代码在计算机上运行时，使得计算机执行本申请提供的数据传输方法中由发送端执行的操作和/或处理。
本申请还提供一种计算机可读存储介质，该计算机可读存储介质中存储有计算机代码，当计算机代码在计算机上运行时，使得计算机执行本申请提供的数据传输方法中由接收端执行的操作和/或处理。
本申请还提供一种计算机程序产品，该计算机程序产品包括计算机代码或计算机程序，当该计算机代码或计算机程序在计算机上运行时，使得本申请提供的数据传输方法中由发送端执行的操作和/或处理被实现。
本申请还提供一种计算机程序产品，该计算机程序产品包括计算机代码或计算机程序，当该计算机代码或计算机程序在计算机上运行时，使得本申请提供的数据传输方法中由接收端执行的操作和/或处理被实现。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (22)

  1. 一种数据传输方法，其特征在于，所述方法包括：
    通过差分传输线接收两路不同的模拟信号，所述差分传输线中的一条传输线对应一路模拟信号，且所述差分传输线共用一条地线；
    通过模数转换器对所述两路不同的模拟信号进行处理，获得两路不同的数字信号；
    通过蝶形均衡器对所述两路不同的数字信号进行均衡处理；
    通过解调器对所述蝶形均衡器输出的结果进行解调，获得两路不同的二进制比特流。
  2. 根据权利要求1所述的方法，其特征在于，所述两路不同的模拟信号中的一路模拟信号被平移和/或线性变换后，无法得到另一路模拟信号。
  3. 根据权利要求1或2所述的方法，其特征在于，所述方法还包括：
    通过双路合并器合并所述两路不同的二进制比特流，获得二进制数据流。
  4. 根据权利要求1-3任一项所述的方法，其特征在于，所述蝶形均衡器用于减少所述两路不同的数字信号之间的干扰。
  5. 根据权利要求1-4任一项所述的方法，其特征在于，所述通过差分传输线接收两路不同的模拟信号包括：
    在所述蝶形均衡器的工作模式为第一模式时，通过所述差分传输线接收所述两路不同的模式信号。
  6. 根据权利要求1-5任一项所述的方法，其特征在于，所述通过蝶形均衡器对所述两路不同的数字信号进行均衡处理之后，以及通过解调器对所述蝶形均衡器输出的结果进行解调，获得两路不同的二进制比特流之前，所述方法还包括：
    将所述蝶形均衡器输出的结果输入至判决器；
    将所述判决器输出的结果反馈至所述蝶形均衡器；
    所述通过解调器对所述蝶形均衡器输出的结果进行解调，获得两路不同的二进制比特流包括：
    通过所述解调器对所述判决器输出的结果进行解调，获得所述两路不同的二进制比特流。
  7. 根据权利要求1-5任一项所述的方法，其特征在于，所述通过蝶形均衡器对所述两路不同的数字信号进行均衡处理之后，以及所述通过解调器对所述蝶形均衡器输出的结果进行解调，获得两路不同的二进制比特流之前，所述方法还包括：
    通过均衡器对所述蝶形均衡器输出的结果再次进行均衡处理；
    所述通过解调器对所述蝶形均衡器输出的结果进行解调，获得两路不同的二进制比特流包括：
    通过所述解调器对所述均衡器输出的结果进行解调，获得所述两路不同的二进制比特流。
  8. 一种数据传输方法，其特征在于，所述方法包括：
    获取两路不同的二进制比特流；
    通过调制器对所述两路不同的二进制比特流进行调制；
    通过数模转换器对所述调制器输出的结果进行处理，获得两路不同的模拟信号；
    通过差分传输线发送所述两路不同的模拟信号，所述差分传输线中的一条传输线对应一路模拟信号，且所述差分传输线共用一条地线。
  9. 根据权利要求8所述的方法，其特征在于，所述两路不同的模拟信号中的一路模拟信号被平移和/或线性变换后，无法得到另一路模拟信号。
  10. 根据权利要求8或9所述的方法，其特征在于，所述获取两路不同的二进制比特流包括：
    通过双路分配器获取两路不同的二进制比特流。
  11. 根据权利要求8-10任一项所述的方法，其特征在于，所述通过调制器对所述两路不同的二进制比特流进行调制之后，以及所述通过数模转换器对所述调制器输出的结果进行处理，获得两路不同的模拟信号之前，所述方法还包括：
    通过蝶形均衡器对所述调制器输出的结果进行均衡处理；
    所述通过数模转换器对所述调制器输出的结果进行处理，获得两路不同的模拟信号包括：
    通过所述数模转换器对所述蝶形均衡器输出的结果进行处理，获得所述两路不同的模拟信号。
  12. 根据权利要求8-11任一项所述的方法，其特征在于，所述两路不同的二进制比特流来自于同一个数据报文或控制报文。
  13. 一种通信装置，其特征在于，所述装置包括：
    差分传输接口，用于接收通过差分传输线传输的两路不同的模拟信号，所述差分传输线中的一条传输线对应一路模拟信号，且所述差分传输线共用一条地线；
    模数转换器，用于对所述两路不同的模拟信号进行处理，获得两路不同的数字信号；
    蝶形均衡器，用于对所述两路不同的数字信号进行均衡处理；
    解调器，用于对所述蝶形均衡器输出的结果进行解调，获得两路不同的二进制比特流。
  14. 根据权利要求13所述的装置，其特征在于，所述两路不同的模拟信号中的一路模拟信号被平移和/或线性变换后，无法得到另一路模拟信号。
  15. 根据权利要求13或14所述的装置，其特征在于，所述装置还包括：
    双路合并器，用于合并所述两路不同的二进制比特流，获得二进制数据流。
  16. 根据权利要求13-15任一项所述的装置，其特征在于，所述蝶形均衡器用于减少所述两路不同的数字信号之间的干扰。
  17. 根据权利要求13-16任一项所述的装置，其特征在于，
    所述差分传输接口，具体用于在所述蝶形均衡器的工作模式为第一模式时，接收所述两路不同的模式信号。
  18. 根据权利要求13-17任一项所述的装置，其特征在于，所述装置还包括：
    判决器，用于对所述蝶形均衡器输出的结果进行处理，以及将所述判决器输出的结果反馈至所述蝶形均衡器；
    所述解调器，具体用于对所述判决器输出的结果进行解调，获得所述两路不同的二进制比特流。
  19. 根据权利要求13-17任一项所述的装置，其特征在于，所述装置还包括：
    均衡器，用于对所述蝶形均衡器输出的结果再次进行均衡处理；
    所述解调器，具体用于对所述均衡器输出的结果进行解调，获得所述两路不同的二进制比特流。
  20. 一种通信装置，其特征在于，所述装置包括：
    双路分配器，用于获取两路不同的二进制比特流；
    调制器，用于对所述两路不同的二进制比特流进行调制；
    数模转换器，用于对所述调制器输出的结果进行处理，获得两路不同的模拟信号；
    差分传输接口，用于发送所述两路不同的模拟信号，所述两路不同的模拟信号通过差分传输线传输，所述差分传输线中的一条传输线对应一路模拟信号，且所述差分传输线共用一条地线。
  21. 根据权利要求20所述的装置，其特征在于，所述两路不同的模拟信号中的一路模拟信号被平移和/或线性变换后，无法得到另一路模拟信号。
  22. 根据权利要求20或21所述的装置，其特征在于，所述装置还包括：
    蝶形均衡器，用于对所述调制器输出的结果进行均衡处理；
    所述数模转换器，具体用于对所述蝶形均衡器输出的结果进行处理，获得所述两路不同的模拟信号。
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