WO2022000315A1 - 一种像素驱动电路 - Google Patents

一种像素驱动电路 Download PDF

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Publication number
WO2022000315A1
WO2022000315A1 PCT/CN2020/099448 CN2020099448W WO2022000315A1 WO 2022000315 A1 WO2022000315 A1 WO 2022000315A1 CN 2020099448 W CN2020099448 W CN 2020099448W WO 2022000315 A1 WO2022000315 A1 WO 2022000315A1
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WIPO (PCT)
Prior art keywords
switch
pixel driving
electrically connected
nmos transistor
node
Prior art date
Application number
PCT/CN2020/099448
Other languages
English (en)
French (fr)
Inventor
方黎明
赵公元
闫潇
Original Assignee
华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to EP20943102.2A priority Critical patent/EP4156159A4/en
Priority to CN202080099887.8A priority patent/CN115398522A/zh
Priority to PCT/CN2020/099448 priority patent/WO2022000315A1/zh
Publication of WO2022000315A1 publication Critical patent/WO2022000315A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/04—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of a single character by selection from a plurality of characters, or by composing the character by combination of individual elements, e.g. segments using a combination of such display devices for composing words, rows or the like, in a frame with fixed character positions
    • G09G3/06—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of a single character by selection from a plurality of characters, or by composing the character by combination of individual elements, e.g. segments using a combination of such display devices for composing words, rows or the like, in a frame with fixed character positions using controlled light sources
    • G09G3/12—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of a single character by selection from a plurality of characters, or by composing the character by combination of individual elements, e.g. segments using a combination of such display devices for composing words, rows or the like, in a frame with fixed character positions using controlled light sources using electroluminescent elements
    • G09G3/14—Semiconductor devices, e.g. diodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/066—Waveforms comprising a gently increasing or decreasing portion, e.g. ramp
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0252—Improving the response speed
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0257—Reduction of after-image effects
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/025—Reduction of instantaneous peaks of current
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2007—Display of intermediate tones
    • G09G3/2077—Display of intermediate tones by a combination of two or more gradation control methods
    • G09G3/2081—Display of intermediate tones by a combination of two or more gradation control methods with combination of amplitude modulation and time modulation

Definitions

  • the present application relates to circuit technology, and in particular, to a pixel driving circuit.
  • LED Light Emitting Diode, light-emitting diode
  • LCD Liquid Crystal Display, liquid crystal display
  • an array of LED pixels is driven by a pixel driver circuit.
  • the pixel driving circuit is gated according to the row gate signal and the column drive signal, thereby driving the LED to emit light.
  • the anode of the LED is connected to the power supply, and the cathode is connected to the pixel driving circuit. Due to the parasitic capacitance and parasitic resistance of the cathode of the LED, when the LED is frequently switched between the on state and the off state, the pixel drive circuit needs to charge or discharge the cathode of the LED at a high speed, and the charging and discharging time affects the switching time of the LED switch, thus Limits the switching speed of the LEDs. When the LED switching speed is slow, the human eye can easily observe the afterimage phenomenon, which affects the user experience.
  • Embodiments of the present application provide a pixel driving circuit, which accelerates the absorption of charges in parasitic capacitors through a charge absorption circuit, thereby increasing the switching frequency of light emitting diodes.
  • an embodiment of the present application provides a pixel driving circuit, including a first switch and a second switch cascaded between a cathode of a light-emitting diode and a ground, and a charge absorption circuit, wherein the anode of the light-emitting diode is connected to a voltage source. connection, one end of the charge absorption circuit is electrically connected to the connection point (first node) of the first switch and the second switch, and the other end is connected to the ground.
  • the first end of the first switch is electrically connected to the cathode of the light emitting diode, and the control end of the first switch receives a control signal and turns on or off according to the control signal, thereby controlling the light emitting diode to turn on or off.
  • the first end of the second switch is electrically connected to the second end of the first switch, the second end of the second switch is grounded, and the control end of the second switch receives the bias voltage and is turned on in the working state.
  • the above-mentioned charge absorption circuit is used to absorb the electric charge from the above-mentioned first node.
  • the first switch When the first switch is turned off, the light-emitting diode is turned off, and the parasitic capacitance on the cathode (second node) of the light-emitting diode D1 will accumulate charges.
  • the first switch When the first switch is turned on, the charges in the parasitic capacitance are discharged through the first switch and the second switch, and can also be discharged through the charge absorption circuit.
  • the charge absorption circuit electrically connected to the first node can speed up the discharge of the charge of the first node, so that the charge in the parasitic capacitance can be discharged more quickly.
  • the discharge speed of the charge in the parasitic capacitance is accelerated, the establishment time of the current signal of the light-emitting diode becomes shorter, and the refresh frequency of the light-emitting diode becomes higher, so that the time from the light-emitting diode off to the light-on process is shortened, which can improve people's health. It can improve the display accuracy of LEDs and improve the user experience.
  • both the first switch and the second switch may be NMOS transistors, wherein the source of the first NMOS transistor as the first switch is electrically connected to the ground, and the drain of the first NMOS transistor is electrically connected to the ground as the first switch
  • the source of the second NMOS transistor of the second switch is electrically connected to the first node, and the drain of the second NMOS transistor is electrically connected to the cathode of the light emitting diode.
  • the charge absorption circuit includes a first capacitor, one end of the first capacitor is electrically connected to the first node, and the other end is grounded.
  • the capacitor as the charge absorption circuit occupies a small area resource, and can significantly improve the display performance of the light emitting diode at the expense of a very small hardware resource.
  • the first capacitor is a metal-insulating layer-metal MIM capacitor, a metal-oxide-metal MOM capacitor, or a metal-oxide-semiconductor MOS capacitor.
  • the above-mentioned charge absorption circuit includes diode-connected MOS transistors, that is, two MOS transistors are connected to form two-terminal devices and used as diodes.
  • the diode-connected MOS tube can better improve the display performance of the light-emitting diode.
  • the diode-connected MOS transistor includes a third NMOS transistor and a fourth NMOS transistor, wherein the drain and gate of the third NMOS transistor are electrically connected to the first node, and the fourth NMOS transistor is electrically connected to the first node.
  • the drain is electrically connected to the source of the third NMOS transistor, the source of the fourth NMOS transistor is grounded, and the gate of the fourth NMOS transistor is electrically connected to the first node.
  • the charge absorption circuit includes a Schottky diode, the cathode of the Schottky diode is electrically connected to the first node, and the anode is grounded.
  • the Schottky diode for the charge absorption circuit occupies a small area resource, and can significantly improve the display performance of the light emitting diode at the expense of a very small hardware resource.
  • the pixel driving circuit further includes a second capacitor, one end of which is electrically connected to the control end of the second switch, and the other end is grounded.
  • control signal input to the first switch is a pulse width modulated PWM signal.
  • the above-mentioned plurality of light emitting diodes may include a plurality of RGB pixels, and each RGB pixel includes three types of pixels: R, G, and B.
  • the above-mentioned multiple pixel driving circuits are respectively provided in multiple chips, wherein each pixel circuit drives a corresponding light emitting diode.
  • embodiments of the present application provide a pixel driving circuit, including a first switch and a second switch cascaded between a cathode of a light-emitting diode and ground, a charge absorption circuit and a ninth switch, wherein the anode of the light-emitting diode It is electrically connected to the voltage source, one end of the charge absorption circuit is electrically connected to the cathode of the light emitting diode through the ninth switch, and the other end is connected to the ground.
  • the first end of the first switch is electrically connected to the cathode of the light-emitting diode, and the control end of the first switch and the control end of the ninth switch receive the same control signal, and are turned on or off according to the control signal, thereby controlling the light-emitting diode to turn on or deadline.
  • the first end of the second switch is electrically connected to the second end of the first switch, the second end of the second switch is grounded, and the control end of the second switch receives the bias voltage and is turned on in the working state.
  • the above-mentioned charge absorption circuit is used to absorb the electric charge from the cathode of the light emitting diode.
  • the first switch When the first switch is turned off, the light-emitting diode is turned off, and the parasitic capacitance on the cathode (second node) of the light-emitting diode D1 will accumulate charges.
  • the first switch When the first switch is turned on, the charges in the parasitic capacitance are discharged through the first switch and the second switch, and can also be discharged through the charge absorption circuit.
  • the charge absorption circuit electrically connected with the cathode of the light emitting diode can speed up the discharge of the cathode charge of the light emitting diode, so that the charge in the parasitic capacitance can be discharged more quickly.
  • the discharge speed of the charge in the parasitic capacitance is accelerated, the establishment time of the current signal of the light-emitting diode becomes shorter, and the refresh frequency of the light-emitting diode becomes higher, so that the time from the light-emitting diode off to the light-on process is shortened, which can improve people's health. It can improve the display accuracy of LEDs and improve the user experience.
  • both the first switch and the second switch may be NMOS transistors, wherein the source of the first NMOS transistor as the first switch is electrically connected to the ground, and the drain of the first NMOS transistor is electrically connected to the ground as the first switch
  • the source of the second NMOS transistor of the second switch is electrically connected to the cathode of the light-emitting diode, and the drain of the second NMOS transistor is electrically connected to the cathode of the light-emitting diode.
  • the charge absorption circuit includes a first capacitor, one end of the first capacitor is electrically connected to the cathode of the light emitting diode, and the other end is grounded.
  • the capacitor as the charge absorption circuit occupies a small area resource, and can significantly improve the display performance of the light emitting diode at the expense of a very small hardware resource.
  • the first capacitor is a metal-insulating layer-metal MIM capacitor, a metal-oxide-metal MOM capacitor, or a metal-oxide-semiconductor MOS capacitor.
  • the above-mentioned charge absorption circuit includes diode-connected MOS transistors, that is, two MOS transistors are connected to form two-terminal devices and used as diodes.
  • the diode-connected MOS tube can better improve the display performance of the light-emitting diode.
  • the diode-connected MOS transistor includes a third NMOS transistor and a fourth NMOS transistor, wherein the drain and gate of the third NMOS transistor are electrically connected to the cathode of the light-emitting diode, and the fourth NMOS transistor is electrically connected to the cathode of the light-emitting diode.
  • the drain of the fourth NMOS transistor is electrically connected to the source of the third NMOS transistor, the source of the fourth NMOS transistor is grounded, and the gate of the fourth NMOS transistor is electrically connected to the cathode of the light-emitting diode.
  • the charge absorption circuit includes a Schottky diode, the cathode of the Schottky diode is electrically connected to the cathode of the light emitting diode, and the anode is grounded.
  • the Schottky diode for the charge absorption circuit occupies a small area resource, and can significantly improve the display performance of the light emitting diode at the expense of a very small hardware resource.
  • the pixel driving circuit further includes a second capacitor, one end of which is electrically connected to the control end of the second switch, and the other end is grounded.
  • control signal input to the first switch is a pulse width modulated PWM signal.
  • an embodiment of the present application provides a display circuit, including a plurality of pixel driving circuits in the first aspect and any possible implementation manner, and a plurality of light-emitting diodes, wherein the plurality of light-emitting diodes are respectively connected with the above-mentioned plurality of light-emitting diodes.
  • the pixel driving circuits are electrically connected, and the plurality of pixel driving circuits are used for respectively driving a plurality of light emitting diodes.
  • an embodiment of the present application provides a display circuit, including a plurality of pixel driving circuits in the second aspect and any possible implementation manner, and a plurality of light-emitting diodes, the plurality of light-emitting diodes are respectively connected with the above-mentioned plurality of light-emitting diodes.
  • the pixel driving circuits are electrically connected, and the plurality of pixel driving circuits are used for respectively driving a plurality of light emitting diodes.
  • embodiments of the present application provide a terminal device, including a back cover, a frame, and the display circuit of the third or fourth aspect, wherein the back cover and the display circuit are disposed opposite to each other and connected through the frame.
  • the pixel driving circuit of the second aspect, the display circuit of the third and fourth aspects, and the terminal device of the fifth aspect have similar effects as the pixel driving circuit of the first aspect, and can improve the human eye to observe the light-emitting diode The afterimage phenomenon at the time, and the improvement of the display accuracy of the light-emitting diode, will not be repeated here.
  • FIG. 1 is a schematic cross-sectional structure diagram of a terminal device according to an embodiment of the present application.
  • FIG. 2 is a schematic diagram of a display circuit provided by an embodiment of the present application.
  • FIG. 3 is a circuit structure diagram of a pixel driving circuit according to an embodiment of the present application.
  • 4a is a waveform diagram of a PWM signal in a pixel driving circuit provided by an embodiment of the present application
  • Fig. 4b is a current waveform diagram in the light-emitting diode
  • Fig. 4c is the waveform diagram of node A in the conventional circuit
  • FIG. 4d is a waveform diagram of node A in the pixel driving circuit provided by the embodiment of the present application.
  • FIG. 5 is a more specific pixel driving circuit provided by an embodiment of the present application.
  • FIG. 6 is another more specific pixel driving circuit provided by an embodiment of the present application.
  • FIG. 7 is yet another more specific pixel driving circuit provided by an embodiment of the present application.
  • FIG. 8 is yet another more specific pixel driving circuit provided by an embodiment of the present application.
  • FIG. 9 is a schematic diagram of still another pixel driving circuit according to an embodiment of the present application.
  • connection should be understood in a broad sense.
  • electrical connection may refer to a physical direct connection, or it may refer to an electrical connection through an intermediate medium, such as through a resistor, an inductor, or other electrical components. Connection.
  • the "first terminal” and the “second terminal” may refer to the connection terminal of the three-terminal switching element, respectively, and the “control terminal” may refer to the control terminal of the three-terminal switching element.
  • the control terminal may refer to the gate of the MOS tube
  • the first terminal may refer to the source of the MOS tube
  • the second terminal may refer to the source of the MOS tube.
  • the terminal refers to the drain of the MOS transistor, or the first terminal may refer to the drain of the MOS transistor, and the second terminal refers to the source of the MOS transistor.
  • the terminal device 200 may be a smart phone, a portable computer, a tablet computer, an electronic bracelet, etc., or an ultra-small display.
  • the above-mentioned terminal device 200 includes a screen 210, a frame 220, and a back cover 230, wherein the screen 210 and the back cover 230 are disposed opposite to each other and are connected by the frame 220 to form a cavity between the screen 210 and the back cover 230.
  • a substrate 240 is arranged in the cavity, and a plurality of driving circuits 250 are arranged on the substrate 240 .
  • the substrate 240 is also provided with an LED array 260, wherein one driving circuit 250 can be connected with one or more LED arrays 260 and drive the corresponding LED arrays 260 to emit light.
  • the above-mentioned substrate 240 may be a PCB (Printed Circuit Board, printed circuit board).
  • the terminal device 200 may further include a touch panel for sensing the touch signal and converting it into an electrical signal.
  • the terminal device 200 may also include other chips such as a processor chip, a memory chip, and a baseband chip.
  • the above-mentioned chip can be disposed on the substrate 240 or other PCB in the terminal device 200 , and is electrically connected to the above-mentioned driving circuit 250 to control the driving circuit 250 to drive the LED array 260 .
  • FIG. 2 is a schematic diagram of a display circuit 300 provided by an embodiment of the present application.
  • the display circuit 300 may be a micro light emitting diode (micro LED, micro Light Emitting Diode) display circuit.
  • the display circuit 300 includes a plurality of pixel driving circuits 310 arranged in an array and a plurality of RGB pixels corresponding thereto.
  • the above-mentioned pixel driving circuit 310 may be the driving circuit 250 shown in FIG. 1
  • the RGB pixels may be the LED array 260 shown in FIG. 1 .
  • Each pixel driving circuit 310 can drive 4 RGB pixels in the connection relationship shown in FIG. 2 , can also drive more RGB pixels, or only drive one RGB pixel.
  • Each RGB pixel includes R (red, red), G (green, green) and B (blue, blue).
  • the above-mentioned plurality of pixel driving circuits 310 may be respectively disposed in a plurality of chips, or may be fabricated on the above-mentioned substrate 240 in the form of thin film transistors (TFTs).
  • TFTs thin film transistors
  • each pixel driving circuit includes 12 current sources to drive 12 light-emitting diodes in the above-mentioned 4 RGB pixels.
  • multiple pixel driving circuits can also be integrated into one chip.
  • FIG. 3 is a circuit structure diagram of a pixel driving circuit 310 provided by an embodiment of the present application.
  • the pixel driving circuit 310 includes a first switch M1 and a second switch M2 connected in cascade, and a charge absorption circuit 311 .
  • the first end of the first switch M1 is electrically connected to the cathode of the light emitting diode D1
  • the second end of the first switch M1 is electrically connected to the first end of the second switch M2
  • the control end of the first switch M1 is used for receiving switch control Signal.
  • the switch control signal may be a PWM (pulse width modulation, pulse width modulation) signal.
  • the second end of the second switch M2 is grounded, and is electrically connected to one end of the second capacitor Cgg.
  • the control terminal of the second switch M2 is used for receiving the bias voltage VBIAS.
  • the anode of the above-mentioned light-emitting diode D1 is connected to a power source to provide a voltage difference applied across the light-emitting diode D1.
  • the above-mentioned charge absorption circuit 311 is electrically connected to the node A (ie, the connection point of the first switch M1 and the second switch M2 ), so as to absorb the charge of the node A. Part of the charge at the node A flows to the ground through the second switch M2 , and the other part is absorbed by the charge absorption circuit 311 .
  • the pixel driving circuit 310 may further include a second capacitor Cgg electrically connected to the control terminal and the second terminal of the second switch M2.
  • the first switch M1 is turned on or off by the received switch control signal, and the second switch M2 is kept on by the received bias voltage VBIAS.
  • the switch control signal turns off the first switch M1
  • the voltage of node B ie the cathode of LED D1 becomes high
  • the current in LED D1 is 0, and the parasitic capacitance Cp on node B will accumulate charge.
  • the switch control signal controls the first switch M1 to be turned on
  • the parasitic capacitance Cp is discharged through the first switch M1 and the second switch M2.
  • the voltage of node B is lower than a certain threshold (depending on the characteristics of the light emitting diode D1), the light emitting diode D1 is turned on.
  • the above-mentioned charge absorption circuit 311 can absorb the charge of the node A after the first switch M1 is turned on. Therefore, the charge accumulated in the parasitic capacitance Cp can be discharged through the first switch M1 first, then through the second switch M2, and at the same time through the charge absorption circuit 311, thereby accelerating the discharge of the parasitic capacitance Cp on the node B and improving the LED D1
  • the settling time of the current signal increases the refresh frequency of the light-emitting diode D1.
  • the bias voltage VBIAS controls the second switch M2 to be turned off.
  • the light-emitting diode D1 When the voltage of the node B is lower than a certain threshold, the light-emitting diode D1 is turned on.
  • the threshold is mainly related to the forward voltage of the light-emitting diode D1.
  • the forward conduction voltage of a silicon (Si) tube is about 0.7V
  • that of a germanium (Ge) tube is about 0.3V.
  • the first switch M1 and the second switch M2 are both NMOS transistors, wherein the control terminal of the first switch M1 is the gate, the first terminal of the first switch M1 is the drain, and the second terminal is source.
  • the control terminal of the second switch M2 is the gate, the first terminal of the second switch M2 is the drain, and the second terminal is the source.
  • the above-mentioned switch control signal is generated by the control signal generator and output to the control terminal of the first switch M1 in the pixel driving circuit 310 .
  • the control signal generator and the pixel driving circuit 310 may be provided in different chips, for example, one pixel driving circuit 310 is provided in a corresponding one of the driver ICs, and the control signal generator is provided in other chips .
  • a control signal generated by a control signal generator, such as a PWM signal, can control the turn-on and turn-off of the first switches M1 in the plurality of pixel driving circuits 310 .
  • FIG. 4a shows the waveform diagram of the PWM signal in the pixel driving circuit 310
  • FIG. 4b shows the waveform diagram of the current I D1 in the light-emitting diode D1
  • FIG. 4c shows the waveform diagram of the conventional circuit in the The waveform diagram of the node A
  • FIG. 4d shows the optimized circuit, that is, the waveform diagram of the node A in the pixel driving circuit 310 provided by the embodiment of the present application.
  • the embodiments of the present application are described by taking the switch control signal as a PWM signal, and the first switch M1 and the second switch M2 both being NMOS transistors as an example.
  • the second switch M2 is turned on. 0 to time t 1, the PWM signal is low, then the first switch M1 is in OFF state, the voltage at node B is higher than the threshold voltage, the current in the light emitting diode D1 to the I D1 0, a light emitting diode D1 is off. At time t 1, the PWM signal from a low level to a high level, while the first switch M1 is switched from the OFF state to the ON state.
  • the conventional circuit in the prior art has a parasitic capacitance Cp at node B, when the first switch M1 is switched from the off state to the on state, the parasitic capacitance Cp First, it needs to discharge through the first switch M1 and the second switch M2 from time t 1 to t 4 until the voltage of node B is lower than the above-mentioned threshold voltage.
  • the light emitting diode D1 D1 of the I current begins to increase and reaches a maximum at time t3, and then holds the maximum value to the time t 2, the light emitting diode D1 is lit.
  • the PWM signal from high to low, the current in the light emitting diode D1 the I D1 becomes small.
  • the node A in the conventional circuit in the prior art needs time T1 to complete the signal establishment after the first switch M1 is turned on.
  • the parasitic capacitance Cp is in the discharging process, which causes the light-emitting diode D1 to take a long time from extinguishing to lighting.
  • the parasitic capacitance Cp is larger, the time from t 1 to t 4 is longer, and it is easier for the human eye to observe the afterimage phenomenon, which affects the user experience.
  • the charge absorption circuit 311 connected to the node A in the pixel driving circuit 310 provided by the embodiment of the present application can absorb the charge of the node A when the parasitic capacitance Cp is discharged, thereby accelerating the discharge process and the refresh frequency of the light emitting diode D1.
  • the current I D1 in the LED D1 can reach the maximum value faster and stabilize, so that the LED D1 can emit light normally.
  • FIG. 4b shows that the current I D1 in the LED D1 can reach the maximum value faster and stabilize, so that the LED D1 can emit light normally.
  • the voltage of the node A in the pixel driving circuit 310 decreases to be close to the normal operating voltage after the time T2 has elapsed, and then reaches the normal operating voltage after the elapse of the time T3 .
  • the pixel driver 310 provided by the embodiment of the present application can reduce the node B to the normal operating voltage in a shorter time, thereby speeding up the signal setup time of the light emitting diode D1, so that the switching frequency of the light emitting diode D1 is increased, so that the To achieve the purpose of eliminating afterimages, improving display accuracy, and improving user experience.
  • a more specific pixel driving circuit 310 provided by an embodiment of the present application, wherein the charge absorption circuit 311 includes a capacitor Ca.
  • the charge in the parasitic capacitor Cp can be absorbed by the capacitor Ca through the first switch M1 and the node A, which is equivalent to redistributing the charge in the capacitor Ca and the parasitic capacitor Cp, accelerating the discharge process to the node B.
  • the capacitance value of the above-mentioned capacitance Ca is related to the capacitance value of the parasitic capacitance Cp.
  • the capacitance Ca also needs a large capacitance value.
  • the first switch M1 is turned off, the larger the voltage difference between the node B and the node A is, the larger the capacitance value of the capacitor Ca is also required.
  • the capacitor Ca may be a metal-insulator-metal (MIM) capacitor, a metal-oxide-metal (MOM) capacitor or a metal-oxide-semiconductor (metal-oxide-) capacitor. semiconductor, MOS) capacitors.
  • MIM metal-insulator-metal
  • MOM metal-oxide-metal
  • MOS metal-oxide-semiconductor
  • the charge absorption circuit 311 includes a diode-connected MOS transistor.
  • the diode-connected MOS transistors include an NMOS transistor M3 and an NMOS transistor M4, wherein the drain and gate of the NMOS transistor M3 are connected to the node A, the drain of the NMOS transistor M4 is connected to the source of the NMOS transistor M3, and the NMOS transistor M4 is connected to the source of the NMOS transistor M3.
  • the source of the transistor M4 is grounded, and the gate of the NMOS transistor M4 is also connected to the above-mentioned node A.
  • the charge in the parasitic capacitor Cp can flow to the ground through the NMOS transistor M3 and the NMOS transistor M4 that are turned on.
  • the first switch M1 when the first switch M1 is turned on, the voltage of the node A increases, the NMOS transistor M3 and the NMOS transistor M4 are turned on at this time, and the voltages of the node A and the node B both drop rapidly.
  • the NMOS transistor M3 and the NMOS transistor M4 are turned off.
  • the second switch M2 continues to discharge the node A and the node B, so that the node B reaches the voltage at which the light-emitting diode D1 works normally.
  • the charge absorption circuit 311 includes a Schottky diode D2.
  • the cathode of the Schottky diode D2 is electrically connected to the node A, and the anode is grounded.
  • the Schottky diode D2 can also absorb the charge of the node A faster, so that the pixel driver 310 can reduce the node B to the normal operating voltage in a shorter time, thereby speeding up the signal establishment time of the light emitting diode D1 and making the switching frequency of the light emitting diode D1.
  • the pixel driving circuit 310 shown in FIG. 8 further includes a fifth switch M5 connected between the second switch M2 and the ground.
  • the fifth switch M5 may be an NMOS transistor.
  • the drain of the fifth switch M5 is connected to the source of the second switch M2, the source is grounded and connected to one end of the capacitor Cgg, and the gate of the fifth switch M5 is connected to the gate of the second switch M2 and connected to the gate of the second switch M2. Connect to the other end of capacitor Cgg to receive bias voltage VBIAS.
  • the charge absorption circuit 311 in FIG. 8 may be any one of the charge absorption circuits provided in the embodiments of the present application.
  • an embodiment of the present application further provides a bias circuit 320 .
  • the bias circuit 320 includes a sixth switch M6, a seventh switch M7 and an eighth switch M8.
  • the sixth switch M6 and the seventh switch M7 are NMOS transistors
  • the eighth switch M8 is a PMOS transistor.
  • the source of the sixth switch M6 is grounded, and the gate is connected to the gate of the seventh switch M7 to generate the bias voltage VBIAS.
  • the drain of the sixth switch M6 is connected to the source of the seventh switch M7.
  • the drain of the seventh switch M7 is connected to the gate of the seventh switch M7 and the drain of the eighth switch M8 respectively, and the source of the eighth switch M8 is connected to the power supply.
  • the bias circuit 320 may provide a bias voltage for any of the pixel driving circuits provided in the embodiments of the present application.
  • the above-mentioned bias circuit 320 and the pixel driving circuit 310 may be respectively provided in different chips.
  • the above-mentioned bias circuit 320 can provide the bias voltage VBIAS for the plurality of pixel driving circuits 310 .
  • the above-mentioned bias circuit 320 may also be integrated with one or more pixel driving circuits 310 in the same chip.
  • an embodiment of the present application further provides a pixel driving circuit 900 .
  • the circuit structure of the pixel driving circuit 900 is similar to that of the pixel driving circuit 310, the difference is that the charge absorption circuit 310 in the pixel driving circuit 900 is connected to the cathode of the light emitting diode D1 through the ninth switch M9.
  • the charge absorption circuit 310 in the pixel driving circuit 900 may be any of the charge absorption circuits in the embodiments of the present application.
  • One end of the ninth switch M9 is connected to one end of the charge absorption circuit 310, and the other end is connected to the cathode of the light emitting diode D1, and the PWM signal received by the gate of the ninth switch M9 is the same as the PWM signal received by the first switch M1.
  • the charge absorption circuit 310 begins to absorb the charge of the light emitting diode D1, thereby accelerating the light emission.
  • the discharge of the cathode charge of the diode D1 enables the charge in the parasitic capacitance to be discharged more quickly.
  • the establishment time of the current signal of the light-emitting diode becomes shorter, and the refresh frequency of the light-emitting diode becomes higher, so that the time from the light-emitting diode off to the light-on process is shortened, which can improve people's health. It can improve the display accuracy of LEDs and improve the user experience.
  • the pixel driving circuits provided in the embodiments of the present application can also be used for other devices, such as super-large indoor display screens, head-mounted displays (HMDs), head-up displays Display (head up display, HUD), wireless optical communication (Li-Fi, Light Fidelity), AR (augmented reality, augmented reality), VR (virtual reality, virtual reality), etc.
  • HMDs head-mounted displays
  • HUD head-up displays Display
  • Wi-Fi Light Fidelity
  • AR augmented reality, augmented reality
  • VR virtual reality, virtual reality

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Abstract

本申请实施例提供一种可以用于micro LED的像素驱动电路，包括级联于发光二极管的阴极和地之间的第一开关和第二开关，以及电荷吸收电路。其中，第一开关被PWM信号控制以控制发光二极管的导通和截止，第二开关的控制端接收偏置电压，电荷吸收电路与第一开关和第二开关的连接点相连，以吸收该连接点上的电荷，加速发光二极管的信号建立，提升像素发光二极管的显示性能。

Description

一种像素驱动电路 技术领域
本申请涉及电路技术，尤其涉及一种像素驱动电路。
背景技术
LED(Light Emitting Diode，发光二极管)显示面板采用LED实现像素显示，其显示性能相较于传统的LCD(Liquid Crystal Display，液晶显示)具有更高的对比度和亮度。
在LED显示面板中，LED像素阵列被像素驱动电路驱动。像素驱动电路根据行选通信号和列驱动信号被选通，从而驱动LED发光。LED的阳极与电源连接，阴极与像素驱动电路连接。由于LED的阴极存在寄生电容和寄生电阻，LED频繁在导通状态和断开状态切换时，像素驱动电路需要对LED的阴极进行高速充电或放电，而充放电时间影响LED开关切换的时间，从而限制了LED的开关速度。当LED开关速度较慢，人眼容易观察到残影现象，影响用户体验。
发明内容
本申请实施例提供一种像素驱动电路，通过电荷吸收电路加速吸收寄生电容中的电荷，从而提升发光二极管的开关频率。
第一方面，本申请实施例提供一种像素驱动电路，包括级联于发光二极管的阴极和地之间的第一开关和第二开关，以及电荷吸收电路，其中发光二极管的阳极与电压源电连接，电荷吸收电路的一端与第一开关和第二开关的连接点(第一节点)电连接，另一端与地连接。上述第一开关的第一端与发光二极管的阴极电连接，第一开关的控制端接收控制信号，根据控制信号导通或断开，从而控制发光二极管导通或截止。第二开关的第一端与第一开关的第二端电连接，第二开关的第二端接地，第二开关的控制端接收偏置电压并在工作状态导通。上述电荷吸收电路用于从上述第一节点吸收电荷。当第一开关断开，发光二极管熄灭，发光二极管D1的阴极(第二节点)上的寄生电容会累积电荷。当第一开关导通，寄生电容中的电荷通过第一开关以及第二开关放电，同时还可以通过电荷吸收电路放电。
与第一节点电连接的电荷吸收电路可以加快第一节点电荷的释放，使得寄生电容中的电荷能够更快地释放。当寄生电容中的电荷释放速度加快，则发光二极管的电流信号的建立时间变短，发光二极管的刷新频率变高，从而使得发光二极管从熄灭到点亮的过程经历的时间变短，可以改善人眼观察发光二极管时的残影现象，以及提高发光二极管的显示精度，提升用户体验。
在一种可能的实施方式中，上述第一开关和第二开关均可以为NMOS管，其中作为第一开关的第一NMOS管的源极与地电连接，第一NMOS管的漏极与 作为第二开关的第二NMOS管的源极电连接于上述第一节点，第二NMOS管的漏极与发光二极管的阴极电连接。
在一种可能的实施方式中，上述电荷吸收电路包括第一电容，该第一电容的一端与上述第一节点电连接，另一端接地。作为电荷吸收电路的电容占用较小的面积资源，可以以极小的硬件资源为代价显著提升发光二极管的显示性能。
在一种可能的实施方式中，上述第一电容为金属-绝缘层-金属MIM电容、金属-氧化物-金属MOM电容或金属-氧化物-半导体MOS电容。
在一种可能的实施方式中，上述电荷吸收电路包括二极管连接的MOS管，即两个MOS管被连接成两端器件作为二极管使用。二极管连接的MOS管可以更好地提升发光二极管的显示性能。
在一种可能的实施方式中，上述二极管连接的MOS管包括第三NMOS管和第四NMOS管，其中第三NMOS管的漏极和栅极与上述第一节点电连接，第四NMOS管的漏极和第三NMOS管的源极电连接，第四NMOS管的源极接地，第四NMOS管的栅极与上述第一节点电连接。
在一种可能的实施方式中，上述电荷吸收电路包括肖特基二极管，该肖特基二极管的阴极与上述第一节点电连接，阳极接地。为电荷吸收电路的肖特基二极管占用较小的面积资源，可以以极小的硬件资源为代价显著提升发光二极管的显示性能。
在一种可能的实施方式中，上述像素驱动电路还包括第二电容，其一端与第二开关的控制端电连接，另一端接地。
在一种可能的实施方式中，输入至上述第一开关的控制信号为脉冲宽度调制PWM信号。
在一种可能的实施方式中，上述多个发光二极管可以包括多个RGB像素，每个RGB像素包括R、G和B三种像素。
在一种可能的实施方式中，上述多个像素驱动电路被分别设置于多个芯片中，其中每个像素电路驱动与之对应的发光二极管。
第二方面，本申请实施例提供一种像素驱动电路，包括级联于发光二极管的阴极和地之间的第一开关和第二开关，以及电荷吸收电路和第九开关，其中发光二极管的阳极与电压源电连接，电荷吸收电路的一端通过第九开关与发光二极管的阴极电连接，另一端与地连接。上述第一开关的第一端与发光二极管的阴极电连接，第一开关的控制端与第九开关的控制端接收相同的控制信号，根据控制信号导通或断开，从而控制发光二极管导通或截止。第二开关的第一端与第一开关的第二端电连接，第二开关的第二端接地，第二开关的控制端接收偏置电压并在工作状态导通。上述电荷吸收电路用于从发光二极管的阴极吸收电荷。当第一开关断开，发光二极管熄灭，发光二极管D1的阴极(第二节点)上的寄生电容会累积电荷。当第一开关导通，寄生电容中的电荷通过第一开关以及第二开关放电，同时还可以通过电荷吸收电路放电。
与发光二极管的阴极电连接的电荷吸收电路可以加快发光二极管的阴极电荷的释放，使得寄生电容中的电荷能够更快地释放。当寄生电容中的电荷释放速度加快，则发光二极管的电流信号的建立时间变短，发光二极管的刷新频率变高，从而使得发光二极管从熄灭到点亮的过程经历的时间变短，可以改善人眼观察发光二极管时的残影现象，以及提高发光二极管的显示精度，提升用户体验。
在一种可能的实施方式中，上述第一开关和第二开关均可以为NMOS管，其中作为第一开关的第一NMOS管的源极与地电连接，第一NMOS管的漏极与作为第二开关的第二NMOS管的源极电连接于上述发光二极管的阴极，第二NMOS管的漏极与发光二极管的阴极电连接。
在一种可能的实施方式中，上述电荷吸收电路包括第一电容，该第一电容的一端与上述发光二极管的阴极电连接，另一端接地。作为电荷吸收电路的电容占用较小的面积资源，可以以极小的硬件资源为代价显著提升发光二极管的显示性能。
在一种可能的实施方式中，上述第一电容为金属-绝缘层-金属MIM电容、金属-氧化物-金属MOM电容或金属-氧化物-半导体MOS电容。
在一种可能的实施方式中，上述电荷吸收电路包括二极管连接的MOS管，即两个MOS管被连接成两端器件作为二极管使用。二极管连接的MOS管可以更好地提升发光二极管的显示性能。
在一种可能的实施方式中，上述二极管连接的MOS管包括第三NMOS管和第四NMOS管，其中第三NMOS管的漏极和栅极与上述发光二极管的阴极电连接，第四NMOS管的漏极和第三NMOS管的源极电连接，第四NMOS管的源极接地，第四NMOS管的栅极与上述发光二极管的阴极电连接。
在一种可能的实施方式中，上述电荷吸收电路包括肖特基二极管，该肖特基二极管的阴极与上述发光二极管的阴极电连接，阳极接地。为电荷吸收电路的肖特基二极管占用较小的面积资源，可以以极小的硬件资源为代价显著提升发光二极管的显示性能。
在一种可能的实施方式中，上述像素驱动电路还包括第二电容，其一端与第二开关的控制端电连接，另一端接地。
在一种可能的实施方式中，输入至上述第一开关的控制信号为脉冲宽度调制PWM信号。
第三方面，本申请实施例提供一种显示电路，包括多个第一方面及任意一种可能的实施方式中的像素驱动电路，和多个发光二极管，上述多个发光二极管分别与上述多个像素驱动电路电连接，上述多个像素驱动电路用于分别驱动多个发光二极管。
第四方面，本申请实施例提供一种显示电路，包括多个第二方面及任意一种可能的实施方式中的像素驱动电路，和多个发光二极管，上述多个发光二极管分别与上述多个像素驱动电路电连接，上述多个像素驱动电路用于分别驱动多个发 光二极管。
第五方面，本申请实施例提供一种终端设备，包括后盖、边框，和第三方面或第四方面中的显示电路，其中上述后盖和显示电路相对设置，并通过边框连接。
第二方面的像素驱动电路，第三方面和第四方面中的显示电路，以及第五方面中的终端设备具有与第一方面中的像素驱动电路相似的效果，均可以改善人眼观察发光二极管时的残影现象，以及提高发光二极管的显示精度，此处不再赘述。
附图说明
图1为本申请实施例提供的一种终端设备的剖面结构示意图。
图2为本申请实施例提供的一种显示电路的示意图。
图3为本申请实施例提供的一种像素驱动电路的电路结构图。
图4a为本申请实施例提供的像素驱动电路中的PWM信号的波形图；
图4b为发光二极管中的电流波形图；
图4c为传统电路中节点A的波形图；
图4d为本申请实施例提供的像素驱动电路中节点A的波形图。
图5为本申请实施例提供的一种更具体的像素驱动电路。
图6为本申请实施例提供的另一种更具体的像素驱动电路。
图7为本申请实施例提供的又一种更具体的像素驱动电路。
图8为本申请实施例提供的又一种更具体的像素驱动电路。
图9为本申请实施例提供的又一种像素驱动电路的示意图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。
在本申请中，术语“第一”、“第二”等仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。此外，术语“电连接”应做广义的理解，例如，“电连接”可以指物理上的直接连接，也可以指通过中间媒介实现电学上的连接，例如通过电阻、电感，或其他电学元件实现的连接。
在用于描述三端开关元件时，“第一端”和“第二端”可以分别指该三端开关元件的连接端，而“控制端”可以指该三端开关元件的控制端。例如对于一个MOS(metal-oxide-semiconductor，金属氧化物半导体)管开关，控制端可以指该MOS管的栅极(gate)，第一端可以指该MOS管的源极(source)，第二端指MOS管的漏极(drain)，或者第一端可以指该MOS管的漏极，第二端指MOS管的源极。
如图1所示的是本申请实施例提供的一种终端设备200的剖面结构示意图，该终端设备200可以为智能手机、便携式电脑、平板电脑、电子手环等或者超小型显示器。上述终端设备200包括屏幕210、边框220、后盖230，其中屏幕210和后盖230相对设置，并通过边框220连接，以在屏幕210和后盖230之间形成 空腔。该空腔中设置有基板240，且基板240上设置有多个驱动电路250。基板240上还设置有LED阵列260，其中一个驱动电路250可以与一个或多个LED阵列260连接，并驱动对应的LED阵列260发光。上述基板240可以是PCB(Printed Circuit Board，印制电路板)。该终端设备200还可以包括触控面板，用于感应接触信号，并转换为电信号。终端设备200还可以包括处理器芯片、存储芯片、基带芯片等其他芯片。上述芯片可以设置于基板240上，也可以设置于终端设备200中的其他PCB上，并与上述驱动电路250电连接，以控制驱动电路250来驱动LED阵列260。
图2所示的是本申请实施例提供的一种显示电路300的示意图，显示电路300可以是微型发光二极管(micro LED，micro Light Emitting Diode)显示电路。显示电路300包括了多个阵列排布的像素驱动电路310和与其对应的多个RGB像素。上述像素驱动电路310可以是图1所示的驱动电路250，RGB像素可以是图1所示的LED阵列260。每个像素驱动电路310可以以图2所示的连接关系驱动4个RGB像素，也可以驱动更多RGB像素，或者仅驱动1个RGB像素。每个RGB像素包括R(red，红)，G(green，绿)和B(blue，蓝)。上述多个像素驱动电路310可以分别设置多个芯片中，也可以以薄膜晶体管(thin film transistor，TFT)的形式制作于上述基板240上。以一个像素驱动电路310驱动4个RGB像素为例，对于分辨率为2560*1440的2K屏幕，显示电路300可以包括2560*1440/4＝921600个像素驱动电路310，每一个像素驱动电路310都设置于一个芯片中并驱动4个RGB像素。具体的，每个像素驱动电路中都包含12个电流源，以驱动上述4个RGB像素中的12个发光二极管。在另一种实施方式中，多个像素驱动电路也可以集成于一个芯片中。
图3所示的是本申请实施例提供的一种像素驱动电路310的电路结构图。像素驱动电路310包括及级联的第一开关M1和第二开关M2，电荷吸收电路311。其中第一开关M1的第一端与发光二极管D1的阴极电连接，第一开关M1的第二端与第二开关M2的第一端电连接，第一开关M1的控制端用于接收开关控制信号。在一种实施方式中，该开关控制信号可以是PWM(pulse width modulation，脉冲宽度调制)信号。第二开关M2的第二端接地，并与第二电容Cgg的一端电连接。第二开关M2的控制端用于接收偏置电压VBIAS。此外，上述发光二极管D1的阳极与电源连接，以提供施加在发光二极管D1两端的电压差。上述电荷吸收电路311与节点A(即第一开关M1和第二开关M2的连接点)电连接，以吸收节点A的电荷。节点A的电荷一部分通过第二开关M2流向地，另一部分被电荷吸收电路311吸收。像素驱动电路310还可以包括电连接于第二开关M2的控制端和第二端的第二电容Cgg。
在工作状态下，上述第一开关M1通过接收的开关控制信号导通或断开，上述第二开关M2通过接收的偏置电压VBIAS保持导通。当开关控制信号控制第一开关M1断开时，节点B(即发光二极管D1的阴极)的电压变高，发光二极管 D1中的电流为0，节点B上的寄生电容Cp会累积电荷。当开关控制信号控制第一开关M1导通时，寄生电容Cp通过第一开关M1和第二开关M2进行放电。当节点B的电压低于某一阈值(取决于发光二极管D1的特性)时，发光二极管D1导通。上述电荷吸收电路311在第一开关M1导通后，可以吸收节点A的电荷。因此，寄生电容Cp中累积的电荷可以先通过第一开关M1，然后通过第二开关M2进行放电，同时通过电荷吸收电路311进行放电，从而加快节点B上的寄生电容Cp放电，提高发光二极管D1的电流信号建立时间，提高发光二极管D1的刷新频率。在非工作状态下，偏置电压VBIAS控制第二开关M2断开。
上述节点B的电压低于某一阈值时，发光二极管D1导通。该阈值主要与发光二极管D1的正向导通电压有关。例如，对于硅(Si)管其正向导通电压约为0.7V，而锗(Ge)管的正向导通电压约为0.3V。
在一种实施方式中，上述第一开关M1和第二开关M2均为NMOS管，其中第一开关M1的控制端为栅极，第一开关M1的第一端为漏极，第二端为源极。第二开关M2的控制端为栅极，第二开关M2的第一端为漏极，第二端为源极。
上述开关控制信号由控制信号产生器产生并输出至像素驱动电路310中第一开关M1的控制端。在一种实施方式中，控制信号产生器与像素驱动电路310可以分别设置在不同的芯片中，例如一个像素驱动电路310设置在对应的一个驱动IC中，而控制信号产生器设置在其他芯片中。一个控制信号产生器产生的控制信号，例如PWM信号，可以控制多个像素驱动电路310中的第一开关M1的导通和关闭。
在同一个充放电周期内，图4a示出了像素驱动电路310中的PWM信号的波形图，图4b示出了发光二极管D1中的电流I D1的波形图，图4c示出了传统电路中节点A的波形图，而图4d示出了优化后的电路，即本申请实施例提供的像素驱动电路310中节点A的波形图。本申请实施例以开关控制信号为PWM信号，第一开关M1和第二开关M2均为NMOS管为例进行说明。
像素驱动电路310正常工作时，第二开关M2导通。在0到t 1时刻，PWM信号为低电平，此时第一开关M1处于断开状态，因此节点B的电压高于上述阈值电压，发光二极管D1中的电流I D1为0，发光二极管D1处于熄灭状态。在t 1时刻，PWM信号从低电平变为高电平，此时第一开关M1从断开状态切换为导通状态。由于第一开关M1和第二开关M2均为导通状态，理想状态下节点B的电压会迅速下降至0，而发光二极管D1中的电流I D1会迅速增大到一个较大的值，如图4b中“理想电流”曲线所示。实际工作中，如图4b中“传统电路”曲线所示，现有技术中的传统电路由于节点B存在寄生电容Cp，当第一开关M1从断开状态切换为导通状态时，寄生电容Cp首先需要在t 1至t 4时刻通过第一开关M1和第二开关M2进行放电，直到节点B的电压低于上述阈值电压。在t 4时刻，发光二极管D1中的电流I D1开始增大，并在t3时刻达到最大值，然后保持该最大值至t 2时刻，发光二极管D1处于点亮状态。在t 2时刻，PWM信号从高电平 变为低电平，发光二极管D1中的电流I D1变小。相应的，如图4c所示，由于放电缓慢，现有技术中的传统电路中的节点A在第一开关M1导通后，需要T1的时间才能完成信号建立。由图4a-5c可知，在t 1至t 4时刻，寄生电容Cp处于放电过程，导致发光二极管D1从熄灭到点亮的过程经历较长时间。当寄生电容Cp越大，则t 1至t 4的时间越长，人眼更容易观察到残影现象，影响用户体验。
本申请实施例提供的像素驱动电路310中与节点A连接的电荷吸收电路311可以在寄生电容Cp放电时吸收节点A的电荷，从而加速放电过程，加快发光二极管D1的刷新频率。如图4b中“优化后电路”曲线所示，由于电荷吸收电路311加速了放电过程，发光二极管D1中的电流I D1能够更快地到达最大值并稳定，使得发光二极管D1能够正常的发光。如图4d所示，像素驱动电路310中节点A的电压在经过了T2时间后降低到接近正常工作电压，然后经过T3时间后达到正常工作电压。与T3时间相比，本申请实施例提供的像素驱动310可以在更短的时间使节点B降低到正常工作电压，从而加快发光二极管D1的信号建立时间，使得发光二极管D1的开关频率提高，以达到消除残影，提升显示精度，提升用户体验的目的。
如图5所示的是本申请实施例提供的一种更具体的像素驱动电路310，其中电荷吸收电路311包括电容Ca。在上述放电过程中，寄生电容Cp中的电荷可以通过第一开关M1和节点A被电容Ca吸收，相当于重新分配电容Ca和寄生电容Cp中的电荷，加速了对节点B的放电过程。上述电容Ca的电容值与寄生电容Cp的电容值有关，当寄生电容Cp的电容值较大时，电容Ca也需要较大的电容值。此外，当第一开关M1断开时，节点B和节点A的电压差越大，则电容Ca也需要较大的电容值。
上述电容Ca可以为金属-绝缘层-金属(metal-insulator-metal，MIM)电容、金属-氧化物-金属(metal-oxide-metal，MOM)电容或金属-氧化物-半导体(metal-oxide-semiconductor,MOS)电容。
如图6所示的是本申请实施例提供的另一种更具体的像素驱动电路310，其中电荷吸收电路311包括二极管连接(diode-connected)的MOS管。具体的，该二极管连接的MOS管包括NMOS管M3和NMOS管M4，其中NMOS管的M3的漏极和栅极与节点A连接，NMOS管M4的漏极与NMOS管M3的源极连接，NMOS管M4的源极接地，NMOS管M4的栅极也与上述节点A连接。
在上述放电过程中，寄生电容Cp中的电荷可以通过导通的NMOS管M3和NMOS管M4流向地。具体的，当第一开关M1导通后，节点A的电压升高，此时NMOS管M3和NMOS管M4导通，节点A和节点B的电压均快速下降。当节点A的电压下降到接近正常工作电压时，NMOS管M3和NMOS管M4截止。在NMOS管M3和NMOS管M4截止后，第二开关M2继续对节点A和节点B放电，使得节点B达到发光二极管D1正常工作的电压。
如图7所示的是本申请实施例提供的又一种更具体的像素驱动电路310，其 中电荷吸收电路311包括肖特基二极管D2。该肖特基二极管D2的阴极与节点A电连接，阳极接地。肖特基二极管D2同样可以加快吸收节点A的电荷，使得像素驱动310可以在更短的时间使节点B降低到正常工作电压，从而加快发光二极管D1的信号建立时间，使得发光二极管D1的开关频率提高，以达到消除残影，提升显示精度，提升用户体验的目的。
如图8所示的是本申请实施例提供的又一种更具体的像素驱动电路310。图8所示的像素驱动电路310还包括连接于第二开关M2和地之间的第五开关M5。第五开关M5可以是NMOS管。在一种实施方式中，该第五开关M5的漏极与第二开关M2的源极连接，其源极接地且与电容Cgg的一端连接，其栅极与第二开关M2的栅极连接并与电容Cgg的另一端连接，以接收偏置电压VBIAS。图8中的电荷吸收电路311可以是本申请实施例提供的任意一种电荷吸收电路。
如图8所示，本申请实施例还提供了一种偏置电路320。偏置电路320包括第六开关M6、第七开关M7和第八开关M8。在一种实施方式中，第六开关M6和第七开关M7为NMOS管，第八开关M8为PMOS管。其中，第六开关M6的源极接地，栅极与第七开关M7的栅极连接并产生偏置电压VBIAS。第六开关M6的漏极与第七开关M7的源极连接。第七开关M7的漏极分别与第七开关M7的栅极和第八开关M8的漏极连接，第八开关M8的源极与电源连接。该偏置电路320可以为本申请实施例提供的任意一种像素驱动电路提供偏置电压。
在一种实施方式中，一个上述偏置电路320与像素驱动电路310可以分别设置在不同的芯片中。上述偏置电路320可以为多个像素驱动电路310提供偏置电压VBIAS。在另一种实施方式中，上述偏置电路320也可以与一个或多个像素驱动电路310集成在同一个芯片中。
如图9所示，本申请实施例还提供一种像素驱动电路900。像素驱动电路900的电路结构与像素驱动电路310结构相似，不同的是，像素驱动电路900中的电荷吸收电路310通过第九开关M9与发光二极管D1的阴极连接。像素驱动电路900中的电荷吸收电路310可以是本申请实施例中任意一种电荷吸收电路。第九开关M9的一端与电荷吸收电路310的一端连接，另一端与发光二极管D1的阴极连接，且第九开关M9的栅极接收的PWM信号与第一开关M1接收的PWM信号相同。在正常工作时，由于PWM信号同时控制第一开关M1和第九开关M9的导通与断开，因此当上述两个开关导通后，电荷吸收电路310开始吸收发光二极管D1的电荷，加快发光二极管D1的阴极电荷的释放，使得寄生电容中的电荷能够更快地释放。当寄生电容中的电荷释放速度加快，则发光二极管的电流信号的建立时间变短，发光二极管的刷新频率变高，从而使得发光二极管从熄灭到点亮的过程经历的时间变短，可以改善人眼观察发光二极管时的残影现象，以及提高发光二极管的显示精度，提升用户体验。
除了本申请实施例提到的上述终端设备之外，本申请实施例提供的像素驱动电路还可以用于其他设备，例如超大室内显示屏幕，头戴式显示器 (helmet-mounted displays，HMD)，抬头显示器(head up display，HUD)，无线光通讯(Li-Fi，Light Fidelity)，AR(augmented reality，增强现实)，VR(virtual reality，虚拟现实)等。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (11)

  1. 一种像素驱动电路，其特征在于，所述像素驱动电路包括：
    级联于发光二极管的阴极和地之间的第一开关和第二开关，所述第一开关的控制端接收控制信号，所述第二开关的控制端接收偏置电压，所述发光二极管的阳极与电源电连接；以及
    电荷吸收电路，电连接于地和第一节点之间，所述第一节点为所述第一开关和所述第二开关的连接点，所述电荷吸收电路用于从所述第一节点吸收电荷。
  2. 如权利要求1所述的像素驱动电路，其特征在于，所述电荷吸收电路包括第一电容，所述第一电容的一端与所述第一节点电连接，另一端与地电连接。
  3. 如权利要求2所述的像素驱动电路，其特征在于，所述第一电容为金属-绝缘层-金属MIM电容、金属-氧化物-金属MOM电容或金属-氧化物-半导体MOS电容。
  4. 如权利要求1所述的像素驱动电路，其特征在于，所述电荷吸收电路包括二极管连接的MOS管。
  5. 如权利要求4所述的像素驱动电路，其特征在于，所述二极管连接的MOS管包括：
    第三NMOS管，所述第三NMOS管的漏极和栅极与所述第一节点电连接；
    第四NMOS管，所述第四NMOS管的漏极和所述第三NMOS管的源极电连接，所述第四NMOS管的源极接地，所述第四NMOS管的栅极与所述第一节点电连接。
  6. 如权利要求1所述的像素驱动电路，其特征在于，所述电荷吸收电路包括肖特基二极管，所述肖特基二极管的阴极与所述第一节点电连接，所述肖特基二极管的阳极接地。
  7. 如权利要求1至6任一项所述的像素驱动电路，其特征在于，所述第一开关为第一NMOS管，所述第二开关为第二NMOS管，其中所述第一NMOS管的源极与地电连接，所述第一NMOS管的漏极与所述第二NMOS管的源极电连接于所述第一节点，所述第二NMOS管的漏极与所述发光二极管的阴极电连接。
  8. 如权利要求1至7任一项所述的像素驱动电路，其特征在于，所述像素驱动电路还包括第二电容，所述第二电容的一端与所述第二开关的控制端电连接，另一端接地。
  9. 如权利要求1至8任一项所述的像素驱动电路，其特征在于，所述控制信号为脉冲宽度调制PWM信号。
  10. 一种显示电路，其特征在于，所述显示电路包括：
    多个如权利要求1至9任一项所述的像素驱动电路；
    多个所述发光二极管，分别与所述多个像素驱动电路电连接，所述多个像素驱动电路用于分别驱动所述多个发光二极管。
  11. 一种终端设备，包括后盖、边框，和如权利要求10所述的显示电路，所述后盖和所述显示电路相对设置并通过所述边框连接。
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