WO2021259758A1

WO2021259758A1 - Power output stage for a device for supplying energy to an electrical load

Info

Publication number: WO2021259758A1
Application number: PCT/EP2021/066429
Authority: WO
Inventors: Felix Stewing; Dennis Bura; Michael JIPTNER
Original assignee: Robert Bosch Gmbh
Priority date: 2020-06-25
Filing date: 2021-06-17
Publication date: 2021-12-30
Also published as: CN115943546A; EP4173123A1; JP2023531061A; DE102020207886A1

Abstract

The invention relates to a power output stage (10) for a device (1) for supplying energy to an electrical load (3), having a power switching device (12) which comprises at least one half-bridge (12.1) and is designed on the basis of gallium-nitride-on-silicon technology, and a control circuit (15) for the power switching device (12), wherein semiconductor power switches of the at least one half-bridge (12. 1) are formed as gallium-nitride semiconductors on a front face of a carrier substrate; the invention also relates to a device (1) for supplying energy to an electrical load (3), which device comprises such a power output stage (10), and to a method for determining a voltage-free switching time point for such a power output stage (10). The control circuit (15) comprises an auxiliary resonant commutated pole (ARCP) module (16B) each for the at least one half-bridge (12.1), which ARCP module has two auxiliary switches and a choke coil and is designed to switch the semiconductor power switches of the corresponding half-bridge (12.1) at a voltage-free switching time point, the control circuit (15) being designed to determine the voltage-free switching time point by means of integrated power measurement and/or by means of an adaptive delay chain.

Description

description

title

Power output stage for a device for supplying energy to an electrical

load

The invention is based on a power output stage for a device for supplying energy to an electrical load according to the preamble of the independent patent claim 1. The present invention also relates to a corresponding device for supplying energy to an electrical load with such a power output stage and a method for determining a voltage-free Switching time for a power output stage.

Three-phase brushless DC motors are usually controlled by a power output stage, which is preferably designed as a B6 inverter based on silicon power semiconductors, preferably with a field-oriented control. In order to control the electrical load, in this case the DC motor, a bridge driver is used in addition to the actual semiconductor power switches, which switches the semiconductor power switches on and off. Typically this happens with small motors with a voltage of less than 60V and a power of less than 3kW with a frequency of approx. 20 kHz. Due to switching losses, the frequency should be as low as possible but above the human hearing threshold.

The gallium nitride-on-silicon technology known from the prior art enables very much higher switching frequencies and lower resistances per area than pure silicon semiconductor switches for the power semiconductor switches. The corresponding lateral technology also enables the integration of further active and passive elements on the same silicon substrate on which the power semiconductors are located. From DE 10 2016 113 121 A1 an energy supply device is known which has an energy module and a capacitor. The energy module has inverting circuits and is designed to supply electrical energy to an electrical machine. The capacitor is arranged adjacent to the energy module and is set up to limit a voltage change due to the ripple current at the input of the inverting circuits. The inverting circuits and the capacitor are overmolded with a monolithic insulating epoxy and encapsulated by this, so that voltage isolation is provided between the power module and the capacitor.

A generic power output stage for a device for supplying energy to an electrical load is known from DE 10 2015 208 150 A1. The power output stage comprises a power switching device, which comprises at least one half-bridge and is based on gallium nitride-on-silicon technology, and a control circuit for the power switching device. Semiconductor power switches of the at least one half-bridge are designed as gallium-nitrite semiconductors on a front side of a silicon substrate.

Disclosure of the invention

The power output stage for a device for supplying energy to an electrical load with the features of independent claim 1 and the device for supplying energy to an electrical load with the features of independent claim 15 and the method for determining a voltage-free switching time for a power output stage with the features of the independent claims 18 and 19 each have the advantage that an ARCP module (ARCP: Auxiliary Resonant Commutated Pole) determines dynamic working points, which enable smooth switching, even if an average voltage of a divided intermediate circuit is determined by many parameters (load point, intermediate circuit voltage, dynamics, Temperature etc.) varies and thus a "charging time" of an inductance or choke coil changes. This ensures that the correct dead times for switching the semiconductor power switches on and off are taken. By Ausfüh approximate forms of the present invention, a hard turn-on with a high voltage jump avoided and a soft switch-on implemented at a virtually voltage-free switching point. A great advantage of the ARCP module is that, by eliminating the switching losses in the at least one half-bridge, its switching frequency can be increased significantly. As a result, the passive components, such as the capacitors of the intermediate circuit capacitance or any sine or edge filters that may be present, can be made significantly smaller and cheaper. In addition, the semiconductor area can be reduced due to the lower power loss.

Embodiments of the present invention provide a power output stage for a device for supplying energy to an electrical load, with a power switching device which comprises at least one half-bridge and is based on gallium nitride-on-silicon technology, and a control circuit for the power switching device. Semiconductor power switches of the at least one half-bridge are designed as gallium-nitrite semiconductors on a front side of a carrier substrate. In this case, the control circuit for the at least one half-bridge each comprises an ARCP module, which has two auxiliary switches and a choke coil and is designed to switch the semiconductor power switches of the corresponding half-bridge at a voltage-free switching time, the control circuit being carried out to switch the voltage-free switching time by a to determine adaptive delay chain and / or by means of an integrated current measurement.

In addition, a device for supplying energy to an electrical load, with an energy supply, a control unit and such a power output stage is proposed.

Furthermore, a method for determining a voltage-free switching point in time for a power output stage is proposed with the following steps: receiving a switching command and switching on the first or second auxiliary switch as a function of the received switching command. Determine and activate a delay period. Switching off the corresponding of the two semiconductor power switches of the at least one half bridge and activating a dead time measurement with a predetermined stop value, which corresponds to a maximum dead time span when the first delay time span has expired. Measuring a node voltage across the first semiconductor power switch and switching on the other of the two semiconductor power switches of the at least one half-bridge and stopping the dead time measurement when the measured node voltage corresponds to a predetermined voltage threshold value or the dead time measurement has reached the stop value. Here, the switched-on auxiliary switch remains switched on after the other of the two semiconductor power switches of the at least one half-bridge has been switched on for the duration of the delay period and is switched off after the delay period has expired.

Preferably, the first auxiliary switch can be switched on to switch off the first semiconductor power switch and to switch on the second semiconductor power switch, and the second auxiliary switch can be switched on to switch off the second semiconductor power switch and to switch on the first semiconductor power switch.

The measures and developments listed in the dependent claims are advantageous improvements of the power output stage specified in the independent claim 1 for a device for supplying energy to an electrical load and the device for supplying energy to an electrical load as well as in the independent claim 18 for determining a voltage-free switching time for a power output stage is possible.

It is particularly advantageous that the power switching device and the control circuit based on gallium nitride-on-silicon technology can be designed as a monolithic circuit module, with at least the individual active components of the monolithic circuit module being able to be arranged on a common carrier substrate. In this case, at least the two auxiliary switches are integrated into the monolithic circuit module and arranged with the semiconductor power switches of the respective half-bridge on the common carrier substrate. This has the advantage that further functionalities for controlling the device can be integrated in the monolithic circuit module and further miniaturization is made possible. For example, to control any electrical load you can use the gallium nitride-on-silicon technology several half bridges of the power switching device and the corresponding drivers for these half bridges are applied to a common carrier substrate, preferably a silicon substrate. For example, three half bridges of a B6 bridge with a corresponding control circuit for supplying energy to a three-phase motor can be arranged on the common carrier substrate. Of course, any other number of half bridges required to supply the electrical load can also be arranged on the common carrier substrate. In addition, protection functions, such as an overcurrent protection function, an excess temperature protection function, etc., can also be applied to the common carrier substrate.

In addition, by shifting the control circuit, which can also perform current regulation for the power switching device, in the monolithic circuit module, control lines that normally have to be routed to a bridge driver circuit are not required, and no modulation from a higher-level control device is required. All fast signals and their switching edges therefore do not "leave" the monolithic circuit module. This can be expected to have a positive effect on the EMC behavior. Due to the small number of contacts required, a particularly compact implementation is possible, since contact pads can hardly fall below a minimum size. In addition, the proposed construction enables EMC interference to be reduced, which can spread in the system through jumping potentials at the individual half bridges via corresponding coupling capacities with a heat sink. For this purpose, for example, a cooling surface of the power switching device can either be connected directly to ground, if possible, or in the monolithic circuit module it can be capacitively connected to ground directly via coupling capacitors in a defined manner. Additional interference suppression capacitors or Y capacitors as well as contacting elements (eg SMD springs) are thus superfluous. Another advantage is that a conductive thermal paste can be used; these are available with much higher thermal conductivities than insulating pastes. In an advantageous embodiment of the power output stage, capacitors of an intermediate circuit capacitance can be designed as silicon capacitors and arranged on the front and / or rear of the carrier substrate. In a particularly advantageous embodiment, these silicon capacitors are formed using deep trench technology on the back of the common carrier substrate in order to buffer the supply voltage. Due to the high possible switching frequencies, the silicon capacitors in deep trench technology can also be used in low-voltage inverters with a voltage of less than 60V for smaller outputs of a few kilowatts to represent an intermediate circuit. By arranging the intermediate circuit capacitance, which is designed as silicon capacitors, on the common carrier substrate, an extremely low-inductance connection to the power switching device is possible. For example, the silicon capacitors on the rear side of the common carrier substrate can be electrically contacted with the semiconductor power switches on the front side by means of plated-through holes through the carrier substrate. In the case of a lateral arrangement of the intermediate circuit capacitance in the form of silicon capacitors on the front side of the common carrier substrate, simple electrical contacting is also possible. This enables a structure without plated-through holes in the carrier substrate.

In a further advantageous embodiment of the power output stage, the monolithic circuit module can be embedded in a multilayer printed circuit board or arranged on the multilayer printed circuit board. With this configuration of the power output stage, capacitors of the intermediate circuit capacitance can be arranged as silicon capacitors on separate carrier substrates and, like the monolithic circuit module, embedded in the multilayer circuit board or arranged on the multilayer circuit board. Alternatively, the capacitors of the intermediate circuit capacitance can be designed as multilayer ceramic capacitors in chip design (MLCC: Multi Layer Ceramic Capacitor) and embedded in the multilayer printed circuit board or arranged on the multilayer printed circuit board.

In a further advantageous embodiment of the power output stage, the two auxiliary switches designed as gallium-nitrite semiconductors can become one bidirectional blocking auxiliary switches are summarized and formed on the front of the Trä gersubstrats. As the auxiliary switch is designed to block bidirectionally, the required semiconductor area can be halved compared to a classic ARCP module, in which two anti-parallel switches are used as auxiliary switches.

In a further advantageous embodiment of the power output stage, the choke coil can be designed without a core as a conductor track in the carrier substrate. This is made possible by the high switching frequencies. Since no core materials are required, a complex structure of the choke coil can be avoided. Alternatively, the choke coil can be designed without a core as a conductor path of the multi-layer circuit board of the power output stage. This means that the choke coil, like the capacitors of the intermediate circuit capacitance, can be embedded in the multilayer circuit board or arranged on the multilayer circuit board in which the monolithic circuit module is embedded or on which the monolithic circuit module is arranged.

In a further advantageous embodiment of the power output stage, the control circuit can include a current control that is designed to receive at least one measurement current, which presents a corresponding current output current re, and at least one reference current as an analog signal, and to compare them with one another and depending on the comparison To generate and output at least a corresponding switching signal. In this case, the at least one measurement current can preferably be recorded within the monolithic circuit module. In addition, the control circuit can include a driver stage which is designed to receive the at least one switching signal from the current regulator, to process it and to output it to the power switching device. Due to the high switching frequencies, other control methods such as direct switching methods are possible, please include. The current control for each of the half bridges of the power switching device can therefore include a comparator which is designed to switch off the corresponding half bridge when the measurement current exceeds the corresponding reference current, and switch on the corresponding half bridge when the measurement current falls below the corresponding reference current. This makes it possible to control the semiconductor power switch directly via a setpoint specification to the corresponding comparators. With a three-phase motor as the electrical load, only three analog reference signals for the phase currents are therefore sent to the monolithic circuit module. The current control takes place with the help of the comparators directly in the monolithic circuit module. The reference value is compared with the measured value of the phase current. If the reference value is exceeded, it is switched off, if it falls below the reference value, it is switched on. The required reference current is thus set on average. To limit the switching frequency, the individual comparators can be sampled and / or executed with hysteresis. The digital output signal of the comparators can then be used directly as a switching status command for the individual semiconductor power switches. The respective reference signal is an analog signal which directly specifies the current in the electrical load or in the individual stator windings of the three-phase motor. It can be specified by a central control unit and contains a maximum of the machine frequencies (including explicitly applied harmonics). The degrees of freedom for controlling the electrical load are still in the control device, but the fast current dynamics are shifted to the monolithic circuit module, which can significantly reduce the demands on the dynamics and computing power of the control device and lead to a cost advantage. At the same time, the fast hardware comparators can be used to obtain a very dynamic current regulator with a high bandwidth, which can also make inexpensive use of the increased actuator bandwidth that is created by increasing the switching frequency. If the current control were to continue to be carried out in the control unit, a more powerful control unit would automatically be required to increase the bandwidth of the current control, which would incur additional costs.

In a further advantageous embodiment of the power output stage, the monolithic circuit module can include an electrical interface which is designed to receive signals from external components and / or assemblies. The electrical interface can receive a supply voltage potential, a ground potential and the at least one reference current . In a further advantageous embodiment of the power output stage, the power switching device can be designed, for example, as a B6 inverter with three half bridges. A cooling surface of the B6 inverter can be connected to ground directly or via at least one coupling capacitor, which has a defined capacitance.

In an advantageous embodiment of the device for supplying energy to an electrical load, the electrical interface can be designed to receive a supply voltage potential and a ground potential of the energy supply and the at least one reference current from the control device.

In a further advantageous embodiment of the device for supplying energy to an electrical load, the electrical load can be designed as a three-phase brushless DC motor, the half-bridges of the B6 inverter each being connectable to a phase of the three-phase brushless DC motor.

In an advantageous embodiment of the method, the delay time span can be determined by an adaptive delay chain, which can be specified by a number of delay steps with identical time spans. Here, the number of delay steps of the delay time span can be increased by one when the dead time measurement has reached the predetermined stop value or the maximum dead time span. The number of delay steps of the delay time span can be reduced by one if the dead time measurement has not reached a predetermined minimum dead time span. The number of delay steps of the delay time span can otherwise remain the same.

Additionally or alternatively, the delay time span can be determined by an integrated current measurement. After switching on the first or second auxiliary switch, a time measurement to determine the delay time span and a measurement of a current through a corresponding one of the two semiconductor power switches of the at least one half-bridge can be activated, whereby the measured current can be compared with a predetermined threshold value. The time measurement can be stopped and the measurement result can be specified as the elapsed delay period when the measured current exceeds the specified threshold value.

Embodiments of the invention are shown in the drawing and who explained in more detail in the following description. In the drawing, the same reference symbols denote components or elements that perform the same or analogous functions.

Brief description of the drawings

1 shows a schematic block diagram of an exemplary embodiment of a device according to the invention for supplying energy to an electrical load with an exemplary embodiment of a power output stage according to the invention.

FIG. 2 shows a schematic circuit diagram of a control circuit for a half bridge of the power output stage according to the invention from FIG. 1.

FIG. 3 shows a schematic circuit diagram of an ARCP module for a half-bridge of the power output stage according to the invention from FIG. 1.

FIG. 4 shows a schematic and perspective illustration of the power output stage from FIG. 1 designed as a monolithic circuit module.

FIG. 5 shows a schematic flow diagram of a first exemplary embodiment of a method according to the invention for determining a voltage-free switching point in time for the power output stage according to the invention from FIG. 1.

6 shows a schematic flow diagram of a second exemplary embodiment of a method according to the invention for determining a voltage-free switching point in time for the power output stage according to the invention from FIG. 1.

Embodiments of the invention

As can be seen from FIG. 1, the illustrated embodiment comprises a device 1 according to the invention for supplying energy to an electrical load 3, each with a power supply 5, a control device 7 and a power output stage 10 according to the invention.

As can also be seen from FIGS. 1 to 3, the illustrated embodiment of the power output stage 10 according to the invention for the device 1 for supplying energy to an electrical load 3 comprises a power switching device 12 which comprises at least one half bridge 12.1 and is based on the gallium nitride -Silicon technology is executed, and a control circuit 15 for the power switching device 12, wherein semiconductor power switches TI, T2 of the at least one half bridge 12.1 are formed as a gallium-nitrite semiconductor on a front side of a carrier substrate SiS. In this case, the control circuit 15 comprises an ARCP module 16B for each of the at least one half-bridge 12.1, which has two auxiliary switches T3, T4 and a choke coil 16.2 and is designed to switch the semiconductor power switches TI, T2 of the corresponding half-bridge 12.1 at a voltage-free switching time, wherein the control circuit 15 is designed to determine the voltage-free switching time by an integrated current measurement and / or by an adaptive delay chain.

As can also be seen in particular from FIGS. 1 and 4, the power switching device 12 and the control circuit 15 are designed as a monolithic circuit module based on gallium nitride-on-silicon technology. Here, at least the individual active components of the monolithic circuit module are arranged on a common SiS carrier substrate.

As can also be seen from Fig. 1, the electrical load 3 is designed in the illustrated embodiment of the device 1 as a three-phase brushless DC motor 3A. The power switching device 12 is designed as a B6 inverter 12A with three half bridges 12.1, the half bridges 12.1 of the B6 inverter 12A each being connected to a phase U, V, W of the three-phase brushless DC motor 3A. In addition, a cooling surface of the B6 inverter 12A is connected to ground GND directly or via at least one coupling capacitor, which has a defined capacitance. In alternative exemplary embodiments that are not illustrated, the power switching device 12 can also have fewer or more than three half bridges 12.1. In addition, the device 1 to supply energy to an electrical load 3, also supply an electrical load 3 other than a three-phase direct current motor 3A with energy.

As can also be seen from Fig. 1 and 5, capacitors CI, C2 of an intermediate circuit capacitance 14 for buffering a supply voltage UBat in the illustrated embodiments are each arranged on the carrier substrate SiS. Thus, the intermediate circuit capacitance 14 is also integrated into the monolithic circuit module in the illustrated Ausführungsbei.

In the case of exemplary embodiments of the power output stage 10 not shown, the monolithic circuit module is embedded in a multilayer printed circuit board or arranged on the multilayer printed circuit board. In these exemplary embodiments, the capacitors CI, C2 of the intermediate circuit capacitance 14 can be arranged on separate carrier substrates and embedded in the multilayer printed circuit board or arranged on the multilayer printed circuit board. Alternatively, the capacitors CI, C2 of the intermediate circuit capacitance 14 can play in these Ausführungsbei directly embedded in the multilayer circuit board or arranged on the multilayer circuit board.

As can also be seen from FIGS. 1 and 2, the control circuit 15 comprises a current control 18 which is designed to include at least one measurement current Im (U, V, W, which represents a corresponding current output current lo (U, V, W), and to receive at least one reference current Ir (U, V, W) as an analog signal and to compare it with one another and to generate and output at least one corresponding switching signal as a function of the comparison Power switching device 12 has a comparator 18.1, which is designed to switch off the corresponding half-bridge 12.1 when the measurement current Im (U, V, W exceeds the corresponding reference current Ir (U, V, W), and to switch on the corresponding half-bridge 12.1 when the measurement current Im (U, V, W) falls below the corresponding reference current Ir (U, V, W) In the exemplary embodiment shown, the current regulator 18 is t the comparator 18.1 clocked by a clock signal TS. As can also be seen from Fig. 1, the at least one measuring current lm (U, V, W) detected in the illustrated embodiment within the monolithic circuit module.

As can also be seen from FIGS. 1 and 2, the control circuit 15 in the illustrated embodiment includes a driver stage 16 which includes a gate control 16A and is designed to supply the at least one switching signal from the current regulator 18 or the corresponding comparator 18.1 receive, process and give trainees to the two semiconductor power switches TI, T2 of the corresponding half-bridge 12.1 of the power switching device 12.

As can also be seen from FIG. 1, the monolithic circuit module comprises an electrical interface 13 which is designed to receive signals from external components and / or assemblies. In the exemplary embodiments shown, the electrical interface 13 receives the supply voltage potential UBat and a ground potential GND from the energy supply 5 and the at least one reference current Ir (U, V, W) from the control device 7. To generate the at least one reference current Ir (U, V, W) the control unit 7 evaluates output signals from a sensor system DWM which, in the exemplary embodiment shown, detects the angle of rotation of the three-phase DC motor 3A and generates the corresponding output signals.

As can also be seen from Fig. 1 and 3, the intermediate circuit capacitance 14 in the illustrated embodiment of the power output stage 10 is divided and comprises two capacitors CI, C2, which each as silicon capacitors in deep trench technology on the back of the common Trä gersubstrates SiS are designed to buffer the supply voltage UBat. Here, the silicon capacitors CI, C2 are electrically contacted by means of vias, not shown, through the carrier substrate SiS with the power switching device 12B.

In alternative exemplary embodiments, not shown, of the power output stage 10, the monolithic circuit module is embedded in a multilayer printed circuit board or arranged on the multilayer printed circuit board. In this embodiment, the capacitors CI, C2 of the intermediate circuit capacitance 14 can be used as Silicon capacitors are formed on separate carrier substrates and embedded in the multilayer printed circuit board or are arranged on the multilayer printed circuit board. In these exemplary embodiments, the capacitors CI, C2 of the intermediate circuit capacitance 14 can alternatively be formed as multilayer ceramic capacitors in chip design (MLCC: Multi Layer Ceramic Capacitor) and embedded directly in the multilayer circuit board or arranged on the multilayer circuit board.

As can also be seen from FIGS. 1 and 3, the ARCP module 16 is designed as part of the driver stage 16 and is integrated into the monolithic circuit module. For this purpose, the two auxiliary switches T3, T4 are combined as gallium nitrite semiconductors to form a bidirectional blocking auxiliary switch 16.1 and formed with the semiconductor power switches TI, T2 of the individual half bridges 12.1 B on the front of the carrier substrate SiS. The choke coil 16.2 is designed without a core as a conductor track in the SiS carrier substrate.

In an alternative embodiment, not shown, of the power output stage 10, in which the monolithic circuit module is embedded in a multilayer printed circuit board or is arranged on the multilayer printed circuit board, the inductor 16.2 is coreless and forms a conductor path of the multilayer printed circuit board.

The first exemplary embodiment of the method 100 shown in FIG. 5 for determining a voltage-free switching time for the power output stage 10 described above is based on an adaptive delay chain. The method 100 is started in a step S100, for example by starting the vehicle. Then in step S110 there is a wait until a switching command for one of the two auxiliary switches T3, T4 is received. In step S120 it is then checked whether a first switching command, which for example represents a transition from a first to a second logic state, or whether a second switching command has been received, which for example represents a transition from the second to the first logic state. If the first switching command was recognized in step S120, the method is continued with step S130. If the second switching command was recognized in step S120, the method is continued with step S230. In step S130, the first auxiliary switch T3 is switched on or switched on as a function of the received first switching command. As a result, a coil current IL increases through the choke coil 16.2. In step S140, a delay period TV is activated, which is predetermined by a number X of delay steps with identical periods of time, and the coil current IL through the choke coil 16.2 continues to rise. After the delay period TV has elapsed, the current IL through the choke coil 16.2 is greater than the corresponding output current lo (U, V, W) and a corresponding current IT1 through the corresponding, here the first semiconductor power switch TI, of the two semiconductor power switches TI, T2 of the at least one half bridge 12.1 is greater than zero and a node voltage US across the first semiconductor switch TI corresponds to a ground potential GND. Therefore, the first semiconductor power switch TI is switched off or switched off in step S150 and a dead time measurement with a predetermined stop value is activated, wel cher corresponds to a maximum value for a dead time period TS. This increases the node voltage US across the first semiconductor power switch TI, which is measured in step S160 and compared with a first voltage threshold value. This first voltage threshold value corresponds, for example, approximately to the supply voltage potential UBat or is selected to be somewhat lower than the supply voltage potential UBat. In step S170, the other, here the second semiconductor power switch T2, of the two semiconductor power switches TI, T2 of the at least one half bridge 12.1 is switched on or switched on and the dead time measurement is stopped when the measured node voltage US corresponds to the specified first voltage threshold value or the dead time measurement has reached the specified stop value or the maximum dead time TS. At the switch-on time, a voltage drop across the second semiconductor power switch T2 is ideally zero. As a result, the second semiconductor power switch T2 is de-energized and can be turned on or switched on without loss. In addition, in step S170 the number X of the delay steps of the delay time span VT is increased by one when the dead time measurement has reached the predetermined stop value or the maximum dead time span TS. The number X of the delay steps of the first delay time span VT1 is reduced by one if the elapsed time span is less than a minimal nimaler value for the dead time period TS, the number X of delay steps of the delay period TV is otherwise kept constant. This means that the delay period TV1 is not changed if the stopped period of the dead time measurement lies between the minimum value and the maximum value of the dead period TS. After the second semiconductor power switch T2 has been switched on, the delay period TV is activated in step S180. After the delay time span TV has elapsed, the switched-on first auxiliary switch T3 is switched off or switched off in step S190. This means that after the second semiconductor power switch T2 has been switched on, the first auxiliary switch T3 remains switched on for the duration of the delay time span TV so that the coil current IL can be reduced through the choke coil 16.2. The method 100 is then continued with step S110 and the receipt of the next switching command is waited for.

In step S230, the second auxiliary switch T4 is switched on or switched on as a function of the received second switching command. As a result, the coil current IL drops through the choke coil 16.2. In step S240, the delay period TV is activated and the coil current IL through the choke coil 16.2 continues to decrease. After the delay period TV has elapsed, the current IL through the choke coil 16.2 is greater than the corresponding output current lo (U, V, W) and a corresponding current IT2 through the corresponding, here the second semiconductor power switch T2, the two semiconductor power switches TI, T2 is at least a half bridge 12.1 is less than zero. The second semiconductor power switch T2 is therefore switched to blocking or off in step S250 and the dead time measurement is activated with the predetermined stop value, which corresponds to the maximum value for the dead time period TS. As a result, the node voltage US drops across the first semiconductor power switch TI, which is measured in step S260 and compared with a second voltage threshold value. This second voltage threshold value corresponds approximately to the ground potential GND or is selected to be somewhat higher than the ground potential GND. In step S270, the other, here the first semiconductor power switch TI, of the two semiconductor power switches TI, T2 of the at least one half bridge 12.1 is switched on or switched on and the dead time measurement is stopped when the measured node voltage US corresponds to the specified second voltage threshold value or the dead time measurement corresponds to the specified value Has reached the stop value. At the switch-on time, a voltage drop across the first semiconductor power switch TI is ideally equal to zero. As a result, the first semiconductor power switch TI is de-energized and can be turned on or switched on without loss. In addition, in step S270, the number X of the delay steps of the delay period VT is increased by one when the dead time measurement has reached the predetermined stop value. The number X of delay steps of the first delay time span VT1 is reduced by one if the elapsed time span is less than the minimum value for the dead time span TS, the number X of delay steps of the delay time span TV being otherwise kept constant. This means that the delay time span TV is not changed if the stopped time duration of the time measurement is between the minimum value and the maximum value of the dead time span TS. After the first semiconductor power switch TI has been switched on, the delay period TV is activated in step S280. After the delay period TV has elapsed, the switched-on second auxiliary switch T4 is switched off in step S290. This means that the second auxiliary switch T4 remains switched on for the duration of the delay period TV after the first semiconductor power switch TI has been switched on. Then the process 100 is continued with step S110 and the receipt of the next switching command is awaited.

The illustrated in Fig. 6 second embodiment of the method 200 for determining a voltage-free switching time for the power output stage 10 described above is based on an integrated current measurement. Here, the method 200 is started in a step S300, for example by starting the vehicle. Then in step S310 there is a wait until a switching command for one of the two auxiliary switches is received. In step S320 it is then checked whether a first switching command, which for example represents a transition from a first to a second logic state, or whether a second switching command has been received, which for example represents a transition from the second to the first logic state . If the first switching command was recognized in step S320, the method is continued with step S330. If the second switching command was recognized in step S320, the method is continued with step S430. In step S330 the first auxiliary switch T3 is switched on or switched on as a function of the received first switching command and a time measurement for determining the delay time span TV is activated or started. As a result, a coil current IL rises through the choke coil 16.2 and a current IT1 through the corresponding, here the first semiconductor power switch TI of the two semiconductor power switches TI, T2 of the at least one half bridge 12.1 is measured in step S340. In step S350, the first semiconductor power switch TI is switched off or switched off and the dead time measurement is activated with a predetermined stop value, which corresponds to the maximum value for the dead time period TS, and the time measurement is stopped and the measurement result is specified as the elapsed delay time period VT when the current IT1 exceeds a specified current threshold through the first semiconductor power switch TI. This means that the current IL through the choke coil 16.2 is greater than the corresponding output current lo (U, V, W) and the node voltage US across the first semiconductor switch TI corresponds approximately to the ground potential GND. In step S360, the node voltage US across the first semiconductor power switch TI is measured and compared with the first voltage threshold value which, for example, corresponds approximately to the supply voltage potential UBat or is selected to be somewhat lower than the supply voltage potential UBat. In step S370 the other, here the second semiconductor power switch T2, the two semiconductor power switches TI, T2 of the at least one half bridge 12.1 is switched on or switched on and the dead time measurement is stopped when the measured node voltage US corresponds to the specified first voltage threshold value or the dead time measurement has reached the specified stop value. At the time of switching on, a voltage drop across the second semiconductor power switch T2 is ideally equal to zero. As a result, the second semiconductor power switch T2 is de-energized and can be turned on or switched on without loss. After the second semiconductor power switch T2 has been switched on, the delay time span TV determined by the time measurement is activated in step S380. After the delay period TV has elapsed, the switched-on first auxiliary switch T3 is switched off or switched to a blocking state in step S390. This means that the first auxiliary switch T3 remains switched on for the duration of the delay period TV after switching on the second semiconductor power switch T2, so that the coil current IL through the choke coil 16.2 can break down. The method 200 is then continued with step S310 and the receipt of the next switching command is waited for.

In step S430, the second auxiliary switch T4 is switched on or switched on as a function of the received second switching command and the time measurement for determining the delay period TV is activated or started. As a result, a coil current IL through the choke coil 16.2 drops and a current through the corresponding, here the second semiconductor power switch T2 of the two semiconductor power switches TI, T2 of the at least one half bridge 12.1 is measured in step S440. In step S450, the second semiconductor power switch T2 is switched off or switched off and the dead time measurement is activated with the specified stop value, which corresponds to the maximum value for the dead time TS, and the time measurement is stopped and the measurement result is specified as the elapsed delay time VT when the current by the second semiconductor power switch T2 exceeds the predetermined current threshold value. This means that the current IL through the Dros selspule 16.2 is greater than the corresponding output current lo (U, V, W). In step S460, the node voltage US is measured across the first semiconductor power switch TI and compared with the second voltage threshold value, which, for example, corresponds approximately to the ground potential GND or is selected to be somewhat greater than the ground potential GND. In step S470, the other, here the first semiconductor power switch TI, of the two semiconductor power switches TI, T2 of the at least one half bridge 12.1 is switched on or switched on when the measured node voltage US corresponds to the specified second voltage threshold value or the dead time measurement has reached the specified stop value . At the switch-on time, a voltage drop across the first semiconductor power switch TI is ideally equal to zero. As a result, the first semiconductor power switch TI is de-energized and can be turned on or switched on without loss. After the first semiconductor power switch TI has been switched on, the delay time span TV determined by the time measurement is activated in step S480. After the delay period TV has elapsed, the switched-on second auxiliary switch T4 is switched off or switched off in step S490. This means that after the first semiconductor power switch TI has been switched on, the second auxiliary switch T4 remains switched on for the duration of the delay period TV. Then the procedure 200 continued with step S310 and waited for the receipt of the next switching command.

The delay time span VT can be implemented, for example, with a switched shift register. The dead time TS can be implemented, for example, with a monostable multivibrator.

The two described exemplary embodiments of the method can in principle be implemented in NMOS logic. The first exemplary embodiment of the method 100 is less sensitive to parameter spreads due to its adaptive nature, but requires a total of more logic elements than the second exemplary embodiment of the method 200. The second exemplary embodiment of the method 200 can, however, only be used if the current measurement is sufficiently accurate. The two methods 100, 200 can also be combined if, for example, the current measurement alone is not sufficiently accurate, but can still be used to support or verify the setting of the adaptive delay chain.

Claims

Expectations

1. Power output stage (10) for a device (1) for supplying energy to an electrical load (3), with a power switching device (12) which comprises at least one half-bridge (12.1) and is based on gallium nitride-on-silicon technology, and a control circuit (15) for the power switching device (12), wherein semi-conductor power switches (TI, T2) of the at least one half bridge (12.1) are formed as a gallium nitrite semiconductor on a front side of a carrier substrate (SiS), characterized in that the control circuit (15) for the at least one half bridge (12.1) each comprises an ARCP module (16B), which has two auxiliary switches (T3, T4) and a choke coil (16.2) and is designed, the semiconductor power switch (TI, T2 ) to switch the corresponding half-bridge (12.1) at egg nem voltage-free switching time, wherein the control circuit (15) is designed to integrate the voltage-free switching time te current measurement and / or to determine by an adaptive delay chain.

2. Power output stage (10) according to claim 1, characterized in that the power switching device (12) and the control circuit (15) based on the gallium nitride-on-silicon technology are designed as a monolithic circuit module, with at least the individual active components of the monolithic circuit module are arranged on a common carrier substrate (SiS).

3. Power output stage (10) according to claim 1 or 2, characterized in that capacitors (CI, C2) of an intermediate circuit capacitance (14) are designed as silicon capacitors and are arranged on the front and / or rear of the carrier substrate (SiS).

4. power output stage (10) according to claim 2 or 3, characterized in that the monolithic circuit module is embedded in a multilayer circuit board or is arranged on the multilayer circuit board.

5. Power output stage (10) according to claim 4, characterized in that the capacitors (CI, C2) of the intermediate circuit capacitance (14) are designed as silicon capacitors on separate carrier substrates or as multilayer ceramic capacitors in chip design and in the multilayer Printed circuit board embedded or arranged on the multilayer circuit board.

6. Power output stage (10) according to one of claims 1 to 5, characterized in that the two auxiliary switches (T3, T4) designed as gallium-nitrite semiconductors are combined to form a bidirectionally blocking auxiliary switch (16.1) and on the front side of the carrier substrate ( SiS) are formed.

7. Power output stage (10) according to one of claims 1 to 6, characterized in that the choke coil (16.2) is designed without a core as a conductor track in the carrier substrate (SiS).

8. power output stage (10) according to any one of claims 4 to 6, characterized in that the choke coil (16.2) is designed without a core as a conductor track of the multilayer printed circuit board.

9. Power output stage (10) according to one of claims 1 to 8, characterized in that the control circuit (15) comprises a current control (18) which is designed to have at least one measurement current (lm (U, V, W)), which a corresponding current output current (lo (U, V, W)) represents, and at least one reference current (lr (U, V, W)) to receive as an analog signal and to compare with each other and depending on the comparison at least one corresponding Generate and output switching signal.

10. Power output stage (10) according to claim 9, characterized in that the at least one measuring current (Im (U, V, W)) can be detected within the monolithic circuit module.

11. Power output stage (10) according to claim 9 or 10, characterized in that the current control (18) for each of the half bridges (12.1) of the power switching device (12) comprises a comparator (18.1), which is designed, the corresponding half bridge ( 12.1) switch off when the measuring current (lm (U, V, W)) exceeds the corresponding reference current (lr (U, V, W)), and switch on the corresponding half-bridge (12.1) when the measuring current (lm ( U, V, W)) falls below the corresponding reference current (lr (U, V, W)).

12. Power output stage (10) according to one of claims 9 to 11, characterized in that the control circuit (15) comprises a driver stage (16) which is designed to receive the at least one switching signal from the current regulator (18), to process and to output to the power switching device (12).

13. Power output stage (10) according to one of claims 1 to 12, characterized in that the monolithic circuit module comprises an electrical interface (13) which is designed to receive signals from external components and / or assemblies.

14. Power output stage (10) according to one of claims 1 to 13, characterized in that the power switching device (12) is designed as a B6 inverter (12A) with three half bridges (12.1).

15. Device (1) for supplying energy to an electrical load (3), with a power supply (5), a control device (7) and a power output stage (10), characterized in that the power output stage (10) according to one of claims 1 to 14 is executed.

16. The device (1) according to claim 15, characterized in that the electrical interface (13) is designed, a supply voltage potential (UBat) and a ground potential (GND) of the energy supply (5) and the at least one reference current (Ir (U, V, W)) from the control unit (7) to receive.

17. Device (1) according to claim 15 or 16, characterized in that the electrical load (3) is designed as a three-phase brushless direct current motor (3A), the half bridges (12.1) of the B6 inverter (12A) each having a phase (U, V, W) of the three-phase brushless DC motor (3A) can be connected.

18. The method (100, 200) for determining a voltage-free switching point for a power output stage (10), which is carried out according to one of claims 1 to 14, with the steps of: receiving a switching command and switching on the first or second auxiliary switch (T3 , T4) depending on the received switching command, determining and activating a delay period (TV), switching off the corresponding of the two semiconductor power switches (TI, T2) of the at least one half-bridge (12.1) and activating a dead time measurement with a predetermined stop value, which is a maximum Dead time span (TS) corresponds, when the first delay time span (TV) has expired, to measuring a node voltage (US) across the first semiconductor power switch (TI) and switching on the other of the two semiconductor power switches (TI, T2) of the at least one half bridge (12.1) and stopping the dead time measurement when the measured node voltage (US) has reached a predetermined voltage threshold well value or the dead time measurement has reached the stop value, the switched on auxiliary switch (T3, T4) remains switched on for the duration of the delay time span (VT) after switching on the other of the two semiconductor power switches (TI, T2) of the at least one half bridge (12.1) and is switched off after the delay period (VT) has elapsed.

19. The method (100, 200) according to claim 18, characterized in that the delay time span (TV) is determined by an adaptive delay chain which is predetermined by a number (X) of delay steps with identical time spans, the number ( X) of the delay steps of the delay time span (VT) is increased by one when the dead time measurement has reached the specified stop value or the maximum dead time span (TS), whereby the number (X) of the delay steps of the delay time span (VT) is reduced by one , if the dead time measurement has not reached a predetermined minimum dead time span (TS), the number (X) of the delay steps of the delay time span (VT) otherwise remaining the same.

20. The method (100, 200) according to claim 18 or 19, characterized in that the delay time span (TV) is determined by an integrated current measurement, after switching on the first or second auxiliary switch (T3, T4) a time measurement for determination the delay time span (VT) and a measurement of a current (IT1, IT2) through a corresponding one of the two semiconductor power switches (TI, T2) of the at least one half-bridge (12.1) are activated, the measured current (IT1, IT2) having a predetermined threshold value is compared, and the time measurement is stopped and the measurement result is specified as the elapsed delay time span (VT) when the measured current (IT1, IT2) exceeds the specified threshold value.