CN115943546A - Power output stage for a device for supplying energy to an electrical load - Google Patents

Power output stage for a device for supplying energy to an electrical load Download PDF

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Publication number
CN115943546A
CN115943546A CN202180044465.5A CN202180044465A CN115943546A CN 115943546 A CN115943546 A CN 115943546A CN 202180044465 A CN202180044465 A CN 202180044465A CN 115943546 A CN115943546 A CN 115943546A
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CN
China
Prior art keywords
designed
output stage
power output
current
switching
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CN202180044465.5A
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Chinese (zh)
Inventor
F·斯特温
D·布拉
M·吉普特内尔
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Robert Bosch GmbH
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Robert Bosch GmbH
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/4811—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode having auxiliary actively switched resonant commutation circuits connected to intermediate DC voltage or between two push-pull branches
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0003—Details of control, feedback or regulation circuits
    • H02M1/0009—Devices or circuits for detecting current in a converter
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0048—Circuits or arrangements for reducing losses
    • H02M1/0054—Transistor switching losses
    • H02M1/0058—Transistor switching losses by employing soft switching techniques, i.e. commutation of transistors when applied voltage is zero or when current flow is zero
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/4815—Resonant converters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/53—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M7/537—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
    • H02M7/5387—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/8252—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using III-V technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0605—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits made of compound material, e.g. AIIIBV
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Inverter Devices (AREA)

Abstract

The invention relates to a power output stage (10) of a device (1) for supplying energy to an electrical load (3), having: a power switching device (12) comprising at least one half bridge (12.1) and designed based on gallium nitride on silicon technology; a control circuit (15) for a power switching device (12), wherein the semiconductor power switches of at least one half-bridge (12.1) are designed as gallium nitrite semiconductors on the front side of a carrier substrate. The invention further relates to a device (1) for supplying an electrical load (3) with such a power output stage (10) and to a method for determining a voltage-free switching time for such a power output stage (10). The control circuit (15) for at least one half-bridge (12.1) comprises an ARCP module (16B) which has two auxiliary switches and a choke coil and is designed to switch the semiconductor power switches of the respective half-bridge (12.1) at a voltage-free switching time, wherein the control circuit (15) is designed to determine the voltage-free switching time by integrating a current measurement and/or an adaptive delay chain.

Description

Power output stage for a device for supplying energy to an electrical load
Technical Field
The invention relates to a power output stage for a device for supplying energy to an electrical load, according to the type of independent claim 1. The invention also relates to a corresponding device for supplying an electrical load with energy having such a power output stage and to a method for determining a voltage-free switching time for a power output stage.
Background
Three-phase brushless dc motors are usually operated by the power output stage of a B6 inverter, preferably designed as a silicon-based power semiconductor, preferably by means of field-oriented regulation. In order to operate an electrical load, in this case a dc motor, in addition to the actual semiconductor power switches, bridge drivers are used which switch the semiconductor power switches on and off. Typically, this is done in a small motor with a voltage below 60V and a power below 3kW and a frequency of about 20 kHz. Due to switching losses, the frequency should be chosen as low as possible, but above the human hearing threshold.
The gallium nitride on silicon technology known from the prior art achieves a much higher switching frequency and a lower resistance per unit area for power semiconductor switches compared to pure silicon semiconductor switches. Furthermore, the corresponding lateral technology enables the integration of further active and passive components on the same silicon substrate on which the power semiconductor is located.
An energy supply device having an energy module and a capacitor is known from DE 10 2016 113 A1. The energy module has an inverter circuit and is designed to supply electrical energy to the motor. The capacitor is arranged adjacent to the energy module and is designed to limit voltage variations due to ripple current at the input of the inverter circuit. The inverter circuit and the capacitor are overmolded and encapsulated by a monolithic insulating epoxy such that voltage isolation is provided between the energy module and the capacitor.
A power output stage of this type for an apparatus for supplying energy to an electrical load is known from DE 10 2015 208 A1. The power output stage comprises a power switching device comprising at least one half bridge and being designed based on gallium nitride on silicon technology, and a steering circuit for the power switching device. The semiconductor power switches of at least one half bridge are designed as gallium nitrite semiconductors on the front side of the silicon substrate.
Disclosure of Invention
The power output stage of the device for supplying energy to an electrical load having the features of independent claim 1, the device for supplying energy to an electrical load having the features of independent claim 15 and the method for determining the voltage-free switching time point for a power output stage having the features of independent patent claims 18 and 19 respectively have the following advantages: the ARCP module (ARCP: auxiliary resonant commutating pole) determines a dynamic operating point which enables soft switching even if the midpoint voltage of the separate intermediate circuit varies via a number of parameters (load point, intermediate circuit voltage, dynamic behavior, temperature, etc.) and thus the "charging time" of the inductor or choke coil itself varies. This ensures that the correct voltage-free time points are assumed for switching on and off the semiconductor power switch. By means of the embodiments of the invention, hard switching with high voltage jumps can be avoided and soft switching can be carried out at quasi-no-voltage switching times. One of the main advantages of the ARCP module is: the switching frequency can be significantly increased by eliminating switching losses in at least one half-bridge. Passive components, i.e. capacitors such as intermediate circuit capacitances or possibly sine or edge filters, can thus be constructed considerably smaller and less expensive. Furthermore, the semiconductor area may be reduced due to lower power losses.
An embodiment of the invention provides a power output stage for a device for supplying energy to an electrical load, the power output stage having: a power switching device comprising at least one half bridge and designed based on gallium nitride on silicon technology; and a steering circuit for the power switching device, wherein the semiconductor power switches of the at least one half-bridge are designed as gallium nitrite semiconductors on the front side of the carrier substrate. The control circuits for at least one half-bridge each comprise an ARCP module which has two auxiliary switches and a choke and is designed to switch the semiconductor power switches of the respective half-bridge at a voltage-free switching time, wherein the control circuits are designed to determine the voltage-free switching time by integrating current measurements and/or adaptive delay chains.
Furthermore, a device for supplying energy to an electrical load is proposed, which has an energy supply, a controller and such a power output stage.
Furthermore, a method for determining a voltage-free switching time point for a power output stage is proposed, having the following steps: a switching command is received and the first or second auxiliary switch is switched on in accordance with the received switching command. A delay period is determined and activated. When the first delay period expires, the respective one of the two semiconductor power switches of the at least one half bridge is turned off and a dead time measurement with a preset stop value is activated, the stop value corresponding to the maximum dead time period. The node voltage across the first semiconductor power switch is measured and when the measured node voltage corresponds to a preset voltage threshold or when the dead time measurement reaches a stop value, the other of the two semiconductor power switches of the at least one half-bridge is switched on and the dead time measurement is stopped. In this case, the switched-on auxiliary switch remains switched on for the duration of the delay period after the other of the two semiconductor power switches of the at least one half bridge has been switched on, and is switched off after the expiration of the delay period.
Preferably, the first auxiliary switch may be switched on for switching off the first semiconductor power switch and for switching on the second semiconductor power switch, and the second auxiliary switch may be switched on for switching off the second semiconductor power switch and for switching on the first semiconductor power switch.
The power output stage of the device for supplying energy to an electrical load described in independent claim 1 and the device for supplying energy to an electrical load described in independent claim 15 and the method for determining a voltage-free switching time point for a power output stage described in independent claim 18 can be advantageously improved by the measures and refinements listed in the dependent claims.
Particularly advantageously, the power switching device and the control circuit can be designed as a monolithic module on the basis of gan technology on silicon, wherein at least the individual active components of the monolithic module can be arranged on a common carrier substrate. In this case, at least the two auxiliary switches are integrated into the monolithic module and are arranged on a common carrier substrate with the semiconductor power switches of the respective half-bridge. This has the advantage that further functions for operating the device can be integrated in the monolithic module and further miniaturization can be achieved. By means of gan technology on silicon, a plurality of half-bridges of a power switching device and corresponding drivers for the half-bridges can be applied to a common carrier substrate, preferably a silicon substrate, in order to handle arbitrary electrical loads. Thus, for example, three half-bridges of the B6 bridge and corresponding control circuits can be arranged on a common carrier substrate for the energy supply of the three-phase motor. It is obvious that any other number of half-bridges required for supplying an electrical load can also be provided on a common carrier substrate. Additionally, the protection functions, i.e. overcurrent protection function, overtemperature protection function, etc., may be applied together on a common carrier substrate.
Furthermore, the shift of the control circuit, which also enables the current regulation for the power switching device, into the monolithic module makes it possible to dispense with the control lines which normally have to be routed to the bridge driver circuit and does not require any modulation in the upper-level controller. Thus, all fast signals and their switching edges do not "leave" the monolithic module. From this, it can be expected that EMV behavior is positively influenced. Due to the small number of contacts required, a particularly compact implementation is feasible, since the contact pads may be difficult to be below a minimum size. Additionally, the proposed structural implementation may reduce EMV interference, which may propagate via corresponding coupling capacitances with the cooling bodies in the system by the jumping potentials at the individual half-bridges. For this purpose, the cooling surfaces of the power switching device can be connected to ground, for example, directly to hard ground, if possible, or capacitively directly in a defined manner in the monolithic module via a coupling capacitor. Thereby, additional interference suppression capacitors or Y-capacitors and contact elements (e.g. SMD springs) become superfluous. Another advantage is that an electrically conductive, thermally conductive paste can be used, which can be obtained with a much higher thermal conductivity than an insulating paste.
In an advantageous embodiment of the power output stage, the capacitors of the intermediate circuit capacitance are designed as silicon capacitors and are arranged on the front side and/or the rear side of the carrier substrate. In a particularly advantageous embodiment, the silicon capacitors are formed on the rear side of the common carrier substrate in a deep trench technology in order to buffer the supply voltage. Due to the high possible switching frequency, silicon capacitors in deep trench technology are used to represent intermediate circuits even in the case of low-voltage inverters for small power of several kilowatts at voltages below 60V. By arranging the intermediate circuit capacitors, which are embodied as silicon capacitors, on a common carrier substrate, coupling to the power switching device is possible with very low inductance. Thus, for example, a silicon capacitor on the rear side of a common carrier substrate is electrically contacted to a semiconductor power switch on the front side by means of a through-hole through the carrier substrate. Simple electrical contacting is likewise possible if the intermediate circuit capacitors formed as silicon capacitors are arranged laterally on the front side of the common carrier substrate. Thus, a structure without through holes in the carrier substrate is possible.
In a further advantageous embodiment of the power output stage, the monolithic module is embedded in or arranged on a multilayer circuit board. In this embodiment of the power output stage, the capacitors of the intermediate circuit capacitance can be arranged as silicon capacitors on a separate carrier substrate and embedded in or arranged on the multilayer circuit board, as in the case of monolithic modules. Alternatively, the capacitors of the intermediate circuit capacitance can be designed in the chip configuration as multilayer Ceramic capacitors (MLCC) and embedded in or arranged on the multilayer circuit board.
In a further advantageous embodiment of the power output stage, two auxiliary switches, which are designed as gallium nitrite semiconductors, are combined to form a bidirectionally blocking auxiliary switch and are designed on the front side of the carrier substrate. The semiconductor area required can be halved by the implementation as an auxiliary switch for bidirectional blocking compared to a conventional ARCP module in which two anti-parallel switches are used as auxiliary switches.
In a further advantageous embodiment of the power output stage, the choke coil can be designed in a coreless manner as a printed conductor in the carrier substrate. This is achieved by a high switching frequency. Since no core material is required, a complicated structure of the choke coil can be avoided. Alternatively, the choke coil can be designed in a coreless manner as a printed conductor of a multilayer circuit board of the power output stage. This means that the choke coil, like the capacitor of the intermediate circuit capacitance, can be embedded in or arranged on a multilayer circuit board in which the monolithic module is embedded or on which the monolithic module is arranged.
In a further advantageous embodiment of the power output stage, the control circuit can comprise a current regulator, which is designed to: at least one measurement current and at least one reference current, which represent the respective present output current, are received in analog signal form and compared with one another, and at least one respective switching signal is generated and output as a function of the comparison. In this case, the at least one measurement current can preferably be detected in the monolithic module. Furthermore, the control circuit may comprise a driver stage, which is designed to: at least one switching signal is received from the current regulator, processed, and output to the power switching device. For high switching frequencies, other regulation methods, i.e. for example direct switching, are possible. Thus, for each half-bridge of the power switching device, the current regulator may comprise a comparator designed to: the corresponding half-bridge is switched off when the measurement current exceeds the corresponding reference current and switched on when the measurement current is below the corresponding reference current.
It is thereby possible to directly actuate the semiconductor power switches directly via presetting target values to the respective comparators. Therefore, in the case of a three-phase motor as an electrical load, only three analog reference signals for the phase currents are transmitted to the monolithic module. The current regulation takes place directly in the monolithic module by means of the comparator. The reference value is compared with the measured value of the phase current. If the reference value is exceeded, the switch is switched off, if the reference value is undershot, the switch is switched on. Thus, the required reference current is set on average. In order to limit the switching frequency, the individual comparators can be sampled and/or implemented with hysteresis. The digital output signal of the comparator can then be used directly as a switch state command for the respective semiconductor power switch. The respective reference signal is an analog signal which directly presets the current in the electrical load or in the respective stator winding of the three-phase motor. The analog signal can be preset by the central controller and contains at most the machine frequency (including the harmonics that are explicitly fed in). Thus, the degrees of freedom for handling the electrical loads remain in the controller, whereas the fast current dynamics move into the monolithic circuit module, which significantly reduces the requirements on the dynamics and the computational power of the controller and results in cost advantages. At the same time, by means of fast hardware comparators, very dynamic current regulators with high bandwidths can be obtained, which can also offset the increased actuator bandwidth that results from the increased switching frequency. If the current regulation is also performed in the control unit, a more powerful controller is automatically required for increasing the bandwidth of the current regulation, which results in additional costs.
In a further advantageous embodiment of the power output stage, the monolithic module can comprise an electrical interface which is designed to receive signals from external components and/or assemblies. The electrical interface can receive a supply voltage potential, a ground potential and at least one reference current.
In a further advantageous embodiment of the power output stage, the power switching device can be designed, for example, as a B6 inverter with three half bridges. The cooling surface of the B6 inverter can be connected to ground directly or via at least one coupling capacitor with a defined capacitance.
In an advantageous embodiment of the device for supplying energy to an electrical load, the electrical interface can be designed to: receiving a supply voltage potential and a ground potential of an energy supply and receiving at least one reference current from a controller.
In a further advantageous embodiment of the device for supplying energy to an electrical load, the electrical load can be designed as a three-phase brushless dc motor, wherein the half-bridges of the B6 inverter can each be connected to one of the three-phase brushless dc motors.
In an advantageous embodiment of the method, the delay time period can be determined by an adaptive delay chain which is preset by a number of delay steps having the same time period. Here, when the dead time measurement reaches a preset stop value or a maximum dead time period, the number of delay steps of the delay time period is increased by one. When the dead time measurement does not reach a preset minimum dead time period, the number of delay steps of the delay time period is reduced by one. In other cases, the number of delay steps of the delay period may remain unchanged.
Additionally or alternatively, the delay period is determined by an integrated current measurement. In this case, the time measurement for determining the delay time period and the measurement of the current are activated by the respective semiconductor power switch of the two semiconductor power switches of the at least one half bridge after the first or second auxiliary switch has been switched on, wherein the measured current can be compared to a predetermined threshold value. When the measured current exceeds a preset threshold, the time measurement may be stopped and the measurement result preset as an expired delay period.
Embodiments of the invention are illustrated in the drawings and are explained in more detail in the following description. In the drawings, the same reference numerals denote parts or elements performing the same or similar functions.
Drawings
Fig. 1 shows a schematic block diagram of an embodiment of an apparatus according to the invention for supplying energy to an electrical load with an embodiment of a power output stage according to the invention.
Fig. 2 shows a schematic circuit diagram of the control circuit of the half bridge of the power output stage according to the invention from fig. 1.
Fig. 3 shows a schematic circuit diagram of the ARCP module of fig. 1 for a half bridge of a power output stage according to the invention.
Fig. 4 shows a schematic diagram and a perspective view of the power output stage of fig. 1 designed as a monolithic module.
Fig. 5 shows a schematic flow chart of a first embodiment of a method according to the invention for determining a voltage-free switching point in time of the output stage in fig. 1 according to the invention.
Fig. 6 shows a schematic flow chart of a second embodiment of the method according to the invention for determining the voltage-free switching time point of the output stage in fig. 1 according to the invention.
Detailed Description
As can be seen from fig. 1, the illustrated embodiments of the device 1 according to the invention for supplying energy to an electrical load 3 each comprise an energy supply 5, a controller 7 and a power output stage 10 according to the invention.
As can also be seen from fig. 1 to 3, the illustrated embodiment of the power output stage 10 according to the invention of the device 1 for supplying energy to an electrical load 3 comprises: a power switching device 12 comprising at least one half bridge 12.1 and designed based on gallium nitride on silicon technology; and a control circuit 15 for the power switching device 12, wherein the semiconductor power switches T1, T2 of the at least one half bridge 12.1 are designed as gallium nitrite semiconductors on the front side of the carrier substrate SiS. The control circuit 15 for at least one half bridge 12.1 in this case comprises an ARCP module 16B, each having two auxiliary switches T3, T4 and a choke coil 16.2, and being designed to switch the semiconductor power switches T1, T2 of the respective half bridge 12.1 at a voltage-free switching time, wherein the control circuit 15 is designed to determine the voltage-free switching time by integrating current measurements and/or by means of an adaptive delay chain.
It can also be seen in particular from fig. 1 and 4 that the power switching device 12 and the control circuit 15 are designed as monolithic modules based on gallium nitride on silicon technology. In this case, at least the individual active components of the monolithic module are arranged on a common carrier substrate SiS.
As can also be seen from fig. 1, in the illustrated embodiment of the device 1, the electrical load 3 is designed as a three-phase brushless dc motor 3A. The power switching device 12 is designed as a B6 inverter 12A with three half bridges 12.1, wherein the half bridges 12.1 of the B6 inverter 12A are connected to the phases U, V, W of the three-phase brushless dc motor 3A, respectively. Furthermore, the cooling surface of the B6 inverter 12A is connected to ground GND either directly or via at least one coupling capacitor with a defined capacitance. In alternative embodiments, which are not shown, the power switching device 12 can also have fewer or more than three half bridges 12.1. Furthermore, the apparatus 1 for supplying energy to the electrical load 3 may also supply energy to an electrical load 3 other than the three-phase dc motor 3A.
As can also be seen from fig. 1 and 5, in the exemplary embodiment shown, capacitors C1, C2 of intermediate circuit capacitance 14 for buffering supply voltage UBat are each arranged on carrier substrate SiS. In the exemplary embodiment shown, the intermediate circuit capacitance 14 is therefore likewise integrated into a monolithic module.
In a not shown embodiment of the power output stage 10, the monolithic module is embedded in or arranged on a multilayer circuit board. In the exemplary embodiment, the capacitors C1, C2 of the intermediate circuit capacitance 14 can be arranged on a separate carrier substrate and embedded in or arranged on the multilayer circuit board. Alternatively, in the exemplary embodiment, the capacitors C1, C2 of the intermediate circuit capacitance 14 can be embedded directly in the multilayer circuit board or arranged thereon.
As can also be seen from fig. 1 and 2, the control circuit 15 comprises a current regulator 18, which is designed to: at least one measurement current Im (U, V, W) and at least one reference current Ir (U, V, W)) representing a corresponding present output current Io (U, V, W) are received in analog signal form and compared with each other, and at least one corresponding switching signal is generated and output depending on the comparison. To this end, in the exemplary embodiment shown, the current regulator 18 comprises, for each half-bridge 12.1 for the power switching device 12, a comparator 18.1 which is designed to: the corresponding half-bridge 12.1 is switched off when the measurement current Im (U, V, W) exceeds the corresponding reference current Ir (U, V, W), and the corresponding half-bridge 12.1 is switched on when the measurement current Im (U, V, W) is below the corresponding reference current Ir (U, V, W). In the illustrated embodiment of the current regulator 18, the comparator 18.1 is clocked by the clock signal TS. It can also be seen from fig. 1 that in the embodiment shown at least one measuring current Im (U, V, W) is detected within the monolithic module.
As can also be seen from fig. 1 and 2, in the embodiment shown, the steering circuit 15 comprises a driver stage 16 which comprises a gate steering device 16A and is designed to: at least one switching signal is received from the current regulator 18 or the respective comparator 18.1, processed and output to the two semiconductor power switches T1, T2 of the respective half bridge 12.1 of the power switching device 12.
As can also be seen from fig. 1, the monolithic module comprises an electrical interface 13 which is designed to receive signals from external components and/or assemblies. In the illustrated embodiment, the electrical interface 13 receives a supply voltage potential UBat and a ground potential GND from the energy supplier 5 and at least one reference current Ir (U, V, W) from the controller 7, respectively. In order to generate at least one reference current Ir (U, V, W), the controller 7 evaluates the output signal of a sensor arrangement DWM, which in the exemplary embodiment shown detects the rotational angle of the three-phase dc motor 3A and generates a corresponding output signal.
As can also be seen from fig. 1 and 3, in the described exemplary embodiment of the power output stage 10, the intermediate circuit capacitance 14 is formed separately and comprises two capacitors C1, C2, which are each formed as a silicon capacitor of deep trench technology on the rear side of a common carrier substrate SiS in order to buffer the supply voltage UBat. In this case, the silicon capacitors C1, C2 are in electrical contact with the power switching device 12B by means of vias, not shown, which extend through the carrier substrate SiS.
In alternative embodiments of the power output stage 10, which are not shown, the monolithic module is embedded in or arranged on a multilayer circuit board. In the exemplary embodiment, the capacitors C1, C2 of the intermediate circuit capacitance 14 can be embodied as silicon capacitors on a separate carrier substrate and embedded in or arranged on a multilayer circuit board. In the exemplary embodiment, the capacitors C1, C2 of the intermediate circuit capacitance 14 can alternatively be designed as multilayer ceramic capacitors (MLCC: multilayer ceramic capacitor) in a chip configuration and be embedded directly in or arranged on the multilayer circuit board.
As can also be seen from fig. 1 and 3, the ARCP module 16 is designed as part of the driver stage 16 and is integrated into a monolithic module. For this purpose, the two auxiliary switches T3, T4 are combined as gallium nitrite semiconductors into a bidirectionally blocking auxiliary switch 16.1 and are formed together with the semiconductor power switches T1, T2 of the respective half-bridge 12.1B on the front side of the carrier substrate SiS. The choke coil 16.2 is designed as a conductor track in the carrier substrate SiS in a coreless manner.
In an alternative embodiment of the power output stage 10, which is not shown, in which the monolithic module is embedded in or arranged on a multilayer circuit board, the choke coil 16.2 is formed as a conductor track of the multilayer circuit board in a coreless manner.
A first embodiment of a method 100 for determining a no-voltage switching point in time of the power output stage 10 described above, shown in fig. 5, is based on an adaptive delay chain. Here, the method 100 starts in step S100, for example by starting the vehicle. Then, it waits in step S110 until a switch command for one of the two auxiliary switches T3, T4 is received. Then, it is checked in step S120 that: whether a first switching command representing, for example, a transition from a first logic state to a second logic state is received, or whether a second switching command representing, for example, a transition from a second logic state to a first logic state is received. If a first switching command is recognized in step S120, the method continues with step S130. If a second switching command is recognized in step S120, the method continues with step S230.
In step S130, the first auxiliary switch T3 is turned on or turned on according to the received first switching command. Thereby increasing the coil current IL through the choke coil 16.2. In step S140, a delay time slice TV is activated, which is preset by a number X of delay steps having the same time period, and the coil current IL through the choke coil 16.2 continues to rise. After the expiration of the delay period TV, the current IL through the choke coil 16.2 is greater than the corresponding output current Io (U, V, W), and the corresponding current IT1 through the corresponding one of the two semiconductor power switches T1, T2 of the at least one half bridge 12.1, here the first semiconductor power switch T1, is greater than zero, and the node voltage US above the first semiconductor switch T1 corresponds to the ground potential GND. Therefore, the first semiconductor power switch T1 is switched off or switched off in step S150 and a dead time measurement with a preset stop value is activated, which corresponds to the maximum value of the dead time period TS. Thereby, the node voltage US over the first semiconductor power switch T1 increases, which is measured in step S160 and compared to the first voltage threshold. The first voltage threshold value corresponds, for example, approximately to the supply voltage potential UBat or is selected to be slightly lower than the supply voltage potential UBat. In step S170, when the measured node voltage US corresponds to a preset first voltage threshold value or the dead time measurement reaches a preset stop value or a maximum dead time period TS, the other of the two semiconductor power switches T1, T2 of the at least one half bridge 12.1, in this case the second semiconductor power switch T2, is switched on or switched on and the dead time measurement is stopped. At the point in time of the switch-on, the voltage drop over the second semiconductor power switch T2 is ideally equal to zero. As a result, the second semiconductor power switch T2 has no voltage and can be switched on or switched on without losses. Further, in step S170, if the dead time measurement reaches the preset stop value or the maximum dead time period TS, the number X of delay steps of the delay time period VT is added by 1. If the expired time period is less than the minimum value of the dead time period TS, the number X of delay steps of the first delay time period VT1 is reduced by one, wherein the number X of delay steps of the delay time period TV is otherwise kept constant. This means that the delay period TV1 does not change when the duration of the stoppage of the dead time measurement lies between the minimum and maximum values of the dead time period TS. After the second semiconductor power switch T2 is turned on, the delay period TV is activated in step S180. After the expiration of the delay period TV, the turned-on first auxiliary switch T3 is turned off or turned off in step S190. This means that after the second semiconductor power switch T2 is switched on, the first auxiliary switch T3 remains switched on also for the duration of the delay period TV, so that the coil current IL through the choke coil 16.2 can be reduced. The method 100 then continues with step S110 and waits for the next switch command to be received.
In step S230, the second auxiliary switch T4 is turned on or turned on according to the received second switch command. This reduces the coil current IL through the choke 16.2. In step S240, the delay period TV is activated and the coil current IL through the choke coil 16.2 drops further. After the expiration of the delay period TV, the current IL through the choke coil 16.2 is greater than the corresponding output current Io (U, V, W) and the corresponding current IT2 through the two semiconductor power switches T1, T2 of the at least one half bridge 12.1, here the second semiconductor power switch T2, is less than zero. Therefore, the second semiconductor power switch T2 is switched off or switched off in step S250 and a dead time measurement with a preset stop value is activated, which corresponds to the maximum value of the dead time period TS. Thereby, the node voltage US above the first semiconductor power switch T1 drops, which is measured in step S260 and compared to the second voltage threshold. The second voltage threshold value corresponds for example approximately to the ground potential GND or is selected to be slightly higher than the ground potential GND. In step S270, when the measured node voltage US corresponds to a predetermined second voltage threshold value or the dead time measurement reaches a predetermined stop value, the other of the two semiconductor power switches T1, T2 of the at least one half bridge 12.1, in this case the first semiconductor power switch T1, is switched on or switched on and the dead time measurement is stopped. At the switch-on point in time, the voltage drop over the first semiconductor power switch T1 is ideally equal to zero. The first semiconductor power switch T1 is thus voltage-free and can be switched on or switched on without losses. Further, in step S270, when the dead time measurement value reaches the preset stop value, the number X of delay steps of the delay period VT is increased by one. If the expired time period is smaller than the minimum value of the dead time period TS, the number X of delay steps of the first delay time period VT1 is reduced by one, wherein the number X of delayed parts of the delay time period TV otherwise remains unchanged. This means that the delay period TV does not change when the measured duration of the stop is between the minimum and maximum values of the dead time period TS. After the first semiconductor power switch T1 is turned on, the delay period TV is activated in step S280. After the delay period TV expires, the turned-on second auxiliary switch T4 is turned off in step S290. This means that the second auxiliary switch T4 remains on for the duration of the delay period TV after the first semiconductor power switch T1 is turned on. The method 100 then continues with step S110 and waits for the next switch command to be received.
A second embodiment of a method 200 for determining a voltage-free switching time point of the power output stage 10 described above, which is shown in fig. 6, is based on integrated current measurement. Here, the method 200 starts in step S300, for example, by starting the vehicle. Then, it waits until a switching command of one of the two auxiliary switches is received in step S310. Then, it is checked in step S320 whether a first switching command is received representing, for example, a transition from the first logic state to the second logic state, or whether a second switching command representing, for example, a transition from the second logic state to the first logic state is received. If a first switching command is recognized in step S320, the method continues with step S330. If a second switching command is recognized in step S320, the method continues with step S430.
In step S330, the first auxiliary switch T3 is switched on or conducted according to the received first switch command and is activated or pneumatically used to determine the time measurement of the delay period TV. As a result, the coil current IL flowing through the choke coil 16.2 increases and in step S340 the current IT1 flowing through the respective one of the two semiconductor power switches T1, T2 of the at least one half bridge 12.1, in this case the first semiconductor power switch T1, is measured. In step S350, the first semiconductor power switch T1 is switched off or switched off and a dead time measurement with a preset stop time corresponding to the maximum value of the dead time period TS is activated and, when the current IT1 through the first semiconductor power switch T1 exceeds a preset current threshold value, the time measurement is stopped and the measurement result is preset as the expired delay time period VT. This means that the current IL through the choke coil 16.2 is greater than the corresponding output current Io (U, V, W) and the node voltage US over the first semiconductor switch T1 corresponds approximately to the ground potential GND. In step S360, the node voltage US over the first semiconductor power switch T1 is measured and compared with a first voltage threshold value, which for example corresponds approximately to the supply voltage potential UBat or is selected to be slightly lower than the supply voltage potential UBat. In step S370, when the measured node voltage US reaches a preset stop value corresponding to a preset first voltage threshold or dead time measurement, the other of the two semiconductor power switches T1, T2 of the at least one half bridge 12.1, in this case the second semiconductor power switch T2, is switched on or switched on and the dead time measurement is stopped. At the point in time of the switch-on, the voltage drop over the second semiconductor power switch T2 is ideally zero. The second semiconductor power switch T2 is therefore voltage-free and can be switched on or switched on without losses. After the second semiconductor power switch T2 is switched on, the delay period TV determined by the time measurement is activated in step S380. After the expiration of the delay period TV, the turned-on first auxiliary switch T3 is turned off or turned off in step S390. This means that the first auxiliary switch T3 is also kept on for the duration of the delay period TV after the second semiconductor power switch T2 is switched on, so that the coil current IL through the choke coil 16.2 can be reduced. The method 200 then continues with step S310 and waits for the next switch command to be received.
In step S430, the second auxiliary switch T4 is switched on or turned on according to the received second switch command and is activated or pneumatically used to determine the time measurement of the delay period TV. As a result, the coil current IL flowing through the choke coil 16.2 decreases and in step S440 the current flowing through the respective, in this case the second semiconductor power switch T2 of the two semiconductor power switches T1, T2 of the at least one half bridge 12.1 is measured. In step S450, the second semiconductor power switch T2 is switched off or switched off and a dead time measurement with a preset stop value corresponding to the maximum value of the dead time period TS is activated, and when the current through the second semiconductor power switch T2 exceeds a preset current threshold value, the time measurement is stopped and the measurement result is preset as the expired delay time period VT. This means that the current IL through the choke coil 16.2 is greater than the corresponding output current Io (U, V, W). In step S460, the node voltage US over the first semiconductor power switch T1 is measured and compared with a second voltage threshold, which for example corresponds approximately to the ground potential GND or is selected to be slightly larger than the ground potential GND. In step S470, the other of the two semiconductor power switches T1, T2 of the at least one half bridge 12.1, in this case the first semiconductor power switch T1, is switched on or switched on when the measured node voltage US corresponds to a preset second voltage threshold value or the dead time measurement reaches a preset stop value. At the switch-on point in time, the voltage drop over the first semiconductor power switch T1 is ideally equal to zero. The first semiconductor power switch T1 is therefore voltage-free and can be switched on or switched on without losses. After the first semiconductor power switch T1 is switched on, the delay period TV determined by the time measurement is activated in step S480. After the expiration of the delay period TV, the turned-on second auxiliary switch T4 is turned off or turned off in step S490. This means that the second auxiliary switch T4 remains on for the duration of the delay period TV after the first semiconductor power switch T1 is turned on. The method 200 then continues with step S310 and waits for the next switch command to be received.
For example, the delay period VT may be implemented by means of a switching shift register. For example, the dead time period TS may be implemented by means of a monostable multivibrator.
In principle, both embodiments of the method can be implemented in NMOS logic. The first embodiment of the method 100 is less sensitive to parameter variance for its adaptive nature, but generally requires more logic elements than the second embodiment of the method 200. However, the second embodiment of the method 200 can only be used if the current measurement is sufficiently accurate. The two methods 100, 200 can also be combined if, for example, the current measurement itself is not accurate enough but still usable to support or verify the setting of the adaptive delay chain.

Claims (20)

1. A power output stage (10) of an apparatus (1) for supplying energy to an electrical load (3), the power output stage having: a power switching device (12) comprising at least one half bridge (12.1) and designed based on gallium nitride on silicon technology; and a control circuit (15) for the power switching device (12), wherein the semiconductor power switches (T1, T2) of the at least one half bridge (12.1) are designed as gallium nitrite semiconductors on the front side of a carrier substrate (SiS),
it is characterized in that the preparation method is characterized in that,
the control circuit (15) for the at least one half-bridge (12.1) comprises an ARCP module (16B) having two auxiliary switches (T3, T4) and a choke coil (16.2) and being designed to switch the semiconductor power switches (T1, T2) of the respective half-bridge (12.1) at a voltage-free switching time, wherein the control circuit (15) is designed to determine the voltage-free switching time by integrating a current measurement and/or an adaptive delay chain.
2. The power output stage (10) according to claim 1, characterized in that the power switching device (12) and the steering circuit (15) are designed as monolithic modules based on gallium nitride on silicon technology, wherein at least the individual active components of the monolithic modules are arranged on a common carrier substrate (SiS).
3. The power output stage (10) according to claim 1 or 2, characterized in that the capacitors (C1, C2) of the intermediate circuit capacitance (14) are designed as silicon capacitors and are arranged on the front side and/or the rear side of the carrier substrate (SiS).
4. A power output stage (10) according to claim 2 or 3, characterized in that the monolithic module is embedded in or provided on a multilayer circuit board.
5. The power output stage (10) according to claim 4, characterized in that the capacitors (C1, C2) of the intermediate circuit capacitance (14) are designed as silicon capacitors on a separate carrier substrate or as multilayer ceramic capacitors in a chip configuration and are embedded in or provided on the multilayer circuit board.
6. The power output stage (10) according to one of claims 1 to 5, characterized in that the two auxiliary switches (T3, T4) designed as gallium nitrite semiconductors form in combination a bidirectionally blocking auxiliary switch (16.1) and are designed on the front side of the carrier substrate (SiS).
7. The power output stage (10) according to one of claims 1 to 6, characterized in that the choke coil (16.2) is designed in a coreless manner as a printed conductor in the carrier substrate (SiS).
8. The power output stage (10) according to one of claims 4 to 6, characterized in that the choke coil (16.2) is designed in a coreless manner as a printed conductor of the multilayer circuit board.
9. The power output stage (10) according to any one of claims 1 to 8, characterized in that the steering circuit (15) comprises a current regulator (18) designed to: at least one measurement current (Im (U, V, W)) and at least one reference current (Ir (U, V, W)) representing a corresponding present output current (Io (U, V, W)) are received in analog signal form and compared with each other, and at least one corresponding switching signal is generated and output depending on the comparison.
10. The power output stage (10) according to claim 9, characterized in that the at least one measurement current (Im (U, V, W)) is detectable within the monolithic module.
11. The power output stage (10) according to claim 9 or 10, characterized in that the current regulator (18) comprises, for each of the half-bridges (12.1) of the power switching device (12), a comparator (18.1) designed to: -switching off the corresponding half-bridge (12.1) when the measurement current (Im (U, V, W)) exceeds the corresponding reference current (Ir (U, V, W)), and-switching on the corresponding half-bridge (12.1) when the measurement current (Im (U, V, W)) is lower than the corresponding reference current (Ir (U, V, W)).
12. The power output stage (10) according to any of claims 9 to 11, characterized in that the steering circuit (15) comprises a driver stage (16) designed for: receive the at least one switching signal from the current regulator (18), process the at least one switching signal and output to the power switching device (12).
13. Power output stage (10) according to one of claims 1 to 12, characterized in that the monolithic module comprises an electrical interface (13) designed for receiving signals from external components and/or assemblies.
14. The power output stage (10) according to any one of claims 1 to 13, characterized in that the power switching device (12) is designed as a B6 inverter (12A) with three half-bridges (12.1).
15. Device (1) for supplying an electrical load (3) with energy, having: energy supply (5), controller (7) and power output stage (10), characterized in that the power output stage (10) is designed according to any one of claims 1 to 14.
16. Device (1) according to claim 15, characterized in that said electrical interface (13) is designed for: receiving a supply voltage potential (UBat) and a ground potential (GND) of the energy supply (5) and receiving the at least one reference current (Ir (U, V, W)) from the controller (7).
17. Device (1) according to claim 15 or 16, characterized in that the electrical load (3) is designed as a three-phase brushless direct current motor (3A), wherein the half-bridges (12.1) of a B6 inverter (12A) can be connected with one phase (U, V, W) of the three-phase brushless direct current motor (3A), respectively.
18. Method (100, 200) for determining a voltage-free switching point in time for a power output stage (10), which power output stage is designed according to one of claims 1 to 14, with the following steps:
-receiving a switching command and switching on a first auxiliary switch (T3) or a second auxiliary switch (T4) according to the received switching command;
determining and activating a delay period (TV);
-turning off a corresponding one of the two semiconductor power switches (T1, T2) of the at least one half-bridge (12.1) and activating a dead time measurement with a preset stop value, which corresponds to a maximum dead time period (TS), when a first delay period (TV) expires;
measuring a node voltage (US) across a first semiconductor power switch (T1); and is
-switching on the other of the two semiconductor power switches (T1, T2) of the at least one half-bridge (12.1) and stopping the dead time measurement when the measured node voltage (US) corresponds to a preset voltage threshold or when the dead time measurement reaches the stop value;
wherein the auxiliary switch (T3, T4) that is switched on remains switched on for the duration of the delay period (VT) after the other of the two semiconductor power switches (T1, T2) of the at least one half bridge (12.1) is switched on, and is switched off after the delay period (VT) has expired.
19. The method (100, 200) according to claim 18, wherein the delay period (TV) is determined by an adaptive delay chain preset by a number (X) of delay steps having the same period, wherein the number (X) of delay steps of the delay period (VT) is increased by one when the dead time measurement reaches a preset stop value or a maximum dead time period (TS), wherein the number (X) of delay steps of the delay period (VT) is decreased by one when the dead time measurement does not reach a preset minimum dead time period (TS), wherein otherwise the number (X) of delay steps of the delay period (VT) remains constant.
20. The method (100, 200) according to claim 18 or 19, characterized in that the delay period (TV) is determined by an integrated current measurement, wherein a time measurement for determining the delay period (VT) and a measurement of a current (IT 1, IT 2) are activated by a corresponding one of the two semiconductor power switches (T1, T2) of the at least one half bridge (12.1) after switching on the first auxiliary switch (T3) or the second auxiliary switch (T4), wherein the measured current (IT 1, IT 2) is compared with a preset threshold value, and wherein the time measurement is stopped and a measurement result is preset as an expired delay period (VT) when the measured current (IT 1, IT 2) exceeds the preset threshold value.
CN202180044465.5A 2020-06-25 2021-06-17 Power output stage for a device for supplying energy to an electrical load Pending CN115943546A (en)

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