JP2023531061A - Power output stage for a device for supplying energy to an electrical load - Google Patents

Abstract

The present invention is a power output stage (10) for a device (1) for supplying energy to an electrical load (3), said power output stage (10) being based on gallium nitride on silicon technology. a power switching device (12) comprising at least one half-bridge (12.1) and a driver circuit (15) for the power switching device (12), the at least one half-bridge The semiconductor power switch of (12.1) comprises a power output stage (10) constructed as a gallium nitrite semiconductor on the surface of a carrier substrate and an electrical load having such a power output stage (10) It relates to a corresponding device (1) for supplying energy to (3) and to a method for determining voltage-free switching instants for such a power output stage (10). In this case the drive circuits (15) for the at least one half-bridge (12.1) each comprise one ARCP module (16B), the ARCP modules (16B) having two auxiliary switches and choke coils. and is adapted to switch the semiconductor power switches of the corresponding half-bridge (12.1) at voltage-free switching instants, the drive circuit (15) converting the voltage-free switching instants to the integrated current It is configured to determine by measurements and/or by adaptive delay chains.

Description

The invention starts from a power output stage of the type specified in the preamble of independent claim 1 for a device for supplying energy to an electrical load. A corresponding device for supplying energy to an electrical load with such a power output stage and a method for determining the voltage-free switching instants for a power output stage are also subject matter of the invention.

A three-phase brushless DC motor is normally driven by a power output stage preferably configured as a B6 inverter, preferably based on silicon power semiconductors, preferably with field-oriented control. In addition to the actual semiconductor power switches, a bridge driver is used to switch the semiconductor power switches on and off for driving an electrical load, here a DC motor. This typically occurs in small motors with a voltage of less than 60V at a frequency of about 20kHz and a power of less than 3kW. The frequency should be chosen as low as possible based on switching losses, but above the human hearing threshold.

The gallium nitride-on-silicon technology known from the prior art allows for power semiconductor switches significantly higher switching frequencies and lower resistance per area than pure silicon semiconductor switches. Furthermore, the corresponding lateral technology makes it possible to integrate further active and passive components on the same silicon substrate on which the power semiconductors are also placed.

DE 10 2016 113 121 A1 discloses an energy supply device with an energy module and a capacitor. The energy module has an inverting circuit and is configured to supply electrical energy to the electrical machine. A capacitor is positioned adjacent to the energy module and configured to limit voltage changes due to ripple current at the input of the inverting circuit. The inverting circuit and capacitor are encapsulated by injection molding with a monolithic insulating epoxy to provide voltage isolation between the energy module and the capacitor.

DE 10 2015 208 150 A1 discloses a power output stage of the generic type for a device for supplying energy to an electrical load. The power output stage includes a power switching device, including at least one half-bridge, constructed based on gallium nitride-on-silicon technology, and a drive circuit for the power switching device. At least one half-bridge semiconductor power switch is constructed as a gallium nitrite semiconductor on the surface of the silicon substrate.

DE-A-102016113121 DE 102015208150 A1

DISCLOSURE OF THE INVENTION A power output stage having the features of independent claim 1 for a device for supplying energy to an electrical load and a device having the features of independent claim 15 for supplying energy to an electrical load , a method having the features of independent claims 18 and 19 for determining the voltage-free switching instants for a power output stage, respectively, wherein the average voltage of the divided intermediate circuit is determined by a number of parameters (load point, Intermediate circuit voltage, dynamics, temperature, etc.), which changes the inductance or choke coil “charging time”, the dynamic operating point that allows soft switching is determined by the ARCP module (ARCP: Auxiliary Resonant It has the advantage of being identified by the Commutated Pole). This makes it possible to ensure that the correct voltage-free instants are met for switching on and switching off the semiconductor power switches. According to embodiments of the present invention, hard switching with very large jumps in voltage can be avoided, so to speak soft switching can be performed at voltage-free switching instants. A major advantage of the ARCP module is that the switching frequency of the at least one half-bridge can be significantly increased by eliminating switching losses in the at least one half-bridge. As a result, passive elements such as, for example, intermediate circuit capacitance capacitors or possibly present sine filters or edge filters can be constructed much more compactly and inexpensively. Furthermore, the semiconductor area can be reduced due to the reduced power loss.

An embodiment of the present invention is a power output stage for an apparatus for supplying energy to an electrical load, the power output stage being constructed based on gallium nitride on silicon technology and comprising at least one A power output stage is provided having a power switching device including a half bridge and a drive circuit for the power switching device. At least one half-bridge semiconductor power switch is constructed as a gallium nitrite semiconductor on the surface of the carrier substrate. In this case, the drive circuit for the at least one half-bridge each comprises an ARCP module, which has two auxiliary switches and choke coils, so that at voltage-free switching instants the corresponding half-bridge The semiconductor power switch is configured to switch, and the drive circuit is configured to identify a voltage-free switching instant by an adaptive delay chain and/or by an integrated current measurement.

Furthermore, a device for supplying energy to an electrical load is proposed, which comprises an energy supply, a control device and such a power output stage.

Furthermore, a method is proposed for determining the voltage-free switching instants for a power output stage, which comprises the following steps: receiving a switching command and, depending on the received switching command, switching the first auxiliary switch or the second 2. Switching on the auxiliary switch of 2. Identifying and activating delay time spans. Switching off the corresponding semiconductor power switch of the two semiconductor power switches of the at least one half-bridge and activating the dead time measurement with a predetermined stop value corresponding to the maximum dead time span after the delay time span has elapsed. step to convert. measuring the node voltage across the first semiconductor power switch and switching on the other of the two semiconductor power switches of the at least one half bridge; Stopping the dead time measurement when the voltage threshold is reached or when the dead time measurement reaches a stop value. In this case, the auxiliary switch that is switched on is switched on for the duration of the delay time span after the other of the two semiconductor power switches of the at least one half-bridge is switched on. It remains and is switched off after the delay time span has elapsed.

Preferably, the first auxiliary switch can be switched on to switch off the first semiconductor power switch and to switch on the second semiconductor power switch, the second semiconductor power switch and to switch on the first semiconductor power switch, a second auxiliary switch can be switched on.

A power output stage according to the independent claim 1 for a device for supplying energy to an electrical load and for supplying energy to an electrical load, by means and developments specified in the dependent claims, Advantageously, it is possible to improve the device according to the independent claim 15 and the method according to the independent claim 18 for determining a voltage-free switching instant for a power output stage.

The power switching device and the drive circuit can be constructed as a monolithic circuit module based on gallium nitride-on-silicon technology, at least the individual active elements of the monolithic circuit module being arranged on a common carrier substrate. It is particularly advantageous to be able to In this case, at least two auxiliary switches are integrated in a monolithic circuit module and arranged on a common carrier substrate together with the respective half-bridge semiconductor power switches. This has the advantage that further functions for driving the device can be integrated into the monolithic circuit module, allowing further miniaturization. Thus, to drive arbitrary electrical loads, for example using gallium nitride-on-silicon technology, a common support for multiple half-bridges of power switching devices and corresponding drivers for these half-bridges. It can be mounted on a body substrate, preferably on a silicon substrate. Thus, for example, three half-bridges of a B6 bridge with corresponding drive circuits for supplying energy to a three-phase motor can be arranged on a common carrier substrate. Of course, any other arbitrary number of half-bridges required to supply the electrical loads may be arranged on a common carrier substrate. Furthermore, protective functions, such as, for example, overcurrent protection, overheating protection, etc., may be mounted on a common support substrate.

Furthermore, by shifting the drive circuitry, which may also implement current control for the power switching device, into the monolithic circuit module, the drive lines that would otherwise have to be routed to the bridge driver circuitry may be eliminated. possible, without the need for any modulation on the part of the higher-level controller. Therefore, all high speed signals and their switching edges never "leave" the monolithic circuit module. This can be expected to positively influence the EMC behavior. A particularly compact implementation is possible because the small number of contacts required allows the contact pads to be significantly smaller than the minimum size. Furthermore, the proposed structure makes it possible to reduce EMC interference that can be propagated by the rapidly changing potentials at the individual half-ridges through the corresponding coupling capacitances with the cooling bodies in the system. Become. For this purpose, for example, the cooling surface of the power switching device can, if possible, be rigidly mounted directly on the ground, or the coupling capacitor can be directly capacitively placed in the monolithic circuit module. can be connected to ground as defined by Therefore, additional interference suppression capacitors or Y-capacitors and contact elements (eg SMD springs) are thereby eliminated. A further advantage is that a conductive thermal compound can be used, ie with a much higher thermal conductivity than an insulating paste.

In an advantageous embodiment of the power output stage, the capacitors of the intermediate circuit capacitance can be constructed as silicon capacitors and can be arranged on the front side and/or on the back side of the carrier substrate. In a particularly advantageous embodiment, these silicon capacitors are formed by deep trench technology on the rear side of a common carrier substrate for buffering the supply voltage. The high switching frequency capability allows silicon capacitors with deep trench technology to be used to provide intermediate circuits even in low voltage inverters with voltages below 60V for relatively small powers of a few kilowatts. . By arranging the intermediate circuit capacitances configured as silicon capacitors on a common carrier substrate, a very low inductance connection to the power switching device is possible. Silicon capacitors on the back side of a common carrier substrate can thus be electrically contacted to semiconductor power switches on the front side, for example by means of through contacts through the carrier substrate. A simple electrical contact is also possible if the intermediate circuit capacitances configured as silicon capacitors are arranged laterally on the surface of a common carrier substrate. This allows a structure without through contacts to the carrier substrate.

In a further advantageous embodiment of the power output stage, the monolithic circuit module can be embedded in or arranged on a multilayer printed circuit board. In this embodiment of the power output stage, the capacitors of the intermediate circuit capacitance can be arranged as silicon capacitors on a separate carrier substrate, embedded in a multilayer printed circuit board, similar to monolithic circuit modules, or , can be placed on a multilayer printed circuit board. Alternatively, the intermediate circuit capacitance capacitor can be configured as a Multi Layer Ceramic Capacitor (MLCC), embedded in a multilayer printed circuit board, or placed on a multilayer printed circuit board. can be done.

In a further advantageous embodiment of the power output stage, two auxiliary switches constructed as gallium nitrite semiconductors can be combined to form a bidirectionally interrupting auxiliary switch, and on the surface of the carrier substrate can be formed into Being configured as a bi-directional blocking auxiliary switch halves the required semiconductor area compared to conventional ARCP modules where two anti-parallel switches are used as auxiliary switches.

In a further advantageous embodiment of the power output stage, the choke coil can be formed coreless as a conductor track on the carrier substrate. This is made possible by the high switching frequency. Complex construction of the choke coil can be avoided as no core material is required. Alternatively, the choke coil can also be constructed coreless as a conductor track on a multilayer printed circuit board of the power output stage. This means that the choke coils as well as the capacitors of the intermediate circuit capacitance can be embedded in or arranged on a multilayer printed circuit board in which the monolithic circuit module is embedded. or that circuit modules are arranged on this multilayer printed circuit board.

In a further advantageous embodiment of the power output stage, the drive circuit may comprise a current control, which controls at least one measurement current representing the corresponding current output current and at least one reference current. as analog signals, compare them with each other, and generate and output at least one corresponding switching signal in response to the comparison. In this case, at least one measurement current is preferably detectable inside the monolithic circuit module. Additionally, the drive circuitry may include a driver stage configured to receive, process, and output at least one switching signal from the current control to the power switching device. High switching frequencies allow other control methods, such as direct switching methods. Accordingly, the current control may include a comparator for each half-bridge of the power switching device, the comparator switching off the corresponding half-bridge when the measured current exceeds the corresponding reference current; It is arranged to switch on the corresponding half-bridge when the measured current falls below the corresponding reference current.

This makes it possible to drive the semiconductor power switches directly via the setpoint setting in the corresponding comparator. Therefore, if the electrical load is a three-phase motor, still only three analog reference signals for the phase currents are sent to the monolithic circuit module. Current control is implemented directly in the monolithic circuit module using comparators. The reference value is compared with the measured value of the phase current. It is switched off when the reference value is exceeded and switched on when it is below. Therefore, on average the desired reference current is generated. To limit the switching frequency, individual comparators can be sampled and/or configured with hysteresis. The digital output signal of the comparator can then be used directly as a switching state command for the individual semiconductor power switches. Each reference signal is an analog signal that directly defines the current in the electrical load or the current in the individual stator windings of a three-phase motor. This signal can be defined by a central controller and includes up to the machine frequency (including explicitly applied harmonics). The degree of freedom for driving the electrical load is still located in the controller, but the fast current dynamics are shifted to the monolithic circuit module, thereby significantly reducing the dynamics and computational performance demands of the controller. can provide cost advantages. At the same time, a fast hardware comparator provides very dynamic current control with a wide bandwidth, which compensates for the increased actuator bandwidth caused by increased switching frequency. can also be used cost-effectively. If the current control were still implemented in the controller, increasing the bandwidth of the current control would automatically require a more sophisticated controller causing additional costs.

In a further advantageous embodiment of the power output stage, the monolithic circuit module may include an electrical interface configured to receive signals from external components and/or assemblies. In this case, the electrical interface can receive the supply voltage potential, the ground potential and at least one reference current.

In a further advantageous embodiment of the power output stage, the power switching device can be configured as a B6 inverter with, for example, three half-bridges. In this case, the cooling surface of the B6 inverter can be connected to ground either directly or via at least one coupling capacitor with a predetermined capacitance.

In an advantageous embodiment of the device for supplying energy to an electrical load, the electrical interface is arranged to receive the supply voltage potential and the ground potential of the energy supply and at least one reference current of the control device. be able to.

In a further advantageous embodiment of the device for supplying energy to an electrical load, the electrical load can be configured as a 3-phase brushless DC motor, the half-bridges of the B6 inverters being respectively connected to each of the 3-phase brushless DC motors. phase can be connected.

In an advantageous embodiment of the method, the delay time span can be specified by an adaptive delay chain that can be defined by the number of delay steps with the same time span. In this case, the number of delay steps in the delay time span can be increased by one if the dead time measurement reaches a predetermined stop value or maximum dead time span. If the dead time measurement does not reach the predetermined minimum dead time span, the number of delay steps in the delay time span can be decreased by one. Otherwise, the number of delay steps in the delay time span can remain the same.

Additionally or alternatively, the delay time span can be determined by an integrated current measurement. In this case, after the first auxiliary switch or the second auxiliary switch is switched on, the time measurement for determining the delay time span and the measurement of the current are performed by the two semiconductor power switches of at least one half-bridge. can be activated by a corresponding semiconductor power switch of the and the measured current can be compared to a predetermined threshold. When the measured current exceeds a predetermined threshold, the time measurement can be stopped and the measurement result defined as the elapsed delay time span.

An embodiment of the invention is illustrated in the drawing and is explained in more detail in the following description. The same reference symbols in the figures indicate components or elements that perform the same or similar functions.

1 is a schematic block diagram of one embodiment of an apparatus according to the invention for supplying energy to an electrical load according to one embodiment of a power output stage according to the invention; FIG. 2 is a schematic circuit diagram of a drive circuit for the half-bridge of the power output stage according to the invention from FIG. 1; FIG. 2 is a schematic circuit diagram of an ARCP module for the half-bridge of the power output stage according to the invention from FIG. 1; FIG. 2 is a schematic perspective view of the power output stage from FIG. 1 configured as a monolithic circuit module; FIG. 2 is a schematic flow chart of a first embodiment of the method according to the invention for determining the voltage-free switching instants for the power output stage according to the invention from FIG. 1; 2 is a schematic flow chart of a second embodiment of the method according to the invention for determining the voltage-free switching instants for the power output stage according to the invention from FIG. 1;

Embodiments of the Invention As can be seen from FIG. 1, the illustrated embodiments of the device 1 according to the invention for supplying energy to an electrical load 3 respectively comprise an energy supply 5, a control device 7 and a device according to the invention. and a power output stage 10 .

As can be further seen from FIGS. 1 to 3, the illustrated embodiment of the power output stage 10 according to the invention for the device 1 for supplying energy to an electrical load 3 is based on gallium nitride-on-silicon technology. a power switching device 12 comprising at least one half-bridge 12.1, and a driver circuit 15 for the power switching device 12, configured as a semiconductor power switch T1, T2 of the at least one half-bridge 12.1 is constructed as a gallium nitrite semiconductor on the surface of a carrier substrate SiS. In this case, the drive circuits 15 for at least one half-bridge 12.1 each comprise one ARCP module 16B, which has two auxiliary switches T3, T4 and a choke coil 16.2. , is adapted to switch the semiconductor power switches T1, T2 of the corresponding half-bridge 12.1 at the voltage-free switching instants, the drive circuit 15 measuring the voltage-free switching instants by an integrated current measurement. , and/or configured to determine by an adaptive delay chain.

As can be further seen in particular from FIGS. 1 and 4, the power switching device 12 and the drive circuit 15 are constructed as monolithic circuit modules based on gallium nitride on silicon technology. In this case, at least the individual active components of the monolithic circuit module are arranged on a common carrier substrate SiS.

As can be further seen from FIG. 1, the electrical load 3 in the illustrated embodiment of the device 1 is configured as a three-phase brushless DC motor 3A. The power switching device 12 is configured as a B6 inverter 12A having three half-bridges 12.1, one half-bridge 12.1 of the B6 inverter 12A for each phase U, V, W of the three-phase brushless DC motor 3A. It is connected to the. Coupling Capacitor Further, the cooling surface of the B6 inverter 12A is connected to ground GND either directly or via at least one coupling capacitor with a predetermined capacitance. In alternative embodiments not shown, the power switching device 12 can also have less or more than three half-bridges 12.1. Furthermore, the device 1 for supplying energy to an electrical load 3 can also supply energy to an electrical load 3 other than a three-phase DC motor 3A.

As can be further seen from FIGS. 1 and 4, the capacitors C1, C2 of the intermediate circuit capacitance 14 for buffering the supply voltage UBat in the illustrated embodiment are each arranged on the carrier substrate SiS. Therefore, the intermediate circuit capacitance 14 in the illustrated embodiment is also integrated into the monolithic circuit module.

In a non-illustrated embodiment of the power output stage 10, the monolithic circuit module is embedded in or arranged on a multilayer printed circuit board. In this embodiment the capacitors C1, C2 of the intermediate circuit capacitance 14 are arranged on a separate carrier substrate, embedded in the multilayer printed circuit board or arranged on the multilayer printed circuit board. Alternatively, the capacitors C1, C2 of the intermediate circuit capacitance 14 in this embodiment may be directly embedded in the multi-layer printed circuit board or may be located on the multi-layer printed circuit board. .

As can be further seen from FIGS. 1 and 2, the drive circuit 15 includes a current control 18 which provides at least one measured current Im (U, V, W) and at least one reference current Ir(U, V, W) are received as analog signals and compared with each other to generate at least one corresponding switching signal in response to the comparison. and output. To this end, the current control 18 in the illustrated embodiment comprises a comparator 18.1 for each half-bridge 12.1 of the power switching device 12, which comparator 18.1 outputs the measured current Im (U , V, W) exceeds the corresponding reference current Ir(U,V,W), it switches off the corresponding half-bridge 12.1 and the measured current Im(U,V,W) exceeds the corresponding reference current Ir Below (U, V, W), it is arranged to switch on the corresponding half-bridge 12.1. In the illustrated embodiment of current control 18, comparator 18.1 is clocked by clock signal TS. As can be further seen from FIG. 1, at least one measurement current Im(U, V, W) in the illustrated embodiment is detected inside the monolithic circuit module.

1 and 2, the drive circuit 15 in the illustrated embodiment includes a driver stage 16, which includes a gate driver 16A and a current control 18 or corresponding comparator 18.n. 1 is arranged to receive, process and output at least one switching signal from the power switching device 12 to the two semiconductor power switches T1, T2 of the corresponding half-bridge 12.1.

As can be further seen from FIG. 1, the monolithic circuit module includes an electrical interface 13 configured to receive signals from external components and/or assemblies. In the example shown, the electrical interface 13 receives the supply voltage potential UBat of the energy supply 5 and the ground potential GND and at least one reference current Ir (U, V, W) of the control device 7 . In order to generate at least one reference current Ir(U, V, W), the control device 7 evaluates the output signal of the sensor DWM, which in the example shown is the rotation of the three-phase DC motor 3A. Detect the angle and generate a corresponding output signal.

As can be further seen from FIGS. 1 and 3, the intermediate circuit capacitance 14 in the illustrated embodiment of the power output stage 10 is of split construction and comprises two capacitors C1, C2, the two capacitors C1, C2 C2 are each formed by deep trench technology on the rear side of a common carrier substrate SiS as a silicon capacitor for buffering the supply voltage UBat. In this case, the silicon capacitors C1, C2 are electrically contacted to the power switching device 12B by through-contacts, not shown, through the carrier substrate SiS.

In an alternative embodiment not shown of power output stage 10, the monolithic circuit module is embedded in or arranged on a multilayer printed circuit board. In this embodiment, the capacitors C1, C2 of the intermediate circuit capacitance 14 can be constructed as silicon capacitors on a separate carrier substrate, embedded in the multilayer printed circuit board, or arranged on the multilayer printed circuit board. can do. Alternatively in this embodiment, the capacitors C1, C2 of the intermediate circuit capacitance 14 can be constructed as Multi Layer Ceramic Capacitors (MLCC) and can be directly embedded in a multilayer printed circuit board. or on a multi-layer printed circuit board.

As can be further seen from FIGS. 1 and 3, ARCP module 16 is configured as part of driver stage 16 and is integrated into a monolithic circuit module. For this purpose, two auxiliary switches T3, T4 as gallium nitrite semiconductors are combined into one bi-directional blocking auxiliary switch 16.1 and the semiconductor power of the individual half-bridges 12.1 are combined. It is formed on the surface of the support substrate SiS together with the switches T1 and T2. The choke coil 16.2 is formed coreless as a conductor track on the carrier substrate SiS.

In a non-illustrated alternative embodiment of the power output stage 10, in which the monolithic circuit module is embedded in or arranged on a multilayer printed circuit board, the choke coil 16.2 comprises a multi-layer It is constructed without a core as a conductor track on a printed circuit board.

A first embodiment, shown in FIG. 5, of the method 100 for determining the no-voltage switching instants for the power output stage 10 described above is based on an adaptive delay chain. In this case, the method 100 begins at step S100, for example by starting the vehicle. Then, in step S110, it waits until a switching command for one of the two auxiliary switches T3, T4 is received. Thereafter, in step S120, whether a first switching instruction is received representing, for example, a transition from a first logic state to a second logic state, or, for example, from a second logic state to a first logic state. It is checked whether a second switching command representing a transition has been received. If the first switching instruction is recognized in step S120, the method continues to step S130. If the second switching instruction is recognized in step S120, the method continues to step S230.

In step S130, the first auxiliary switch T3 is switched on or in a conductive state according to the received first switching command. This increases the coil current IL flowing through choke coil 16.2. In step S140, the delay time span TV defined by the number X of delay steps having the same time span is activated to further increase the coil current IL through choke coil 16.2. After the delay time span TV has elapsed, the current IL flowing through the choke coil 16.2 is greater than the corresponding output current Io(U,V,W) and the two semiconductor power switches of the at least one half-bridge 12.1 The corresponding current IT1 through the corresponding semiconductor power switch of T1, T2, here the first semiconductor power switch T1, becomes greater than zero and the node voltage US across the first semiconductor switch T1 is ground. It corresponds to the potential GND. Thus, in step S150, the first semiconductor power switch T1 is switched off or switched off to activate the dead time measurement with a predetermined stop value corresponding to the maximum value of the dead time span TS. This increases the node voltage US across the first semiconductor power switch T1, which is measured in step S160 and compared to the first voltage threshold. This first voltage threshold is, for example, selected to approximately correspond to the supply voltage potential UBat or to be somewhat lower than the supply voltage potential UBat. In step S170, the at least one half-bridge 12 . The other semiconductor power switch of the two semiconductor power switches T1, T2 of 1, here the second semiconductor power switch T2, is switched on or switched into a conductive state to stop the dead time measurement. At switch-on time, the voltage drop across the second semiconductor power switch T2 is ideally equal to zero. Thereby, the second semiconductor power switch T2 is voltage-free and can be losslessly switched into the conductive state or switched on. Further, in step S170, the number of delay steps X of the delay time span VT is incremented by one if the dead time measurement has reached a predetermined stop value or the maximum dead time span TS. If the elapsed time span is less than the minimum value of the dead time span TS, the number of delay steps X of the first delay time span VT1 is reduced by one, otherwise the number of delay steps of the delay time span TV is reduced. The number X of delay steps is kept constant. This means that the delay time span TV is not changed if the duration for which the dead time measurement is stopped is between the minimum and maximum values of the dead time span TS. After the second semiconductor power switch T2 is switched on, the delay time span TV is activated in step S180. After the delay time span TV has elapsed, in step S190 the first auxiliary switch T3, which is switched on, is switched off or switched off. This means that in order to be able to reduce the coil current IL through the choke coil 16.2, the first auxiliary switch T3 is still switched on after the second semiconductor power switch T2 has been switched on. , remains switched on for the duration of the delay time span TV. Method 100 then continues to step S110 to wait for receipt of the next switching command.

In step S230, the second auxiliary switch T4 is switched on or switched to a conductive state according to the received second switching command. This reduces the coil current IL flowing through choke coil 16.2. In step S240, delay time span TV is activated to further reduce coil current IL through choke coil 16.2. After the delay time span TV has elapsed, the current IL flowing through the choke coil 16.2 is greater than the corresponding output current Io(U,V,W) and the two semiconductor power switches of the at least one half-bridge 12.1 The corresponding current IT2 flowing through the corresponding semiconductor power switch of T1, T2, here the second semiconductor power switch T2, is less than zero. Therefore, in step S250, the second semiconductor power switch T2 is switched off or switched to the blocked state, activating the dead time measurement with a predetermined stop value corresponding to the maximum value of the dead time span TS. This reduces the node voltage US across the first semiconductor power switch T1, which is measured in step S260 and compared to the second voltage threshold. This second voltage threshold is, for example, selected to approximately correspond to ground potential GND or to be somewhat higher than ground potential GND. In step S270, the two semiconductor powers of the at least one half-bridge 12.1 are switched off when the measured node voltage US corresponds to a predetermined second voltage threshold or when the dead time measurement reaches a predetermined stop value. The other semiconductor power switch of the switches T1, T2, here the first semiconductor power switch T1, is switched on or switched into a conducting state to stop the dead time measurement. At switch-on time, the voltage drop across the first semiconductor power switch T1 is ideally equal to zero. Thereby, the first semiconductor power switch T1 becomes voltage-free and can be losslessly switched into a conductive state or switched on. Additionally, in step S270, the number X of delay steps in the delay time span VT is increased by one if the dead time measurement has reached a predetermined stop value. If the elapsed time span is less than the minimum value of the dead time span TS, the number of delay steps X of the first delay time span VT1 is reduced by one, otherwise the number of delay steps of the delay time span TV is reduced. The number X of delay steps is kept constant. This means that the delay time span TV is not changed if the duration for which the dead time measurement is stopped is between the minimum and maximum values of the dead time span TS. After the first semiconductor power switch T1 is switched on, the delay time span TV is activated in step S280. After the delay time span TV has elapsed, in step S290 the second auxiliary switch T4, which has been switched on, is switched off. This means that the second auxiliary switch T4 remains switched on for the duration of the delay time span TV even after the first semiconductor power switch T1 has been switched on. . Method 100 then continues to step S110 to wait for receipt of the next switching command.

A second embodiment, shown in FIG. 6, of the method 200 for determining the voltage-free switching instants of the power output stage 10 described above is based on integrated current measurements. In this case, the method 200 begins at step S300, for example by starting the vehicle. Then, in step S310, it waits until a switching command for one of the two auxiliary switches is received. Thereafter, in step S320, whether a first switching instruction is received representing, for example, a transition from a first logic state to a second logic state; It is checked whether a second switching command representing a transition has been received. If the first switching instruction is recognized in step S320, the method continues to step S330. If the second switching instruction is recognized in step S320, the method continues to step S430.

In step S330, the first auxiliary switch T3 is switched on or switched into a conducting state in response to the received first switching command, and a time measurement for determining the delay time span TV is activated or initiated. . This increases the coil current IL through the choke coil 16.2 and in step S340 the corresponding semiconductor power switch of the two semiconductor power switches T1, T2 of the at least one half-bridge 12.1, here the second A current IT1 flowing through one semiconductor power switch T1 is measured. In step S350, when the current IT1 through the first semiconductor power switch T1 exceeds a predetermined current threshold, the first semiconductor power switch T1 is switched off or cut off, corresponding to the maximum value of the dead time span TS. A dead time measurement having a predetermined stop value of 0 is activated to stop the time measurement and the measurement result is defined as the elapsed delay time span VT. This means that the current IL flowing through the choke coil 16.2 is greater than the corresponding output current Io(U,V,W) and the node voltage US across the first semiconductor switch T1 is reduced to the ground potential GND. means that it is approximately equivalent to In step S360, the node voltage US across the first semiconductor power switch T1 is measured and compared to a first voltage threshold, which corresponds, for example, approximately to the supply voltage potential UBat. , or is chosen to be somewhat lower than the supply voltage potential UBat. In step S370 the two semiconductor powers of the at least one half-bridge 12.1 are switched off when the measured node voltage US corresponds to a predetermined first voltage threshold or when the dead time measurement reaches a predetermined stop value. The other semiconductor power switch of the switches T1, T2, here the second semiconductor power switch T2, is switched on or switched into a conducting state to stop the dead time measurement. At switch-on time, the voltage drop across the second semiconductor power switch T2 is ideally equal to zero. Thereby, the second semiconductor power switch T2 is voltage-free and can be losslessly switched into the conductive state or switched on. After the second semiconductor power switch T2 is switched on, in step S380 the delay time span TV specified by the time measurement is activated. After the delay time span TV has elapsed, in step S390 the first auxiliary switch T3 which is switched on is switched off or switched off. This means that in order to be able to reduce the coil current IL through the choke coil 16.2, the first auxiliary switch T3 is still switched on after the second semiconductor power switch T2 has been switched on. , remains switched on for the duration of the delay time span TV. The method 200 then continues to step S310 to await receipt of the next switching command.

In step S430, the second auxiliary switch T4 is switched on or switched into a conductive state in response to the received second switching command to activate or initiate a time measurement for determining the delay time span TV. . This reduces the coil current IL through the choke coil 16.2 and in step S440 the corresponding semiconductor power switch of the two semiconductor power switches T1, T2 of the at least one half-bridge 12.1, here the second 2, the current through the semiconductor power switch T2 is measured. In step S450, when the current through the second semiconductor power switch T2 exceeds a predetermined current threshold, the second semiconductor power switch T2 is switched off or cut off, corresponding to the maximum value of the dead time span TS. A dead time measurement with a predetermined stop value is activated to stop time measurement and the measurement result is defined as the elapsed delay time span VT. This means that the current IL through the choke coil 16.2 is greater than the corresponding output current Io(U,V,W). In step S460, the node voltage US across the first semiconductor power switch T1 is measured and compared to a second voltage threshold, which, for example, approximately corresponds to the ground potential GND. Alternatively, it is selected to be somewhat higher than the ground potential GND. In step S470, the two semiconductor powers of the at least one half-bridge 12.1 are switched off when the measured node voltage US corresponds to a predetermined second voltage threshold or when the dead time measurement reaches a predetermined stop value. The other semiconductor power switch of the switches T1, T2, here the first semiconductor power switch T1, is switched on or switched into a conductive state. At switch-on time, the voltage drop across the first semiconductor power switch T1 is ideally equal to zero. Thereby, the first semiconductor power switch T1 becomes voltage-free and can be losslessly switched into a conductive state or switched on. After the first semiconductor power switch T1 is switched on, in step S480 the delay time span TV specified by the time measurement is activated. After the delay time span TV has elapsed, in step S490 the second auxiliary switch T4, which has been switched on, is switched off or switched off. This means that the second auxiliary switch T4 remains switched on for the duration of the delay time span TV even after the first semiconductor power switch T1 has been switched on. . The method 200 then continues to step S310 to await receipt of the next switching command.

The delay time span VT can be implemented, for example, by a connected shift register. Dead time span TS can be implemented, for example, by a monostable multivibrator.

The two described embodiments of the method can in principle be implemented in NMOS logic. The first embodiment of method 100 is less sensitive to parameter variations due to its adaptive nature, but requires more logic elements overall than the second embodiment of method 200 . However, the second embodiment of method 200 can only be used if the current measurements are sufficiently accurate. For example, both methods 100, 200 can be combined if current measurements alone are not sufficiently accurate, but can still be used to aid or verify adaptive delay chain settings. .

Claims (20)

A power output stage (10) for a device (1) for supplying energy to an electrical load (3), comprising:
The power output stage (10) comprises a power switching device (12) comprising at least one half-bridge (12.1) constructed based on gallium nitride on silicon technology, and said power switching device (12) and a drive circuit (15) for
the semiconductor power switches (T1, T2) of the at least one half-bridge (12.1) are constructed as gallium nitrite semiconductors on the surface of a carrier substrate (SiS),
In the power output stage (10),
said driving circuits (15) for said at least one half-bridge (12.1) each comprising one ARCP module (16B);
The ARCP module (16B) has two auxiliary switches (T3, T4) and a choke coil (16.2) which, at voltage-free switching instants, allows the semiconductor power of the corresponding half-bridge (12.1) to configured to switch the switches (T1, T2),
Power output stage, characterized in that the drive circuit (15) is arranged to determine the voltage-free switching instant by an integrated current measurement and/or by an adaptive delay chain. (10). said power switching device (12) and said drive circuit (15) being constructed as a monolithic circuit module based on said gallium nitride on silicon technology,
at least the individual active elements of said monolithic circuit module are arranged on a common support substrate (SiS);
A power output stage (10) according to claim 1. the capacitors (C1, C2) of the intermediate circuit capacitance (14) are constructed as silicon capacitors and are arranged on the front side and/or on the back side of the carrier substrate (SiS),
A power output stage (10) according to claim 1 or 2. wherein the monolithic circuit module is embedded in a multilayer printed circuit board or disposed on the multilayer printed circuit board;
A power output stage (10) according to claim 2 or 3. The capacitors (C1, C2) of the intermediate circuit capacitance (14) are constructed as silicon capacitors on a separate carrier substrate or as multilayer ceramic chip capacitors and are embedded in the multilayer printed circuit board or located on the printed circuit board,
A power output stage (10) according to claim 4. Said two auxiliary switches (T3, T4) constructed as gallium nitrite semiconductors are combined into one bi-directional blocking auxiliary switch (16.1), said support substrate (SiS) formed on the surface of
A power output stage (10) according to any one of the preceding claims. the choke coil (16.2) is formed coreless as a conductor track on the carrier substrate (SiS),
A power output stage (10) according to any one of the preceding claims. The choke coil (16.2) is formed coreless as a conductor track of the multilayer printed circuit board,
A power output stage (10) according to any one of claims 4 to 6. said drive circuit (15) comprising a current control (18),
Said current control (18) comprises at least one measurement current (Im(U,V,W)) representing a corresponding current output current (Io(U,V,W)) and at least one reference current (Ir (U, V, W)) as analog signals, compare them with each other, and generate and output at least one corresponding switching signal in response to the comparison.
A power output stage (10) according to any one of the preceding claims. the at least one measured current (Im(U,V,W)) is detectable inside the monolithic circuit module;
Power output stage (10) according to claim 9. said current control (18) comprising a comparator (18.1) for each of said half-bridges (12.1) of said power switching device (12);
The comparator (18.1) selects the corresponding half-bridge (12 .1) and when the measured current (Im(U,V,W)) falls below the corresponding reference current (Ir(U,V,W)), the corresponding half-bridge (12.1 ) is configured to switch on the
Power output stage (10) according to claim 9 or 10. The drive circuit (15) comprises a driver stage (16),
said driver stage (16) is configured to receive, process and output said at least one switching signal from said current control (18) to said power switching device (12);
A power output stage (10) according to any one of claims 9 to 11. the monolithic circuit module includes an electrical interface (13) configured to receive signals from external components and/or assemblies;
A power output stage (10) according to any one of the preceding claims. said power switching device (12) is configured as a B6 inverter (12A) with three half-bridges (12.1),
A power output stage (10) according to any one of the preceding claims. A device (1) for supplying energy to an electrical load (3), comprising an energy supply (5), a control device (7) and a power output stage (10), comprising:
The power output stage (10) is configured like the power output stage (10) according to any one of claims 1 to 14,
A device (1), characterized in that: An electrical interface (13) connects the supply voltage potential (UBat) and ground potential (GND) of the energy supply (5) and at least one reference current (Ir(U,V,W) of the controller (7) ) and configured to receive
Device (1) according to claim 15. The electric load (3) is configured as a three-phase brushless DC motor (3A),
A half-bridge (12.1) of a B6 inverter (12A) is connectable to each phase (U, V, W) of said three-phase brushless DC motor (3A) respectively,
Device (1) according to claim 15 or 16. Method (100, 200) for determining voltage-free switching instants for a power output stage (10) configured like the power output stage (10) according to any one of claims 1 to 14 and
The method (100, 200) comprises:
receiving a switching command and switching on a first auxiliary switch (T3) or a second auxiliary switch (T4) depending on said switching command received;
identifying and activating a delay time span (TV);
switching off the corresponding semiconductor power switch of the two semiconductor power switches (T1, T2) of the at least one half-bridge (12.1) and after said delay time span (TV) has elapsed, a maximum dead time span. activating a dead time measurement with a predetermined stop value equal to (TS);
Measure the node voltage (US) across the first semiconductor power switch (T1) and measure the other of the two semiconductor power switches (T1, T2) of the at least one half-bridge (12.1). switching on the semiconductor power switch;
stopping the dead time measurement when the measured node voltage (US) corresponds to a predetermined voltage threshold or when the dead time measurement reaches the stop value;
has
The auxiliary switches (T3, T4) that are switched on are switched on by the other of the two semiconductor power switches (T1, T2) of the at least one half-bridge (12.1). after being switched on for the duration of said delay time span (VT) and switched off after said delay time span (VT) has elapsed;
method (100, 200). said delay time span (TV) is specified by an adaptive delay chain defined by the number of delay steps (X) having the same time span;
The number of delay steps (X) of the delay time span (VT) is increased by one if the dead time measurement has reached the predetermined stop value or the maximum dead time span (TS). be
the number of delay steps (X) of the delay time span (VT) is reduced by one if the dead time measurement has not reached a predetermined minimum dead time span (TS);
otherwise, the number of delay steps (X) of the delay time span (VT) remains the same.
19. The method (100, 200) of claim 18. the delay time span (TV) is determined by an integrated current measurement;
a time measurement to determine the delay time span (VT) and a current (IT1, IT2) measurement after the first auxiliary switch (T3) or the second auxiliary switch (T4) is switched on; is activated by a corresponding semiconductor power switch of said two semiconductor power switches (T1, T2) of said at least one half-bridge (12.1),
the measured currents (IT1, IT2) are compared with a predetermined threshold,
when the measured currents (IT1, IT2) exceed the predetermined threshold, the time measurement is stopped and the measurement result is defined as the elapsed delay time span (VT);
20. A method (100, 200) according to claim 18 or 19.

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