WO2021248958A1 - 高压互锁装置及其故障检测方法 - Google Patents

高压互锁装置及其故障检测方法 Download PDF

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Publication number
WO2021248958A1
WO2021248958A1 PCT/CN2021/081137 CN2021081137W WO2021248958A1 WO 2021248958 A1 WO2021248958 A1 WO 2021248958A1 CN 2021081137 W CN2021081137 W CN 2021081137W WO 2021248958 A1 WO2021248958 A1 WO 2021248958A1
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Prior art keywords
sampling signal
signal
module
detected
voltage interlock
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PCT/CN2021/081137
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English (en)
French (fr)
Inventor
李伟强
傅焱辉
刘昌鑑
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宁德时代新能源科技股份有限公司
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Priority to JP2022542953A priority Critical patent/JP7324950B2/ja
Priority to KR1020227024427A priority patent/KR20220116252A/ko
Priority to EP21755345.2A priority patent/EP3943956B1/en
Priority to US17/486,993 priority patent/US11366462B2/en
Publication of WO2021248958A1 publication Critical patent/WO2021248958A1/zh

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/327—Testing of circuit interrupters, switches or circuit-breakers
    • G01R31/3271—Testing of circuit interrupters, switches or circuit-breakers of high voltage or medium voltage devices
    • G01R31/3275—Fault detection or status indication
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/327—Testing of circuit interrupters, switches or circuit-breakers
    • G01R31/3277—Testing of circuit interrupters, switches or circuit-breakers of low voltage devices, e.g. domestic or industrial devices, such as motor protections, relays, rotation switches
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B60—VEHICLES IN GENERAL
    • B60L—PROPULSION OF ELECTRICALLY-PROPELLED VEHICLES; SUPPLYING ELECTRIC POWER FOR AUXILIARY EQUIPMENT OF ELECTRICALLY-PROPELLED VEHICLES; ELECTRODYNAMIC BRAKE SYSTEMS FOR VEHICLES IN GENERAL; MAGNETIC SUSPENSION OR LEVITATION FOR VEHICLES; MONITORING OPERATING VARIABLES OF ELECTRICALLY-PROPELLED VEHICLES; ELECTRIC SAFETY DEVICES FOR ELECTRICALLY-PROPELLED VEHICLES
    • B60L3/00—Electric devices on electrically-propelled vehicles for safety purposes; Monitoring operating variables, e.g. speed, deceleration or energy consumption
    • B60L3/0023—Detecting, eliminating, remedying or compensating for drive train abnormalities, e.g. failures within the drive train
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B60—VEHICLES IN GENERAL
    • B60L—PROPULSION OF ELECTRICALLY-PROPELLED VEHICLES; SUPPLYING ELECTRIC POWER FOR AUXILIARY EQUIPMENT OF ELECTRICALLY-PROPELLED VEHICLES; ELECTRODYNAMIC BRAKE SYSTEMS FOR VEHICLES IN GENERAL; MAGNETIC SUSPENSION OR LEVITATION FOR VEHICLES; MONITORING OPERATING VARIABLES OF ELECTRICALLY-PROPELLED VEHICLES; ELECTRIC SAFETY DEVICES FOR ELECTRICALLY-PROPELLED VEHICLES
    • B60L3/00—Electric devices on electrically-propelled vehicles for safety purposes; Monitoring operating variables, e.g. speed, deceleration or energy consumption
    • B60L3/0023—Detecting, eliminating, remedying or compensating for drive train abnormalities, e.g. failures within the drive train
    • B60L3/0069—Detecting, eliminating, remedying or compensating for drive train abnormalities, e.g. failures within the drive train relating to the isolation, e.g. ground fault or leak current
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B60—VEHICLES IN GENERAL
    • B60L—PROPULSION OF ELECTRICALLY-PROPELLED VEHICLES; SUPPLYING ELECTRIC POWER FOR AUXILIARY EQUIPMENT OF ELECTRICALLY-PROPELLED VEHICLES; ELECTRODYNAMIC BRAKE SYSTEMS FOR VEHICLES IN GENERAL; MAGNETIC SUSPENSION OR LEVITATION FOR VEHICLES; MONITORING OPERATING VARIABLES OF ELECTRICALLY-PROPELLED VEHICLES; ELECTRIC SAFETY DEVICES FOR ELECTRICALLY-PROPELLED VEHICLES
    • B60L3/00—Electric devices on electrically-propelled vehicles for safety purposes; Monitoring operating variables, e.g. speed, deceleration or energy consumption
    • B60L3/04—Cutting off the power supply under fault conditions
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
    • G01R19/165—Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
    • G01R19/25—Arrangements for measuring currents or voltages or for indicating presence or sign thereof using digital measurement techniques
    • G01R19/2506—Arrangements for conditioning or analysing measured signals, e.g. for indicating peak values ; Details concerning sampling, digitizing or waveform capturing
    • G01R19/2509—Details concerning sampling, digitizing or waveform capturing
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/005—Testing of electric installations on transport means
    • G01R31/006—Testing of electric installations on transport means on road vehicles, e.g. automobiles or trucks
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/327—Testing of circuit interrupters, switches or circuit-breakers
    • G01R31/3271—Testing of circuit interrupters, switches or circuit-breakers of high voltage or medium voltage devices
    • G01R31/3272—Apparatus, systems or circuits therefor
    • G01R31/3274—Details related to measuring, e.g. sensing, displaying or computing; Measuring of variables related to the contact pieces, e.g. wear, position or resistance
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/50—Testing of electric apparatus, lines, cables or components for short-circuits, continuity, leakage current or incorrect line connections
    • G01R31/52—Testing for short-circuits, leakage current or ground faults
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/50—Testing of electric apparatus, lines, cables or components for short-circuits, continuity, leakage current or incorrect line connections
    • G01R31/54—Testing for continuity
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B23/00—Testing or monitoring of control systems or parts thereof
    • G05B23/02—Electric testing or monitoring
    • G05B23/0205—Electric testing or monitoring by means of a monitoring system capable of detecting and responding to faults
    • G05B23/0218—Electric testing or monitoring by means of a monitoring system capable of detecting and responding to faults characterised by the fault detection method dealing with either existing or incipient faults
    • G05B23/0256—Electric testing or monitoring by means of a monitoring system capable of detecting and responding to faults characterised by the fault detection method dealing with either existing or incipient faults injecting test signals and analyzing monitored process response, e.g. injecting the test signal while interrupting the normal operation of the monitored system; superimposing the test signal onto a control signal during normal operation of the monitored system
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H3/00—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection
    • H02H3/02—Details
    • H02H3/05—Details with means for increasing reliability, e.g. redundancy arrangements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q11/00—Selecting arrangements for multiplex systems
    • H04Q11/0001—Selecting arrangements for multiplex systems using optical switching
    • H04Q11/0005—Switch and router aspects
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B60—VEHICLES IN GENERAL
    • B60Y—INDEXING SCHEME RELATING TO ASPECTS CROSS-CUTTING VEHICLE TECHNOLOGY
    • B60Y2306/00—Other features of vehicle sub-units
    • B60Y2306/15—Failure diagnostics
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q11/00—Selecting arrangements for multiplex systems
    • H04Q11/0001—Selecting arrangements for multiplex systems using optical switching
    • H04Q11/0005—Switch and router aspects
    • H04Q2011/0037—Operation
    • H04Q2011/0039—Electrical control
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
    • H04Q2213/08—Power supply
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02T—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO TRANSPORTATION
    • Y02T10/00—Road transport of goods or passengers
    • Y02T10/60—Other road transportation technologies with climate change mitigation effect
    • Y02T10/70—Energy storage systems for electromobility, e.g. batteries

Definitions

  • This application relates to the field of battery technology, in particular to a high-voltage interlock device and a fault detection method thereof.
  • a common high-voltage circuit safety monitoring system is a high-voltage interlock device, which is mainly used to monitor the high-voltage components of electric vehicles, such as high-voltage connectors, manual maintenance switches (Manual Service Disconnect, MSD), or high-voltage power supply equipment and other high-voltage components.
  • MSD Manual Service Disconnect
  • the vehicle controller decides whether to disconnect the high-voltage circuit and keep the vehicle in a safe state.
  • the signals collected at both ends of the high-voltage component are directly input to the fault detection device.
  • the fault detection device may be directly lost, and the safety of the high-voltage interlock device cannot be guaranteed.
  • the high-voltage interlock device and its fault detection method provided in the embodiments of the present application can avoid damage to the controller by a large external voltage, so as to improve the safety of the high-voltage interlock device.
  • an embodiment of the present application provides a high-voltage interlock device, including: a first signal detection circuit; The second connection end of the first signal detection circuit is connected to one end of the first switch module, and the output end of the first signal detection circuit is connected to the fault diagnosis module.
  • the first original electrical signal is collected from the high-voltage interlock component to be detected, and the first original electrical signal is converted into the first sampling signal;
  • the second signal detection circuit the first connection end of the second signal detection circuit and the to-be-detected The other end of the high-voltage interlock component is connected, the second connection end of the second signal detection circuit is connected to one end of the second switch module, the output end of the second signal detection circuit is connected to the fault diagnosis module, and the second signal detection circuit is used for Under the premise of ensuring that the high-voltage interlock component to be tested is isolated from the fault diagnosis module, collect the second original electrical signal from the high-voltage interlock component to be tested, and convert the second original electrical signal into a second sampling signal;
  • the first switch module The other end of the first switch module is connected to the first power terminal;
  • the second switch module the other end of the second switch module is connected to the second power terminal;
  • the fault diagnosis module is used for at least one of the first switch module and the second switch module In the case of one of
  • an embodiment of the present application provides a fault detection method for a high-voltage interlock device, including: acquiring a first sampling signal and a first sampling signal when at least one of the first switching module and the second switching module is in a disconnected state Two sampling signals; according to the first sampling signal and the second sampling signal, it is determined that the high-voltage interlock component to be detected is faulty.
  • the high-voltage interlock device since the high-voltage interlock device includes a first signal detection circuit and a second signal detection circuit, and the first signal detection circuit and the second signal detection circuit are Under the premise that the high-voltage interlock component to be detected is isolated from the fault diagnosis module, the electrical signal at the end of the high-voltage interlock component to be detected can be converted into the electrical signal to be detected, and the electrical signal to be detected can be transmitted to the fault diagnosis module , So that the fault diagnosis module performs fault detection on the high-voltage interlock component to be detected based on the electrical signal to be detected.
  • the diagnosis modules are separated to avoid damage to the fault diagnosis module by the target electrical signal output by the high-voltage interlock component to be tested, and the safety of the high-voltage interlock device is improved.
  • Figure 1 is a schematic structural diagram of a high-voltage interlocking device provided by an embodiment of the present application
  • Figure 2 is a schematic structural diagram of an exemplary high-voltage interlocking device provided by an embodiment of the present application
  • Fig. 3 is a schematic structural diagram of an exemplary second switch module provided by an embodiment of the present application.
  • FIG. 4 is a schematic structural diagram of another high-voltage interlocking device provided by an embodiment of the present application.
  • FIG. 5A is an exemplary waveform diagram of the first sampling signal and the second sampling signal corresponding to the high-voltage interlock component G to be detected in a normal state provided by an embodiment of the present application;
  • FIG. 5B is a waveform diagram of the first sampling signal and the second sampling signal corresponding to an exemplary high-voltage interlocking component G to be detected with a short power supply failure provided by an embodiment of the present application;
  • FIG. 5C is a waveform diagram of the first sampling signal and the second sampling signal corresponding to an exemplary high-voltage interlock component G to be detected with an open-circuit fault in an embodiment of the present application;
  • FIG. 5D is a waveform diagram of the first sampling signal and the second sampling signal corresponding to an exemplary high-voltage interlocking component G to be detected with a short ground fault according to an embodiment of the present application;
  • Fig. 6A is an exemplary waveform diagram of the first sampling signal, the second sampling signal, and the third sampling signal corresponding to the high-voltage interlock component G to be detected in a normal state provided by an embodiment of the present application;
  • FIG. 6B is an exemplary waveform diagram of the first sampling signal, the second sampling signal, and the third sampling signal corresponding to the high-voltage interlocking component G to be detected with a short power supply failure according to an embodiment of the present application;
  • FIG. 6C is a waveform diagram of the first sampling signal, the second sampling signal, and the third sampling signal corresponding to an exemplary high-voltage interlocking component G to be detected with a short ground fault according to an embodiment of the present application;
  • 6D is an exemplary waveform diagram of the first sampling signal, the second sampling signal, and the third sampling signal corresponding to the high-voltage interlock component G to be detected with an open-circuit fault in an embodiment of the present application;
  • FIG. 7A is an exemplary waveform diagram of the first sampling signal, the second sampling signal, the third sampling signal, and the fourth sampling signal corresponding to the high-voltage interlock component G to be detected in a normal state provided by an embodiment of the present application ;
  • FIG. 7B is a waveform diagram of the first sampling signal, the second sampling signal, the third sampling signal, and the fourth sampling signal corresponding to an exemplary high-voltage interlocking component G to be detected with a short power supply failure provided by an embodiment of the present application ;
  • FIG. 7C is a waveform diagram of the first sampling signal, the second sampling signal, the third sampling signal, and the fourth sampling signal corresponding to an exemplary high-voltage interlocking component G to be detected with a short ground fault provided by an embodiment of the present application ;
  • FIG. 7D is an exemplary waveform diagram of the first sampling signal, the second sampling signal, the third sampling signal, and the fourth sampling signal corresponding to the high-voltage interlock component G to be detected with an open-circuit fault in the embodiment of the present application;
  • FIG. 8 is a schematic flowchart of a high-voltage interlocking method provided by an embodiment of the present application.
  • the embodiments of the present application provide a high-voltage interlock device and a detection method thereof, which are suitable for specific scenarios of fault detection of high-voltage devices.
  • the high-voltage interlock component to be tested if the high-voltage interlock component to be tested has no fault, that is, the high-voltage interlock component to be tested is in a normal state. If there is a fault in the high-voltage interlock component to be detected, the fault type of the high-voltage interlock component to be detected may specifically include a short power supply fault, a short ground fault, and an open circuit fault.
  • the short power supply failure means that either or both ends of the high-voltage interlock component to be detected are short-circuited with the power supply, and the short-circuited power supply may be an unknown power supply.
  • Short ground fault means that either one or both ends of the high-voltage interlocking component to be tested are short-grounded.
  • An open circuit fault means that the interior of the high-voltage interlock component to be detected is always in a disconnected state, that is to say, the interior of the high-voltage interlock component to be detected is always in an electrically disconnected state.
  • Fig. 1 is a schematic structural diagram of a high-voltage interlocking device provided by an embodiment of the present application.
  • the high-voltage interlocking device in the embodiment of the present application can be implemented as a high-voltage interlocking circuit, or it can also be another structure that can realize the function of the high-voltage interlocking device of the embodiment of the present application, which is not specific. limited.
  • the high-voltage interlock device includes a first signal detection circuit, a second signal detection circuit 12, a first switch module S1, a second switch module S2, and a fault diagnosis module 13.
  • a first signal detection circuit connected to a first end 11 to one end of the interlocking member T to be detected G in the high-pressure connection, a first signal detection circuit connected to a second end 11 connected to one end of the first switching means S1, the first detection signal
  • the output terminal of the circuit 11 is connected with the fault diagnosis module 13.
  • the first signal detection circuit 11 is used to collect the first original electrical signal from the high-voltage interlock component G to be detected under the premise of ensuring that the high-voltage interlock component G to be detected is isolated from the fault diagnosis module 13 and combine the first original electrical signal Converted to the first sampled signal.
  • the second signal detection circuit 12 is used to collect a second original electrical signal from the high-voltage interlock component G to be detected under the premise of ensuring that the high-voltage interlock component G to be detected is isolated from the fault diagnosis module 13 and combine the second original electrical signal Converted to the second sampling signal.
  • the other end of the first switch module S1 is connected to the first power supply terminal VCC1.
  • the voltage of the first power supply terminal VCC1 is less than or equal to the voltage of the low-voltage power supply in the vehicle.
  • the first power terminal VCC1 may be a battery such as a lead-acid battery or a lithium battery of the entire vehicle, which is not specifically limited.
  • the other end of the second switch module S2 is connected to the second power terminal VCC2.
  • the second power supply terminal VCC2 please refer to the related description of the first power supply terminal VCC1.
  • the voltages of the first power supply terminal VCC1 and the second power supply terminal VCC2 can be the same.
  • the same power supply can be used or different power supplies can be used. limited.
  • the fault diagnosis module 13 is used to determine the to-be-detected high-voltage interlock component G according to the first sampling signal and/or the second sampling signal when at least one of the first switch module S1 and the second switch module S2 is disconnected Fault.
  • the high-voltage interlock device since the high-voltage interlock device includes a first signal detection circuit and a second signal detection circuit, and the first signal detection circuit and the second signal detection circuit are guaranteed to be Under the premise that the detection high-voltage interlock component is isolated from the fault diagnosis module, the electrical signal at the end of the high-voltage interlock component to be detected can be converted into the electrical signal to be detected, and the electrical signal to be detected can be transmitted to the fault diagnosis module for failure
  • the diagnostic module performs fault detection on the high-voltage interlock component to be tested based on the electrical signal to be detected.
  • FIG. 2 is a schematic structural diagram of an exemplary high-voltage interlocking device provided by an embodiment of the present application.
  • the first signal detection circuit 11 includes a third switch module Q1, a first resistance module R1, a second resistance module R2, and a third resistance module R3.
  • the third switch module Q1 includes a first drive unit M1 and a first switch unit K1 that are arranged in isolation.
  • the first driving unit M1 and the first switch unit K1 are arranged in isolation, which means that there is no direct electrical connection between the two.
  • the first resistor module R3 may include one or more resistors connected in parallel, in series, or in series.
  • P 1 and the other end connected to the second terminal of the first signal detection circuit 11 of the first driving unit K1, and the other end P 1 of the first driving unit K1 are also module end of the first resistor R1, the second resistor R2 of the module Connect at the other end.
  • the second reference potential may be provided by the second ground terminal GND2.
  • One end P 3 of the first switch unit K1 is connected to the fault diagnosis module 13, and one end P 3 of the first switch unit K1 serves as the output end of the first signal detection circuit 11.
  • One end of the first switching unit K1 P 3 is also connected with the third block R3 VCC3 supply terminal through a third resistor.
  • the other end of the first switching unit K1 is P 4 is connected to the first reference potential of the bit.
  • the first reference potential may be provided by the first ground terminal GND1.
  • the voltage output from the third power terminal VCC3 is less than the voltage output from the first power terminal VCC1. If the first power supply terminal VCC1 is a low-voltage power supply for the vehicle, such as a lead-acid battery.
  • the value range of the third power supply terminal VCC3 can be (0,12V) and (0,24V), respectively.
  • the voltage of the third power terminal VCC3 may be 5V.
  • the first driving unit M1 may convert the electrical signals at both ends of the first driving unit M1 into other forms of signals in addition to the electrical signals, and transmit the other forms of signals to the first switch unit K1.
  • the first switch unit K1 responds to other forms of signals and converts them into electrical signals.
  • a first driving unit M1 can be provided with unidirectional continuity, when the end of the first driving unit M1 P 2 voltage greater than the voltage. 1 P M1 and the other end of the first drive unit, a first driving unit driving the first switching unit M1 may K1 Conduction.
  • K1 when the first switch unit is turned on can be collected from the other end of the first switch unit K1 is P 1 to a low level signal, when the second switching unit K1 is turned off, from the other end P of the first switching unit K1 1 Collect a high-level signal.
  • a high level signal and low level signal is a relative term, the first switch unit is turned on and the other end K1 of the first switching unit K1 P 1 and a first voltage switching unit switches off the first guide K1 the other end of the P-K1 cell voltage compared to a high voltage value is high-level signal.
  • the first driving unit M1 may include a light-emitting element capable of converting an electric signal into an optical signal, such as a light-emitting diode.
  • the cathode of the light emitting diode serves as the other end P 1 of the first driving unit M1, and the anode of the light emitting diode serves as one end P 2 of the first driving unit M1.
  • the first switch unit K1 may include an optical switch that converts an optical signal into an electrical signal, such as a photodiode, a phototransistor, a photoelectric metal oxide semiconductor field effect transistor (Metal Oxide Semiconductor, MOS), and the like.
  • suitable first driving unit M1 and first switching unit K1 can be selected according to the work scenario and work requirements, and the specific implementation manner of the first driving unit M1 and the first switching unit K1 is not limited.
  • the first resistance module R1 may include one or more resistors connected in parallel, series, or hybrid connection. Specifically, one end of the first resistance module R1 is also connected to the other end of the second resistance module R2, and the other end of the first resistance module R1 is connected to the second reference potential. Exemplarily, as shown in FIG. 2, the second reference potential may be provided by the second ground terminal GND2.
  • the second resistance module R2 and the third resistance module R3 may include one or more resistors connected in parallel, series, or hybrid connection.
  • the first signal detection circuit 11 further includes a seventh resistance module.
  • the seventh resistance module is disposed between the first power terminal VCC1 and the first switch module S1.
  • FIG. 4 is a schematic structural diagram of another high-voltage interlocking device provided by an embodiment of the present application.
  • the seventh resistance module can be represented as R7 in FIG. 3. Wherein, the seventh resistance module R7 may include at least one resistance.
  • the seventh resistance module R7 has a current limiting function, which can prevent the third switch module Q1 and the fourth switch module Q2 from being damaged by overcurrent. It should be noted that other resistance modules in the embodiments of the present application also have a current limiting function, and can also prevent the third switch module Q1 and the fourth switch module Q2 from being damaged by overcurrent.
  • the first signal detection circuit 11 further includes a first anti-reverse module.
  • the input end of the first anti-reverse module is connected to the first power terminal, and the output end of the first anti-reverse module is connected to one end of the first switch module S1.
  • the first anti-reverse module may be specifically implemented as a diode D1.
  • the anode of the diode D1 is used as the input terminal of the first anti-reverse module. If the first signal detection circuit 11 does not include the seventh resistance module R7, the anode of the diode D1 is connected to the first power terminal VCC1.
  • the anode of the diode D1 is connected to the first power terminal VCC1 through the seventh resistance module R7.
  • the cathode of the diode D1 serves as the output terminal of the first anti-reverse module and is connected to the first switch module S1.
  • the positions of the seventh resistance module R7 and the first anti-reverse module can be interchanged, and the positions of the two are not limited.
  • the current in the high-voltage interlock device can be prevented from flowing into the first power terminal VCC1 and causing damage to the first power terminal VCC1.
  • the first signal detection circuit 11 further includes a fifth switch module arranged between the first resistance module R1 and the second resistance module R2.
  • the fifth switch module may be implemented as S3 in FIG. 3. The on-off state of S3 is synchronized with the on-off state of S2.
  • the second signal detection circuit includes a fourth switch module Q′, a fourth resistance module R4, a fifth resistance module R5, and a sixth resistance module R6.
  • the fourth switch module Q2 includes a second drive unit M2 and a second switch unit K2 that are arranged in isolation.
  • the second drive means M2 as a second signal detection circuit connected to a first end 12, the second drive means M2 P 6 further end module connected to one end of the fifth resistor R5.
  • the other end of the second driving unit M2 P 5 as a second signal detection circuit connected to a second end 12, the other end of the second drive means M2 and P 5 are also module end of the fourth resistor R4, the fifth resistor R5 of the module Connect at the other end.
  • One end P 7 of the second switch unit K2 serves as the output end of the second signal detection circuit 12. End of the second switching means K2, P 7 further module is connected via a sixth resistor and the fourth power supply terminal VCC4.
  • the fourth power terminal VCC4 please refer to the related content of the third power terminal VCC2 in the above-mentioned embodiment of the present application, which will not be repeated here.
  • the other end of the second switching unit P 8 K2 is connected to the third reference potential location.
  • the third reference potential may be provided by the third ground terminal GND3.
  • One end of the fourth resistance module R4 is also connected to the other end of the fifth resistance unit R5.
  • Both the fourth resistance module R4 and the fifth resistance unit R5 may include one or more resistors connected in parallel, series, or hybrid connection.
  • the specific content of the fourth resistance module R4 please refer to the related description of the first resistance module R1 in the above-mentioned embodiment of the present application, which will not be repeated here.
  • the specific content of the fifth resistance module R5 please refer to the related description of the second resistance module R2 in the above-mentioned embodiment of the present application, which will not be repeated here.
  • the other end of the fourth resistance mode R4 block is connected to the fourth reference potential.
  • the fourth reference potential may be provided by the fourth ground terminal GND4.
  • the first ground terminal GND1 to the fourth ground terminal GND4 in the embodiment of the present application may be the same ground terminal or different ground terminals, which is not limited.
  • the second signal detection circuit 12 further includes an eighth resistance module.
  • the eighth resistance module is arranged between the second power terminal VCC2 and the second switch module S2.
  • the eighth resistance module can be represented as R8 in FIG. 3.
  • the eighth resistance module R8 may include at least one resistance.
  • the second signal detection circuit 12 further includes a second anti-reverse module.
  • the input end of the second anti-reverse module is connected to the second power supply terminal VCC3, and the output end of the second anti-reverse module is connected to one end of the second switch module S2.
  • the second anti-reverse module may be specifically implemented as a diode D2.
  • the diode D2 please refer to the relevant description of the diode D1 in the above-mentioned embodiment of the present application, which will not be repeated here.
  • the current in the high-voltage interlock device can be prevented from flowing into the first power terminal VCC2 and causing damage to the first power terminal VCC2.
  • the second signal detection circuit 12 further includes a sixth switch module arranged between the fourth resistance module R4 and the fifth resistance module R5.
  • the sixth switch module may be implemented as S4 in FIG. 4.
  • the high-voltage interlock device includes a third switch module and a fourth switch module, and both the third switch module and the fourth switch module include a drive unit and a switch unit that are arranged in isolation. Since the drive unit and the switch unit can convert the electrical signal at one end of the high-voltage interlock component to be detected into the electrical signal to be detected at both ends of the drive unit, and transmit the electrical signal to be detected to the fault diagnosis module for the fault diagnosis module according to the The detection electrical signal performs fault detection on the high-voltage interlock component to be detected.
  • the fault diagnosis module 13 After the introduction of the first signal detection circuit 11 and the second signal detection circuit 12, the following parts of the embodiments of the present application will specifically describe the fault diagnosis module 13.
  • the fault diagnosis module 13 is used to determine whether one end P of the first switch unit K1 of the third switch module Q1 is in the disconnected state of at least one of the first switch module S1 and the second switch module S2.
  • One end of the first sampling signal and second switching elements 3 of K2 / or the fourth switch module Q2 is second sampling signal P 7, high voltage interlock member is determined to be G fault detection.
  • the fault diagnosis module 13 can be specifically implemented as a vehicle control unit (VCU), a motor controller (Motor Control Unit, MCU) or a battery management system (Battery Management System, BMS) or other systems with processing functions or Device.
  • VCU vehicle control unit
  • MCU Motor Controller
  • BMS Battery Management System
  • the high-voltage interlocking device since the high-voltage interlocking device includes a third switch module Q1 and a fourth switch module Q2, and both the third switch module Q1 and the fourth switch module Q2 include an isolated drive unit and Switch unit. Since the drive unit and the switch unit can convert the electrical signal at one end of the high-voltage interlock component to be detected into the electrical signal to be detected at both ends of the drive unit, and transmit the electrical signal to be detected to the fault diagnosis module for the fault diagnosis module according to the The detection electrical signal performs fault detection on the high-voltage interlock component to be detected.
  • the case where at least one of the first switch module S1 and the second switch module S2 is in the off state specifically includes three sub-cases.
  • the first sampling signal and the second sampling signal collected from the high-voltage interlock device shown in FIG. 1 will be described in detail below in combination with the above three sub-conditions and the state of the high-voltage interlock component G to be detected.
  • the first sampling signal and the second sampling signal can be seen in Table 1 below, where the symbol "&" in Table 1 means “and", for example, "S1&S2 disconnected” means the first switch module S1 and the second switch Modules S2 are all disconnected.
  • the high-voltage interlock component G to be tested is in a normal state.
  • the first switch module S1 and the second switch module S2 are both in the disconnected state, at this time, the entire high-voltage interlock device has no current.
  • the first driving unit M1 cannot drive the first switch unit K1 to be turned on.
  • the first sampling signal is a low-level signal.
  • the voltages at both ends of the second driving unit M2 are also equal, and the second switch unit K2 cannot be driven to be turned on, and the second sampling signal is also a low-level signal.
  • the current output by the first power terminal VCC1 has two transmission paths, respectively, the first transmission path: the first power terminal VCC1 ⁇ the first Switch module S1 ⁇ first resistance module R1 ⁇ second reference potential GND2; second transmission path: first power supply terminal VCC1 ⁇ first switch module S1 ⁇ second resistance module R2 ⁇ high-voltage interlock component G to be tested ⁇ fifth The resistance module R5 ⁇ the fourth resistance module R4 ⁇ the fourth reference potential GND4.
  • the end of the first driving unit M1 P 2 is lower than the voltage of the other voltage terminal of the first driving unit M1 P 1, a first driving unit driving the first switching unit M1 K1 can not be turned on, the first sampling signal is high Level signal.
  • the end of the second voltage. 6 P M2 is higher than the second driving unit driving unit M2 in the other end P of the voltage 5, a second driving unit driving the second switching unit M2 may M2 is turned on, the second sampling signal is a low level signal .
  • the current output by the second power supply terminal VCC2 has two transmission paths, respectively, the first transmission path: the second power supply terminal VCC2 ⁇ the second Switch module S2 ⁇ fourth resistance module R4 ⁇ fourth reference potential GND4; second transmission path: second power supply terminal VCC2 ⁇ second switch module S2 ⁇ fifth resistance module R5 ⁇ high-voltage interlock component to be tested G ⁇ second
  • one end of a first drive unit M1 P 2 is higher than the voltage of the first driving unit M1, a first driving unit driving the first switching unit M1 can be turned K1, the first sampling signal is low Level signal.
  • One end of the voltage of the second driving unit M2. 6 P P is lower than the other end of the second drive means M2 voltage 5, the second drive unit drives the second switching unit M2 M2 can not be turned on, the second sampling signal is a high signal .
  • the voltage at both ends of the high-voltage interlock component G to be detected is the voltage V x of the short-circuited power supply
  • the other of the first drive unit M1 P 2 is an end voltage is always higher than the voltage of the P. 1 end of the first driving unit M1
  • the voltage at the other end P of the second drive means M2 6 is always higher than the voltage of one end of the second driving unit P M2.
  • the first switching unit K1 and the second switching unit K2 are always in a conducting state, and the first sampling signal and the second sampling signal are always low-level signals.
  • the short power failure of the high-voltage interlock component G to be detected can be diagnosed based on the first sampling signal and/or the second sampling signal collected when the first switch module S1 and the second switch module S2 are both in the off state.
  • the first sampling signal collected when the first switch module S1 is in the on state and the second switch module S2 is in the off state the short power supply failure of the high-voltage interlock component G to be detected is diagnosed.
  • the second sampling signal collected when the first switch module S1 is in the off state and the second switch module S2 is in the on state the short power failure of the high-voltage interlock component G to be detected is diagnosed.
  • the high-voltage interlock component G to be tested has an open circuit fault.
  • the entire high-voltage interlock device has no current, and the first drive unit M1 cannot drive the first switch unit K1 to be turned on.
  • the first sampling signal is a low-level signal.
  • the second driving unit M2 cannot drive the second switch unit K2 to turn on, and the second sampling signal is also a low-level signal.
  • the transmission path of the current output by the first power terminal VCC1 is the first power terminal VCC1 ⁇ the first switch module S1 ⁇ the first resistance module R1 ⁇
  • the second reference potential is GND2.
  • the current flows through the first signal detection circuit 11, and there is no current in the second signal detection circuit 12.
  • the end of the first driving unit M1 P 2 is lower than the voltage of the other voltage terminal of the first driving unit M1 P 1, a first driving unit driving the first switching unit M1 K1 can not be turned on, the first sampling signal is high Level signal.
  • One end of the second drive means M2 voltage is equal to P 6 P voltage and the other end of the second driving unit 5 M2, M2 can not be the second driving unit driving the second switch unit K2 is turned on, the second sampling signal is also high Signal.
  • the transmission path of the current output by the second power terminal VCC2 is the second power terminal VCC2 ⁇ the second switch module S2 ⁇ the fourth resistance module R4 ⁇
  • the fourth reference potential is GND4.
  • the current flows through the second signal detection circuit 12, and there is no current in the first signal detection circuit 11.
  • the end of the first driving unit M1 P 2 voltage equal to the voltage of the other end of the first drive unit M1 P 1 a first driving unit driving the first switching unit M1 K1 can not be turned on, the first sampling signal is high Flat signal.
  • End of the second driving unit M2 a voltage lower than the other end. 6 P P M2 of the second driving unit 5 of the voltage, a second driving unit driving the second switch M2 can not be turned on unit K2, the same second sampling signal is high Flat signal.
  • the voltage across the high-voltage interlock component G to be detected is the reference potential (ideally regarded as 0)
  • the first drive unit M1 P 2 is an end voltage of the first driving unit M1 is not higher than the voltage of the other end P 1
  • P. 6 is an end voltage of the second driving unit M2 is not higher than the other end P of the second drive means M2 voltage 5
  • the first A driving unit M1 and a second driving unit M2 cannot drive the first switching unit K1 and the second switching unit K2 to conduct, and the first sampling signal and the second sampling signal are high-level signals.
  • the high-voltage interlock device further includes the fifth switch module S3 and/or the sixth switch module S4 as shown in FIG. 4, at least one of the first switch module S1 and the second switch module S2 is disconnected
  • the first sampling signal and the second sampling signal in the three-substance case conform to the above-mentioned FIG. 1, and will not be repeated here.
  • the fault diagnosis module 13 can not only determine that the high-voltage interlock component G to be detected is faulty, but also can detect the specific fault type of the high-voltage interlock component G to be detected.
  • the fault diagnosis module 13 is specifically configured to: if the first switch module S1 and the second switch module S2 are both in the off state, and the first sampling signal and/or the second sampling signal are low-level signals, determine the to-be-detected The high-voltage interlock component has a short power supply failure.
  • the fault diagnosis module 13 is also specifically configured to: if the first switch module S1 is in the on state and the second switch module S2 is in the off state, and the first sampling signal is a low-level signal, determine that the to-be-detected high-voltage interlock component G has occurred Short power supply failure; and, if the second sampling signal is a high level signal, it is determined that the to-be-detected high-voltage interlock component G has a short ground failure or an open circuit failure.
  • the fault diagnosis module 13 is also specifically configured to: if the first switch module S1 is in the off state and the second switch module S2 is in the on state, and the second sampling signal is a low-level signal, determine that the to-be-detected high-voltage interlocking component G has occurred Short power supply failure; and, if the first sampling signal is a high level signal, it is determined that the high-voltage interlock component G to be detected has a short ground failure or an open circuit failure.
  • the fault diagnosis module 13 can also diagnose that the high-voltage interlock component G to be tested is normal. Specifically, referring to Table 1, when one of the first switch module S1 and the second switch module S2 is in the on state and the other is in the off state, if the difference between the first sampling signal and the second sampling signal is If the level is opposite, it is determined that the high-voltage interlock component G to be tested is in a normal state.
  • the high-voltage interlock device may further include a control module.
  • the control module is used to control the on and off of the first switch module S1 and the second switch module S2 according to a preset control strategy.
  • the function of the control module can be realized by the fault diagnosis module.
  • the control module can be specifically implemented as a VCU, MCU or BMS.
  • the preset control strategy includes: controlling the first switch module S1 and the second switch module S2 to be in a disconnected state during the first time period T1. After the first time period T1 is exceeded, the first switch module and the second switch module are controlled to be switched off periodically.
  • a pulse width modulation (Pulse Width Modulation, PWM) signal may be used to control the on and off of the first switch module S1 and the second switch module S2. For example, in the first time period T1, the pulse width modulation signal is not output to the first switch module S1 and the second switch module S2, and after the first time period T1 is exceeded, the pulse width modulation signal is sent to the first switch module S1 and the second switch module S2.
  • PWM Pulse Width Modulation
  • the fault diagnosis module 13 is specifically configured to: determine the high-voltage mutual to be detected according to the duty cycle of the first sampling signal and/or the duty cycle of the second sampling signal.
  • the lock component is faulty.
  • the first sampling signal and the second sampling signal collected under the control of the control module are described in detail.
  • FIG. 5A is an exemplary first sampling signal and second sampling signal corresponding to the high-voltage interlock component G to be detected in a normal state provided by an embodiment of the present application.
  • the waveform diagram of the sampled signal As shown in FIG. 5A, in the first time period T1, both the first sampling signal and the second sampling signal are in a high level state. After the first time period T1 is exceeded, the levels of the first sampling signal and the second sampling signal are opposite, that is, when the first sampling signal is a high-level signal, the second sampling signal is a low-level signal.
  • FIG. 5B is an exemplary first sampling signal and corresponding first sampling signal and Waveform diagram of the second sampled signal. As shown in FIG. 5B, the first sampling signal and the second sampling signal are both low-level signals.
  • FIG. 5C is an exemplary first sampling signal and second sampling signal corresponding to the high-voltage interlock component G to be detected with an open circuit fault in an embodiment of the present application.
  • FIG. 5D is an exemplary first sampling signal and corresponding first sampling signal and Waveform diagram of the second sampled signal. As shown in FIG. 5D, the first sampling signal and the second sampling signal are both high-level signals.
  • the duty cycle of the first sampling signal and the duty cycle of the second sampling signal are both greater than 0 and less than 1.
  • the signal for controlling the first switch module S1 and the second switch module S2 is a PWM signal and the PWM signal applied to the switch module is at a high level, when the switch module is turned on, when the first time period T1 is sufficiently short
  • the duty cycle of the first sampling signal is equal to the duty cycle of the PWM signal applied to the first switch module S1
  • the duty cycle of the second sampling signal is equal to the duty cycle of the PWM signal applied to the second switch module S2. The duty cycle is equal.
  • the PWM signal applied to the switch module is at a high level when the switch module is turned off, it can be approximately considered that the duty cycle of the first sampling signal is the same as the duty cycle of the PWM signal applied to the first switch module S1. Adding to 1, the duty cycle of the second sampling signal and the duty cycle of the PWM signal applied to the second switch module S2 are added to one. If the high-voltage interlock component G to be detected has a short power failure, the duty cycle of the first sampling signal and the duty cycle of the second sampling signal can be considered to be equal to zero in an ideal state. If the high-voltage interlock component G to be detected has an open circuit fault or a short-circuit fault, the duty cycle of the first sampling signal and the duty cycle of the second sampling signal can be considered to be equal to one in an ideal state.
  • the fault diagnosis module 13 can be specifically configured to: if the duty cycle of the first sampling signal is 0, and/or the duty cycle of the second sampling signal is 0, determine that the high-voltage interlock component G to be detected is short. electricity failure.
  • the fault diagnosis module 13 may also be specifically configured to: if the duty cycle of the first sampling signal is 1, and/or the duty cycle of the second sampling signal is 1, determine that the fault G of the high-voltage interlock component to be detected has an open-circuit fault Or it fails briefly.
  • the fault diagnosis module 13 can also determine that the high-voltage interlock component G to be tested is in a normal state.
  • the fault diagnosis module 13 is also used for determining the high-voltage interlock component to be detected if the duty cycle of the first sampling signal is greater than 0 and less than 1, and/or the duty cycle of the second sampling signal is greater than 0 and less than 1. G is in a normal state.
  • the fault diagnosis module 13 may also be specifically configured to: determine the high-voltage interlock component to be detected according to the waveform diagram of the first sampling signal and/or the waveform diagram of the second sampling signal Fault. Please refer to FIGS. 5A to 5C for details, which will not be repeated here.
  • fault diagnosis module 13 in order to improve the diagnostic accuracy of the high voltage interlock device, fault diagnosis module 13 also detects an end of the high voltage interlock member G T 1 to be connected to T to be detected from one end of a high voltage interlock member G collected directly The third sample signal.
  • the fault diagnosis module 13 may be specifically used to: in the case that at least one of the first switch module S1 and the second switch module S2 is in the disconnected state, according to the first sampling signal, the second sampling signal, and the third sampling signal , Determine the failure of the high-voltage interlock component to be detected.
  • the fault diagnosis module 13 can capture the third sampling signal from the sampling point A 1. When the potential of the sampling point A 1 is greater than 0, the third sampling signal is a high-level signal; when the potential of the sampling point A 1 is equal to 0, the third sampling signal is a low-level signal.
  • the output current of the first power supply terminal VCC1 may flow through the sample point A 1-bit second reference potential GND2, and a fourth reference potential of the bit GND4, respectively, the first case
  • the voltage of a power terminal VCC1 can be applied to the sampling point A 1 , and the third sampling signal is a high-level signal.
  • the output current of the second power supply terminal VCC2 may flow through the sample point A 1, respectively, the second reference potential GND2 of bits, the third sampling signal is high at this time Signal.
  • the potential of the sampling point A 1 can be considered to be approximately equal to the potential of one end T 1 of the high-voltage interlock component G to be tested. Since the voltage across the high-voltage interlock component G to be detected is always the voltage V x of the short-circuited power supply, no matter whether the first switch module S1 and the second switch module S2 are turned on or not, the third sampling signal is a high-level signal.
  • the voltage of the first power terminal VCC1 can be applied to the sampling point A 1 , and the third sampling signal is a high-level signal.
  • the voltage of the second power supply terminal VCC2 can be applied to the sampling point A 1 , and the third sampling signal is Low-level signal.
  • the potential of the sampling point A 1 can be considered to be approximately equal to the potential of one end T 1 of the high-voltage interlock component G to be detected. Since the voltage across the high-voltage interlock component G to be detected is the ground voltage, the third sampling signal is a low-level signal regardless of whether the first switch module S1 and the second switch module S2 are turned on.
  • the third sampling signal is a high-level signal.
  • the third sampling signal corresponding to the high-voltage interlock component G that has an open-circuit fault is a high-level signal
  • the high-voltage interlock that has a short-circuit fault is a high-level signal.
  • the third sampling signal corresponding to component G is a low-level signal.
  • the fault diagnosis module 13 is specifically configured to: if the first switch module S1 and the second switch module S2 are both in the off state, the first sampling signal is a low-level signal, and the second sampling signal is a low-level signal or the first If the three-sample signal is a high-level signal, it is determined that the high-voltage interlock component G to be detected has a short power supply failure.
  • the fault diagnosis module 13 is also specifically configured to: if the first switch module S1 is in the on state and the second switch module S2 is in the off state, and the first sampling signal is a low-level signal, determine that the to-be-detected high-voltage interlock component G has occurred Short power failure. And, if the third sampling signal is a low-level signal, it is determined that the to-be-detected high-voltage interlock component G has a short ground fault; and, if the second sampling signal and the third sampling signal are both high-level signals, it is determined that the to-be-detected high-voltage Interlock part G has an open circuit failure.
  • the fault diagnosis module 13 is also specifically configured to: if the first switch module S1 is in the off state and the second switch module S2 is in the on state, and the second sampling signal is a low-level signal, determine that the to-be-detected high-voltage interlocking component G has occurred Short power failure; and, if the first sampling signal is a high-level signal and/or the third sampling signal is a low-level signal, it is determined that the high-voltage interlock component G to be detected has a short-ground failure or an open-circuit failure.
  • the control module controls the first switch module S1 and the second switch module S2 to be turned on and off according to the aforementioned preset control strategy.
  • the fault diagnosis module 13 is specifically configured to determine the high voltage to be detected according to at least one of the duty cycle of the first sampling signal, the duty cycle of the second sampling signal, and the duty cycle of the third sampling signal. Interlock part G is malfunctioning.
  • the third sampling signal collected under the control of the control module is specifically explained.
  • the relevant content of the first sampling signal and the second sampling signal please refer to the specific description of the first sampling signal and the second sampling signal in the above embodiment of the present application in conjunction with FIG. 5A to FIG. 5D, which will not be repeated here.
  • FIG. 6A is an exemplary first sampling signal and second sampling signal corresponding to the high-voltage interlock component G to be detected in a normal state provided by an embodiment of the present application.
  • Waveform diagram of the sampled signal and the third sampled signal As shown in FIG. 6A, in the first time period T1, the third sampling signal is a low-level signal. After the first time period T1 is exceeded, the third sampling signal is a high-level signal.
  • FIG. 6B is an exemplary first sampling signal corresponding to the high-voltage interlock component G to be detected that has a short power supply failure provided by an embodiment of the present application, Waveform diagrams of the second sampling signal and the third sampling signal. As shown in FIG. 6B, the third sampling signal is always a high-level signal.
  • FIG. 6C is an exemplary first sampling signal and the first sampling signal corresponding to the high-voltage interlock component G to be detected with a short-ground fault in an embodiment of the present application.
  • Waveform diagram of the second sample signal and the third sample signal As shown in FIG. 6C, in the first time period T1, the third sampling signal is a low-level signal. After the first time period T1 is exceeded, the third sampling signal is a PWM signal.
  • FIG. 6D is an exemplary first sampling signal and the first sampling signal corresponding to the high-voltage interlock component G to be detected with an open-circuit fault in an embodiment of the present application. Waveform diagram of the second sample signal and the third sample signal. As shown in FIG. 6D, the third sampling signal is always a low-level signal.
  • the duty cycle of the third sampling signal is equal to 1-T1/T0, where T0 is the total duration. If a short power failure occurs in the high-voltage interlock component G to be detected, the duty cycle of the third sampling signal is equal to 1. If a short ground fault occurs in the high-voltage interlock component G to be detected, the duty cycle of the third sampling signal is equal to zero.
  • the signals controlling the first switch module S1 and the second switch module S2 are PWM signals and are applied to the first switch module S1
  • the PWM signal is at a high level
  • the first switch module S1 is turned on, and it can be approximately considered that the duty cycle of the third sampling signal is equal to the duty cycle of the PWM signal applied to the first switch module S1.
  • the first switch module S1 is turned off when the PWM signal applied to the first switch module S1 is at a high level, it can be approximated as the duty cycle of the third sampling signal and the PWM signal applied to the first switch module S1.
  • the duty cycle adds up to 1.
  • the fault diagnosis module 13 may also be specifically used to: if the duty cycle of the third sampling signal is 0, determine The high-voltage interlock component H to be tested has a short power supply failure.
  • the fault diagnosis module 13 may also be specifically configured to: if the duty cycle of the third sampling signal is 0, it is determined that an open-circuit fault has occurred in the fault of the high-voltage interlock component to be detected.
  • the fault diagnosis module 13 may also be specifically configured to: if the duty cycle of the third sampling signal is approximately equal to the duty cycle of the PWM signal applied to the first switch module S1, determine that the fault of the high-voltage interlock component to be detected has an open-circuit fault.
  • the fault diagnosis module 13 can also determine that the high-voltage interlock component G to be tested is in a normal state. Correspondingly, the fault diagnosis module 13 is also used for determining that the high-voltage interlock component G to be detected is in a normal state if the duty cycle of the third sampling signal is equal to 1-T1/T0.
  • the fault diagnosis module 13 is specifically configured to: determine the to-be-detected high voltage interlock according to at least one of the waveform diagram of the first sampling signal, the waveform diagram of the second sampling signal, and the waveform diagram of the third sampling signal Component G is faulty. Reference may be made to FIGS. 6A-6D for details, which will not be repeated here.
  • fault diagnosis module 13 in addition to the high-pressure end of the interlocking member to be detected T 1 of G is connected, but also be detected with the other end of the high voltage interlock member G T 2 is connected to directly collect the fourth sampling signal from the other end T 2 of the high-voltage interlock component G to be tested.
  • the fault diagnosis module 13 may be specifically configured to: when at least one of the first switch module S1 and the second switch module S2 is in the disconnected state, according to the first sampling signal, the second sampling signal, and the third sampling signal And the fourth sampling signal to determine the failure of the high-voltage interlock component G to be detected. Exemplarily, continuing to refer to FIG. 1 and FIG.
  • the fault diagnosis module 13 may collect the fourth sampling signal from the sampling point A 2.
  • the fourth sampling signal is a high-level signal; when the potential of the sampling point A 2 is equal to 0, the fourth sampling signal is a low-level signal.
  • the fourth sampling signal for the specific content of the first sampling signal, the second sampling signal, and the third sampling signal, please refer to the related description in the above-mentioned embodiment of the present application, which will not be repeated here.
  • the following parts of the embodiments of the present application mainly describe the fourth sampling signal in detail in combination with the state of the high-voltage interlock component G to be detected.
  • the fourth sampling signal can be seen in Table 3 below.
  • the voltage of the first power terminal VCC2 cannot be applied to the sampling point A 2 because the high-voltage interlock component G to be detected is always in the off state, and the third sampling signal It is a low-level signal.
  • the voltage of the second power terminal VCC2 can be applied to the sampling point A 2 , and the third sampling signal is a low-level signal.
  • the third sampling signal is a high-level signal.
  • the third sampling signal corresponding to the high-voltage interlock component G that has an open circuit fault to be detected is a high-level signal
  • the high-voltage interlock that has a short-circuit fault to be detected is a high-level signal
  • the third sampling signal corresponding to component G is a low-level signal.
  • the fault diagnosis module 13 is specifically configured to: if the first switch module S1 and the second switch module S2 are both in the off state, the first sampling signal is a low-level signal, the second sampling signal is a low-level signal, and the first sampling signal is a low-level signal. If the third sampling signal is a high-level signal or the fourth sampling signal is a high-level signal, it is determined that the high-voltage interlock component G to be detected has a short power supply failure.
  • the fault diagnosis module 13 is also specifically configured to: if the first switch module S1 is in the on state and the second switch module S2 is in the off state, and the first sampling signal is a low-level signal, determine that the to-be-detected high-voltage interlock component G has occurred Short power failure; and, if the third sampling signal is a low-level signal, it is determined that the high-voltage interlock component G to be detected has a short-term failure; and, if the second sampling signal and the third sampling signal are both high-level signals, Or if the third sampling signal is at a high level and the fourth sampling signal is at a low level, it is determined that the to-be-detected high-voltage interlock component G has an open-circuit fault.
  • the fault diagnosis module 13 is also specifically configured to: if the first switch module S1 is in the off state and the second switch module S2 is in the on state, and the second sampling signal is a low-level signal, determine the high-voltage interlock component G to be detected A short power failure occurs; and, if the fourth sampling signal is a low-level signal, it is determined that the high-voltage interlock component G to be detected has a short-ground failure; and, if the first sampling signal and the fourth sampling signal are both high-level signals , Or if the third sampling signal is a low-level signal and the fourth sampling signal is a high-level signal, it is determined that the to-be-detected high-voltage interlock component G has an open-circuit fault.
  • the control module controls the first switch module S1 and the second switch module S2 to be turned on and off according to the aforementioned preset control strategy.
  • the fault diagnosis module 13 is specifically used for: according to the duty cycle of the first sampling signal, the duty cycle of the second sampling signal, the duty cycle of the third sampling signal, and the duty cycle of the fourth sampling signal. At least one of the high-voltage interlock components G to be detected is determined to be faulty.
  • the fourth sampling signal collected under the control of the control module is specifically explained.
  • the relevant content of the first sampling signal, the second sampling signal, and the third sampling signal please refer to the above-mentioned embodiment of the present application in conjunction with FIGS. The specific description of the three-sampled signal will not be repeated here.
  • FIG. 7A is an exemplary first sampling signal and second sampling signal corresponding to the high-voltage interlock component G to be detected in a normal state provided by an embodiment of the present application. Waveform diagrams of the sampled signal, the third sampled signal, and the fourth sampled signal. As shown in FIG. 7A, in the first time period T1, the fourth sampling signal is a low-level signal. After the first time period T1 is exceeded, the fourth sampling signal is a high-level signal.
  • FIG. 7B is an exemplary first sampling signal corresponding to the high-voltage interlock component G to be detected that has a short power supply failure provided by an embodiment of the present application, Waveform diagrams of the second sampling signal, the third sampling signal, and the fourth sampling signal. As shown in FIG. 7B, the fourth sampling signal is a high-level signal.
  • FIG. 7C is an exemplary first sampling signal and the first sampling signal corresponding to the high-voltage interlock component G to be detected with a short-ground fault in an embodiment of the present application.
  • Waveform diagrams of the second sampling signal, the third sampling signal, and the fourth sampling signal As shown in FIG. 7C, in the first time period T1, the fourth sampling signal is a low-level signal. After the first time period T1 is exceeded, the fourth sampling signal is a PWM signal.
  • FIG. 7D is an exemplary first sampling signal and the first sampling signal corresponding to the high-voltage interlock component G to be detected with an open-circuit fault in an embodiment of the present application. Waveform diagrams of the second sampling signal, the third sampling signal, and the fourth sampling signal. As shown in FIG. 7D, the fourth sampling signal is a low-level signal.
  • the third sampling signal is the same as the third sampling signal described in conjunction with FIGS. 6A-6D in that if the high-voltage interlock component G to be detected is normal, the duty ratio of the fourth sampling signal is equal to 1-T1 /T0, where T0 is the total duration. If a short power failure occurs in the high-voltage interlock component G to be detected, the duty cycle of the third sampling signal is equal to 1. If a short ground fault occurs in the high-voltage interlock component G to be detected, the duty cycle of the third sampling signal is equal to zero.
  • the difference from the third sampling signal described in conjunction with FIGS. 6A to 6D is that if the first time period T1 is exceeded, the level of the third sampling signal is opposite to the level of the fourth sampling signal. Specifically, if an open circuit fault occurs in the high-voltage interlock component G to be detected, when the first time period T1 is sufficiently short, if the signals controlling the first switch module S1 and the second switch module S2 are PWM signals and are applied to the second switch module When the PWM signal on S2 is at a high level, the second switch module S2 is turned on, and it can be approximated that the duty cycle of the fourth sampling signal is equal to the duty cycle of the PWM signal applied to the second switch module S2.
  • the second switch module S2 is turned off when the PWM signal applied to the second switch module S2 is at a high level, it can be approximated as the duty cycle of the fourth sampling signal and the PWM signal applied to the second switch module S2.
  • the duty cycle adds up to 1.
  • the fault diagnosis module 13 is specifically configured to: according to at least one of the waveform diagram of the first sampling signal, the waveform diagram of the second sampling signal, the waveform diagram of the third sampling signal, and the waveform diagram of the fourth sampling signal. Otherwise, it is determined that the high-voltage interlock component G to be detected is faulty. Please refer to FIGS. 7A-7D for details, which will not be repeated here.
  • FIG. 8 is a schematic flowchart of a high-voltage interlocking method provided by an embodiment of the present application. As shown in FIG. 8, the high-voltage interlocking method 800 includes S810 and S820.
  • S820 specifically includes: if both the first switch module S1 and the second switch module S2 are in the off state, and the first sampling signal and/or the second sampling signal are low-level signals, determining The high-voltage interlock component G to be tested has a short power supply failure.
  • the first switch module S1 is in the on state and the second switch module S2 is in the off state, and the first sampling signal is a low-level signal, it is determined that the high-voltage interlock component G to be detected has a short power failure; and, if If the second sampling signal is a high-level signal, it is determined that the high-voltage interlock component to be detected has a short-ground fault or an open-circuit fault.
  • the second sampling signal is a low-level signal
  • the high-voltage interlock component G to be detected has a short power failure
  • the first sampling signal is a high-level signal
  • the to-be-detected high-voltage interlocking component has a short ground fault or an open circuit fault.
  • S820 specifically includes: at least in the first switch module S1 and the second switch module S2 In the case of one of the disconnected states, the failure of the high-voltage interlock component G to be detected is determined based on the first sampling signal, the second sampling signal, and the third sampling signal at one end of the high-voltage interlock component G to be detected.
  • S820 specifically includes: if the first switch module S1 and the second switch module S2 are both in the off state, the first sampling signal is a low-level signal, the second sampling signal is a low-level signal, or the third If the sampling signal is a high-level signal, it is determined that the high-voltage interlock component G to be detected has a short power supply failure.
  • the first switch module S1 is in the on state and the second switch module S2 is in the off state, and the first sampling signal is a low-level signal, it is determined that the high-voltage interlock component G to be detected has a short power failure; and, if If the third sampling signal is a low-level signal, it is determined that the high-voltage interlock component to be detected has a short ground fault; and, if the second sampling signal and the third sampling signal are both high-level signals, it is determined that the high-voltage interlock component to be detected is An open circuit fault has occurred.
  • the second sampling signal is a low-level signal
  • the high-voltage interlock component G to be detected has a short power failure
  • the first sampling signal is a high-level signal and/or the third sampling signal is a low-level signal
  • S820 specifically includes: in the first switch module S1 and the second switch module S2 When at least one of them is disconnected, the high-voltage interlock component G to be detected is determined according to the first sampling signal, the second sampling signal, the third sampling signal, and the fourth sampling signal at the other end of the high-voltage interlock component G to be detected Fault.
  • S820 specifically includes: if the first switch module S1 and the second switch module S2 are both in the off state, the first sampling signal is a low-level signal, the second sampling signal is a low-level signal, and the third If the sampling signal is a high-level signal or the fourth sampling signal is a high-level signal, it is determined that the high-voltage interlock component G to be detected has a short power supply failure.
  • the first switch module S1 is in the on state and the second switch module S2 is in the off state, and the first sampling signal is a low-level signal, it is determined that the high-voltage interlock component G to be detected has a short power failure; and, if If the third sampling signal is a low-level signal, it is determined that the high-voltage interlock component to be detected has a short ground fault; and, if the second sampling signal and the third sampling signal are both high-level, or if the third sampling signal is a high-level If the fourth sampling signal is low and the fourth sampling signal is low, it is determined that the to-be-detected high-voltage interlock component has an open-circuit fault.
  • the second sampling signal is a low-level signal
  • the high-voltage interlock component G to be detected has a short power failure
  • the fourth sampling signal is a low-level signal
  • the high-voltage interlock component to be detected has a short ground fault
  • the first sampling signal and the fourth sampling signal are both high-level signals, or if the third sampling signal is low Level signal and the fourth sampling signal is a high level signal, it is determined that the high-voltage interlock component to be detected has an open-circuit fault.
  • the fault detection method 800 of the high-voltage interlock device further includes: the control module controls the on and off of the first switch module S1 and the second switch module S2 according to a preset control strategy.
  • the preset control strategy includes: controlling the first switch module S1 and the second switch module S2 to be in the off state during the first time period; after the first time period, controlling the first switch module S1 and The second switch module S2 is periodically switched off alternately.
  • S820 specifically includes: determining the failure of the high-voltage interlock component G to be detected according to the duty cycle of the first sampling signal and/or the duty cycle of the second sampling signal.
  • S820 specifically includes: if the duty cycle of the first sampling signal is 0, and/or the duty cycle of the second sampling signal is 0, determining the high-voltage interlock to be detected Component G has a short power failure; if the duty cycle of the first sampling signal is 1, and/or the duty cycle of the second sampling signal is 1, it is determined that the failure of the high-voltage interlock component G to be detected has an open circuit fault or a short ground fault .
  • the functional modules in the foregoing embodiments may be implemented as hardware, software, firmware, or a combination thereof.
  • it can be, for example, an electronic circuit, an application specific integrated circuit (ASIC), appropriate firmware, a plug-in, a function card, and so on.
  • ASIC application specific integrated circuit
  • the elements of this application are programs or code segments used to perform required tasks.
  • the program or code segment may be stored in a machine-readable medium, or transmitted on a transmission medium or a communication link through a data signal carried in a carrier wave.
  • "Machine-readable medium" may include any medium that can store or transmit information.

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Abstract

高压互锁装置及其故障检测方法，高压互锁装置包括：第一信号检测电路（11），用于在保证待检测高压互锁部件（G）与故障诊断模块（13）相隔离的前提下，从待检测高压互锁部件（G）采集第一原始电信号，并转换为第一采样信号；第二信号检测电路（12），用于在保证待检测高压互锁部件（G）与故障诊断模块（13）相隔离的前提下，从待检测高压互锁部件（G）采集第二原始电信号，并转换为第二采样信号；故障诊断模块（13），用于在第一开关模块（S1）和第二开关模块（S2）中至少一者断开状态的情况下，根据第一采样信号和/或第二采样信号，确定待检测高压互锁部件（G）故障。避免了外部大电压对控制器的损坏，可以提高高压互锁装置的安全性。

Description

高压互锁装置及其故障检测方法
相关申请的交叉引用
本申请要求享有于2020年06月12日提交的名称为“高压互锁电路及其故障检测方法”的中国专利申请202010536684.2的优先权，该申请的全部内容通过引用并入本文中。
技术领域
本申请涉及电池技术领域，特别是涉及高压互锁装置及其故障检测方法。
背景技术
随着新能源汽车的快速发展，人们对新能源汽车的安全问题越来越重视。新能源汽车区别与传统汽车最大的不同就是新能源汽车靠高电压和大电流为车提供动力，故高压安全问题在新能源汽车的设计中不可忽略。常见的高压回路的安全监控系统是高压互锁装置，主要用来监控电动汽车各高压部件，例如包括高压连接器，手动维护开关(Manual Service Disconnect，MSD)或高压供电设备等高压部件间的通断情况。根据检测的情况让整车控制器决定是否断开高压回路，让车辆处于安全状态。
现有的检测方案中，将在高压部件两端采集的信号直接输入到故障检测装置。当外部出现大电压时，有可能直接损耗故障检测装置，无法保障高压互锁装置的安全性。
发明内容
本申请实施例提供的高压互锁装置及其故障检测方法，可避免外部大电压对控制器的损坏，以提高高压互锁装置的安全性。
一方面，本申请实施例提供了一种高压互锁装置，包括：第一信号检测电路，第一信号检测电路的第一连接端与待检测高压互锁部件的一端连接，第一信号检测电路的第二连接端与第一开关模块的一端连接，第一信号检测电路的输出端与故障诊断模块连接，第一信号检测电路用于在保证待检测高压互锁部件与故障诊断模块相隔离的前提下，从待检测高压互锁部件采集第一原始电信号，并将第一原始电信号转换为第一采样信号；第二信号检测电路，第二信号检测电路的第一连接端与待检测高压互锁部件的另一端连接，第二信号检测电路的第二连接端与第二开关模块的一端连 接，第二信号检测电路的输出端与故障诊断模块连接，第二信号检测电路用于在保证待检测高压互锁部件与故障诊断模块相隔离的前提下，从待检测高压互锁部件采集第二原始电信号，并将第二原始电信号转换为第二采样信号；第一开关模块，第一开关模块的另一端与第一电源端连接；第二开关模块，第二开关模块的另一端与第二电源端连接；故障诊断模块用于在第一开关模块和第二开关模块中至少一者断开状态的情况下，根据第一采样信号和/或第二采样信号，确定待检测高压互锁部件故障。
另一方面，本申请实施例提供一种高压互锁装置的故障检测方法，包括：在第一开关模块和第二开关模块中至少一者断开状态的情况下，获取第一采样信号和第二采样信号；根据第一采样信号和第二采样信号，确定待检测高压互锁部件故障。
根据本申请实施例中的高压互锁装置及其故障检测方法，由于高压互锁装置包括第一信号检测电路和第二信号检测电路，且第一信号检测电路和第二信号检测电路在保证所述待检测高压互锁部件与所述故障诊断模块相隔离的前提下，能够将待检测高压互锁部件端部的电信号转换为待检测电信号，并将待检测电信号传输至故障诊断模块，以供故障诊断模块根据待检测电信号对待检测高压互锁部件进行故障检测，待检测高压互锁部件与故障诊断模块之间无直接的连接关系，从而能够将待检测高压互锁部件与故障诊断模块相隔离，避免了待检测高压互锁部件输出的目标电信号对故障诊断模块的损坏，提高了高压互锁装置的安全性。
附图说明
为了更清楚地说明本申请实施例的技术方案，下面将对本申请实施例中所需要使用的附图作简单地介绍，显而易见地，下面所描述的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据附图获得其他的附图。
[根据细则91更正 19.04.2021]　
图1是本申请实施例提供的一种高压互锁装置的结构示意图；
图2是本申请实施例提供的一种示例性的高压互锁装置的结构示意图；
图3是本申请实施例提供的一种示例性的第二开关模块的结构示意图；
图4是本申请实施例提供的另一种高压互锁装置的结构示意图；
图5A是本申请实施例提供的一种示例性的处于正常状态下的待检测高压互锁部件G对应的第一采样信号和第二采样信号的波形图；
图5B是本申请实施例提供的一种示例性的出现短电源故障的待检测高压互锁部件G对应的第一采样信号和第二采样信号的波形图；
图5C是本申请实施例提供的一种示例性的出现开路故障的待检测高压互锁部件G对应的第一采样信号和第二采样信号的波形图；
图5D是本申请实施例提供的一种示例性的出现短地故障的待检测高压互锁部件G对应的第一采样信号和第二采样信号的波形图；
图6A是本申请实施例提供的一种示例性的处于正常状态下的待检测高压互锁 部件G对应的第一采样信号、第二采样信号和第三采样信号的波形图；
图6B是本申请实施例提供的一种示例性的出现短电源故障的待检测高压互锁部件G对应的第一采样信号、第二采样信号和第三采样信号的波形图；
图6C是本申请实施例提供的一种示例性的出现短地故障的待检测高压互锁部件G对应的第一采样信号、第二采样信号和第三采样信号的波形图；
图6D是本申请实施例提供的一种示例性的出现开路故障的待检测高压互锁部件G对应的第一采样信号、第二采样信号和第三采样信号的波形图；
图7A是本申请实施例提供的一种示例性的处于正常状态下的待检测高压互锁部件G对应的第一采样信号、第二采样信号、第三采样信号和第四采样信号的波形图；
图7B是本申请实施例提供的一种示例性的出现短电源故障的待检测高压互锁部件G对应的第一采样信号、第二采样信号、第三采样信号和第四采样信号的波形图；
图7C是本申请实施例提供的一种示例性的出现短地故障的待检测高压互锁部件G对应的第一采样信号、第二采样信号、第三采样信号和第四采样信号的波形图；
图7D是本申请实施例提供的一种示例性的出现开路故障的待检测高压互锁部件G对应的第一采样信号、第二采样信号、第三采样信号和第四采样信号的波形图；
图8是本申请实施例提供的一种高压互锁方法的流程示意图；
在附图中，附图并未按照实际的比例绘制。
具体实施方式
下面结合附图和实施例对本申请的实施方式作进一步详细描述。以下实施例的详细描述和附图用于示例性地说明本申请的原理，但不能用来限制本申请的范围，即本申请不限于所描述的实施例。
在本申请的描述中，需要说明的是，除非另有说明，“多个”的含义是两个以上；术语“上”、“下”、“左”、“右”、“内”、“外”等指示的方位或位置关系仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。此外，术语“第一”、“第二”、“第三”等仅用于描述目的，而不能理解为指示或暗示相对重要性。“垂直”并不是严格意义上的垂直，而是在误差允许范围之内。“平行”并不是严格意义上的平行，而是在误差允许范围之内。
下述描述中出现的方位词均为图中示出的方向，并不是对本申请的具体结构进行限定。在本申请的描述中，还需要说明的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是直接相连，也可以通过中间媒介间接相连。对于本领域的普通技术人员而言，可视具体情况理解上述术语在本申请中的具体含义。
本申请实施例提供了一种高压互锁装置及其检测方法，适用于对高压器件进行 故障检测的具体场景中。针对待检测高压互锁部件，如果待检测高压互锁部件无故障，即待检测高压互锁部件处于正常状态。如果待检测高压互锁部件存在故障，待检测高压互锁部件的故障类型可具体包括短电源故障、短地故障和开路故障。其中，短电源故障表示待检测高压互锁部件的任意一端或两端短接电源，短接的电源可能是未知电源。短地故障表示待检测高压互锁部件的任意一端或两端短接地。开路故障表示待检测高压互锁部件内部始终处于断开状态，也就是说待检测高压互锁部件内部始终处于电气不连通的状态。
图1是本申请实施例提供的一种高压互锁装置的结构示意图。在一个实施例中，本申请实施例中的高压互锁装置可以实现为高压互锁电路，又或者还可以是其他能够实现本申请实施例的高压互锁装置的功能的结构，对此不作具体限定。
如图1所示，高压互锁装置包括第一信号检测电路，第二信号检测电路12、第一开关模块S1、第二开关模块S2和故障诊断模块13。
第一信号检测电路11的第一连接端与待检测高压互锁部件G的一端T 1连接，第一信号检测电路11的第二连接端与第一开关模块S1的一端连接，第一信号检测电路11的输出端与故障诊断模块13连接。第一信号检测电路11用于在保证待检测高压互锁部件G与故障诊断模块13相隔离的前提下，从待检测高压互锁部件G采集第一原始电信号，并将第一原始电信号转换为第一采样信号。
第二信号检测电路12的第一连接端与待检测高压互锁部件G的另一端T 2连接，第二信号检测电路12的第二连接端与第二开关模块S2的一端连接，第二信号检测电路12的输出端与故障诊断模块13连接。第二信号检测电路12用于在保证待检测高压互锁部件G与故障诊断模块13相隔离的前提下，从待检测高压互锁部件G采集第二原始电信号，并将第二原始电信号转换为第二采样信号。
第一开关模块S1的另一端与第一电源端VCC1连接。在一个实施例中，第一电源端VCC1的电压小于等于车辆内低压供电源的电压。在一个示例中，第一电源端VCC1可以是整车的铅酸蓄电池、锂电池等蓄电池，对此不作具体限定。
第二开关模块S2的另一端与第二电源端VCC2连接。其中，第二电源端VCC2可以参见对第一电源端VCC1的相关说明，第一电源端VCC1和第二电源端VCC2的电压可以相同，例如选用同一电源，也可以选用不同的电源，对此不作限定。
故障诊断模块13用于在第一开关模块S1和第二开关模块S2中至少一者断开状态的情况下，根据第一采样信号和/或第二采样信号，确定待检测高压互锁部件G故障。
根据本申请实施例中的高压互锁装置及其故障检测方法，由于高压互锁装置包括第一信号检测电路和第二信号检测电路，且第一信号检测电路和第二信号检测电路在保证待检测高压互锁部件与故障诊断模块相隔离的前提下，能够将待检测高压互锁部件端部的电信号转换为待检测电信号，并将待检测电信号传输至故障诊断模块，以供故障诊断模块根据待检测电信号对待检测高压互锁部件进行故障检测，待检测高压互锁部件与故障诊断模块之间无直接的连接关系，从而能够将待检测高压互锁部件与故障诊断模块相隔离，避免了待检测高压互锁部件输出的目标电信号对故障诊断模块 的损坏，提高了高压互锁装置的安全性。
在一些实施例中，图2是本申请实施例提供的一种示例性的高压互锁装置的结构示意图。如图2所示，第一信号检测电路11包括第三开关模块Q1，第一电阻模块R1，第二电阻模块R2和第三电阻模块R3。
首先，对于，第三开关模块Q1包括隔离设置的第一驱动单元M1和第一开关单元K1。其中，第一驱动单元M1和第一开关单元K1之间隔离设置，表示两者之间不进行直接的电气连接。第一电阻模块R3可以包括一个或多个并联、串联或者混联等方式连接的电阻。
具体地，第一驱动单元M1的一端P 2作为第一信号检测电路11的第一连接端，第一驱动单元M1的一端P 2还与第二电阻模块R2的一端连接。第一驱动单元K1的另一端P 1作为第一信号检测电路11的第二连接端，第一驱动单元K1的另一端P 1还分别与第一电阻模块R1的一端、第二电阻模块R2的另一端连接。示例性的，如图2所示，第二基准电势位可以由第二地端GND2提供。
第一开关单元K1的一端P 3与故障诊断模块13连接，第一开关单元K1的一端P 3作为第一信号检测电路11的输出端。第一开关单元K1的一端P 3还通过第三电阻模块R3与第三电源端VCC3连接。第一开关单元K1的另一端P 4与第一基准电势位连接。示例性的，如图2所示，第一基准电势位可以由第一地端GND1提供。在一个实施例中，第三电源端VCC3输出的电压小于第一电源端VCC1输出的电压。若第一电源端VCC1为车辆的低压供电源，例如铅酸电池等。由于低压供电源往往输出12V或24V的电压，则第三电源端VCC3的取值范围可以分别为(0,12V)和(0,24V)。比如，第三电源端VCC3的电压可以是5V。
在一个实施例中，第一驱动单元M1可以将其两端的电信号转换为除电信号之外的其他形式的信号，并将该其他形式的信号传输至第一开关单元K1。第一开关单元K1响应于其他形式的信号，转换为电信号。第一驱动单元M1可具备单向导通性，当第一驱动单元M1的一端P 2的电压大于第一驱动单元M1另一端P 1的电压时，第一驱动单元M1可以驱动第一开关单元K1导通。在第一开关单元K1导通时，可以从第一开关单元K1的另一端P 1采集到低电平信号，在第二开关单元K1断开时，可以从第一开关单元K1的另一端P 1采集到高电平信号。其中，高电平信号和低电平信号是相对而言的，第一开关单元K1导通时第一开关单元K1的另一端P 1的电压和第一开关单元K1导断开时第一开关单元K1的另一端P 1的电压相比较，电压值较高的为高电平信号。
示例性的，若该其他形式的信号为光信号，本申请实施例可采用如图3所示的示例性的第三开关模块。如图3所示，第一驱动单元M1可以包括能够将电信号转换为光信号的发光元件，例如发光二极管。发光二极管的阴极作为第一驱动单元M1的另一端P 1，发光二极管的阳极作为第一驱动单元M1的一端P 2。第一开关单元K1可以包括将光信号转换为电信号的光开关，例如光电二极管、光电三极管、光电金属氧化物半导体场效应晶体管(Metal Oxide Semiconductor，MOS)等。其中，可以根据工作场景和工作需求选择合适的第一驱动单元M1和第一开关单元K1，对第一驱动单元M1 和第一开关单元K1的具体实现方式不做限定。
其次，对于第一电阻模块R1，第一电阻模块R1可以包括一个或多个以并联、串联或者混联等方式连接的电阻。具体地，第一电阻模块R1的一端还与第二电阻模块R2的另一端连接，第一电阻模块R1的另一端与第二基准电势位连接。示例性的，如图2所示，第二基准电势位可以由第二地端GND2提供。
然后，对于第二电阻模块R2和第三电阻模块R3，第二电阻模块R2和第三电阻模块R3可以包括一个或多个以并联、串联或者混联等方式连接的电阻。
在一个实施例中，第一信号检测电路11还包括第七电阻模块。第七电阻模块设置于第一电源端VCC1与第一开关模块S1之间。示例性的，图4是本申请实施例提供的另一种高压互锁装置的结构示意图。第七电阻模块可表示为图3中的R7。其中，第七电阻模块R7可以包括至少一个电阻。
通过设置第七电阻模块R7，第七电阻模块R7具有限流作用，能够防止第三开关模块Q1和第四开关模块Q2过流损坏。需要说明的是，本申请实施例中的其他电阻模块也具有限流作用，也能够防止第三开关模块Q1和第四开关模Q2过流损坏。
在一个实施例中，第一信号检测电路11还包括第一防反模块。第一防反模块的输入端与第一电源端连接，第一防反模块的输出端与第一开关模块S1的一端连接。
示例性的，继续参考图3，第一防反模块可以具体实现为二极管D1。二极管D1的阳极作为第一防反模块的输入端，若第一信号检测电路11不包括第七电阻模块R7，二极管D1的阳极与第一电源端VCC1连接。
若第一信号检测电路11包括第七电阻模块R7，二极管D1的阳极通过第七电阻模块R7与第一电源端VCC1连接。二极管D1的阴极作为第一防反模块的输出端，与第一开关模块S1相连接。此外，第七电阻模块R7和第一防反模块的位置可以互换，对两者的位置不做限定。
通过设置第一防反模块，可以防止高压互锁装置中的电流流入第一电源端VCC1而对第一电源端VCC1造成的损坏。
在一个实施例中，第一信号检测电路11还包括设置于第一电阻模块R1与第二电阻模块R2之间的第五开关模块。示例性的，第五开关模块可实现为图3中的S3。其中S3的通断状态与S2的通断状态保持同步。
在介绍完第一信号检测电路11之后，本申请下述部分对第二信号检测电路12做具体的说明。
在一些实施例中，继续参见图2，第二信号检测电路包括第四开关模块Q,，第四电阻模块R4，第五电阻模块R5和第六电阻模块R6。
第四开关模块Q2包括隔离设置的第二驱动单元M2和第二开关单元K2。
第二驱动单元M2的P 6一端作为第二信号检测电路12的第一连接端，第二驱动单元M2的P 6一端还与第五电阻模块R5的一端连接。第二驱动单元M2的另一端P 5作为第二信号检测电路12的第二连接端，第二驱动单元M2的另一端P 5还分别与第四电阻模块R4的一端、第五电阻模块R5的另一端连接。
第二开关单元K2的一端P 7作为第二信号检测电路12的输出端。第二开关单 元K2的一端P 7还通过第六电阻模块与第四电源端VCC4连接。第四电源端VCC4的具体内容可参见本申请上述实施例中第三电源端VCC2的相关内容，在此不再赘述。
第二开关单元K2的另一端P 8与第三基准电势位连接。示例性的，继续参见图2，第三基准电势位可以由第三地端GND3提供。
此外，第二驱动单元M2和第二开关单元K2的具体内容可参见本申请上述实施例中对第一驱动单元M1和第一开关单元K1的相关说明，在此不再赘述。
第四电阻模块R4的一端还与第五电阻单元R5的另一端连接。第四电阻模块R4和第五电阻单元R5均可以包括一个或多个以并联、串联或者混联等方式连接的电阻。第四电阻模块R4的具体内容可参见本申请上述实施例中对第一电阻模块R1的相关说明，在此不再赘述。第五电阻模块R5的具体内容可参见本申请上述实施例中对第二电阻模块R2的相关说明，在此不再赘述。
第四电阻模R4块的另一端与第四基准电势位连接。示例性的，如图1所示，第四基准电势位可以由第四地端GND4提供。需要说明的是，本申请实施例中的第一地端GND1至第四地端GND4可以是同一地端，也可以是不同地端，对此不作限定。
在一个实施例中，第二信号检测电路12还包括第八电阻模块。第八电阻模块设置于第二电源端VCC2与第二开关模块S2之间。示例性的，第八电阻模块可表示为图3中的R8。其中，第八电阻模块R8可以包括至少一个电阻。
在一个实施例中，第二信号检测电路12还包括第二防反模块。第二防反模块的输入端与第二电源端VCC3连接，第二防反模块的输出端与第二开关模块S2的一端连接。示例性的，继续参考图4，第二防反模块可以具体实现为二极管D2。二极管D2的具体内容可参见本申请上述实施例对二极管D1的相关描述，对此不再赘述。
通过设置第二防反模块，可以防止高压互锁装置中的电流流入第一电源端VCC2而对第一电源端VCC2造成的损坏。
在一个实施例中，第二信号检测电路12还包括设置于第四电阻模块R4与第五电阻模块R5之间的第六开关模块。示例性的，第六开关模块可实现为图4中的S4。
本申请实施例提供的高压互锁装置包括第三开关模块和第四开关模块，且第三开关模块和第四开关模块均包括隔离设置的驱动单元和开关单元。由于驱动单元和开关单元能够将驱动单元两端能够将待检测高压互锁部件一端的电信号转换为待检测电信号，并将待检测电信号传输至故障诊断模块，以供故障诊断模块根据待检测电信号对待检测高压互锁部件进行故障检测，待检测高压互锁部件与故障诊断模块之间无直接的连接关系，从而能够将待检测高压互锁部件与故障诊断模块相隔离，避免了待检测高压互锁部件输出的目标电信号对故障诊断模块的损坏，提高了高压互锁装置的安全性。
在介绍完了第一信号检测电路11和第二信号检测电路12之后，本申请实施例的下述部分对故障诊断模块13作具体说明。
针对故障诊断模块13，故障诊断模块13用于在第一开关模块S1和第二开关模块S2中至少一者断开状态的情况下，根据第三开关模块Q1的第一开关单元K1的一端P 3的第一采样信号和/或第四开关模块Q2的第二开关单元K2的一端P 7的第二采样 信号，确定待检测高压互锁部件G故障。其中，故障诊断模块13可以具体实现为整车控制器(Vehicle control unit，VCU)、电机控制器(Motor Control Unit，MCU)或者电池管理系统(Battery Management System，BMS)等具有处理功能的系统或者装置。
根据本申请实施例中的高压互锁装置，由于高压互锁装置包括第三开关模块Q1和第四开关模块Q2，且第三开关模块Q1和第四开关模块Q2均包括隔离设置的驱动单元和开关单元。由于驱动单元和开关单元能够将驱动单元两端能够将待检测高压互锁部件一端的电信号转换为待检测电信号，并将待检测电信号传输至故障诊断模块，以供故障诊断模块根据待检测电信号对待检测高压互锁部件进行故障检测，待检测高压互锁部件与故障诊断模块之间无直接的连接关系，从而能够将待检测高压互锁部件与故障诊断模块相隔离，避免了待检测高压互锁部件输出的目标电信号对故障诊断模块的损坏，提高了高压互锁装置的安全性。
在本申请的一些实施例中，在第一开关模块S1和第二开关模块S2中至少一者处于断开状态的情况具体包括三种子情况。第一子情况：第一开关模块S1和第二开关模块S2均处于断开状态。第二子情况：第一开关模块S1处于导通状态且第二开关模块S2处于断开状态。第三子情况：第一开关模块S1处于断开状态且第二开关模块S2处于导通状态。下面结合上述三种子情况和待检测高压互锁部件G的状态，对从图1示出的高压互锁装置所采集的第一采样信号和第二采样信号作详细的说明。第一采样信号和第二采样信号可详见下述表1，其中，表1中的符号“&”表示“和”的意思，比如“S1&S2断开”表示第一开关模块S1和第二开关模块S2均断开。
表1
Figure PCTCN2021081137-appb-000001
本实施例的下述部分，将结合表1对第一采样信号和第二采样信号展开具体说明。
(1)若待检测高压互锁部件G处于正常状态。参见表1，若第一开关模块S1 和第二开关模块S2均处于断开状态，此时，整个高压互锁装置没有电流。理想状态下可认为第一驱动单元M1两端的电压相等，第一驱动单元M1无法驱动第一开关单元K1导通。此时，第一采样信号为低电平信号。同理，第二驱动单元M2两端的电压也相等，无法驱动第二开关单元K2导通，第二采样信号同样为低电平信号。
若第一开关模块S1导通且第二开关模块S2断开，此时，第一电源端VCC1输出的电流具有两条传输路径，分别为，第一传输路径：第一电源端VCC1→第一开关模块S1→第一电阻模块R1→第二基准电势位GND2；第二传输路径：第一电源端VCC1→第一开关模块S1→第二电阻模块R2→待检测高压互锁部件G→第五电阻模块R5→第四电阻模块R4→第四基准电势位GND4。此时，第一驱动单元M1的一端P 2的电压低于第一驱动单元M1的另一端P 1的电压，第一驱动单元M1无法驱动第一开关单元K1导通，第一采样信号为高电平信号。第二驱动单元M2的一端P 6的电压高于第二驱动单元M2的另一端P 5的电压，第二驱动单元M2可以驱动第二开关单元M2导通，第二采样信号为低电平信号。
若第一开关模块S1断开且第二开关模块S2导通，此时，第二电源端VCC2输出的电流具有两条传输路径，分别为，第一传输路径：第二电源端VCC2→第二开关模块S2→第四电阻模块R4→第四基准电势位GND4；第二传输路径：第二电源端VCC2→第二开关模块S2→第五电阻模块R5→待检测高压互锁部件G→第二电阻模块R2→第一电阻模块R1→第二基准电势位GND2。此时，第一驱动单元M1的一端P 2的电压高于第一驱动单元M1的另一端P 1的电压，第一驱动单元M1能够驱动第一开关单元K1导通，第一采样信号为低电平信号。第二驱动单元M2的一端P 6的电压低于第二驱动单元M2的另一端P 5的电压，第二驱动单元M2无法驱动第二开关单元M2导通，第二采样信号为高电平信号。
(2)、若待检测高压互锁部件G出现短电源故障。继续参见表1，无论第一开关模块S1和第二开关模块S2导通与否，待检测高压互锁部件G两端的电压为所短接的电源的电压V x，第一驱动单元M1的另一端P 2的电压始终高于第一驱动单元M1的一端P 1的电压，第二驱动单元M2的另一端P 6的电压始终高于第二驱动单元M2的一端P 5的电压，在第一驱动单元M1和第二驱动单元M2的驱动下，第一开关单元K1和第二开关单元K2始终处于导通状态，第一采样信号和第二采样信号始终为低电平信号。
通过表1可发现，在第一开关模块S1和第二开关模块S2均处于断开状态的情况下，当待检测高压互锁部件G出现短电源故障时，第一采样信号为低电平信号，以及第二采样信号为低电平信号。在第一开关模块S1处于导通状态且第二开关模块S2处于断开状态的情况下，当待检测高压互锁部件G出现短电源故障时，第一采样信号为低电平信号。在第一开关模块S1处于断开状态且第二开关模块S2处于导通状态的情况下，当待检测高压互锁部件G出现短电源故障时，第二采样信号为低电平信号。
因此，可以根据第一开关模块S1和第二开关模块S2均处于断开状态时采集的第一采样信号和/或第二采样信号来诊断待检测高压互锁部件G的短电源故障。根据第一开关模块S1处于导通状态且第二开关模块S2处于断开状态时采集的第一采样信号 来诊断待检测高压互锁部件G的短电源故障。根据第一开关模块S1处于断开状态且第二开关模块S2处于导通状态时采集的第二采样信号来诊断待检测高压互锁部件G的短电源故障。
(3)、若待检测高压互锁部件G出现开路故障。继续参见表1，在第一开关模块S1和第二开关模块S2均处于断开状态的情况下，整个高压互锁装置没有电流，第一驱动单元M1无法驱动第一开关单元K1导通。此时，第一采样信号为低电平信号。同理，第二驱动单元M2也无法驱动第二开关单元K2导通，第二采样信号同样为低电平信号。
在第一开关模块S1导通且第二开关模块S2断开的情况下，第一电源端VCC1输出的电流的传输路径为第一电源端VCC1→第一开关模块S1→第一电阻模块R1→第二基准电势位GND2。电流流经第一信号检测电路11，第二信号检测电路12内无电流。此时，第一驱动单元M1的一端P 2的电压低于第一驱动单元M1的另一端P 1的电压，第一驱动单元M1无法驱动第一开关单元K1导通，第一采样信号为高电平信号。第二驱动单元M2的一端P 6的电压等于第二驱动单元M2的另一端P 5的电压，第二驱动单元M2也无法驱动第二开关单元K2导通，第二采样信号同样为高电平信号。
在第一开关模块S1断开且第二开关模块S2导通的情况下，第二电源端VCC2输出的电流的传输路径为第二电源端VCC2→第二开关模块S2→第四电阻模块R4→第四基准电势位GND4。电流流经第二信号检测电路12，第一信号检测电路11内无电流。此时，第一驱动单元M1的一端P 2的电压等于第一驱动单元M1的另一端P 1的电压，第一驱动单元M1无法驱动第一开关单元K1导通，第一采样信号为高电平信号。第二驱动单元M2的一端P 6的电压低于第二驱动单元M2的另一端P 5的电压，第二驱动单元M2也无法驱动第二开关单元K2导通，第二采样信号同样为高电平信号。
(4)、若待检测高压互锁部件G出现短地故障。继续参见表1，无论第一开关模块S1和第二开关模块S2导通与否，待检测高压互锁部件G两端的电压为基准电势(理想情况下可视为0)，第一驱动单元M1的一端P 2的电压不高于第一驱动单元M1的另一端P 1的电压，第二驱动单元M2的一端P 6的电压不高于第二驱动单元M2的另一端P 5的电压，第一驱动单元M1和第二驱动单元M2无法驱动第一开关单元K1和第二开关单元K2导通，第一采样信号和第二采样信号为高电平信号。
通过表1可发现，当待检测高压互锁部件G出现开路故障或者短地故障时，第一开关模块S1和第二开关模块S2中的任意一者闭合时，第一采样信号和第二采样信号均为高电平信号，与待检测高压互锁部件G处于正常状态时，采集的第一采样信号和第二采样信号不同。
同理地，若高压互锁装置还包括如图4示出的第五开关模块S3和/或第六开关模块S4，在第一开关模块S1和第二开关模块S2中至少一者断开的三种子情况下的第一采样信号和第二采样信号符合上述图1所示，在此不再赘述。
基于上述分析可知，在本实施例中，故障诊断模块13不仅可以判断出待检测高压互锁部件G发生故障，还可以检测出待检测高压互锁部件G的具体故障类型。
具体地，故障诊断模块13具体用于：若第一开关模块S1和第二开关模块S2 均处于断开状态，第一采样信号和/或第二采样信号为低电平信号，则确定待检测高压互锁部件发生短电源故障。
故障诊断模块13还具体用于：若第一开关模块S1处于导通状态且第二开关模块S2处于断开状态，第一采样信号为低电平信号，则确定待检测高压互锁部件G发生短电源故障；以及，若第二采样信号为高电平信号，则确定待检测高压互锁部件G发生短地故障或者开路故障。
故障诊断模块13还具体用于：若第一开关模块S1处于断开状态且第二开关模块S2处于导通状态，第二采样信号为低电平信号，则确定待检测高压互锁部件G发生短电源故障；以及，若第一采样信号为高电平信号，则确定待检测高压互锁部件G发生短地故障或者开路故障。
此外，故障诊断模块13还可以诊断待检测高压互锁部件G正常。具体地，参见表1，在第一开关模块S1和第二开关模块S2两者中的一者处于导通状态且另一者处于断开状态时，若第一采样信号和第二采样信号的电平高低相反，则确定待检测高压互锁部件G处于正常状态。
在一些实施例中，高压互锁装置还可以包括控制模块。具体地，控制模块用于按照预设控制策略控制第一开关模块S1和第二开关模块S2的通断。其中，控制模块的功能可以是由故障诊断模块实现。例如，该控制模块可以具体实现为VCU、MCU或者BMS。
在一个实施例中，预设控制策略包括：在第一时间段T1内，控制第一开关模块S1和第二开关模块S2处于断开状态。超出第一时间段T1后，控制第一开关模块和第二开关模块周期性交替断开。具体地，可以利用脉冲宽度调制(Pulse Width Modulation，PWM)信号来控制第一开关模块S1和第二开关模块S2的通断。例如，在第一时间段T1内，不向第一开关模块S1和第二开关模块S2输出脉冲宽度调制信号，在超出第一时间段T1后，向第一开关模块S1和第二开关模块S2分别输出PWM信号，并保持第一开关模块S1和第二开关模块S2处于互斥的通断状态，即第一开关模块S1断开时第二开关模块S2闭合，第一开关模块S1闭合时第二开关模块S2。
相应地，对应于该预设控制策略，在一个示例中，故障诊断模块13具体用于：根据第一采样信号的占空比和/或第二采样信号的占空比，确定待检测高压互锁部件故障。
首先，结合待检测高压互锁部件G的状态，对在控制模块的控制下采集的第一采样信号和第二采样信号做具体说明。
(1)若待检测高压互锁部件G处于正常状态，图5A是本申请实施例提供的一种示例性的处于正常状态下的待检测高压互锁部件G对应的第一采样信号和第二采样信号的波形图。如图5A所示，在第一时间段T1内，第一采样信号和第二采样信号均处于高电平状态。超出第一时间段T1之后，第一采样信号和第二采样信号的电平相反，即第一采样信号为高电平信号时，第二采样信号为低电平信号。
(2)、若待检测高压互锁部件G出现短电源故障，图5B是本申请实施例提供的一种示例性的出现短电源故障的待检测高压互锁部件G对应的第一采样信号和第 二采样信号的波形图。如图5B所示，第一采样信号和第二采样信号均为低电平信号。
(3)、若待检测高压互锁部件G出现开路故障，图5C是本申请实施例提供的一种示例性的出现开路故障的待检测高压互锁部件G对应的第一采样信号和第二采样信号的波形图。如图5C所示，第一采样信号和第二采样信号均为高电平信号。
(4)、若待检测高压互锁部件G出现短地故障，图5D是本申请实施例提供的一种示例性的出现短地故障的待检测高压互锁部件G对应的第一采样信号和第二采样信号的波形图。如图5D所示，第一采样信号和第二采样信号均为高电平信号。
通过图5A-图5D对比可知，若待检测高压互锁部件G正常，第一采样信号的占空比和第二采样信号的占空比均大于0且小于1。示例性的，若控制第一开关模块S1和第二开关模块S2的信号为PWM信号且施加至开关模块上的PWM信号为高电平时该开关模块导通时，当第一时间段T1足够短时，可近似认为第一采样信号的占空比与施加至第一开关模块S1的PWM信号的占空比相等，第二采样信号的占空比与施加至第二开关模块S2的PWM信号的占空比相等。相反地，若施加至开关模块上的PWM信号为高电平时该开关模块断开时，可近似认为第一采样信号的占空比与施加至第一开关模块S1的PWM信号的占空比相加为1，第二采样信号的占空比与施加至第二开关模块S2的PWM信号的占空比相加为1。若待检测高压互锁部件G出现短电源故障，在理想状态下第一采样信号的占空比和第二采样信号的占空比可认为等于0。若待检测高压互锁部件G出现开路故障或者短地故障，在理想状态下第一采样信号的占空比和第二采样信号的占空比可认为等于1。
相应地，故障诊断模块13可具体用于：若第一采样信号的占空比为0，和/或，第二采样信号的占空比为0，则确定待检测高压互锁部件G出现短电源故障。
故障诊断模块13还可具体用于：若第一采样信号的占空比为1，和/或，第二采样信号的占空比为1，则确定待检测高压互锁部件故障G出现开路故障或者短地故障。
此外，故障诊断模块13还可以判断出待检测高压互锁部件G处于正常状态。相应地，故障诊断模块13还用于若第一采样信号的占空比大于0且小于1，和/或，第二采样信号的占空比大于0且小于1，确定待检测高压互锁部件G处于正常状态。
在另一个示例中，对应于该预设控制策略，故障诊断模块13还可以具体用于：根据第一采样信号的波形图和/或第二采样信号的波形图，确定待检测高压互锁部件故障。可具体参照图5A-图5C，在此不再赘述。
在一些实施例中，为了提高高压互锁装置的诊断精度，故障诊断模块13还与待检测高压互锁部件G的一端T 1连接，以从待检测高压互锁部件G的一端T 1直接采集第三采样信号。相应地，故障诊断模块13可以具体用于：在第一开关模块S1和第二开关模块S2中至少一者断开状态的情况下，根据第一采样信号、第二采样信号和第三采样信号，确定待检测高压互锁部件故障。示例性，继续参照图2和图3，故障诊断模块13可以从采样点A 1采集第三采样信号。当采样点A 1的电势大于0时，第三采样信号为高电平信号；当采样点A 1的电势等于0时，第三采样信号为低电平信号。
其中，第一采样信号和第二采样信号的具体内容可参见本申请上述实施例中的 相关描述，在此不再赘述。本申请实施例的下述部分主要结合待检测高压互锁部件G的状态对第三采样信号作具体说明。第三采样信号可详见下述表2。
表2
Figure PCTCN2021081137-appb-000002
本实施例的下述部分，将结合表2对第三采样信号展开具体说明。
(1)若待检测高压互锁部件G处于正常状态，参见表2，若第一开关模块S1和第二开关模块S2均处于断开状态，此时，整个高压互锁装置没有电流。理想状态下，可认为采样点A 1的电势等于0，此时第三采样信号为低电平信号。
若第一开关模块S1导通且第二开关模块S2断开，第一电源端VCC1输出的电流可以经过采样点A 1分别流向第二基准电势位GND2和第四基准电势位GND4，此时第一电源端VCC1的电压可施加至采样点A 1，第三采样信号为高电平信号。
若第一开关模块S1断开且第二开关模块S2导通，第二电源端VCC2输出的电流可以经过采样点A 1分别流向第二基准电势位GND2，此时第三采样信号为高电平信号。
(2)、若待检测高压互锁部件G出现短电源故障，继续参见表2，采样点A 1的电势可认为近似等于待检测高压互锁部件G一端T 1的电势。由于待检测高压互锁部件G两端的电压始终为所短接的电源的电压V x，无论第一开关模块S1和第二开关模块S2导通与否，第三采样信号为高电平信号。
(3)、若待检测高压互锁部件G出现开路故障，继续参见表2，若第一开关模块S1和第二开关模块S2均处于断开状态，整个高压互锁装置没有电流，可近似认为采样点A 1的电势等于0，此时第三采样信号为低电平信号。
若第一开关模块S1导通且第二开关模块S2断开，第一电源端VCC1的电压可施加至采样点A 1，第三采样信号为高电平信号。
若第一开关模块S1断开且第二开关模块S2导通，由于待检测高压互锁部件G处于断开状态，第二电源端VCC2的电压可施加至采样点A 1，第三采样信号为低电平信号。
(4)、若待检测高压互锁部件G出现短地故障，采样点A 1的电势可认为近似等于待检测高压互锁部件G一端T 1的电势。由于待检测高压互锁部件G两端的电压为地端的电压，无论第一开关模块S1和第二开关模块S2导通与否，第三采样信号为低电平信号。
通过表2和上述分析内容可知，当第一开关模块S1和第二开关模块S2均断开时，当待检测高压互锁部件G出现短地故障时，第三采样信号为高电平信号。当第一开关模块S1闭合且第二开关模块S2断开时，出现开路故障的待检测高压互锁部件G对应的第三采样信号为高电平信号，出现短地故障的待检测高压互锁部件G对应的第三采样信号为低电平信号。
相应地，故障诊断模块13具体用于：若第一开关模块S1和第二开关模块S2均处于断开状态，第一采样信号为低电平信号、第二采样信号为低电平信号或第三采样信号为高电平信号，则确定待检测高压互锁部件G发生短电源故障。
故障诊断模块13还具体用于：若第一开关模块S1处于导通状态且第二开关模块S2处于断开状态，第一采样信号为低电平信号，则确定待检测高压互锁部件G发生短电源故障。以及，第三采样信号为低电平信号，则确定待检测高压互锁部件G发生短地故障；以及，若第二采样信号和第三采样信号均为高电平信号，则确定待检测高压互锁部件G发生开路故障。
故障诊断模块13还具体用于：若第一开关模块S1处于断开状态且第二开关模块S2处于导通状态，第二采样信号为低电平信号，则确定待检测高压互锁部件G发生短电源故障；以及，若第一采样信号为高电平信号和/或第三采样信号为低电平信号，则确定待检测高压互锁部件G发生短地故障或者开路故障。
在一些实施例中，若控制模块按照上述预设控制策略控制第一开关模块S1和第二开关模块S2通断。在一个示例中，故障诊断模块13具体用于：根据第一采样信号的占空比、第二采样信号的占空比和第三采样信号的占空比中的至少一者，确定待检测高压互锁部件G故障。
首先，结合待检测高压互锁部件G的状态，对在控制模块的控制下采集的第三采样信号做具体说明。其中，第一采样信号和第二采样信号的相关内容可参见本申请上述实施例结合图5A-图5D对第一采样信号和第二采样信号的具体说明，在此不再赘述。
(1)若待检测高压互锁部件G处于正常状态，图6A是本申请实施例提供的一种示例性的处于正常状态下的待检测高压互锁部件G对应的第一采样信号、第二采样信号和第三采样信号的波形图。如图6A所示，在第一时间段T1内，第三采样信号为低电平信号。超出第一时间段T1之后，第三采样信号为高电平信号。
(2)、若待检测高压互锁部件G出现短电源故障，图6B是本申请实施例提供的一种示例性的出现短电源故障的待检测高压互锁部件G对应的第一采样信号、第 二采样信号和第三采样信号的波形图。如图6B所示，第三采样信号始终为高电平信号。
(3)、若待检测高压互锁部件G出现开路故障，图6C是本申请实施例提供的一种示例性的出现短地故障的待检测高压互锁部件G对应的第一采样信号、第二采样信号和第三采样信号的波形图。如图6C所示，在第一时间段T1内，第三采样信号为低电平信号。超出第一时间段T1之后，第三采样信号为PWM信号。
(4)、若待检测高压互锁部件G出现短地故障，图6D是本申请实施例提供的一种示例性的出现开路故障的待检测高压互锁部件G对应的第一采样信号、第二采样信号和第三采样信号的波形图。如图6D所示，第三采样信号始终为低电平信号。
通过图6A-图6D对比可知，若待检测高压互锁部件G正常，第三采样信号的占空比等于1-T1/T0，其中，T0为总时长。若待检测高压互锁部件G出现短电源故障，第三采样信号的占空比等于1。若待检测高压互锁部件G出现短地故障，第三采样信号的占空比等于0。若待检测高压互锁部件G出现开路故障，当第一时间段T1足够短时，若控制第一开关模块S1和第二开关模块S2的信号为PWM信号且施加至第一开关模块S1上的PWM信号为高电平时第一开关模块S1导通，可近似认为第三采样信号的占空比与施加至第一开关模块S1的PWM信号的占空比相等。相反地，若施加至第一开关模块S1上的PWM信号为高电平时第一开关模块S1断开，可近似认为第三采样信号的占空比与施加至第一开关模块S1的PWM信号的占空比相加为1。
相应地，在上述实施例结合图6A-图6D说明的故障诊断模块13的具体功能的基础上，故障诊断模块13还可具体用于：若第三采样信号的占空比为0，则确定待检测高压互锁部件H出现短电源故障。
故障诊断模块13还可具体用于：若第三采样信号的占空比为0，则确定待检测高压互锁部件故障出现开路故障。
故障诊断模块13还可具体用于：若第三采样信号的占空比近似等于施加至第一开关模块S1上的PWM信号的占空比，则确定待检测高压互锁部件故障出现开路故障。
此外，故障诊断模块13还可以判断出待检测高压互锁部件G处于正常状态。相应地，故障诊断模块13还用于若第三采样信号的占空比等于1-T1/T0，确定待检测高压互锁部件G处于正常状态。
在另一个示例中，故障诊断模块13具体用于：根据第一采样信号的波形图、第二采样信号的波形图和第三采样信号的波形图中的至少一者，确定待检测高压互锁部件G故障。可具体参照图6A-图6D，在此不再赘述。
在一些实施例中，为了提高高压互锁装置的诊断精度，故障诊断模块13除了与待检测高压互锁部件G的一端T 1连接之外，还与待检测高压互锁部件G的另一端T 2连接，以从待检测高压互锁部件G的另一端T 2直接采集第四采样信号。相应地，故障诊断模块13可以具体用于：在第一开关模块S1和第二开关模块S2中至少一者断开状态的情况下，根据第一采样信号、第二采样信号、第三采样信号和第四采样信号，确定待检测高压互锁部件G故障。示例性，继续参照图1和图2，故障诊断模块13可 以从采样点A 2采集第四采样信号。当采样点A 2的电势大于0时，第四采样信号为高电平信号；当采样点A 2的电势等于0时，第四采样信号为低电平信号。
其中，第一采样信号、第二采样信号和第三采样信号的具体内容可参见本申请上述实施例中的相关描述，在此不再赘述。本申请实施例的下述部分主要结合待检测高压互锁部件G的状态对第四采样信号作具体说明。第四采样信号可详见下述表3。
表3
Figure PCTCN2021081137-appb-000003
本实施例的下述部分，将结合表3对第四采样信号展开具体说明。
(1)若待检测高压互锁部件G处于正常状态，参见图3，第四采样信号的原理和电平高低与第三采样信号的相同，在此不再赘述。
(2)、若待检测高压互锁部件G出现短电源故障，继续参见表3，第四采样信号的原理和电平高低与第三采样信号的相同，在此不再赘述。
(3)、若待检测高压互锁部件G出现开路故障，继续参见表3，若第一开关模块S1和第二开关模块S2均处于断开状态，第四采样信号的原理和电平高低与第三采样信号的相同，在此不再赘述。
若第一开关模块S1导通且第二开关模块S2断开，由于待检测高压互锁部件G始终处于断开状态，第一电源端VCC2的电压无法施加至采样点A 2，第三采样信号为低电平信号。
若第一开关模块S1断开且第二开关模块S2导通，第二电源端VCC2的电压可施加至采样点A 2，第三采样信号为低电平信号。
(4)、若待检测高压互锁部件G出现短地故障，第四采样信号的原理和电势高低与第三采样信号的相同，在此不再赘述。
通过表3和上述分析内容可知，当第一开关模块S1和第二开关模块S2均断开时，当待检测高压互锁部件G出现短地故障时，第三采样信号为高电平信号。当第一开关模块S1断开且第二开关模块S2闭合时，出现开路故障的待检测高压互锁部件G对应的第三采样信号为高电平信号，出现短地故障的待检测高压互锁部件G对应的第三采样信号为低电平信号。
相应地，故障诊断模块13具体用于：若第一开关模块S1和第二开关模块S2均处于断开状态，第一采样信号为低电平信号、第二采样信号为低电平信号、第三采样信号为高电平信号或第四采样信号为高电平信号，则确定待检测高压互锁部件G发生短电源故障。
故障诊断模块13还具体用于：若第一开关模块S1处于导通状态且第二开关模块S2处于断开状态，第一采样信号为低电平信号，则确定待检测高压互锁部件G发生短电源故障；以及，若第三采样信号为低电平信号，则确定待检测高压互锁部件G发生短地故障；以及，若第二采样信号和第三采样信号均为高电平信号，或者若第三采样信号为高电平且第四采样信号为低电平，则确定待检测高压互锁部件G发生开路故障。
故障诊断模块13还具体用于：若第一开关模块S1处于断开状态且第二开关模块S2均处于导通状态，第二采样信号为低电平信号，则确定待检测高压互锁部件G发生短电源故障；以及，若第四采样信号为低电平信号，则确定待检测高压互锁部件G发生短地故障；以及，若第一采样信号和第四采样信号均为高电平信号，或者若第三采样信号为低电平信号且第四采样信号为高电平信号，则确定待检测高压互锁部件G发生开路故障。
通过本申请实施例，控制第一开关模块S1和第二开关模块S2中一者处于导通状态且另一者处于断开时，无需控制第一开关模块S1和第二开关模块S2交替断开，即可诊断出待检测高压互锁部件G具体的故障类型。
在一些实施例中，若控制模块按照上述预设控制策略控制第一开关模块S1和第二开关模块S2通断。在一个示例中，故障诊断模块13具体用于：根据第一采样信号的占空比、第二采样信号的占空比、第三采样信号的占空比、第四采样信号的占空比中的至少一者，确定待检测高压互锁部件G故障。
首先，结合待检测高压互锁部件G的状态，对在控制模块的控制下采集的第四采样信号做具体说明。其中，第一采样信号、第二采样信号和第三采样信号的相关内容可参见本申请上述实施例结合图5A-图5D以及图6A-图6D对第一采样信号、第二采样信号和第三采样信号的具体说明，在此不再赘述。
(1)若待检测高压互锁部件G处于正常状态，图7A是本申请实施例提供的一种示例性的处于正常状态下的待检测高压互锁部件G对应的第一采样信号、第二采样信号、第三采样信号和第四采样信号的波形图。如图7A所示，在第一时间段T1内，第四采样信号为低电平信号。超出第一时间段T1之后，第四采样信号为高电平信号。
(2)、若待检测高压互锁部件G出现短电源故障，图7B是本申请实施例 提供的一种示例性的出现短电源故障的待检测高压互锁部件G对应的第一采样信号、第二采样信号、第三采样信号和第四采样信号的波形图。如图7B所示，第四采样信号为高电平信号。
(3)、若待检测高压互锁部件G出现开路故障，图7C是本申请实施例提供的一种示例性的出现短地故障的待检测高压互锁部件G对应的第一采样信号、第二采样信号、第三采样信号和第四采样信号的波形图。如图7C所示，在第一时间段T1内，第四采样信号为低电平信号。超出第一时间段T1之后，第四采样信号为PWM信号。
(4)、若待检测高压互锁部件G出现短地故障，图7D是本申请实施例提供的一种示例性的出现开路故障的待检测高压互锁部件G对应的第一采样信号、第二采样信号、第三采样信号和第四采样信号的波形图。如图7D所示，第四采样信号为低电平信号。
通过图7A-图7D对比可知，与结合图6A-图6D说明的第三采样信号的相同之处在于，若待检测高压互锁部件G正常，第四采样信号的占空比等于1-T1/T0，其中，T0为总时长。若待检测高压互锁部件G出现短电源故障，第三采样信号的占空比等于1。若待检测高压互锁部件G出现短地故障，第三采样信号的占空比等于0。
与结合图6A-图6D说明的第三采样信号的不同之处在于，若超出第一时间段T1，第三采样信号的电平高低与第四采样信号的电平高低相反。具体地，若待检测高压互锁部件G出现开路故障，当第一时间段T1足够短时，若控制第一开关模块S1和第二开关模块S2的信号为PWM信号且施加至第二开关模块S2上的PWM信号为高电平时第二开关模块S2导通，可近似认为第四采样信号的占空比与施加至第二开关模块S2的PWM信号的占空比相等。相反地，若施加至第二开关模块S2上的PWM信号为高电平时第二开关模块S2断开，可近似认为第四采样信号的占空比与施加至第二开关模块S2的PWM信号的占空比相加为1。
相应地，在上述实施例结合图5A-图5D说明的故障诊断模块13的具体功能的基础上，结合图7A-图7D示出的故障诊断模块13的具体功能与结合图6A-图6D示出的故障诊断模块13的具体功能相似，在此不再赘述。
在另一个示例中，故障诊断模块13具体用于：根据第一采样信号的波形图、第二采样信号的波形图、第三采样信号的波形图和第四采样信号的波形图中的至少一者，确定待检测高压互锁部件G故障。可具体参照图7A-图7D，在此不再赘述。
基于相同的申请构思，在结合图1至图7D示出的高压互锁装置的基础上，本申请实施例提供了一种高压互锁方法。图8是本申请实施例提供的一种高压互锁方法的流程示意图。如图8所示，高压互锁方法800包括S810和S820。
S810，在第一开关模块S1和第二开关模块S2中至少一者断开状态的情况下，获取第一开关单元的一端的第一采样信号和第二开关单元的一端的第二采样信号。
S820，根据第一采样信号和第二采样信号，确定待检测高压互锁部件G故障。
在本申请的一些实施例中，S820具体包括：若第一开关模块S1和第二开关模块S2均处于断开状态，第一采样信号和/或第二采样信号为低电平信号，则确定待检测高压互锁部件G发生短电源故障。
或者，若第一开关模块S1处于导通状态且第二开关模块S2处于断开状态，第一采样信号为低电平信号，则确定待检测高压互锁部件G发生短电源故障；以及，若第二采样信号为高电平信号，则确定待检测高压互锁部件发生短地故障或者开路故障。
或者，若第一开关模块S1处于断开状态且第二开关模块S2处于导通状态，第二采样信号为低电平信号，则确定待检测高压互锁部件G发生短电源故障；以及，若第一采样信号为高电平信号，则确定待检测高压互锁部件发生短地故障或者开路故障。
在本申请的一些实施例中，若高压互锁装置中的故障诊断模块13与待检测高压互锁部件G的一端连接，S820具体包括：在第一开关模块S1和第二开关模块S2中至少一者断开状态的情况下，根据第一采样信号、第二采样信号和待检测高压互锁部件G的一端的第三采样信号，确定待检测高压互锁部件G故障。
在一些实施例中，S820具体包括：若第一开关模块S1和第二开关模块S2均处于断开状态，第一采样信号为低电平信号、第二采样信号为低电平信号或第三采样信号为高电平信号，则确定待检测高压互锁部件G发生短电源故障。
或者，若第一开关模块S1处于导通状态且第二开关模块S2处于断开状态，第一采样信号为低电平信号，则确定待检测高压互锁部件G发生短电源故障；以及，若第三采样信号为低电平信号，则确定待检测高压互锁部件发生短地故障；以及，若第二采样信号和第三采样信号均为高电平信号，则确定待检测高压互锁部件发生开路故障。
或者，若第一开关模块S1处于断开状态且第二开关模块S2处于导通状态，第二采样信号为低电平信号，则确定待检测高压互锁部件G发生短电源故障；以及，若第一采样信号为高电平信号和/或第三采样信号为低电平信号，则确定待检测高压互锁部件发生短地故障或者开路故障。
在本申请的一些实施例中，若高压互锁装置中的故障诊断模块13与待检测高压互锁部件G的另一端连接，S820具体包括：在第一开关模块S1和第二开关模块S2中至少一者断开状态的情况下，根据第一采样信号、第二采样信号、第三采样信号和待检测高压互锁部件G的另一端的第四采样信号，确定待检测高压互锁部件G故障。
在一些实施例中，S820具体包括：若第一开关模块S1和第二开关模块S2均处于断开状态，第一采样信号为低电平信号、第二采样信号为低电平信号、第三采样信号为高电平信号或第四采样信号为高电平信号，则确定待检测高压互锁部件G发生短电源故障。
或者，若第一开关模块S1处于导通状态且第二开关模块S2处于断开状态，第一采样信号为低电平信号，则确定待检测高压互锁部件G发生短电源故障；以 及，若第三采样信号为低电平信号，则确定待检测高压互锁部件发生短地故障；以及，若第二采样信号和第三采样信号均为高电平，或者若第三采样信号为高电平且第四采样信号为低电平，则确定待检测高压互锁部件发生开路故障。
或者，若第一开关模块S1处于断开状态且第二开关模块S2处于导通状态，第二采样信号为低电平信号，则确定待检测高压互锁部件G发生短电源故障；以及，若第四采样信号为低电平信号，则确定待检测高压互锁部件发生短地故障；以及，若第一采样信号和第四采样信号均为高电平信号，或者若第三采样信号为低电平信号且第四采样信号为高电平信号，则确定待检测高压互锁部件发生开路故障。
在本申请的一些实施例中，高压互锁装置的故障检测方法800还包括：控制模块按照预设控制策略控制第一开关模块S1和第二开关模块S2的通断。
在一些实施例中，预设控制策略包括：在第一时间段内，控制第一开关模块S1和第二开关模块S2处于断开状态；超出第一时间段后，控制第一开关模块S1和第二开关模块S2周期性交替断开。
在一些实施例中，基于上述预设控制策略，S820具体包括：根据第一采样信号的占空比和/或第二采样信号的占空比，确定待检测高压互锁部件G故障。
在一些实施例中，基于上述预设控制策略，S820具体包括：若第一采样信号的占空比为0，和/或第二采样信号的占空比为0，则确定待检测高压互锁部件G出现短电源故障；若第一采样信号的占空比为1，和/或第二采样信号的占空比为1，则确定待检测高压互锁部件G故障出现开路故障或者短地故障。
根据本申请实施例的高压互锁装置的故障检测方法的其他细节与以上结合图1至图7D描述的根据本申请实施例的高压互锁装置类似，在此不再赘述。
需要明确的是，本说明书中的各个实施例均采用递进的方式描述，各个实施例之间相同或相似的部分互相参见即可，每个实施例重点说明的都是与其他实施例的不同之处。其中方法实施例描述得比较简单，相关之处请参见系统实施例的说明部分。本申请并不局限于上文所描述并在图中示出的特定步骤和结构。本领域的技术人员可以在领会本申请的精神之后，作出各种改变、修改和添加，或者改变步骤之间的顺序。并且，为了简明起见，这里省略对已知方法技术的详细描述。
上述实施例中的功能模块可以实现为硬件、软件、固件或者它们的组合。当以硬件方式实现时，其可以例如是电子电路、专用集成电路(ASIC)、适当的固件、插件、功能卡等等。当以软件方式实现时，本申请的元素是被用于执行所需任务的程序或者代码段。程序或者代码段可以存储在机器可读介质中，或者通过载波中携带的数据信号在传输介质或者通信链路上传送。“机器可读介质”可以包括能够存储或传输信息的任何介质。
虽然已经参考优选实施例对本申请进行了描述，但在不脱离本申请的范围的情况下，可以对其进行各种改进并且可以用等效物替换其中的部件。尤其是，只要不存在结构冲突，各个实施例中所提到的各项技术特征均可以任意方式组合起来。本申请并不局限于文中公开的特定实施例，而是包括落入权利要求的范围内的所有技术方案。

Claims (15)

  1. 一种高压互锁装置，包括：
    第一信号检测电路，所述第一信号检测电路的第一连接端与待检测高压互锁部件的一端连接，所述第一信号检测电路的第二连接端与第一开关模块的一端连接，所述第一信号检测电路的输出端与故障诊断模块连接，所述第一信号检测电路用于在保证所述待检测高压互锁部件与所述故障诊断模块相隔离的前提下，从所述待检测高压互锁部件采集第一原始电信号，并将所述第一原始电信号转换为第一采样信号；
    第二信号检测电路，所述第二信号检测电路的第一连接端与所述待检测高压互锁部件的另一端连接，所述第二信号检测电路的第二连接端与第二开关模块的一端连接，所述第二信号检测电路的输出端与所述故障诊断模块连接，所述第二信号检测电路用于在保证所述待检测高压互锁部件与所述故障诊断模块相隔离的前提下，从所述待检测高压互锁部件采集第二原始电信号，并将所述第二原始电信号转换为第二采样信号；
    所述第一开关模块，所述第一开关模块的另一端与第一电源端连接；
    所述第二开关模块，所述第二开关模块的另一端与第二电源端连接；
    所述故障诊断模块，用于在所述第一开关模块和所述第二开关模块中至少一者断开状态的情况下，根据所述第一采样信号和/或所述第二采样信号，确定所述待检测高压互锁部件故障。
  2. 根据权利要求1所述的高压互锁装置，其中，
    所述第一信号检测电路包括第三开关模块，第一电阻模块，第二电阻模块和第三电阻模块，其中，
    所述第三开关模块包括隔离设置的第一驱动单元和第一开关单元，
    所述第一驱动单元的一端作为所述第一信号检测电路的第一连接端，所述第一驱动单元的一端还与所述第二电阻模块的一端连接；所述第一驱动单元的另一端作为所述第一信号检测电路的第二连接端，所述第一驱动单元的另一端还分别与所述第一电阻模块的一端、所述第二电阻模块的另一端连接，
    所述第一开关单元的一端作为所述第一信号检测电路的输出端，所述第一开关单元的一端还通过所述第三电阻模块与第三电源端连接；所述第一开关单元的另一端与第一基准电势位连接，
    所述第一电阻模块的一端还与所述第二电阻模块的另一端连接，所述第一电阻模块的另一端与第二基准电势位连接；
    所述第二信号检测电路包括第四开关模块，第四电阻模块，第五电阻模块和第六电阻模块，其中，
    所述第四开关模块包括隔离设置的第二驱动单元和第二开关单元，
    所述第二驱动单元的一端作为所述第二信号检测电路的第一连接端，所述第二驱动单元的一端还与所述第五电阻模块的一端连接；所述第二驱动单元的另一 端作为所述第二信号检测电路的第二连接端，所述第二驱动单元的另一端还分别与所述第四电阻模块的一端、所述第五电阻模块的另一端连接，
    所述第二开关单元的一端作为所述第二信号检测电路的输出端，所述第二开关单元的一端还通过所述第六电阻模块与第四电源端连接；所述第二开关单元的另一端与第三基准电势位连接，
    所述第四电阻模块的一端还与所述第五电阻单元的另一端连接，所述第四电阻模块的另一端与第四基准电势位连接。
  3. 根据权利要求1或2所述的高压互锁装置，其中，所述故障诊断模块用于：
    若所述第一开关模块和所述第二开关模块均处于断开状态，所述第一采样信号和/或所述第二采样信号为低电平信号，则确定所述待检测高压互锁部件发生短电源故障；
    或者，
    若所述第一开关模块处于导通状态且所述第二开关模块处于断开状态，所述第一采样信号为低电平信号，则确定所述待检测高压互锁部件发生短电源故障；以及，若所述第二采样信号为高电平信号，则确定所述待检测高压互锁部件发生短地故障或者开路故障；
    或者，
    若所述第一开关模块处于断开状态且所述第二开关模块均处于导通状态，所述第二采样信号为低电平信号，则确定所述待检测高压互锁部件发生短电源故障；以及，若所述第一采样信号为高电平信号，则确定所述待检测高压互锁部件发生短地故障或者开路故障。
  4. 根据权利要求1-3任一项所述的高压互锁装置，其中，
    所述故障诊断模块与所述待检测高压互锁部件的一端连接，
    所述故障诊断模块具体用于：
    在所述第一开关模块和所述第二开关模块中至少一者断开状态的情况下，根据所述第一采样信号、所述第二采样信号和所述待检测高压互锁部件的一端的第三采样信号，确定所述待检测高压互锁部件故障。
  5. 根据权利要求4所述的高压互锁装置，其中，所述故障诊断模块用于：
    若所述第一开关模块和所述第二开关模块均处于断开状态，所述第一采样信号为低电平信号、所述第二采样信号为低电平信号或所述第三采样信号为高电平信号，则确定所述待检测高压互锁部件发生短电源故障；
    或者，
    若所述第一开关模块处于导通状态且所述第二开关模块均处于断开状态，所述第一采样信号为低电平信号，则确定所述待检测高压互锁部件发生短电源故障；以及，若所述第三采样信号为低电平信号，则确定所述待检测高压互锁部件发生短地故障；以及，若所述第二采样信号和所述第三采样信号均为高电平信号，则确定所述待检测高压互锁部件发生开路故障；
    或者，
    若所述第一开关模块处于断开状态且所述第二开关模块均处于导通状态，所述第二采样信号为低电平信号，则确定所述待检测高压互锁部件发生短电源故障；以及，若所述第一采样信号为高电平信号和/或所述第三采样信号为低电平信号，则确定所述待检测高压互锁部件发生短地故障或者开路故障。
  6. 根据权利要求4或5所述的高压互锁装置，其中，
    所述故障诊断模块与所述待检测高压互锁部件的另一端连接；
    所述故障诊断模块具体用于：
    在所述第一开关模块和所述第二开关模块中至少一者断开状态的情况下，根据所述第一采样信号、所述第二采样信号、所述第三采样信号和所述待检测高压互锁部件的另一端的第四采样信号，确定所述待检测高压互锁部件故障。
  7. 根据权利要求6所述的高压互锁装置，其中，所述故障诊断模块用于：
    若所述第一开关模块和所述第二开关模块均处于断开状态，所述第一采样信号为低电平信号、所述第二采样信号为低电平信号、所述第三采样信号为高电平信号或所述第四采样信号为高电平信号，则确定所述待检测高压互锁部件发生短电源故障；
    或者，
    若所述第一开关模块处于导通状态且所述第二开关模块均处于断开状态，所述第一采样信号为低电平信号，则确定所述待检测高压互锁部件发生短电源故障；以及，若所述第三采样信号为低电平信号，则确定所述待检测高压互锁部件发生短地故障；以及，若所述第二采样信号和所述第三采样信号均为高电平，或者若所述第三采样信号为高电平且所述第四采样信号为低电平，则确定所述待检测高压互锁部件发生开路故障；
    或者，
    若所述第一开关模块处于断开状态且所述第二开关模块均处于导通状态，所述第二采样信号为低电平信号，则确定所述待检测高压互锁部件发生短电源故障；以及，若所述第四采样信号为低电平信号，则确定所述待检测高压互锁部件发生短地故障；以及，若所述第一采样信号和所述第四采样信号均为高电平信号，或者若所述第三采样信号为低电平信号且所述第四采样信号为高电平信号，则确定所述待检测高压互锁部件发生开路故障。
  8. 根据权利要求1-7任一项所述的高压互锁装置，还包括：
    控制模块，用于按照预设控制策略控制所述第一开关模块和所述第二开关模块的通断。
  9. 根据权利要求8所述的高压互锁装置，其中，所述预设控制策略包括：
    在第一时间段内，控制所述第一开关模块和所述第二开关模块处于断开状态；
    超出所述第一时间段后，控制所述第一开关模块和所述第二开关模块周期性交替断开。
  10. 根据权利要求9所述的高压互锁装置，其中，所述故障诊断模块用于：
    根据第一采样信号的占空比和/或第二采样信号的占空比，确定所述待检测高压互锁部件故障。
  11. 根据权利要求9或10所述的高压互锁装置，其中，所述故障诊断模块具体用于：
    若第一采样信号的占空比为0，和/或，第二采样信号的占空比为0，则确定所述待检测高压互锁部件出现短电源故障；
    若第一采样信号的占空比为1，和/或，第二采样信号的占空比为1，则确定所述待检测高压互锁部件故障出现开路故障或者短地故障。
  12. 根据权利要求1-11任一项所述的高压互锁装置，还包括：
    第七电阻模块，设置于所述第一电源端与所述第一开关模块之间；和/或
    第八电阻模块，设置于所述第二电源端与所述第二开关模块之间。
  13. 根据权利要求1-12任一项所述的高压互锁装置，还包括：
    第一防反模块，所述第一防反模块的输入端与所述第一电源端连接，所述第一防反模块的输出端与所述第一开关模块的一端连接；和/或
    第二防反模块，所述第二防反模块的输入端与所述第二电源端连接，所述第二防反模块的输出端与所述第二开关模块的一端连接。
  14. 根据权利要求2所述的高压互锁装置，其中，
    所述第一驱动单元和所述第二驱动单元包括发光元件；
    所述第一开关单元和所述第二开关单元包括光开关。
  15. 一种高压互锁装置的故障检测方法，应用于如权利要求1-14任一项所述的故障诊断模块，所述方法包括：
    在所述第一开关模块和所述第二开关模块中至少一者断开状态的情况下，获取所述第一采样信号和所述第二采样信号；
    根据所述第一采样信号和所述第二采样信号，确定所述待检测高压互锁部件故障。
PCT/CN2021/081137 2020-06-12 2021-03-16 高压互锁装置及其故障检测方法 WO2021248958A1 (zh)

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