WO2021244279A1 - 显示面板和显示装置 - Google Patents

显示面板和显示装置 Download PDF

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Publication number
WO2021244279A1
WO2021244279A1 PCT/CN2021/094383 CN2021094383W WO2021244279A1 WO 2021244279 A1 WO2021244279 A1 WO 2021244279A1 CN 2021094383 W CN2021094383 W CN 2021094383W WO 2021244279 A1 WO2021244279 A1 WO 2021244279A1
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WO
WIPO (PCT)
Prior art keywords
wire
display panel
pixel
wires
display area
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2021/094383
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English (en)
French (fr)
Chinese (zh)
Inventor
黄耀
黄炜赟
龙跃
王彬艳
杨国波
王本莲
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by BOE Technology Group Co Ltd, Chengdu BOE Optoelectronics Technology Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to EP21818977.7A priority Critical patent/EP4106001B1/en
Priority to US17/760,461 priority patent/US12615928B2/en
Priority to EP25173421.6A priority patent/EP4586786A3/en
Priority to JP2022533191A priority patent/JP7716404B2/ja
Publication of WO2021244279A1 publication Critical patent/WO2021244279A1/zh
Priority to US17/936,533 priority patent/US20240114731A1/en
Anticipated expiration legal-status Critical
Priority to US18/166,874 priority patent/US20230189596A1/en
Priority to JP2025061828A priority patent/JP2025092740A/ja
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04M—TELEPHONIC COMMUNICATION
    • H04M1/00—Substation equipment, e.g. for use by subscribers
    • H04M1/02—Constructional features of telephone sets
    • H04M1/0202—Portable telephone sets, e.g. cordless phones, mobile phones or bar type handsets
    • H04M1/026—Details of the structure or mounting of specific components
    • H04M1/0266—Details of the structure or mounting of specific components for a display module assembly
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/123—Connection of the pixel electrodes to the thin film transistors [TFT]
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04M—TELEPHONIC COMMUNICATION
    • H04M1/00—Substation equipment, e.g. for use by subscribers
    • H04M1/02—Constructional features of telephone sets
    • H04M1/0202—Portable telephone sets, e.g. cordless phones, mobile phones or bar type handsets
    • H04M1/026—Details of the structure or mounting of specific components
    • H04M1/0264—Details of the structure or mounting of specific components for a camera module assembly
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels
    • H10K59/351—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels comprising more than three subpixels, e.g. red-green-blue-white [RGBW]

Definitions

  • At least one embodiment of the present disclosure relates to a display panel and a display device.
  • the display panel usually includes a high pixel density (Pixels Per Inch, PPI) area and a low PPI area.
  • PPI Pixel Density
  • the light transmittance of the usual display panel in the low PPI area is low, which is not conducive to improving the camera’s performance.
  • the display effect of the imaging area is not conducive to improving the camera’s performance.
  • At least one embodiment of the present disclosure relates to a display panel and a display device.
  • At least one embodiment of the present disclosure provides a display panel including: a first display area; a second display area located at least on one side of the first display area; a plurality of pixel units located in the first display area and In the second display area, the density of pixel units in the first display area is less than the density of pixel units in the second display area, and the pixel units include pixel circuits; and a first power supply line configured to The pixel circuit provides a first voltage signal; the first power line includes a plurality of first wires, a plurality of second wires, and a plurality of third wires, and the first wires extend from the second display area to the In the first display area, the plurality of second wires are located in the first display area and between adjacent first wires, the second wires extend in a first direction, and the third wires extend in a second direction Extending, the first direction intersects the second direction, the third wire extends from the second display area to the first display area, and adjacent second wires are spaced apart from each other along the
  • the plurality of second conductive lines are sequentially arranged along the first direction.
  • the adjacent second wires are not directly connected.
  • the length of the portion of the first wire located in the first display area in the first direction is greater than the length of the second wire in the first direction. length.
  • the first wire includes portions located in different layers, and the portions located in the different layers are connected by via holes penetrating the insulating layer.
  • the first power cord further includes a fourth wire, the fourth wire extends along the second direction, and the second wire is connected to The length of the first wire and the fourth wire in the second direction is less than or equal to the length of the third wire in the second direction.
  • a display panel provided according to some embodiments of the present disclosure includes a plurality of fourth wires, the plurality of fourth wires are located between adjacent third wires, and the plurality of fourth wires are arranged in sequence along the second direction , Adjacent fourth wires are spaced apart from each other in the second direction.
  • a part of the first wire and the third wire are located on the same layer, and the fourth wire and the third wire are located on the same layer.
  • the pixel units located in the first display area constitute a plurality of pixel islands
  • the pixel islands include at least two pixel units located in two adjacent rows
  • the first wire And the second conductive line respectively overlap with two pixel units located in the two adjacent rows.
  • the pixel unit further includes a light-emitting element
  • the pixel circuit includes a first transistor and a second transistor, the first transistor is connected to the second transistor, and the first transistor is connected to the second transistor.
  • Two transistors are connected to the light-emitting element, the first transistor includes a first channel and a second channel, the first channel and the second channel are connected by a conductive portion
  • the second wire further includes A connecting arm, the connecting arm and the conductive portion of a pixel unit overlapping the second wire in the pixel island are spaced apart from each other in the third direction and partially overlapped in the third direction, the The third direction is perpendicular to the first direction and perpendicular to the second direction.
  • the shape of the connecting arm includes a C shape.
  • the first conductive line has a branch, and the conductive portion of a pixel unit that overlaps the first conductive line in the pixel island is in the pixel island.
  • the third directions are spaced apart from each other and partially overlap in the third direction.
  • the first direction is perpendicular to the second direction.
  • the first power cord further includes a fifth wire extending along the first direction, and the fifth wire is located in the second display area, The fifth wire is located between adjacent first wires, and the fifth wire and the second wire adjacent to the fifth wire are spaced apart from each other along the first direction.
  • the display panel further includes an initialization signal line configured to provide an initialization signal to the pixel circuit, and the second wire is part of the initialization signal line. surround.
  • the first wire includes a first portion and a second portion, the first portion of the first wire and the second wire are located on the same layer, and the first wire of the first wire The two parts are not on the same layer as the second wire, and the first part of the first wire is surrounded by a part of the initialization signal wire.
  • the first portion of the first wire has a first sub-portion extending in the first direction and a second sub-portion extending in the second direction, so The second sub-portion has a branch, and the branch extends along the first direction.
  • the length of the branch in the first direction is smaller than the length of the first sub-part in the first direction.
  • the pixel unit further includes a light-emitting element
  • the pixel circuit includes a first transistor and a second transistor, the first transistor is connected to the second transistor, and the first transistor is connected to the second transistor.
  • Two transistors are connected to the light-emitting element, the first transistor includes a first channel and a second channel, the first channel and the second channel are connected by a conductive portion, and the branch is connected to the pixel
  • the conductive portions of a pixel unit in the island that overlap the first conductive line are spaced apart from each other in the third direction, and partially overlap in the third direction, and the third direction is perpendicular to the first Direction, and perpendicular to the second direction.
  • the second wire further includes a connecting arm, and the connecting arm is connected to the conductive portion of a pixel unit in the pixel island that overlaps the second wire Spaced apart from each other in the third direction, and partially overlapped in the third direction.
  • the display panel further includes a base substrate and a data line
  • the data line is configured to provide a data signal to the pixel circuit
  • the data line includes a first data line, wherein The first data line extends from the first display area to the second display area, and the first data line overlaps the orthographic projection of the third wire on the base substrate.
  • the first data line includes a first part and a second part, the first part of the first data line overlaps the third wire part, and the second The second part of a data line and the third conductive line do not overlap, and the first part of the first data line and the second part of the first data line are respectively located in different layers.
  • the display panel provided by some embodiments of the present disclosure, there is a light-transmitting area between adjacent pixel islands, and the first part of the first data line is located between the adjacent pixel islands.
  • two first data lines are provided, and the two first data lines are respectively connected to two adjacent columns of pixel units, and the two first data lines are connected to the same first data line.
  • the orthographic projections of the three wires on the base substrate overlap.
  • the display panel further includes a gate line configured to provide a scan signal to a row of pixel units, the gate line includes a first gate line, and the first gate line Extending from the second display area to the first display area, the light-transmitting area is surrounded by two adjacent first gate lines and two adjacent first data lines.
  • Some embodiments of the present disclosure also provide a display device including any of the above-mentioned display panels.
  • FIGS. 1A to 1C are schematic diagrams of display panels provided by some embodiments of the present disclosure.
  • FIG. 2 is a schematic diagram of a second display area of a display panel provided by an embodiment of the present disclosure
  • FIG. 3 is a schematic diagram of a first display area of a display panel provided by an embodiment of the present disclosure
  • FIG. 4 is a schematic diagram of a pixel unit in a display panel and a signal line that provides signals for the pixel unit according to an embodiment of the present disclosure
  • Figure 5 is a schematic diagram of a display panel
  • 6A to 6E are schematic diagrams of display panels provided by some embodiments of the present disclosure.
  • FIG. 7A is a schematic diagram of a display panel provided by an embodiment of the present disclosure.
  • FIG. 7B is a schematic diagram of a display panel provided by an embodiment of the present disclosure.
  • FIG. 8 is a schematic diagram of a pixel circuit of a display panel provided by an embodiment of the present disclosure.
  • FIG. 9 is a plan view of a semiconductor pattern in a display panel provided by an embodiment of the present disclosure.
  • FIG. 10 is a plan view of a first conductive pattern layer in a display panel provided by an embodiment of the present disclosure
  • FIG. 11 is a plan view of a second conductive pattern layer in a display panel provided by an embodiment of the present disclosure.
  • FIG. 12 is a plan view of a first insulating layer in a display panel provided by an embodiment of the present disclosure.
  • FIG. 13 is a plan view of a third conductive pattern layer in a display panel provided by an embodiment of the present disclosure.
  • FIG. 14 is a plan view of a second insulating layer in a display panel provided by an embodiment of the present disclosure.
  • FIG. 15 is a plan view of a pixel electrode layer in a display panel provided by an embodiment of the present disclosure.
  • FIG. 16 is a plan view of a pixel definition layer in a display panel provided by an embodiment of the present disclosure.
  • FIG. 17 is a schematic diagram of forming an active layer of a thin film transistor in a display panel according to an embodiment of the present disclosure
  • FIG. 18 is a schematic plan view of a display panel after forming a second conductive pattern layer and a first insulating layer in an embodiment of the present disclosure
  • FIG. 19 is a schematic plan view of a display panel after forming a third conductive pattern layer according to an embodiment of the present disclosure
  • FIG. 20 is a schematic plan view after forming a second insulating layer in a display panel provided by an embodiment of the present disclosure
  • FIG. 21 is a schematic plan view of a display panel after forming a pixel electrode layer according to an embodiment of the present disclosure
  • FIG. 22 is a schematic plan view of a display panel after forming pixel definitions according to an embodiment of the present disclosure
  • FIG. 23 is a schematic plan view of adjacent pixel islands in a second direction in a first display area of a display panel according to an embodiment of the present disclosure
  • FIG. 24 is a schematic cross-sectional view of a display panel provided by an embodiment of the present disclosure.
  • FIG. 25 is a schematic cross-sectional view of a display panel provided by an embodiment of the present disclosure.
  • the first power line adopts a mesh structure.
  • the display panel provided by the embodiments of the present disclosure optimizes the signal line in the low PPI area to achieve higher transmittance, for example, The embodiment of the present disclosure optimizes the horizontal and vertical wires of the first power cord in the form of a mesh.
  • FIGS. 1A to 1C are schematic diagrams of display panels provided by some embodiments of the present disclosure.
  • the display panel includes a first display area R1 and a second display area R2.
  • the first display area R1 is a high pixel density (Pixels Per Inch, PPI) area
  • the second display area R2 is a low PPI area.
  • the second display area R2 is a partial light-transmitting area.
  • the second display area R2 is located at least on one side of the first display area R1.
  • the display panel shown in FIGS. 1A and 1B further includes a third region R3.
  • a sensor such as a camera may be arranged in the first display area R1 (as shown in FIG.
  • the third region R3 shown in FIGS. 1A and 1B may be a hole-digging region, that is, the material at the position corresponding to the third region R3 is removed to form a through hole.
  • the sensor can receive ambient light. Taking the sensor as the camera as an example, the under-screen camera is realized, so that when the screen is used normally, the first display area corresponding to the sensor can display the picture normally, and when the camera is shooting, the first display area can transmit ambient light, supporting normal usage of.
  • the sensor is provided on the non-display side of the display panel.
  • the sensor can also be called an under-screen device.
  • FIG. 1A also shows a plurality of gate lines 113 and a plurality of data lines 313.
  • the plurality of gate lines 113 include a first gate line GL1, and the plurality of data lines 313 include a first data line DL1.
  • the first gate line GL1 extends from the second display area R2 to the first display area R1.
  • the first data line DL1 extends from the first display area R1 to the second display area R2.
  • a certain element extending from the first display area R1 to the second display area R2 can be understood as the element located in the first display area R1 and the second display area R2, or it can be said that a certain element extends from the first display area R1 and the second display area R2.
  • the second display area R2 extends to the first display area R1.
  • FIG. 1A schematically shows several gate lines 113 and several data lines 313, and the number of gate lines 113 and data lines 313 can be determined according to needs.
  • the plurality of gate lines 113 and the plurality of data lines 313 cross each other and are insulated from each other.
  • FIG. 2 is a schematic diagram of a second display area of a display panel provided by an embodiment of the present disclosure.
  • FIG. 3 is a schematic diagram of a first display area of a display panel provided by an embodiment of the present disclosure.
  • the display panel includes a plurality of pixel units P0, and the plurality of pixel units P0 includes a first pixel unit 101, a second pixel unit 102, a third pixel unit 103, and a fourth pixel unit 104.
  • One first pixel unit 101, one second pixel unit 102, one third pixel unit 103, and one fourth pixel unit 104 constitute a pixel group P1.
  • a pixel group P1 includes two pixels.
  • a first pixel unit 101 and a second pixel unit 102 constitute a pixel
  • a third pixel unit 103 and a fourth pixel unit 104 constitute a pixel.
  • One pixel group P1 forms two virtual pixels to improve the display effect.
  • a pixel group P1 is a repeating unit arranged in an array in the second display area R2.
  • one pixel group P1 is called a pixel island A1.
  • the first display area R1 includes a plurality of light-transmitting areas R0; the light-transmitting area R0 is located between adjacent pixel islands A1.
  • the light-transmitting area R0 can transmit ambient light.
  • the light-transmitting area R0 may include a base substrate and a transparent insulating layer on the base substrate, and the light-transmitting area R0 does not have a light shielding structure, for example, does not have a metal wiring.
  • the light-transmitting area R0 is located in the area surrounded by four adjacent pixel islands A1, but it is not limited to this. For example, as shown in FIG. 3, adjacent pixel islands A1 are arranged at intervals.
  • the first pixel unit 101 is a red pixel unit
  • the second pixel unit 102 is a green pixel unit
  • the third pixel unit 103 is a blue pixel unit
  • the fourth pixel unit 104 is a green pixel unit as an example.
  • the pixel group may also use pixel units of other colors.
  • the arrangement of the multiple pixel units P0 in the display panel is not limited to those shown in FIGS. 2 and 3.
  • a plurality of pixel units P0 are located in the first display area R1 and the second display area R2, and the density of the pixel units in the first display area R1 is less than the density of the pixel units in the second display area R2.
  • the density of pixels in the first display area R1 is less than the density of pixels in the second display area R2.
  • the density of the pixel units in the first display area R1 shown in FIG. 3 is one quarter of the density of the pixel units in the second display area R2. That is, the density of pixels in the first display region R1 shown in FIG. 3 is one-fourth of the density of pixels in the second display region R2.
  • the arrangement of the light-transmitting area R0 and the pixel units in the first display area R1 is not limited to that shown in FIG. 3, and can be set as required.
  • the density of the pixel units in the first display area R1 is one-half, one-third, one-sixth, or eighth of the density of the pixel units in the second display area R2.
  • One grade is different from other values of one quarter.
  • the display panel further includes gate lines 113 and data lines 313.
  • the gate line 113 and the data line 313 are insulated from each other.
  • Each gate line 113 is connected to a row of pixel units, and each data line 313 is connected to a column of pixel units.
  • the gate line 113 is configured to provide a scan signal to a row of pixel units.
  • the data line 313 includes a first data line DL1.
  • the first data line DL1 is located at least in the first display area R1.
  • the first data line DL1 extends from the first display area R1 to the second display area R2.
  • the gate line includes a first gate line GL1, and the first gate line GL1 extends from the second display region R2 to the first display region R1.
  • the light-transmitting area R0 is surrounded by two adjacent first gate lines GL1 and two adjacent first data lines DL1, but is not limited thereto.
  • FIG. 4 is a schematic diagram of a pixel unit in a display panel and a signal line that provides a signal for the pixel unit according to an embodiment of the present disclosure.
  • the display panel includes a plurality of pixel units P0.
  • Each pixel unit P0 includes a light-emitting element EMC and a pixel circuit 10 that provides a driving current for the light-emitting element EMC.
  • the light-emitting element EMC may be an electroluminescent element, for example,
  • the organic electroluminescence element for example, may be an organic light emitting diode (OLED).
  • the display panel further includes an initialization signal line 210, a light emission control signal line 110, a data line 313, a first power line 311, and a second power line 312.
  • the gate line 113 is configured to provide the scan signal SCAN to the pixel circuit 10.
  • the emission control signal line 110 is configured to provide an emission control signal EM to the pixel unit P0.
  • the data line 313 is configured to provide a data signal DATA to the pixel circuit 10
  • the first power line 311 is configured to provide a constant first voltage signal ELVDD to the pixel circuit 10
  • the second power line 312 is configured to provide a constant voltage signal to the pixel circuit 10.
  • the second voltage signal ELVSS is greater than the second voltage signal ELVSS, and the first voltage signal ELVDD is greater than the second voltage signal ELVSS.
  • the initialization signal line 210 is configured to provide an initialization signal Vint to the pixel circuit 10.
  • the initialization signal Vint is a constant voltage signal, and its magnitude may be between the first voltage signal ELVDD and the second voltage signal ELVSS, but is not limited thereto. For example, the initialization signal Vint may be less than or equal to the second voltage signal ELVSS.
  • the pixel circuit 10 outputs a driving current under the control of the scan signal SCAN, the data signal DATA, the initialization signal Vint, the first voltage signal ELVDD, the second voltage signal ELVSS, the light emission control signal EM and other signals to drive the light emitting element EMC to emit light.
  • the light-emitting element EMC includes a pixel electrode E1 and a common electrode E2.
  • the pixel electrode E1 is connected to the pixel circuit 10, and the common electrode E2 is connected to the second power line 312.
  • Fig. 5 is a schematic diagram of a display panel. As shown in FIG. 5, whether in the first display area R1 or the second display area R2, the first power line 3110 adopts a mesh structure, and the lateral part of the first power line 3110 is directly connected, and the first power line 3110 The vertical parts are directly connected. However, the wiring method of the first power supply line with the mesh structure makes the light transmittance of the first display region R1 low.
  • the first power line 311 includes a plurality of first wires L1, a plurality of second wires L2, and a plurality of third wires L3, and the first wires L1 extend from the second display area R2 to the first In the display area R1, a plurality of second conductive lines L2 are located in the first display area R1 and between adjacent first conductive lines L1.
  • Each second conductive line L2 extends along the first direction D1, and the third conductive line L3 is at least located in the first display area.
  • the area R1 for example, the third wire L3 extends from the second display area R2 to the first display area R1, the third wire L3 extends along the second direction D2, the first direction D1 intersects the second direction D2, and is adjacent to the second
  • the wires L2 are spaced apart from each other along the first direction D1, and the second wire L2 is connected to the first wire L1 through the third wire L3.
  • the first direction D1 is perpendicular to the second direction D2, but it is not limited thereto.
  • the first conductive line L1 extends along the first direction D1.
  • the second wire L2 is only located in the first display area R1.
  • the element extending along a certain direction is not necessarily a straight line, but may also have a curved or broken line part.
  • the extension direction of a certain element refers to the general extension trend of the element, for example, the element Each part of does not necessarily extend in this direction.
  • the display panel provided by the embodiment of the present disclosure adjusts the structure of the first power line in the first display area, which is equivalent to removing part of the first power line arranged along the second direction in the common display panel, which simplifies the configuration of the first display area.
  • the first power line improves the light transmittance of the first display area.
  • the first wire L1 and the second wire L2 are respectively connected to two adjacent rows of pixel units in a pixel island A1, but it is not limited to this.
  • the pixel island A1 It may also include more than two rows of pixel units.
  • the pixel island A1 includes at least two pixel units located in two adjacent rows, and the first wire L1 and the second wire L2 overlap with the two pixel units located in two adjacent rows, respectively. .
  • the first wire L1 overlaps the first pixel unit 101
  • the second wire L2 overlaps the third pixel unit 103.
  • the first wire L1 also overlaps the second pixel unit 102
  • the second wire L2 also overlaps the fourth pixel unit 104.
  • a plurality of second conductive lines L2 are sequentially arranged along the first direction D1.
  • adjacent second conductive lines L2 are not directly connected, and a plurality of second conductive lines L2 that are not directly connected are formed by removing part of the first power line arranged along the first direction.
  • the length of the portion of the first wire L1 located in the first display area R1 in the first direction D1 is greater than the length of the second wire L2 in the first direction D1. The length in the first direction D1.
  • the first power line 311 further includes a fourth wire L4, the fourth wire L4 extends along the second direction D2, and the second wire L2 is connected to the first wire L1 through the fourth wire L4,
  • the length of the fourth wire L4 in the second direction D2 is less than or equal to the length of the third wire L3 in the second direction D2.
  • the length of the fourth wire L4 in the second direction D2 is smaller than the length of the third wire L3 in the second direction D2.
  • the length of the fourth wire L4 in the second direction D2 is equal to the length of the third wire L3 in the second direction D2.
  • a plurality of fourth conductive lines L4 are provided, and the plurality of fourth conductive lines L4 are arranged in sequence along the second direction D2, and are adjacent to the fourth conductive line L4.
  • the wires L4 are spaced apart from each other in the second direction D2.
  • a plurality of fourth wires L41 are located between the third wire L31 and the third wire L32, and the third wire L31 and the third wire L32 are adjacent third wires L3.
  • FIG. 6A shows three fourth conductive lines L41, but the number of fourth conductive lines L4 located between adjacent third conductive lines L3 is not limited to that shown in the figure, and can be determined according to needs. Because the multiple fourth wires L4 are spaced apart from each other in the second direction D2, it is equivalent to removing part of the first power line in the common display panel that is arranged along the second direction, thereby reducing wiring, optimizing the wiring space, and improving The transmittance of light.
  • the first power line 311 further includes a fifth wire L5, the fifth wire L5 extends along the first direction D1, the fifth wire L5 is located in the second display area R2, and the fifth wire L5 is located in Between adjacent first conductive lines L1, the fifth conductive line L5 and the second conductive line L2 adjacent thereto are spaced apart from each other along the first direction D1. Therefore, at the boundary position of the first display area and the second display area, the wiring is reduced, and the light transmittance is improved.
  • each pixel island includes two rows and three columns of pixel units.
  • the number of pixel units included in each pixel island and the arrangement of the pixel units are not limited. As long as the number of pixel units included in each pixel island is greater than or equal to two rows, the present invention can be used.
  • the arrangement of the first power cord provided by the disclosed embodiment.
  • the first power line 311 further includes a plurality of sixth wires L6, the sixth wires L6 are located in the second display area R2, and the sixth wires L6 extend along the second direction D2.
  • a plurality of fifth wires L5 and a plurality of sixth wires L6 are intersectedly arranged.
  • the fifth wire L5 and the sixth wire L6 are both located only in the second display area R2.
  • FIG. 7A is a schematic diagram of a display panel provided by an embodiment of the present disclosure.
  • the same gate line 113 connects the pixel units located in the second display area on both sides of the first display area R1 and the pixel units located in the first display area R1 to form a row of pixel units.
  • the embodiment of the present disclosure does not limit the form of the first wire, as long as it can extend from the second display area R2 to the first display area R1.
  • the first power line in FIG. 7A can also be replaced with the first power line in other embodiments of the present disclosure.
  • the extending manner of the gate line 113 is not limited to that shown in FIG. 7A, as long as the arrangement of the gate line 113 can connect the pixels in the second display region R2 and the pixels in the first display region R1.
  • FIG. 7B is a schematic diagram of a display panel provided by an embodiment of the present disclosure. Compared with the display panel shown in FIG. 7A, the display panel shown in FIG. 7B has adjusted the position of the partial gate lines in the first display area. That is, in the display panel shown in FIG. 7B, one gate line is respectively provided above and below the pixel island. In the display panel shown in FIG. 7A, two gate lines are provided under the pixel island.
  • FIGS. 6A to 6E, FIGS. 7A and 7B take as examples that the second wire is connected to one of the two adjacent first wires, but is not directly connected to the other.
  • the fourth wire is in contact with one of the two adjacent first wires, for example, through a via hole penetrating the insulating layer.
  • a row of pixel units are pixel units connected to the same gate line 113
  • a column of pixel units are pixel units connected to the same data line 313.
  • the first wire L1, the second wire L2, and the fifth wire L5 all extend in the row direction
  • the third wire L3, the fourth wire L4, and the sixth wire L6 extend in the column direction as an example To explain, but not limited to this.
  • the first wire L1, the second wire L2, and the fifth wire L5 may all extend in the column direction
  • the third wire L3, the fourth wire L4, and the sixth wire L6 may extend in the row direction.
  • Ground, the second direction D2 and the first direction D1 also replace each other.
  • the pixel island may also include three rows or more than three rows of pixel units.
  • the above-mentioned multiple second conductive lines may It is understood as the second wire connected to the pixel unit in the same row.
  • the plurality of second wires described above The wire can be understood as a second wire connected to the pixel unit of the same column.
  • FIGS. 8 to 25 take the pixel circuit of 7T1C as an example for description.
  • FIG. 8 is a schematic diagram of a pixel circuit of a display panel provided by an embodiment of the present disclosure.
  • FIG. 9 is a plan view of a semiconductor pattern in a display panel provided by an embodiment of the disclosure.
  • FIG. 10 is a plan view of a first conductive pattern layer in a display panel provided by an embodiment of the present disclosure.
  • FIG. 11 is a plan view of a second conductive pattern layer in a display panel provided by an embodiment of the present disclosure.
  • FIG. 12 is a plan view of a first insulating layer in a display panel provided by an embodiment of the present disclosure.
  • FIG. 13 is a plan view of a third conductive pattern layer in a display panel provided by an embodiment of the present disclosure.
  • FIG. 14 is a plan view of a second insulating layer in a display panel provided by an embodiment of the present disclosure.
  • FIG. 15 is a plan view of a pixel electrode layer in a display panel provided by an embodiment of the present disclosure.
  • FIG. 16 is a plan view of a pixel definition layer in a display panel provided by an embodiment of the disclosure.
  • FIG. 17 is a schematic diagram of forming an active layer of a thin film transistor in a display panel provided by an embodiment of the present disclosure.
  • FIG. 18 is a schematic plan view of a display panel after forming a second conductive pattern layer and a first insulating layer in an embodiment of the present disclosure.
  • FIG. 19 is a schematic plan view of a display panel after forming a third conductive pattern layer according to an embodiment of the present disclosure.
  • FIG. 20 is a schematic plan view after forming a second insulating layer in a display panel according to an embodiment of the present disclosure.
  • FIG. 21 is a schematic plan view of a display panel after forming a pixel electrode layer according to an embodiment of the present disclosure.
  • FIG. 22 is a schematic plan view of a display panel after forming pixel definitions according to an embodiment of the present disclosure.
  • FIG. 23 is a schematic plan view of adjacent pixel islands in a second direction in a first display area of a display panel according to an embodiment of the present disclosure.
  • FIG. 24 is a schematic cross-sectional view of a display panel provided by an embodiment of the present disclosure.
  • FIG. 25 is a schematic cross-sectional view of a display panel provided by an embodiment of the present disclosure.
  • the insulating layer is shown in the form of via holes in the plan view, and the insulating layer itself is transparent.
  • the gate line 113 is configured to provide the scan signal SCAN to the pixel circuit 10.
  • the emission control signal line 110 is configured to provide an emission control signal EM to the pixel unit P0.
  • the data line 313 is configured to provide a data signal DATA to the pixel circuit 10
  • the first power line 311 is configured to provide a constant first voltage signal ELVDD to the pixel circuit 10
  • the second power line 312 is configured to provide a constant voltage signal to the pixel circuit 10.
  • the second voltage signal ELVSS is greater than the second voltage signal ELVSS
  • the first voltage signal ELVDD is greater than the second voltage signal ELVSS.
  • the initialization signal line 210 is configured to provide an initialization signal Vint to the pixel circuit 10.
  • the initialization signal Vint is a constant voltage signal, and its magnitude may be between the first voltage signal ELVDD and the second voltage signal ELVSS, but is not limited thereto.
  • the initialization signal Vint may be less than or equal to the second voltage signal ELVSS.
  • the pixel circuit outputs a driving current to drive the light-emitting element 20 to emit light under the control of the scan signal SCAN, the data signal DATA, the initialization signal Vint, the first voltage signal ELVDD, the second voltage signal ELVSS, and the light emission control signal EM.
  • the light-emitting element 20 emits red light, green light, blue light, or white light under the driving of its corresponding pixel circuit 10.
  • the pixel circuit 10 includes a driving transistor T1, a data writing transistor T2, a threshold compensation transistor T3, a first light emission control transistor T4, a second light emission control transistor T5, a first reset transistor T6, and a second reset transistor T7 and storage capacitor C1.
  • the driving transistor T1 is electrically connected to the light-emitting element 20, and outputs a driving current to drive the light-emitting element 20 to emit light under the control of the scan signal SCAN, the data signal DATA, the first voltage signal ELVDD, and the second voltage signal ELVSS.
  • the display panel provided by the embodiment of the present disclosure further includes: a data driving circuit and a scan driving circuit.
  • the data driving circuit is configured to provide a data signal DATA to the pixel unit P0 according to an instruction of the control circuit;
  • the scan driving circuit is configured to provide a light emission control signal EM, a scan signal SCAN, a reset control signal RESET, etc. to the pixel unit P0 according to an instruction of the control circuit Signal.
  • the control circuit includes an external integrated circuit (IC), but is not limited thereto.
  • the scan driving circuit is a GOA (Gate Driver On Array) structure mounted on the display panel, or a driver chip (IC) structure that is bonded to the display panel.
  • GOA Gate Driver On Array
  • the display panel further includes a power supply (not shown in the figure) to provide the above-mentioned voltage signal, which can be a voltage source or a current source as required, and the power source is configured to pass through the first power line 311, the second power line 312, and the And the initialization signal line 210 provides the first voltage signal ELVDD, the second power supply voltage ELVSS, and the initialization signal Vint to the pixel unit P0.
  • a power supply (not shown in the figure) to provide the above-mentioned voltage signal, which can be a voltage source or a current source as required, and the power source is configured to pass through the first power line 311, the second power line 312, and the And the initialization signal line 210 provides the first voltage signal ELVDD, the second power supply voltage ELVSS, and the initialization signal Vint to the pixel unit P0.
  • the second electrode C12 of the storage capacitor C1 is electrically connected to the first power line 311, and the first electrode C11 of the storage capacitor C1 is electrically connected to the second electrode T32 of the threshold compensation transistor T3.
  • the gate T20 of the data writing transistor T2 is electrically connected to the gate line 113, and the first electrode T21 and the second electrode T22 of the data writing transistor T2 are electrically connected to the data line 313 and the first electrode T11 of the driving transistor T1, respectively.
  • the gate T30 of the threshold compensation transistor T3 is electrically connected to the gate line 113, the first pole T31 of the threshold compensation transistor T3 is electrically connected to the second pole T12 of the drive transistor T1, and the second pole T32 of the threshold compensation transistor T3 is electrically connected to the drive transistor T1.
  • the gate T10 is electrically connected.
  • the gate T40 of the first light emission control transistor T4 and the gate T50 of the second light emission control transistor T5 are both connected to the light emission control signal line 110.
  • the first pole T41 and the second pole T42 of the first light-emitting control transistor T4 are electrically connected to the first power line 311 and the first pole T11 of the driving transistor T1, respectively.
  • the first electrode T51 and the second electrode T52 of the second light-emitting control transistor T5 are electrically connected to the second electrode T12 of the driving transistor T1 and the pixel electrode E1 (which may be the anode of the OLED) of the light-emitting element 20, respectively.
  • the common electrode E2 (which may be a common electrode of an OLED, such as a cathode) of the light-emitting element 20 is electrically connected to the second power line 312.
  • the gate T60 of the first reset transistor T6 is electrically connected to the first reset control signal line 111, and the first pole T61 of the first reset transistor T6 is connected to the initialization signal line 210 (the first initialization signal line 211). ) Is electrically connected, and the second electrode T62 of the first reset transistor T6 is electrically connected to the gate T10 of the driving transistor T1.
  • the gate T70 of the second reset transistor T7 is electrically connected to the second reset control signal line 112, the first pole T71 of the second reset transistor T7 is electrically connected to the initialization signal line 210 (the second initialization signal line 212), and the second reset transistor The second pole T72 of T7 is electrically connected to the pixel electrode E1 of the light-emitting element 20.
  • FIG. 9 shows the semiconductor pattern SCP
  • FIG. 10 shows the first conductive pattern layer LY1, and a first gate insulating layer is provided between the first conductive pattern layer LY1 and the semiconductor pattern SCP.
  • the semiconductor pattern SCP is doped with the first conductive pattern layer LY1 as a mask, so that the area of the semiconductor pattern SCP that is not covered by the first conductive pattern layer LY1 retains the semiconductor characteristics, forming the channel of the thin film transistor, and the semiconductor pattern SCP
  • the area covered by the first conductive pattern layer LY1 is made conductive to form the source or drain of the thin film transistor.
  • Figure 17 shows the active layer ALT formed after the semiconductor pattern SCP is partially conductive.
  • the first conductive pattern layer LY1 includes a first reset control signal line 111, a second reset control signal line 112, a light emission control signal line 110, a gate line 113, and a first electrode C11 of a storage capacitor C1.
  • FIG. 10 also shows the first portion DL11 (wire 114) of the first data line DL1.
  • FIG. 10 also shows a gate line GL0, which is a part of the gate line extending from the second display area to the first display area.
  • the first reset control signal line 111 and the second reset control signal line 112 are connected.
  • FIG. 11 shows the second conductive pattern layer LY2, and a second gate insulating layer is provided between the second conductive pattern layer LY2 and the first conductive pattern layer LY1.
  • the second conductive pattern layer LY2 includes a stopper BK0, a stopper BK1, an initialization signal line 210, and a second pole C12 of the storage capacitor C1.
  • the second pole C12 of the storage capacitor C1 has an opening OPN.
  • the initialization signal line 210 includes a first initialization signal line 211 and a second initialization signal line 212.
  • the second conductive pattern layer LY2 includes a first portion L11 and a third portion L13 of the first conductive line L1.
  • the stopper BK0 extends from the first wire L1.
  • Figure 12 shows the pattern of the first insulating layer ISL1.
  • the dots in the figure are via holes in the first insulating layer ISL1.
  • the first insulating layer ISL1 includes a first gate insulating layer, a second gate insulating layer and interlayers. At least one of the insulating layers.
  • the interlayer insulating layer is located between the second conductive pattern layer LY2 and the third conductive pattern layer LY3.
  • FIGS. 24 and 25 For the first gate insulating layer, the second gate insulating layer and the interlayer insulating layer, the first conductive pattern layer LY1, the second conductive pattern layer LY2, and the third conductive pattern layer LY3, please refer to FIGS. 24 and 25.
  • FIG. 18 shows a schematic plan view after forming the first insulating layer ISL1.
  • FIG. 13 shows the third conductive pattern layer LY3.
  • the third conductive pattern layer LY3 includes a third wire L3 (a part of the first power line 311), a second part DL12 of the data line (a part of the data line 313), and the first The connection electrode 31a, the second connection electrode 31b, the third connection electrode 31c, and the fourth connection electrode 31d.
  • the third conductive pattern layer LY3 further includes a second portion L12 of the first conductive line L1.
  • the first part L11 and the third part L13 of the first wire L1 are connected by the second part L12.
  • the data line 313 is electrically connected to the first pole T21 of the data writing transistor T2 through the via hole V4, and the first power line 311 is electrically connected to the first light emitting control transistor T4 through the via hole V3.
  • the first pole T41 is electrically connected, the first power line 311 is electrically connected to the second pole C12 of the storage capacitor C1 through the via hole V6, and the first power line 311 is electrically connected to the conductive block BK1 through the via hole V5.
  • One end of the first connection electrode 31a is electrically connected to the first initialization signal line 211 through the via hole V11, and the other end of the first connection electrode 31a is connected to the first electrode T61 of the first reset transistor T6 through the via hole V12, so that the first The first pole T61 of the reset transistor T6 is electrically connected to the first initialization signal line 211.
  • One end of the second connection electrode 31b is electrically connected to the second electrode T62 of the first reset transistor T6 through the via hole V21, and the other end of the second connection electrode 31b is electrically connected to the gate T10 of the driving transistor T1 (that is, the storage capacitor) through the via hole V22.
  • the first electrode C11 of C1 is electrically connected, so that the second electrode T62 of the first reset transistor T6 is electrically connected to the gate T10 of the driving transistor T1 (that is, the first electrode C11 of the storage capacitor C1).
  • One end of the third connection electrode 31c is electrically connected to the second initialization signal line 212 through the via hole V31, and the other end of the third connection electrode 31c is connected to the first electrode T71 of the second reset transistor T7 through the via hole V32, so that the second The first pole T71 of the reset transistor T7 is electrically connected to the first initialization signal line 211.
  • the fourth connection electrode 31d is electrically connected to the second electrode T52 of the second light emission control transistor T5 through the via hole V1.
  • the fourth connection electrode 31d can be used to electrically connect with the pixel electrode E1 (refer to FIG. 8) of the light-emitting element 20 to be formed later.
  • FIG. 14 shows the second insulating layer ISL2, and the dots in FIG. 14 are via holes V1 in the second insulating layer ISL2.
  • the via V1 includes a via V10, a via V20, a via V30, and a via V40.
  • Fig. 20 is a plan view after forming the second insulating layer.
  • Fig. 15 shows the electrode layer ETL.
  • the electrode layer ETL includes a plurality of pixel electrodes E1.
  • the electrode layer ETL includes the pixel electrode E11 of the first pixel unit 101, the pixel electrode E12 of the second pixel unit 102, the pixel electrode E13 of the third pixel unit 103, and the pixel electrode E14 of the fourth pixel unit 104.
  • FIG. 21 is a plan view of the display panel after forming the electrode layer.
  • the pixel electrode E14 of the fourth pixel unit 104 includes a supplementary part E0, and the orthographic projection of the supplementary part E0 on the base substrate can cover the common electrode (
  • the second pole T22 of the data writing transistor T2 and the second pole T42 of the first light emitting control transistor T4) are projected onto the base substrate to improve the stability and stability of the data writing transistor T2 and the first light emitting control transistor T4. Life, thereby improving the long-term luminous stability and life of the display panel.
  • FIG. 16 shows a plan view of the pixel definition layer.
  • the pixel definition layer PDL includes a plurality of openings, and the plurality of openings includes an opening OPN1, an opening OPN2, an opening OPN3, and an opening OPN4.
  • FIG. 22 shows a schematic diagram of the display panel after forming the pixel definition layer.
  • the opening OPN1 exposes a part of the pixel electrode E11
  • the opening OPN2 exposes a part of the pixel electrode E12
  • the opening OPN3 exposes a part of the pixel electrode E13
  • the opening OPN4 exposes a part of the pixel electrode E14.
  • the light-emitting functional layer and the common electrode are formed, and then the light-emitting element EMC is formed.
  • the transistors used in an embodiment of the present disclosure may be thin film transistors, field effect transistors, or other switching devices with the same characteristics.
  • the source and drain of the transistor used here can be symmetrical in structure, so the source and drain of the transistor can be structurally indistinguishable.
  • one pole is directly described as the first pole and the other pole is the second pole. Therefore, all or part of the first pole of the transistor in the embodiment of the present disclosure And the second pole is interchangeable according to needs.
  • the first electrode of the transistor described in the embodiments of the present disclosure may be a source electrode, and the second electrode may be a drain electrode; or, the first electrode of the transistor may be a drain electrode and the second electrode of the transistor may be a source electrode.
  • transistors can be divided into N-type and P-type transistors according to their characteristics.
  • the transistors all adopt P-type transistors as an example for description. Based on the description and teaching of the implementation in the present disclosure, those of ordinary skill in the art can easily think of using N-type transistors for at least part of the transistors in the pixel circuit of the embodiments of the present disclosure without creative work, that is, using N-type transistors. The implementation of the transistor or the combination of the N-type transistor and the P-type transistor, therefore, these implementations are also within the protection scope of the present disclosure.
  • FIGS. 8 to 25 take a 7T1C pixel circuit as an example for description, and the embodiments of the present disclosure include but are not limited to this. It should be noted that the embodiments of the present disclosure do not limit the number of thin film transistors and the number of capacitors included in the pixel circuit.
  • the pixel circuit of the display base panel may also be a structure including other numbers of transistors, such as a 7T2C structure, a 6T1C structure, a 6T2C structure, or a 9T2C structure, which is not limited in the embodiments of the present disclosure.
  • FIG. 25 is a schematic cross-sectional view of a display panel provided by an embodiment of the disclosure.
  • the display panel includes a thin film transistor 50 and a storage capacitor C1.
  • the thin film transistor 50 includes an active layer ATL1 located on the base substrate BS, a first gate insulating layer GI1 located on the side of the active layer ATL1 away from the base substrate BS, and located on the side of the first gate insulating layer GI1 away from the base substrate BS The gate GE.
  • the display panel further includes a second gate insulating layer GI2 located on the side of the gate GE away from the base substrate BS, an interlayer insulating layer ILD located on the side of the second gate insulating layer GI2 away from the base substrate BS, and an interlayer insulating layer
  • the ILD is away from the connection electrode CNE1 on the side of the base substrate BS.
  • the active layer ATL1 includes a channel CN11 and a first electrode ET1 and a second electrode ET2 respectively located on both sides of the channel CN11.
  • the connection electrode CNE1 passes through the first gate insulating layer GI1, the second gate insulating layer GI2, and the interlayer insulation.
  • the via hole of the layer ILD is connected to the second pole ET2.
  • the storage capacitor C1 includes a first electrode C11 and a second electrode C12.
  • the first electrode C11 and the gate GE are located on the same layer, and both are located on the first conductive pattern layer LY1, and the second electrode C12 is located on the second gate insulating layer GI2 and the interlayer insulation Between the layers ILD, the second conductive pattern layer LY2 is located.
  • One of the first electrode ET1 and the second electrode ET2 is a source, and the other of the first electrode ET1 and the second electrode ET2 is a drain.
  • the connection electrode CNE1 is located on the third conductive pattern layer LY3.
  • the display panel also includes a passivation layer PVX and a planarization layer PLN.
  • the connection electrode CNE1 is the aforementioned fourth connection electrode 31d
  • the thin film transistor 50 can be the aforementioned second light emission control transistor T5.
  • the display panel also includes a light-emitting element EMC.
  • the light-emitting element EMC includes a pixel electrode E1, a light-emitting functional layer EML, and a common electrode E2.
  • the pixel electrode E1 is connected to the through hole through the passivation layer PVX and the planarization layer PLN
  • the electrode CNE1 is connected.
  • the display panel further includes an encapsulation layer CPS, and the encapsulation layer CPS includes a first encapsulation layer CPS1, a second encapsulation layer CPS2, and a third encapsulation layer CPS3.
  • the first encapsulation layer CPS1 and the third encapsulation layer CPS3 are inorganic material layers, and the second encapsulation layer CPS2 is an organic material layer.
  • the pixel electrode E1 is an anode
  • the common electrode E2 is a cathode, but it is not limited thereto.
  • the light-emitting element EMC includes an organic light-emitting diode.
  • the light-emitting function layer is located between the common electrode E2 and the pixel electrode E1.
  • the light-emitting functional layer EML includes at least a light-emitting layer, and may also include at least one of a hole transport layer, a hole injection layer, an electron transport layer, and an electron injection layer.
  • the display panel further includes a pixel definition layer PDL and spacers PS.
  • the pixel defining layer PDL has an opening configured to define the light emitting area (light emitting area, effective light emitting area) of the pixel unit, and the spacer PS is configured to support the fine metal mask when forming the light emitting function layer EML.
  • FIG. 25 shows that spacers PS are provided on opposite sides of the light-emitting element, but it is not limited to this.
  • the data line is configured to input a data signal to the pixel unit
  • the first power signal line is configured to input a first power voltage to the driving transistor.
  • the second power signal line is configured to input a second power voltage to the pixel unit.
  • the first power supply voltage is a constant voltage
  • the second power supply voltage is a constant voltage.
  • the first power supply voltage is a positive voltage
  • the second power supply voltage is a negative voltage, but it is not limited thereto.
  • the first power supply voltage is a positive voltage
  • the second power supply signal line is grounded.
  • the first insulating layer ISL1 includes at least one of a first gate insulating layer GI1, a second gate insulating layer GI2, and an interlayer insulating layer ILD, and the second insulating layer ISL2 includes a planarization Layer PLN.
  • the first gate insulating layer GI1, the second gate insulating layer GI2, the interlayer insulating layer ILD, the passivation layer PVX, the planarization layer PLN, the pixel definition layer PDL and the spacer PS are all made of insulating materials.
  • the material of the first gate insulating layer GI1, the second gate insulating layer GI2, the interlayer insulating layer ILD, and the passivation layer PVX includes at least one of SiOx and SiNx, but is not limited thereto.
  • the planarization layer PLN, the pixel definition layer PDL, and the spacer PS may be made of organic insulating materials, for example, resin may be used, but not limited thereto.
  • the threshold compensation transistor T3 includes a first channel CN1 and a second channel CN2, and the first channel CN1 and the second channel CN2 are connected by a conductive portion CP.
  • the second wire L2 further includes a connecting arm L21.
  • the threshold compensation transistor T3 is a double-gate transistor, and the conductive part CP is in a floating state when the threshold compensation transistor T3 is turned off. It is easily affected by the surrounding line voltage and jumps. The voltage jump of the conductive part CP will affect the threshold compensation transistor.
  • the leakage current of T3 affects the light-emitting brightness of the pixel unit. Therefore, it is necessary to keep the voltage of the conductive part CP stable.
  • the stopper and the conductive part CP can be designed to form a capacitor, and the stopper can have a constant voltage signal to make it in a floating state.
  • the voltage of the conductive part CP also remains stable.
  • the stopper BK0, the stopper BK, and the connecting arm L21 mentioned in the embodiment of the present disclosure all play a role in stabilizing the voltage of the conductive portion CP.
  • the connecting arm L21 partially overlaps the conductive portion CP of the threshold compensation transistor T3 to form a capacitor C0, and a first gate insulating layer GI1 and a second gate insulating layer GI2 are provided between the connecting arm L21 and the conductive portion CP.
  • Fig. 24 also shows the second channel CN2.
  • the capacitor C0 can be referred to as a stable capacitor, and the connecting arm L21 and the conductive portion CP are the two plates of the capacitor C0.
  • the gate GE2 and the second channel CN2 overlap in a direction perpendicular to the base substrate BS.
  • the gate GE2 is a gate of the threshold compensation transistor T3.
  • the second connection electrode 31b is connected to the second electrode T32 of the threshold compensation transistor T3.
  • the second wire L2 further includes a connecting arm L21, and the connecting arm L21 and the conductive portion CP are spaced apart from each other in the third direction D3 and partially overlapped in the third direction D3 (refer to FIG. 24).
  • the shape of the connecting arm L21 includes a C shape.
  • the connecting arm L21 may be substantially C-shaped.
  • the connecting arm L21 may also adopt other shapes as long as it can stabilize the threshold compensation transistor T3.
  • the third direction D3 is perpendicular to the first direction D1 and perpendicular to the second direction D2, the third direction D3 is a direction perpendicular to the base substrate BS, and a first gate insulation is provided between the connecting arm L21 and the conductive portion CP.
  • the first direction D1 and the second direction D2 are directions parallel to the main surface of the base substrate BS
  • the third direction D3 is a direction perpendicular to the main surface of the base substrate BS.
  • Various elements are fabricated on the main surface of the base substrate BS.
  • the first portion L11 includes a first sub-portion La extending in the first direction D1 and a second sub-portion Lb extending in the second direction.
  • the second sub-portion Lb has branches that extend along the first direction. Extending in one direction D1, the stop BK0 is a branch of the second sub-part Lb.
  • the branch (stop BK0) of the second sub-portion Lb and the conductive portion of one pixel unit overlapping the first conductive line L1 in the pixel island are spaced apart from each other in the third direction D3, And partly overlap in the third direction D3. Referring to FIG. 17, FIG. 19 and FIG.
  • the branch (stop BK0) of the second sub-portion Lb is connected to a pixel unit (the pixel unit in the upper left corner of FIG. 24) that overlaps with the first wire L1 in the pixel island.
  • the parts CP are spaced apart from each other in the third direction D3, and partially overlap in the third direction D3.
  • the length of the branch (stop BK0) in the first direction D1 is smaller than the length of the first sub-portion La in the first direction D1.
  • the pixel circuit 10 includes a first transistor and a second transistor.
  • the first transistor is connected to the second transistor, the second transistor is connected to the light-emitting element, and the first transistor includes a first transistor.
  • the channel CN1 and the second channel CN2, the first channel CN1 and the second channel CN2 are connected by the conductive portion CP, the second wire L2 further includes a connecting arm L21, the connecting arm L21 and the second wire L2 in the pixel island
  • the conductive portions CP of an overlapping pixel unit (the pixel unit located at the lower left corner in FIG. 19) are spaced apart from each other in the third direction D3, and partially overlap in the third direction D3.
  • the above-mentioned first transistor and the second transistor are the threshold compensation transistor T3 and the light emission control transistor connected to the light emitting element in the pixel circuit 10, respectively.
  • the light-emission control transistor connected to the light-emitting element is the above-mentioned second light-emission control transistor T5.
  • the stopper or the connecting arm that forms a capacitor with the conductive portion CP in the first transistor in the pixel island can also take other forms, which are not limited here.
  • the stopper BK0 (the branch of the second sub-part Lb) and the connecting arm L21 are both connected to the third wire L3 of the pixel unit of this column, and the stopper BK is connected to it.
  • the initialization signal line 210 includes a plurality of hollow areas HP
  • the second wire L2 is located in a hollow area HP and is surrounded by the portion of the initialization signal line that surrounds the hollow area HP
  • the second wire L2 It does not overlap with the part of the initialization signal line that surrounds the hollowed-out area. That is, the second wire L2 is completely surrounded by the part of the initialization signal line that surrounds the hollow area HP.
  • the hollow area HP is a position corresponding to the part of the thin film that is removed when the initialization signal line 210 is made.
  • the first wire L1 includes a first portion L11 and a second portion L12, the first portion L11 of the first wire L1 and the second wire L2 are located on the same layer, and the second wire L1 The portion L12 is not located on the same layer as the second wire L2, and the second portion L12 of the first wire L1 at least partially overlaps the initialization signal line 210.
  • the first portion L11 of the first wire L1 and the second wire L2 are located on the second conductive pattern layer LY2, and the second portion L12 of the first wire L1 is located on the third conductive pattern layer LY3.
  • the second wire L2 is surrounded by a part of the initialization signal line 210, and the first portion L11 of the first wire L1 is surrounded by a part of the initialization signal line 210.
  • the second wire L2 is surrounded by the lower portion 210 a of the initialization signal line 210, and the first portion L11 of the first wire L1 is surrounded by the upper portion 210 b of the initialization signal line 210.
  • the data line 313 includes a first data line DL1.
  • the first data line DL1 extends from the first display area R1 to the second display area R2.
  • the orthographic projections on the base substrate BS partially overlap. This arrangement is beneficial to reduce the wiring area and increase the light transmittance.
  • the first data line DL1 includes a first portion DL11 and a second portion DL12, the first portion DL11 of the first data line DL1 partially overlaps the third conductive line L3, and the first data line DL1
  • the second portion DL12 and the third conductive line L4 do not overlap, and the first portion DL11 of the first data line DL1 and the second portion DL12 of the first data line DL1 are respectively located in different layers.
  • FIG. 19 is located on the second conductive pattern layer, and the second portion DL12 of the first data line DL1 on the left is located on the third conductive pattern layer, FIG. 19
  • the first portion DL11 (wire 114) of the first data line DL1 on the right side is located on the first conductive pattern layer, and the second portion DL12 of the first data line DL1 on the right side is located on the third conductive pattern layer.
  • the first portion DL11 of the first data line DL1 is located between adjacent pixel islands A1.
  • two first data lines DL1 are provided, the two first data lines DL1 are respectively connected to two adjacent columns of pixel units, and the two first data lines DL1 are connected to the same third conductive line L3.
  • the orthographic projections on the base substrate BS overlap. This arrangement allows the data lines located between the pixel islands in two adjacent columns of pixel units to be hidden under the third wire, thereby reducing the wiring area and improving the light transmittance.
  • the first wire L1 includes portions located in different layers, and the portions located in the different layers are connected by via holes penetrating the insulating layer.
  • the first wire L1 includes a first portion L11, a second portion L12, and a third portion L13.
  • the first portion L11 and the third portion L13 are located on the second conductive pattern layer LY2, and the second portion L12 is located on the third conductive pattern layer LY3.
  • the first part L11 and the second part L12 are connected through a via hole V41 that penetrates the insulating layer, and the third part L13 and the second part L12 are connected through a via hole V42 that penetrates the insulating layer.
  • an interlayer dielectric layer ILD is provided between the second conductive pattern layer LY2 and the third conductive pattern layer LY3, that is, the via hole V41 penetrates the interlayer dielectric layer ILD, and the via hole V42 penetrates the interlayer dielectric. Electric layer ILD.
  • a part of the first conductive line L1 (the second portion L12) and the third conductive line L3 are located on the same layer, and both are located on the third conductive pattern layer LY3.
  • the fourth conductive line L4 and the third conductive line L3 are located on the same layer, and both are located on the third conductive pattern layer LY3.
  • the display device can be a display device such as an Organic Light-Emitting Diode (OLED) display, as well as any TV, digital camera, mobile phone, watch, tablet computer, notebook computer, navigator, etc. that include these display devices. Products or parts.
  • OLED Organic Light-Emitting Diode
  • the first conductive line L1 may include a portion located in the first conductive pattern layer and a portion located in the second conductive pattern layer
  • the second conductive line L2 is composed of only the portion located in the second conductive pattern layer.
  • the third wire L3 is only composed of a portion located on the third conductive pattern layer
  • the fourth wire L43 is only composed of a portion located on the third conductive pattern layer
  • the fifth wire L5 may include a portion located on the first conductive pattern layer and a portion located on the second conductive pattern layer.
  • the part of the conductive pattern layer constitutes, but is not limited to this, and can be set as required.
  • the second pole C12 of the storage capacitor C1 of the pixel unit P0 is a part of the second wire L2 or a part of the first wire L1.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Signal Processing (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Electroluminescent Light Sources (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Control Of El Displays (AREA)
PCT/CN2021/094383 2020-06-04 2021-05-18 显示面板和显示装置 Ceased WO2021244279A1 (zh)

Priority Applications (7)

Application Number Priority Date Filing Date Title
EP21818977.7A EP4106001B1 (en) 2020-06-04 2021-05-18 Display panel and display device
US17/760,461 US12615928B2 (en) 2020-06-04 2021-05-18 Display panel and display device
EP25173421.6A EP4586786A3 (en) 2020-06-04 2021-05-18 Display panel and display device
JP2022533191A JP7716404B2 (ja) 2020-06-04 2021-05-18 表示パネル及び表示装置
US17/936,533 US20240114731A1 (en) 2020-06-04 2022-09-29 Display panel and display device
US18/166,874 US20230189596A1 (en) 2020-06-04 2023-02-09 Display panel and display device
JP2025061828A JP2025092740A (ja) 2020-06-04 2025-04-03 表示パネル及び表示装置

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CN202010498518.8 2020-06-04
CN202010498518.8A CN113764461B (zh) 2020-06-04 2020-06-04 显示面板和显示装置

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US17/760,461 A-371-Of-International US12615928B2 (en) 2020-06-04 2021-05-18 Display panel and display device
US17/936,533 Continuation US20240114731A1 (en) 2020-06-04 2022-09-29 Display panel and display device
US18/166,874 Continuation US20230189596A1 (en) 2020-06-04 2023-02-09 Display panel and display device

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US20240114731A1 (en) 2024-04-04
US12615928B2 (en) 2026-04-28
CN113764461A (zh) 2021-12-07
JP2025092740A (ja) 2025-06-19
JP7716404B2 (ja) 2025-07-31
CN117396032A (zh) 2024-01-12
EP4586786A3 (en) 2025-10-08
JP2023529038A (ja) 2023-07-07
US20230091142A1 (en) 2023-03-23
US20230189596A1 (en) 2023-06-15
EP4586786A2 (en) 2025-07-16
CN113764461B (zh) 2024-11-05
EP4106001A1 (en) 2022-12-21
EP4106001B1 (en) 2026-03-04
EP4106001A4 (en) 2023-10-04

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