WO2021238249A1 - 一种数据存储方法、装置、设备及可读存储介质 - Google Patents

一种数据存储方法、装置、设备及可读存储介质 Download PDF

Info

Publication number
WO2021238249A1
WO2021238249A1 PCT/CN2021/073323 CN2021073323W WO2021238249A1 WO 2021238249 A1 WO2021238249 A1 WO 2021238249A1 CN 2021073323 W CN2021073323 W CN 2021073323W WO 2021238249 A1 WO2021238249 A1 WO 2021238249A1
Authority
WO
WIPO (PCT)
Prior art keywords
transmission mode
volatile memory
target
data
target data
Prior art date
Application number
PCT/CN2021/073323
Other languages
English (en)
French (fr)
Inventor
蒋东东
赵雅倩
董刚
李仁刚
刘海威
杨宏斌
李辰
Original Assignee
浪潮电子信息产业股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 浪潮电子信息产业股份有限公司 filed Critical 浪潮电子信息产业股份有限公司
Priority to US17/927,716 priority Critical patent/US11698730B2/en
Publication of WO2021238249A1 publication Critical patent/WO2021238249A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/062—Securing storage systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/062—Securing storage systems
    • G06F3/0623—Securing storage systems in relation to content
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/50—Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems
    • G06F21/55—Detecting local intrusion or implementing counter-measures
    • G06F21/556—Detecting local intrusion or implementing counter-measures involving covert channels, i.e. data leakage between processes
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/60—Protecting data
    • G06F21/604—Tools and structures for managing or administering access control systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/78—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure storage of data
    • G06F21/79—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure storage of data in semiconductor storage media, e.g. directly-addressable memories
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/062—Securing storage systems
    • G06F3/0622—Securing storage systems in relation to access
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0629—Configuration or reconfiguration of storage systems
    • G06F3/0634—Configuration or reconfiguration of storage systems by changing the state or mode of one or more devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the present invention relates to the field of storage technology, in particular to a data storage method, device, equipment and readable storage medium.
  • the purpose of the present invention is to provide a data storage method, device, equipment and readable storage medium.
  • the memory characteristics of the volatile memory can be eliminated and data theft can be avoided.
  • the risk of data security can be guaranteed.
  • the present invention provides the following technical solutions:
  • a data storage method including:
  • the target transmission mode is different from the historical transmission mode determined after the volatile memory was last powered on;
  • the target data is mutually transmitted with the volatile memory.
  • the target transmission mode is the bit value change transmission mode
  • the mutual transmission of the target data with the volatile memory according to the target transmission mode includes:
  • the target transmission mode is the bit value change transmission mode
  • the mutual transmission of the target data with the volatile memory according to the target transmission mode includes:
  • the mutual transmission of the target data with the volatile memory according to the target transmission mode includes:
  • the bit stream is read from the volatile memory to obtain the target data.
  • the determining the target transmission mode from the bit value variable transmission mode and the bit value fixed transmission mode includes:
  • the fixed bit value transmission mode is the target transmission mode.
  • the obtaining the number of times of power-on of the volatile memory includes:
  • the obtaining the target data to be stored in the fixed storage address in the volatile memory includes:
  • a data storage device includes:
  • the target data acquisition module is configured to acquire target data to be stored in a fixed storage address in the volatile memory after the volatile memory is powered on;
  • the transmission mode determination module is used to determine the target transmission mode from the bit value change transmission mode and the bit value fixed transmission mode; the target transmission mode and the historical transmission determined after the volatile memory is last powered on Different modes;
  • the data transmission module is configured to transmit the target data to and from the volatile memory according to the target transmission mode.
  • a data storage device including:
  • Memory used to store computer programs
  • the processor is used to implement the steps of the above data storage method when the computer program is executed.
  • the target data to be stored in the fixed storage address in the volatile memory is obtained; from the bit value change transmission mode and the bit value fixed transmission mode, determine The target transmission mode is different; the target transmission mode is different from the historical transmission mode determined after the volatile memory is last powered on; according to the target transmission mode, the target data is exchanged with the volatile memory.
  • the target data for the target data that needs to be stored in a fixed storage address in the volatile memory, the target data is not stolen due to the volatile memory characteristics, which makes the target data insecure.
  • the optional transmission modes include bit value change transmission mode and bit value fixed transmission mode. Among them, the bit value change transmission mode, that is, when the target data is transmitted, the bit value in the bit stream of the target data will be modified; and the bit value fixed transmission mode , That is, when transmitting the target data, the bit stream of the target data will not be modified.
  • the target data can be exchanged with the volatile storage to ensure that the target data is stored in the volatile memory this time. There is a difference between the bit values of the target data stored in, which destroys the memory characteristics based on the volatile memory, and then obtains the prerequisites for the target data. It can ensure that the target data is prevented from being stolen after the power is off, and the security of the data is guaranteed.
  • the embodiments of the present invention also provide data storage devices, equipment, and readable storage media corresponding to the above-mentioned data storage method, which have the above-mentioned technical effects, and will not be repeated here.
  • Figure 1 is an implementation flowchart of a data storage method in an embodiment of the present invention
  • Figure 2 is a schematic diagram of the hardware architecture of an FPGA-based reasoning deep learning model
  • Figure 3 is a schematic diagram of an implementation of a data storage method in an embodiment of the present invention.
  • Figure 5 is a schematic structural diagram of a data storage device in an embodiment of the present invention.
  • Figure 6 is a schematic structural diagram of a data storage device in an embodiment of the present invention.
  • FIG. 7 is a schematic diagram of a specific structure of a data storage device in an embodiment of the present invention.
  • FIG. 1 is a flowchart of a data storage method in an embodiment of the present invention. The method includes the following steps:
  • RAM Random Access Memory
  • the target data is long-term unchanging data stored in a fixed storage address of the volatile memory.
  • the target data may be data that requires high security and is frequently used, such as model parameters of a deep learning model, or configuration parameters in important systems.
  • the target data to be stored can be obtained.
  • the target transmission mode is different from the historical transmission mode determined after the volatile memory is last powered on.
  • Data stored in a readable storage medium often needs to be stored in bits, that is, the storage medium stores potentials corresponding to "1" and "0".
  • the potential appears Change, to avoid the occurrence of data stolen due to the memory characteristics of volatile memory.
  • the bit value change transmission mode that is, when the target data is transmitted, the bit value in the bit stream of the target data is changed to make it different from the bit stream of the target data (that is, the bit value in the same storage location is reversed, Including "1" to "0" and “0" to “1”); while the bit value fixed transmission mode, when the bit stream of the target data is transmitted, the bit value in the bit stream is not changed.
  • different transmission modes are used alternately after power-on, so that even if the same data is stored in the volatile memory, memory characteristics of all bits corresponding to the target data will not appear, which can prevent data from being stolen.
  • bit value transmission mode There are many ways to change the bit value transmission mode, and one or more can be set in practical applications.
  • the method for determining the target transmission mode may be by recording the transmission mode of each power-on, and then quickly determine the target transmission mode of the target data after the current power-on.
  • the specific implementation process includes:
  • Step 1 Obtain the power-on times of the volatile memory
  • Step 2 If the number of power-on times is an even number, it is determined that the bit value change transmission mode is the target transmission mode
  • Step 3 If the number of power-on times is an odd number, it is determined that the bit value fixed transmission mode is the target transmission mode.
  • a host computer (such as a CPU) can be used to record the number of power-on times, that is, the above-mentioned step 1 can be specifically to obtain the number of power-on times from the host computer.
  • the number of power-on times is an even number and bit value change transmission mode one-to-one correspondence
  • the number of power-on times is odd number and bit value fixed transmission mode one-to-one correspondence
  • you can also The corresponding relationship is changed, such as one-to-one correspondence between the power-on times being an odd number and the bit value change transmission mode, and the power-on times being an even number and the bit value fixed transmission mode one-to-one correspondence.
  • the target data can be exchanged with the volatile memory according to the target transmission mode. That is, it is transferred to the volatile memory to store the target data, and the target data is read from the volatile memory.
  • the mutual transmission of target data includes but not limited to the following situations:
  • the target data transmission process includes:
  • Step 1 Flip the bit value of the target data bit by bit to obtain the flip bit stream corresponding to the target data
  • Step 2 Send the flipped bit stream to the volatile memory
  • Step 3 Read the flipped bit stream from the volatile memory
  • Step 4 Flip the flipped bit stream bit by bit to obtain the target data.
  • the bit value of the target data is flipped bit by bit, and the binary form of the target data is inverted, that is, "1" is flipped to "0", and "0" is flipped to "1". It should be noted that when the bit value of the target data is flipped, all of the bits can be flipped, or some bits can be flipped according to a certain rule, for example, one or more bits can be flipped.
  • the flipped bit stream is obtained after flipping, and the flipped bit stream is directly stored in the volatile memory, and then after the flipped bit stream is read from the volatile memory, the flipped bit stream needs to be correspondingly flipped to obtain the target data.
  • the target data transmission process includes:
  • Step 1 Perform shift processing on the bit stream of the target data to obtain the shift bit stream corresponding to the target data;
  • Step 2 Send the shifted bit stream to the volatile memory
  • Step 3 Read the shift bit stream from the volatile memory
  • Step 4 Shift and restore the shifted bit stream to obtain the target data.
  • the bit stream of the target data is "10101010”
  • the bit stream "10101010” can be shifted from the beginning to the end, and then the other positions are shifted forward in turn, "01010101".
  • the bit value of the bit that appears before and after the shift changes.
  • the shifted bit stream is shifted and restored, that is, the shifted bit stream is reversely shifted to obtain the target data.
  • the target data transmission process includes:
  • Step 1 Send the bit stream of the target data to the volatile memory
  • Step 2 Read the bit stream from the volatile memory to obtain the target data.
  • the target data to be stored in the fixed storage address in the volatile memory is obtained; from the bit value change transmission mode and the bit value fixed transmission mode, determine The target transmission mode is different; the target transmission mode is different from the historical transmission mode determined after the volatile memory is last powered on; according to the target transmission mode, the target data is exchanged with the volatile memory.
  • the target data for the target data that needs to be stored in a fixed storage address in the volatile memory, the target data is not stolen due to the volatile memory characteristics, which makes the target data insecure.
  • the optional transmission modes include bit value change transmission mode and bit value fixed transmission mode. Among them, the bit value change transmission mode, that is, when the target data is transmitted, the bit value in the bit stream of the target data will be modified; and the bit value fixed transmission mode , That is, when transmitting the target data, the bit stream of the target data will not be modified.
  • the target data can be exchanged with the volatile storage to ensure that the target data is stored in the volatile memory this time. There is a difference between the bit values of the target data stored in, which destroys the memory characteristics based on the volatile memory, and then obtains the prerequisites for the target data. It can ensure that the target data is prevented from being stolen after the power is off, and the security of the data is guaranteed.
  • the embodiments of the present invention also provide corresponding improvement solutions.
  • the same steps as in the above-mentioned embodiments or the corresponding steps can be referred to each other, and the corresponding beneficial effects can also be referred to each other, which will not be repeated in the preferred/improved embodiments herein.
  • the target data may specifically be model parameters of a deep learning model, so that the deep learning mode can be protected. That is, the above step S101 may specifically include:
  • Step 1 Obtain the model parameters of the deep learning model from the host computer
  • Step 2 Use model parameters as target data.
  • deep learning models are suitable for complex pattern recognition and require a large number of samples and expensive machines to be trained. They are high-value assets. Therefore, the trained models need to be protected.
  • the parameters of the deep learning model will be stored in the fixed address space of the volatile memory for a long time and remain unchanged for a long time. Because volatile memory will accumulate certain memory characteristics when storing fixed models and parameters for a long time, it may cause high-value reasoning models to be illegally copied and read.
  • the data storage method provided by the embodiment of the present invention, by constructing a method for periodically flipping to eliminate the memory characteristics of volatile memory, the deep learning model data can be better protected and illegal copying can be prevented.
  • the deep learning model mainly runs on two hardware architectures: GPU (Graphics Processing Unit) and FPGA (Field Programmable Gate Array).
  • GPU Graphics Processing Unit
  • FPGA Field Programmable Gate Array
  • the general FPGA solution uses a hard disk + CPU + FPGA + DDR (Double Data Rate, double-rate synchronous dynamic random access memory) architecture.
  • the model parameters are generally stored in the non-volatile CPU side Storage (such as mechanical hard disk, SATA (Serial Advanced Technology Attachment, Serial Advanced Technology Attachment) disk, NVME (Non-Volatile Memory express, non-volatile memory standard) disk, etc.); after power on, due to software encryption protection, Generally, it is impossible to crack model data at the software level.
  • the model parameters will be stored in the DDR on the FPGA side in clear code.
  • the FPGA program has an encryption function, and generally cannot be Cracked, volatile memory, after power failure, according to the characteristics of volatile, the model parameters should also be lost, and there should be no risk of being stolen.
  • the model and parameters of the inference device will not change easily, and after the device is powered on, it will be stored in a fixed address space of the volatile memory for a long time. After thousands of hours of operation, the volatile memory System characteristics tend to remember the level values of these model data. Even if the power is turned off and on again, if the CPU does not operate on the DDR, affected by the electrical design principle of the volatile memory, the volatile memory will easily change to the previously stored state for a long time, resulting in the model data stored in the volatile memory There is a risk of loss, and further property loss, and loss of relevant technological leadership.
  • the FPGA-based inference deep learning model is shown in Figure 2. After power on, the software running on the CPU downloads the encrypted model data in the hard disk to the DDR on the FPGA side, and then the FPGA performs deep learning calculations by extracting the data on the specific DDR address , And put the calculation result in DDR for CPU to read.
  • the relevant model parameters of deep learning will be downloaded to the fixed address area of DDR after power-on. Because it is an inference operation, the model parameters that have been trained and no longer need to be modified are used, so in this address area, the value of DDR Will stay the same for a long time. Due to the long-term effects of electrical stress, thermal effects, and electromigration, the voltage threshold of the relevant position of the DDR changes. Under the long-term effect, the relevant changes will produce physical accumulation, causing volatile memories such as DDR to have a certain memory effect, even after power failure When power is on, the CPU does not operate on the DDR, and the DDR can also restore the previous data, and the model parameters will also have security risks.
  • the number of times of writing 0 and 1 in the same address space of the DDR can be effectively balanced, and the probability of the memory effect of the DDR is reduced, thereby realizing the purpose of protecting model data.
  • the system framework is shown as in Fig. 3.
  • the implementation flow chart is shown in Figure 4.
  • the implementation process includes:
  • S2 The software divides the odd and even according to the number of startups this time, and sends the working mode to the FPGA.
  • the odd number sends the normal operating mode
  • the even number sends the inverted operating mode.
  • S3 The mode selector on the FPGA side selects the working mode of the bidirectional data interface between FPGA and DDR after receiving the working mode command word of the CPU.
  • the FPGA will flip the data according to the bit before writing the data to the DDR (for example, lut realizes the NOT gate); when the FPGA reads the DDR data to the CPU or deep learning unit, it will also do the same.
  • the data is flipped by bit. That is, to ensure that the data can be correctly parsed by the computing unit, and at the same time, 0 and 1 values are written into the same address space of the DDR with equal probability and balance. To ensure the same physical location, the number of times of writing 0 and 1 is approximately the same.
  • the balanced write data flip strategy can effectively eliminate the memory characteristics of volatile memory, reduce the risk of model data leakage, and form effective protection for high-value deep learning models, protect data assets, and maintain Technology leadership.
  • the embodiment of the present invention also provides a data storage device.
  • the data storage device described below and the data storage method described above can be referenced correspondingly.
  • the device includes the following modules:
  • the target data acquisition module 101 is configured to acquire target data to be stored in a fixed storage address in the volatile memory after the volatile memory is powered on;
  • the transmission mode determination module 102 is used to determine the target transmission mode from the bit value variable transmission mode and the bit value fixed transmission mode; the target transmission mode is different from the historical transmission mode determined after the volatile memory is last powered on;
  • the data transmission module 103 is used to transmit target data to and from the volatile memory according to the target transmission mode.
  • the target data to be stored in the fixed storage address in the volatile memory is obtained; from the bit value change transmission mode and the bit value fixed transmission mode, determine The target transmission mode is different; the target transmission mode is different from the historical transmission mode determined after the volatile memory is last powered on; according to the target transmission mode, the target data is exchanged with the volatile memory.
  • Optional transmission modes include bit value change transmission mode and bit value fixed transmission mode. Among them, bit value change transmission mode, that is, when the target data is transmitted, the bit value in the bit stream of the target data will be modified; and the bit value fixed transmission mode , That is, when the target data is transmitted, the bit stream of the target data will not be modified.
  • the target data can be exchanged with the volatile storage to ensure that the target data is stored in the volatile memory this time. There is a difference between the bit values of the target data stored in the, which destroys the memory characteristics based on the volatile memory, and then obtains the prerequisites for the target data. It can ensure that the target data is prevented from being stolen after the power is off, and the security of the data is guaranteed.
  • the data transmission module 103 is specifically configured to flip the bit value of the target data bit by bit to obtain the flip bit stream corresponding to the target data;
  • the flipped bit stream is sent to the volatile memory; the flipped bit stream is read from the volatile memory; the flipped bit stream is flipped bit by bit to obtain the target data.
  • the data transmission module 103 is specifically configured to perform shift processing on the bit stream of the target data to obtain the shift bit corresponding to the target data. Stream; send the shifted bitstream to the volatile memory; read the shifted bitstream from the volatile memory; shift and restore the shifted bitstream to obtain the target data.
  • the data transmission module 103 is specifically configured to send the bit stream of the target data to the volatile memory; from the volatile memory Read the bit stream to get the target data.
  • the transmission mode determining module 102 is specifically configured to obtain the power-on times of the volatile memory; if the power-on times is an even number, determine the bit value change transmission mode as the target transmission mode; if If the number of power-on times is an odd number, it is determined that the bit value fixed transmission mode is the target transmission mode.
  • the transmission mode determination module 102 is specifically configured to obtain the number of power-on times from the upper computer.
  • the target data acquisition module 101 is specifically configured to acquire the model parameters of the deep learning model from the upper computer; the model parameters are used as target data.
  • the embodiment of the present invention also provides a data storage device.
  • the data storage device described below and the data storage method described above can be referred to each other.
  • the data storage device includes:
  • the memory 332 is used to store computer programs
  • the processor 322 is configured to implement the steps of the data storage method in the foregoing method embodiment when the computer program is executed.
  • FIG. 7 is a schematic diagram of a specific structure of a data storage device provided by this embodiment.
  • the data storage device may have relatively large differences due to different configurations or performance, and may include one or more processors ( Central processing units (CPU) 322 (for example, one or more processors) and a memory 332, and the memory 332 stores one or more computer application programs 342 or data 344.
  • the memory 332 may be short-term storage or persistent storage.
  • the program stored in the memory 332 may include one or more modules (not shown in the figure), and each module may include a series of instruction operations on the data processing device.
  • the central processing unit 322 may be configured to communicate with the memory 332 and execute a series of instruction operations in the memory 332 on the data storage device 301.
  • the data storage device 301 may also include one or more power supplies 326, one or more wired or wireless network interfaces 350, one or more input and output interfaces 358, and/or one or more operating systems 341.
  • the steps in the data storage method described above can be implemented by the structure of the data storage device.
  • the embodiment of the present invention also provides a readable storage medium.
  • a readable storage medium described below and a data storage method described above can be referenced correspondingly.
  • the readable storage medium can specifically be a U disk, a mobile hard disk, a read-only memory (Read-Only Memory, ROM), a random access memory (Random Access Memory, RAM), a magnetic disk, or an optical disk that can store program codes. Readable storage medium.

Abstract

一种数据存储方法、装置、设备及可读存储介质，该方法包括: 在易失性存储器上电后，获取待存入易失性存储器中固定存储地址的目标数据; 从比特值变化传输模式和比特值固定传输模式中，确定出目标传输模式; 目标传输模式与易失性存储器上一次上电后所确定出的历史传输模式不同; 按照目标传输模式，与易失性存储器互传目标数据。该方法可保证目标数据在掉电后，避免发生数据被盗取，保障了数据的安全。

Description

一种数据存储方法、装置、设备及可读存储介质
本申请要求于2020年05月28日提交至中国专利局、申请号为202010469856.9、发明名称为“一种数据存储方法、装置、设备及可读存储介质”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及存储技术领域，特别是涉及一种数据存储方法、装置、设备及可读存储介质。
背景技术
易失性存储器在掉电后，通常按照易失性的特点，掉电之后，数据会丢失，不存在数据被盗取的风险。
但是，当存储在易失性存储器的某段固定的地址空间内数据，经过上千小时的运行，易失性存储器的系统特性会倾向于记住这些数据的电平值。也就是说，即使掉电再上电，如果CPU(Central Processing Unit，中央处理器)没有对易失性存储器进行操作，受易失性存储器的电气设计原理影响，易失性存储器会易于变为之前长期保存的状态。如此，便导致长期存储在易失性存储器中不变的数据具有盗取的风险，存在安全风险。
当易失性存储器中存储的数据至关重要时，可能会产生较大损失。例如，当存储的是深度学习模型的模型参数，可能会导致整个深度学习模型的被盗取。
综上所述，如何有效地消除易失性存储器的记忆特性等问题，是目前本领域技术人员急需解决的技术问题。
发明内容
本发明的目的是提供一种数据存储方法、装置、设备及可读存储介质，通过变化存储在易失性存储器中的数据比特值，可消除易失性存储器的记忆特点，避免出现数据盗取的风险，可保障数据安全。
为解决上述技术问题，本发明提供如下技术方案：
一种数据存储方法，包括：
在易失性存储器上电后，获取待存入所述易失性存储器中固定存储地址的目标数据；
从比特值变化传输模式和比特值固定传输模式中，确定出目标传输模式；所述目标传输模式与所述易失性存储器上一次上电后所确定出的历史传输模式不同；
按照所述目标传输模式，与所述易失性存储器互传所述目标数据。
优选地，若所述目标传输模式为所述比特值变化传输模式，则所述按照所述目标传输模式，与所述易失性存储器互传所述目标数据，包括：
按位翻转所述目标数据的比特值，得到所述目标数据对应的翻转比特流；
将所述翻转比特流发送给所述易失性存储器；
从所述易失性存储器中读取所述翻转比特流；
将所述翻转比特流按位翻转，得到所述目标数据。
优选地，若所述目标传输模式为所述比特值变化传输模式，则所述按照所述目标传输模式，与所述易失性存储器互传所述目标数据，包括：
对所述目标数据的比特流进行移位处理，得到所述目标数据对应的移位比特流；
将所述移位比特流发送给所述易失性存储器；
从所述易失性存储器中读取所述移位比特流；
对所述移位比特流移位恢复，得到所述目标数据。
优选地，若所述目标传输模式为所述比特值固定传输模式，则所述按照所述目标传输模式，与所述易失性存储器互传所述目标数据，包括：
将所述目标数据的比特流发送给所述易失性存储器；
从所述易失性存储器中读取所述比特流，得到所述目标数据。
优选地，所述从比特值变化传输模式和比特值固定传输模式中，确定出目标传输模式，包括：
获取所述易失性存储器的上电次数；
若所述上电次数为偶数，则确定所述比特值变化传输模式为所述目标传输模式；
若所述上电次数为奇数，则确定所述比特值固定传输模式为所述目标 传输模式。
优选地，所述获取所述易失性存储器的上电次数，包括：
从上位机中获取上电次数。
优选地，所述获取待存入易失性存储器中固定存储地址的目标数据，包括：
从上位机中获取深度学习模型的模型参数；
将所述模型参数作为所述目标数据。
一种数据存储装置，包括：
目标数据获取模块，用于在易失性存储器上电后，获取待存入所述易失性存储器中固定存储地址的目标数据；
传输模式确定模块，用于从比特值变化传输模式和比特值固定传输模式中，确定出目标传输模式；所述目标传输模式与所述易失性存储器上一次上电后所确定出的历史传输模式不同；
数据传输模块，用于按照所述目标传输模式，与所述易失性存储器互传所述目标数据。
一种数据存储设备，包括：
存储器，用于存储计算机程序；
处理器，用于执行所述计算机程序时实现上述数据存储方法的步骤。
一种可读存储介质，所述可读存储介质上存储有计算机程序，所述计算机程序被处理器执行时实现上述数据存储方法的步骤。
应用本发明实施例所提供的方法，在易失性存储器上电后，获取待存入易失性存储器中固定存储地址的目标数据；从比特值变化传输模式和比特值固定传输模式中，确定出目标传输模式；目标传输模式与易失性存储器上一次上电后所确定出的历史传输模式不同；按照目标传输模式，与易失性存储器互传目标数据。
在本方法中，对于需要固定存储到易失性存储器中固定存储地址的目标数据，为避免易失性的记忆特点导致目标数据被盗取，使得目标数据不安全。在上电存储目标数据时，首先选定与易失性存储器传输目标数据的传输模式。可选的传输模式有比特值变化传输模式以及比特值固定传输模式，其中，比特值变化传输模式，即传输目标数据时，会修改目标数据的 比特流中的比特值；而比特值固定传输模式，即传输目标数据时，不会修改目标数据的比特流。通过选择与上一次上电传输目标数据的传输方式不同的目标传输模式，按照该目标传输模型，与易失性存储互传目标数据，即可保证本次存储目标数据时，在易失性存储器中存储的目标数据的比特值之间存在区别，破坏了基于易失性存储器的记忆特点，进而得到目标数据的前提条件。可保证目标数据在掉电后，避免发生数据被盗取，保障了数据的安全。
相应地，本发明实施例还提供了与上述数据存储方法相对应的数据存储装置、设备和可读存储介质，具有上述技术效果，在此不再赘述。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本发明实施例中一种数据存储方法的实施流程图；
图2为一种基于FPGA的推理深度学习模型的硬件架构示意图；
图3为本发明实施例中一种数据存储方法的实施示意图；
图4为本发明实施例中一种数据存储方法的具体实施流程图；
图5为本发明实施例中一种数据存储装置的结构示意图；
图6为本发明实施例中一种数据存储设备的结构示意图；
图7为本发明实施例中一种数据存储设备的具体结构示意图。
具体实施方式
为了使本技术领域的人员更好地理解本发明方案，下面结合附图和具体实施方式对本发明作进一步的详细说明。显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
请参考图1，图1为本发明实施例中一种数据存储方法的流程图，该方法包括以下步骤：
S101、在易失性存储器上电后，获取待存入易失性存储器中固定存储地址的目标数据。
易失性存储器(Random Access Memory)，简称RAM，常用来存储和保存数据，是作为操作系统或其他正在运行程序的临时存储介质。
其中，目标数据为长期不变的存储在易失性存储器固定存储地址的数据。该目标数据可为安全性要求高，且使用频繁的数据，例如深度学习模型的模型参数，或重要系统中的配置参数等。
在易失性存储器上电之后，便可获取需存储的目标数据。
S102、从比特值变化传输模式和比特值固定传输模式中，确定出目标传输模式。
其中，目标传输模式与易失性存储器上一次上电后所确定出的历史传输模式不同。
数据存储到可读存储介质，往往需按比特位进行存储，即存储介质中存储的是与“1”和“0”对应的电位。在本实施例中，为了使得相同的数据，在不同的时间段(本文一次上电为一个时段，当然也可采用其他时段)存储在同一个易失性存储器中的固定位置时，使得电位出现变化，避免出现易失性存储器的记忆特点导致数据被盗取的情况发生。
其中，比特值变化传输模式，即在传输目标数据时，对目标数据的比特流中的比特值进行变化，使之与目标数据的比特流出现差异(即同一个存储位置的比特值出现翻转，包括“1”变为“0”，“0”变为“1”)；而比特值固定传输模式，则在传输目标数据的比特流时，不对比特流中的比特值进行改变。如此，上电交替采用不同的传输模式，便可使得易失性存储器中即便是存储同样的数据，也不会出现目标数据对应的全部比特位出现记忆特性，可避免数据被盗取。
比特值变化传输模式的方式有多种，在实际应用中可设置一种或多种。
具体的，目标传输模式的确定方式，可通过记录每一次上电的传输模式，进而快速确定本次上电后目标数据的目标传输模式。
还可通过记录上电次数，通过上电次数的奇数偶数的区别确定采用何 种传输模式。具体实现过程，包括：
步骤一、获取易失性存储器的上电次数；
步骤二、若上电次数为偶数，则确定比特值变化传输模式为目标传输模式；
步骤三、若上电次数为奇数，则确定比特值固定传输模式为目标传输模式。
为便于描述，下面将上述三个步骤结合起来进行说明。
其中，可利用上位机(如CPU)记录上电次数，即上述步骤一可具体为从上位机中获取上电次数。
需要说明的是，在上述步骤中，将上电次数为偶数与比特值变化传输模式一一对应，将上电次数为奇数与比特值固定传输模式一一对应；在实际应用中，还可将对应关系进行变化，如将上电次数为奇数与比特值变化传输模式一一对应，将上电次数为偶数与比特值固定传输模式一一对应。
S103、按照目标传输模式，与易失性存储器互传目标数据。
确定目标传输模式之后，便可按照该目标传输模式与易失性存储器互换目标数据。即传输给易失性存储器存储目标数据，从易失性存储器中读取目标数据。
基于目标传输模式不同，目标数据的互传方式包括但不限于以下几种情况：
情况一：若目标传输模式为比特值变化传输模式，目标数据的传输过程，包括：
步骤一、按位翻转目标数据的比特值，得到目标数据对应的翻转比特流；
步骤二、将翻转比特流发送给易失性存储器；
步骤三、从易失性存储器中读取翻转比特流；
步骤四、将翻转比特流按位翻转，得到目标数据。
其中，按位翻转目标数据的比特值，将对二进制形式的目标数据的取反，即将“1”翻转为“0”，将“0”翻转为“1”。需要说明的是，翻转目标数据的比特值时，可全部均进行翻转，也可按照一定规律对部分比特进行翻转，例如间隔一位或多位进行翻转。
翻转后得到翻转比特流，直接将翻转比特流存入易失性存储器，而后从易失性存储器中读取翻转比特流之后，也需对应进行翻转进而得到目标数据。
情况二：若目标传输模式为比特值变化传输模式，则目标数据的传输过程，包括：
步骤一、对目标数据的比特流进行移位处理，得到目标数据对应的移位比特流；
步骤二、将移位比特流发送给易失性存储器；
步骤三、从易失性存储器中读取移位比特流；
步骤四、对移位比特流移位恢复，得到目标数据。
例如，当目标数据的比特流为“10101010”，则可对比特流“10101010”将首位移至末尾，然后其他位置依次向前移位，“01010101”。如此，移位前后便出现的比特位的比特值变化。当然，从易失性存储器中读取到移位比特流之后，对移位比特流进行移位恢复，即对移位比特流进行反移位，得到目标数据。
情况三：若目标传输模式为比特值固定传输模式，则目标数据的传输过程，包括：
步骤一、将目标数据的比特流发送给易失性存储器；
步骤二、从易失性存储器中读取比特流，得到目标数据。
对于未进行比特值变化的传输方式，即直接对目标数据的传输，无需在传输前后进行变化操作。
应用本发明实施例所提供的方法，在易失性存储器上电后，获取待存入易失性存储器中固定存储地址的目标数据；从比特值变化传输模式和比特值固定传输模式中，确定出目标传输模式；目标传输模式与易失性存储器上一次上电后所确定出的历史传输模式不同；按照目标传输模式，与易失性存储器互传目标数据。
在本方法中，对于需要固定存储到易失性存储器中固定存储地址的目标数据，为避免易失性的记忆特点导致目标数据被盗取，使得目标数据不安全。在上电存储目标数据时，首先选定与易失性存储器传输目标数据的传输模式。可选的传输模式有比特值变化传输模式以及比特值固定传输模 式，其中，比特值变化传输模式，即传输目标数据时，会修改目标数据的比特流中的比特值；而比特值固定传输模式，即传输目标数据时，不会修改目标数据的比特流。通过选择与上一次上电传输目标数据的传输方式不同的目标传输模式，按照该目标传输模型，与易失性存储互传目标数据，即可保证本次存储目标数据时，在易失性存储器中存储的目标数据的比特值之间存在区别，破坏了基于易失性存储器的记忆特点，进而得到目标数据的前提条件。可保证目标数据在掉电后，避免发生数据被盗取，保障了数据的安全。
需要说明的是，基于上述实施例，本发明实施例还提供了相应的改进方案。在优选/改进实施例中涉及与上述实施例中相同步骤或相应步骤之间可相互参考，相应的有益效果也可相互参照，在本文的优选/改进实施例中不再一一赘述。
优选地，该目标数据可具体为深度学习模型的模型参数，如此便可深度学习模式进行保护。即上述步骤S101可具体包括：
步骤一、从上位机中获取深度学习模型的模型参数；
步骤二、将模型参数作为目标数据。
为便于理解，下面针对在易失性存储器中存储深度学习模型的模型参数的具体应用场景对数据存储方法进行说明。
在深度学习领域，深度学习模型适合复杂的模式识别，需要大量的样本以及高昂的机器才能训练获得，是高价值资产，因此需要对训练出来的模型进行保护。在推理应用场景中，深度学习模型参数会长时间存储到易失性存储器的固定地址空间中，并且长时间保持不变。由于易失性存储器在长期存储固定模型和参数时，会累积产生一定的记忆特性，可能导致高价值推理模型被非法复制和读出。采用本发明实施例所提供的数据存储方法，通过构建一种定期翻转消除易失性存储器记忆特性的方法，可以更好地的保护深度学习的模型数据，防止非法复制。
目前，深度学习模型主要运行在GPU(Graphics Processing Unit，图形处理器)和FPGA(Field Programmable Gate Array，现场可编程门阵列)两种硬件架构上。其中，一般FPGA的方案，采用硬盘+CPU+FPGA+DDR (Double Data Rate，双倍速率同步动态随机存储器)的架构，在掉电的情况下，模型参数一般都存储在CPU端的非易失性存储器上(如机械硬盘，SATA(Serial Advanced Technology Attachment，串行高级技术附件)盘，NVME(Non-Volatile Memory express，非易失存储器标准)盘等)；上电后，由于软件的加密保护，一般无法通过软件层面破解模型数据，为了实现FPGA的快速计算(卷积，全连接网络等)，会将模型参数通过明码的方式存储到FPGA端的DDR中，FPGA的程序有加密功能，一般无法被破解，易失性存储器在掉电后，按照易失性的特点，模型参数也应该也应丢失，不应该有被盗取的风险。
但是，因为推理设备的模型和参数不会轻易改变，并且在设备上电后，会长期存储在易失性存储器的某段固定的地址空间内，经过上千小时的运行，易失性存储器的系统特性会倾向于记住这些模型数据的电平值。即使掉电再上电，如果CPU没有对DDR进行操作，受易失性存储器的电气设计原理影响，易失性存储器会易于变为之前长期保存的状态，导致易失性存储器中存储的模型数据具有丢失的风险，进而财产损失，并丧失相关技术领先优势。
为了降低上述模型数据丢失风险，消除易失性存储器的记忆特性是非常重要的。在断电前，先清空易失性存储器中的相关数据，然后再掉电，也不能有效的消除易失性存储器在长期保持相同数据时的记忆特性，重新上电后，易失性存储器依然具有一定的记忆性。
基于FPGA的推理深度学习模型如图2所示，上电后，CPU运行的软件将硬盘中加密的模型数据下载到FPGA端的DDR中，然后FPGA通过提取特定DDR地址上的数据，进行深度学习计算，并将计算结果放在DDR中，供CPU读取。
深度学习的相关模型参数，在上电后会下载到DDR固定的地址区域，因为是推理运算，使用的是已经训练好且不再需要修改的模型参数，所以在此地址区域内，DDR的数值会长期保持不变。由于电应力、热效应以及电迁移等长期作用，造成DDR相关位置的电压门限改变，长期作用下，相关改变会产生物理累积，造成DDR等易失性存储器具有一定的记忆效应，即使在掉电后上电，CPU不对DDR进行操作，DDR也可以恢复出之 前的数据，模型参数也会存在安全风险。
采用本发明实施例所提供的数据存储方法，能够有效均衡DDR相同地址空间写入0和1的次数，降低DDR产生记忆效应的概率，进而实现对模型数据保护的目的。系统框架如图3所示。
实施流程图如图4所示，实施流程包括：
S1：CPU软件端在硬盘上记录设备的启动次数。每次上电运行软件，该计数器都会加一。
S2：软件根据本次启动次数，分奇偶，给FPGA下发工作模式，奇数发送正常工作模式，偶数发送翻转工作模式。
S3：FPGA端的模式选择器，在接收到CPU的工作模式命令字后，对FPGA和DDR之间的双向数据接口进行工作模式选择。
S4：如果工作在正常工作模式，则FPGA不对DDR的读写数据进行任何处理。读写DDR的数据和CPU端数据完全一致。
S5：如果工作在翻转工作模式，则FPGA在将数据写入DDR前，会对数据进行按照bit翻转(如lut实现非门)；当FPGA读出DDR数据给CPU或深度学习单元前，也对数据进行按bit翻转。即保证数据可以被计算单元正确解析，同时也将0和1值以等概率、均衡地写入DDR相同地址空间。保证相同物理位置，写入0和1的次数大致相同。
由此可见，通过均衡写入数据翻转策略，可以有效的消除易失性存储器的记忆特性，降低模型数据泄露的风险，可以对高价值的深度学习模型形成有效的保护，保护数据资产，并保持技术领先性。
相应于上面的方法实施例，本发明实施例还提供了一种数据存储装置，下文描述的数据存储装置与上文描述的数据存储方法可相互对应参照。
参见图5所示，该装置包括以下模块：
目标数据获取模块101，用于在易失性存储器上电后，获取待存入易失性存储器中固定存储地址的目标数据；
传输模式确定模块102，用于从比特值变化传输模式和比特值固定传输模式中，确定出目标传输模式；目标传输模式与易失性存储器上一次上电后所确定出的历史传输模式不同；
数据传输模块103，用于按照目标传输模式，与易失性存储器互传目标数据。
应用本发明实施例所提供的装置，在易失性存储器上电后，获取待存入易失性存储器中固定存储地址的目标数据；从比特值变化传输模式和比特值固定传输模式中，确定出目标传输模式；目标传输模式与易失性存储器上一次上电后所确定出的历史传输模式不同；按照目标传输模式，与易失性存储器互传目标数据。
在本装置中，对于需要固定存储到易失性存储器中固定存储地址的目标数据，为避免易失性的记忆特点导致目标数据被盗取，使得目标数据不安全。在上电存储目标数据时，首先选定与易失性存储器传输目标数据的传输模式。可选的传输模式有比特值变化传输模式以及比特值固定传输模式，其中，比特值变化传输模式，即传输目标数据时，会修改目标数据的比特流中的比特值；而比特值固定传输模式，即传输目标数据时，不会修改目标数据的比特流。通过选择与上一次上电传输目标数据的传输方式不同的目标传输模式，按照该目标传输模型，与易失性存储互传目标数据，即可保证本次存储目标数据时，在易失性存储器中存储的目标数据的比特值之间存在区别，破坏了基于易失性存储器的记忆特点，进而得到目标数据的前提条件。可保证目标数据在掉电后，避免发生数据被盗取，保障了数据的安全。
在本发明的一种具体实施方式中，若目标传输模式为比特值变化传输模式，则数据传输模块103，具体用于按位翻转目标数据的比特值，得到目标数据对应的翻转比特流；将翻转比特流发送给易失性存储器；从易失性存储器中读取翻转比特流；将翻转比特流按位翻转，得到目标数据。
在本发明的一种具体实施方式中，若目标传输模式为比特值变化传输模式，则数据传输模块103，具体用于对目标数据的比特流进行移位处理，得到目标数据对应的移位比特流；将移位比特流发送给易失性存储器；从易失性存储器中读取移位比特流；对移位比特流移位恢复，得到目标数据。
在本发明的一种具体实施方式中，若目标传输模式为比特值固定传输模式，则数据传输模块103，具体用于将目标数据的比特流发送给易失性存储器；从易失性存储器中读取比特流，得到目标数据。
在本发明的一种具体实施方式中，传输模式确定模块102，具体用于获取易失性存储器的上电次数；若上电次数为偶数，则确定比特值变化传输模式为目标传输模式；若上电次数为奇数，则确定比特值固定传输模式为目标传输模式。
在本发明的一种具体实施方式中，传输模式确定模块102，具体用于从上位机中获取上电次数。
在本发明的一种具体实施方式中，目标数据获取模块101，具体用于从上位机中获取深度学习模型的模型参数；将模型参数作为目标数据。
相应于上面的方法实施例，本发明实施例还提供了一种数据存储设备，下文描述的一种数据存储设备与上文描述的一种数据存储方法可相互对应参照。
参见图6所示，该数据存储设备包括：
存储器332，用于存储计算机程序；
处理器322，用于执行计算机程序时实现上述方法实施例的数据存储方法的步骤。
具体的，请参考图7，为本实施例提供的一种数据存储设备的具体结构示意图，该数据存储设备可因配置或性能不同而产生比较大的差异，可以包括一个或一个以上处理器(central processing units，CPU)322(例如，一个或一个以上处理器)和存储器332，存储器332存储有一个或一个以上的计算机应用程序342或数据344。其中，存储器332可以是短暂存储或持久存储。存储在存储器332的程序可以包括一个或一个以上模块(图示没标出)，每个模块可以包括对数据处理设备中的一系列指令操作。更进一步地，中央处理器322可以设置为与存储器332通信，在数据存储设备301上执行存储器332中的一系列指令操作。
数据存储设备301还可以包括一个或一个以上电源326，一个或一个以上有线或无线网络接口350，一个或一个以上输入输出接口358，和/或，一个或一个以上操作系统341。
上文所描述的数据存储方法中的步骤可以由数据存储设备的结构实现。
相应于上面的方法实施例，本发明实施例还提供了一种可读存储介质，下文描述的一种可读存储介质与上文描述的一种数据存储方法可相互对应参照。
一种可读存储介质，可读存储介质上存储有计算机程序，计算机程序被处理器执行时实现上述方法实施例的数据存储方法的步骤。
该可读存储介质具体可以为U盘、移动硬盘、只读存储器(Read-Only Memory，ROM)、随机存取存储器(Random Access Memory，RAM)、磁碟或者光盘等各种可存储程序代码的可读存储介质。
本领域技术人员还可以进一步意识到，结合本文中所公开的实施例描述的各示例的单元及算法步骤，能够以电子硬件、计算机软件或者二者的结合来实现，为了清楚地说明硬件和软件的可互换性，在上述说明中已经按照功能一般性地描述了各示例的组成及步骤。这些功能究竟以硬件还是软件方式来执行，取决于技术方案的特定应用和设计约束条件。本领域技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本发明的范围。

Claims (10)

  1. 一种数据存储方法，其特征在于，包括：
    在易失性存储器上电后，获取待存入所述易失性存储器中固定存储地址的目标数据；
    从比特值变化传输模式和比特值固定传输模式中，确定出目标传输模式；所述目标传输模式与所述易失性存储器上一次上电后所确定出的历史传输模式不同；
    按照所述目标传输模式，与所述易失性存储器互传所述目标数据。
  2. 根据权利要求1所述的数据存储方法，其特征在于，若所述目标传输模式为所述比特值变化传输模式，则所述按照所述目标传输模式，与所述易失性存储器互传所述目标数据，包括：
    按位翻转所述目标数据的比特值，得到所述目标数据对应的翻转比特流；
    将所述翻转比特流发送给所述易失性存储器；
    从所述易失性存储器中读取所述翻转比特流；
    将所述翻转比特流按位翻转，得到所述目标数据。
  3. 根据权利要求1所述的数据存储方法，其特征在于，若所述目标传输模式为所述比特值变化传输模式，则所述按照所述目标传输模式，与所述易失性存储器互传所述目标数据，包括：
    对所述目标数据的比特流进行移位处理，得到所述目标数据对应的移位比特流；
    将所述移位比特流发送给所述易失性存储器；
    从所述易失性存储器中读取所述移位比特流；
    对所述移位比特流移位恢复，得到所述目标数据。
  4. 根据权利要求1所述的数据存储方法，其特征在于，若所述目标传输模式为所述比特值固定传输模式，则所述按照所述目标传输模式，与所述易失性存储器互传所述目标数据，包括：
    将所述目标数据的比特流发送给所述易失性存储器；
    从所述易失性存储器中读取所述比特流，得到所述目标数据。
  5. 根据权利要求1所述的数据存储方法，其特征在于，所述从比特值 变化传输模式和比特值固定传输模式中，确定出目标传输模式，包括：
    获取所述易失性存储器的上电次数；
    若所述上电次数为偶数，则确定所述比特值变化传输模式为所述目标传输模式；
    若所述上电次数为奇数，则确定所述比特值固定传输模式为所述目标传输模式。
  6. 根据权利要求5所述的数据存储方法，其特征在于，所述获取所述易失性存储器的上电次数，包括：
    从上位机中获取上电次数。
  7. 根据权利要求1所述的数据存储方法，其特征在于，所述获取待存入易失性存储器中固定存储地址的目标数据，包括：
    从上位机中获取深度学习模型的模型参数；
    将所述模型参数作为所述目标数据。
  8. 一种数据存储装置，其特征在于，包括：
    目标数据获取模块，用于在易失性存储器上电后，获取待存入所述易失性存储器中固定存储地址的目标数据；
    传输模式确定模块，用于从比特值变化传输模式和比特值固定传输模式中，确定出目标传输模式；所述目标传输模式与所述易失性存储器上一次上电后所确定出的历史传输模式不同；
    数据传输模块，用于按照所述目标传输模式，与所述易失性存储器互传所述目标数据。
  9. 一种数据存储设备，其特征在于，包括：
    存储器，用于存储计算机程序；
    处理器，用于执行所述计算机程序时实现如权利要求1至7任一项所述数据存储方法的步骤。
  10. 一种可读存储介质，其特征在于，所述可读存储介质上存储有计算机程序，所述计算机程序被处理器执行时实现如权利要求1至7任一项所述数据存储方法的步骤。
PCT/CN2021/073323 2020-05-28 2021-01-22 一种数据存储方法、装置、设备及可读存储介质 WO2021238249A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US17/927,716 US11698730B2 (en) 2020-05-28 2021-01-22 Data storage method, apparatus, and device, and readable storage medium

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202010469856.9 2020-05-28
CN202010469856.9A CN111722799B (zh) 2020-05-28 2020-05-28 一种数据存储方法、装置、设备及可读存储介质

Publications (1)

Publication Number Publication Date
WO2021238249A1 true WO2021238249A1 (zh) 2021-12-02

Family

ID=72565291

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2021/073323 WO2021238249A1 (zh) 2020-05-28 2021-01-22 一种数据存储方法、装置、设备及可读存储介质

Country Status (3)

Country Link
US (1) US11698730B2 (zh)
CN (1) CN111722799B (zh)
WO (1) WO2021238249A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117335898A (zh) * 2023-12-01 2024-01-02 成都华兴大地科技有限公司 一种基于fpga软件的tr模块快速自动提数的方法

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111722799B (zh) 2020-05-28 2024-02-09 浪潮电子信息产业股份有限公司 一种数据存储方法、装置、设备及可读存储介质

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090138655A1 (en) * 2007-11-23 2009-05-28 Samsung Electronics Co. Ltd. Method and terminal for demand paging at least one of code and data requiring real-time response
CN103268294A (zh) * 2013-04-19 2013-08-28 深圳创维数字技术股份有限公司 一种存取数据的操作方法和数据处理设备
CN104166523A (zh) * 2014-08-08 2014-11-26 上海新储集成电路有限公司 一种存储器及提高计算机系统加载数据速率的方法
CN110895477A (zh) * 2018-09-13 2020-03-20 杭州海康威视数字技术股份有限公司 一种设备启动方法、装置及设备
CN111722799A (zh) * 2020-05-28 2020-09-29 浪潮电子信息产业股份有限公司 一种数据存储方法、装置、设备及可读存储介质

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA2053261A1 (en) * 1989-04-28 1990-10-29 Gary D. Hornbuckle Method and apparatus for remotely controlling and monitoring the use of computer software
JP3607407B2 (ja) * 1995-04-26 2005-01-05 株式会社日立製作所 半導体記憶装置
US7369422B2 (en) * 2006-02-23 2008-05-06 Laurence Hager Cooke Serial content addressable memory
US10359949B2 (en) * 2011-10-31 2019-07-23 Apple Inc. Systems and methods for obtaining and using nonvolatile memory health information
JP5795697B2 (ja) * 2012-05-16 2015-10-14 サイデンス コーポレーション メモリデバイス用の電源投入検出システム
US8861283B1 (en) * 2012-09-06 2014-10-14 Altera Corporation Systems and methods for reducing leakage current in memory arrays
US9196339B2 (en) * 2013-09-30 2015-11-24 Qualcomm Incorporated Resistance-based memory cells with multiple source lines
US9557936B2 (en) * 2014-12-31 2017-01-31 Texas Instruments Incorporated Protection of memories, datapath and pipeline registers, and other storage elements by distributed delayed detection and correction of soft errors
CN112036196A (zh) * 2019-06-03 2020-12-04 广州智慧城市发展研究院 一种适用于iso14443协议阅读器的编码模块
CN110943913A (zh) * 2019-07-31 2020-03-31 广东互动电子网络媒体有限公司 一种工业安全隔离网关
JP7048195B2 (ja) * 2019-12-12 2022-04-05 株式会社大一商会 遊技機

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090138655A1 (en) * 2007-11-23 2009-05-28 Samsung Electronics Co. Ltd. Method and terminal for demand paging at least one of code and data requiring real-time response
CN103268294A (zh) * 2013-04-19 2013-08-28 深圳创维数字技术股份有限公司 一种存取数据的操作方法和数据处理设备
CN104166523A (zh) * 2014-08-08 2014-11-26 上海新储集成电路有限公司 一种存储器及提高计算机系统加载数据速率的方法
CN110895477A (zh) * 2018-09-13 2020-03-20 杭州海康威视数字技术股份有限公司 一种设备启动方法、装置及设备
CN111722799A (zh) * 2020-05-28 2020-09-29 浪潮电子信息产业股份有限公司 一种数据存储方法、装置、设备及可读存储介质

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117335898A (zh) * 2023-12-01 2024-01-02 成都华兴大地科技有限公司 一种基于fpga软件的tr模块快速自动提数的方法
CN117335898B (zh) * 2023-12-01 2024-02-27 成都华兴大地科技有限公司 一种基于fpga软件的tr模块快速自动提数的方法

Also Published As

Publication number Publication date
CN111722799B (zh) 2024-02-09
US20230133665A1 (en) 2023-05-04
CN111722799A (zh) 2020-09-29
US11698730B2 (en) 2023-07-11

Similar Documents

Publication Publication Date Title
CN110832590B (zh) 在基于相变存储器的存储设备中减轻写入放大的方法和系统
US5963970A (en) Method and apparatus for tracking erase cycles utilizing active and inactive wear bar blocks having first and second count fields
WO2021238249A1 (zh) 一种数据存储方法、装置、设备及可读存储介质
US8862806B2 (en) Semiconductor storage device and method of throttling performance of the same
CN111095223A (zh) 通过存储器总线实现主动持久存储器的方法和系统
US8782428B2 (en) Encryption device and encryption method
US20120324156A1 (en) Method and system of organizing a heterogeneous memory architecture
US10698840B2 (en) Method and apparatus to generate zero content over garbage data when encryption parameters are changed
KR20090019819A (ko) 시행착오에 의한 에러 보정 디코딩
US8732436B2 (en) Device for storing data by utilizing pseudorandom number sequence
US10929251B2 (en) Data loss prevention for integrated memory buffer of a self encrypting drive
CN106415502A (zh) 数据存储的方法和装置
KR102282879B1 (ko) 고체 상태 드라이브의 전송 버퍼 사용률을 향상시키기 위해 nand 페이지 버퍼들을 사용하는 방법 및 시스템
US10552643B2 (en) Fast boot up memory controller
JP2017033500A (ja) 記憶装置およびデータ退避方法
US9235532B2 (en) Secure storage of full disk encryption keys
US9135002B1 (en) Systems and methods for recovering an application on a computing device
KR20160080742A (ko) 메모리 컨트롤러, 그 동작 방법 및 이를 포함하는 메모리 시스템
US20200233604A1 (en) Information processing apparatus, storage control apparatus, and recording medium
US10289326B2 (en) Optimized data layout for object store system
US20160026582A1 (en) Encrypt data of storage device
US10785024B2 (en) Encryption key structure within block based memory
US20220114112A1 (en) Algebraic and deterministic memory authentication and correction with coupled cacheline metadata
JP7101500B2 (ja) 暗号化装置、暗号化システム、及び暗号化方法
KR20230056920A (ko) 스토리지 장치의 구동 방법 및 이를 이용한 스토리지 시스템의 구동 방법

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 21813307

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 21813307

Country of ref document: EP

Kind code of ref document: A1