WO2021237540A1

WO2021237540A1 - Display panel and display apparatus

Info

Publication number: WO2021237540A1
Application number: PCT/CN2020/092731
Authority: WO
Inventors: 高永益; 王本莲; 黄炜赟; 龙跃; 程羽雕
Original assignee: 京东方科技集团股份有限公司; 成都京东方光电科技有限公司
Priority date: 2020-05-27
Filing date: 2020-05-27
Publication date: 2021-12-02
Also published as: EP3996083A4; CN113994419A; US20220199734A1; CN113994419B; JP2023536370A; EP3996083A1

Abstract

Provided are a display panel and a display apparatus. The display panel comprises a conventional display area; a winding area, wherein the conventional display area surrounds the winding area; a notch area, wherein the winding area surrounds the notch area; a plurality of pixel drive circuits, which are located in the conventional display area; and a plurality of light-emitting devices, which are located on the side of the pixel drive circuits that is away from a base substrate, wherein one pixel drive circuit is correspondingly electrically connected to one light-emitting device; an orthographic projection of at least one of the plurality of light-emitting devices on the base substrate overlaps with the winding area, and orthographic projections of the other light-emitting devices are located in the conventional display area; and the light-emitting device of which the orthographic projection on the base substrate overlaps with the winding area is electrically connected to the pixel drive circuits by means of a first conductive wire, and the first conductive wire extends from the conventional display area to the winding area.

Description

Display panel and display device

Technical field

The embodiments of the present disclosure relate to the field of display technology, and in particular to a display panel and a display device.

Background technique

Organic Light Emitting Diode (OLED), Quantum Dot Light Emitting Diodes (QLED), Micro Light Emitting Diode (Micro LED) and other electroluminescent diodes have self-luminous, low energy consumption, etc. The advantages are one of the hot spots in the application research field of electroluminescent display devices.

Summary of the invention

The display panel provided by the embodiment of the present disclosure includes:

Conventional display area;

A winding area, wherein the conventional display area surrounds the winding area;

A gap area, wherein the winding area surrounds the gap area;

Multiple pixel drive circuits located in the conventional display area;

A plurality of light-emitting devices are located on a side of the pixel drive circuit away from the base substrate, and one of the pixel drive circuits is electrically connected to one of the light-emitting devices;

Wherein, the orthographic projection of at least one of the plurality of light-emitting devices on the base substrate overlaps the winding area, and the remaining light-emitting devices are located in the conventional display area;

The light emitting device overlapping the orthographic projection of the base substrate and the winding area is electrically connected to the corresponding pixel driving circuit through a first conductive line, and the first conductive line extends from the conventional display area To the winding area.

Optionally, in the embodiment of the present disclosure, the conventional display area includes: a first area, a second area, and a third area arranged in a second direction;

The second area includes a first sub-area and a second sub-area arranged along a first direction; wherein the first sub-area and the second sub-area are separated by the notch area;

The orthographic projection of the light emitting device in the second direction that overlaps the orthographic projection of the base substrate and the winding area is located in at least one of the first sub-area and the second sub-area .

Optionally, in the embodiment of the present disclosure, the light-emitting devices in the first region and the third region are first light-emitting devices, and the light-emitting region of each first light-emitting device is located on the front side of the base substrate. The area enclosed by the projection is roughly equal;

The pixel driving circuit electrically connected to the first light-emitting device is a first pixel driving circuit, and the area enclosed by the orthographic projection of each of the first pixel driving circuits on the base substrate is approximately the same.

Optionally, in the embodiment of the present disclosure, the light-emitting device overlapping the orthographic projection of the base substrate and the winding area is a second light-emitting device, and a pixel drive circuit electrically connected to the second light-emitting device Is the second pixel driving circuit;

The area of the light-emitting area of the second light-emitting device enclosed by the orthographic projection of the base substrate is larger than the area of the light-emitting area enclosed by the orthographic projection of the first light-emitting device.

Optionally, in the embodiment of the present disclosure, along the first direction and directed from the notch area to at least one of the first sub-area and the second sub-area, the second light-emitting device The area of the light-emitting area enclosed by the orthographic projection of the base substrate decreases successively.

Optionally, in the embodiment of the present disclosure, the area of the area enclosed by the orthographic projection of the light-emitting area of each of the second light-emitting devices on the base substrate is approximately the same.

Optionally, in the embodiment of the present disclosure, the area enclosed by the orthographic projection of each of the second pixel drive circuits on the base substrate and the orthographic projection of the first pixel drive circuit on the base substrate The area of the enclosed area is approximately equal.

Optionally, in the embodiment of the present disclosure, the second pixel driving circuit is located in the same column as the first pixel driving circuit in the first area and the second area, respectively.

Optionally, in the embodiment of the present disclosure, the orthographic projection of the light-emitting area of the first light-emitting device on the base substrate has a first width along the first direction, and the light-emitting area of the first light-emitting device The orthographic projection of the light-emitting area on the base substrate has a second width along the second direction;

The orthographic projection of the light-emitting area of the second light-emitting device on the base substrate has a third width along the first direction, and the orthographic projection of the light-emitting area of the second light-emitting device on the base substrate Having a fourth width along the second direction;

The third width is greater than the first width, and the second width is substantially equal to the fourth width.

Optionally, in the embodiment of the present disclosure, the light-emitting device located in the second area is a third light-emitting device, and the pixel driving circuit electrically connected to the third light-emitting device is a third pixel driving circuit;

The area of the area enclosed by the orthographic projection of each of the third pixel driving circuits on the base substrate is substantially equal to the area of the enclosed area by the orthographic projection of the first pixel driving circuit on the base substrate.

Optionally, in the embodiment of the present disclosure, the area enclosed by the orthographic projection of the light-emitting area of the third light-emitting device on the base substrate is smaller than that of the light-emitting area of the second light-emitting device on the base substrate. The area of the area enclosed by the orthographic projection;

Along the first direction and pointing from the notch area to at least one of the first sub-area and the second sub-area, the light-emitting area of the third light-emitting device is located directly on the base substrate The area of the area enclosed by the projection decreases successively.

Optionally, in the embodiment of the present disclosure, the area of the area enclosed by the orthographic projection of the third light-emitting device on the base substrate and the light-emitting area of the second light-emitting device on the base substrate The area enclosed by the orthographic projection of is approximately the same.

The distribution density of the second pixel driving circuit is greater than the distribution density of the first pixel driving circuit.

Optionally, in the embodiment of the present disclosure, the area enclosed by the orthographic projection of the second pixel drive circuit on the base substrate is smaller than the area enclosed by the orthographic projection of the first pixel drive circuit on the base substrate. The area of the region.

Optionally, in the embodiment of the present disclosure, along the first direction and directed from the notch area to at least one of the first sub-area and the second sub-area, the second pixel drives The area of the area enclosed by the orthographic projection of the circuit on the base substrate increases sequentially.

Optionally, in the embodiment of the present disclosure, the area enclosed by the orthographic projection of each of the second pixel driving circuits on the base substrate is approximately the same.

Optionally, in the embodiment of the present disclosure, the number of transistors in the second pixel driving circuit is smaller than the number of transistors in the first pixel driving circuit.

Optionally, in the embodiments of the present disclosure, the area of the area enclosed by the orthographic projection of each of the second light-emitting devices on the base substrate is the same as that of the light-emitting area of the first light-emitting device on the substrate. The area enclosed by the orthographic projection of the substrate is approximately the same.

Optionally, in the embodiment of the present disclosure, the second light emitting device in the second area is located in the same column as the first light emitting device in the first area and the second area, respectively.

The orthographic projection of the light-emitting area of the third light-emitting device on the base substrate is less than or approximately equal to the orthographic projection of the light-emitting area of the first light-emitting device on the base substrate.

Optionally, in the embodiment of the present disclosure, along the first direction and directed from the notch area to at least one of the first sub-area and the second sub-area, the third pixel drives The area of the area enclosed by the orthographic projection of the circuit on the base substrate decreases successively.

Optionally, in the embodiment of the present disclosure, for at least one third light emitting device adjacent to the second light emitting device, the third light emitting device is electrically connected to the third pixel driving circuit through a second conductive line .

Optionally, in the embodiment of the present disclosure, the display panel further includes: a plurality of scan lines; wherein one row of the pixel driving circuit is electrically connected to at least one of the scan lines;

At least one of the first conductive line and the second conductive line and the scan line have the same layer and the same material and are arranged at intervals.

The display device provided by the embodiment of the present disclosure includes the above-mentioned display panel.

Description of the drawings

FIG. 1 is a schematic diagram of the structure of some display panels provided by the embodiments of the present disclosure;

2a is a schematic diagram of the structure of some pixel driving circuits provided by the embodiments of the disclosure;

2b is a timing diagram of some signals provided by the embodiments of the disclosure;

3 is a schematic diagram of the layout structure of some pixel driving circuits provided by the embodiments of the disclosure;

4a is a schematic diagram of the layout structure of some semiconductor layers provided by the embodiments of the present disclosure;

4b is a schematic diagram of the layout structure of some gate conductive layers provided by the embodiments of the present disclosure;

4c is a schematic diagram of the layout structure of some capacitor electrode layers provided by the embodiments of the disclosure;

4d is a schematic diagram of the layout structure of some first conductive layers provided by the embodiments of the present disclosure;

Fig. 5 is a schematic cross-sectional view of the layout structure shown in Fig. 3 along the AA' direction;

FIG. 6 is a schematic diagram of the structure of still other display panels provided by the embodiments of the present disclosure;

FIG. 7 is a schematic diagram of specific structures of still other display panels provided by the embodiments of the present disclosure;

FIG. 8 is a schematic diagram of a specific structure of a second area of some display panels provided by the embodiments of the present disclosure;

Fig. 9a is a partial cross-sectional structural diagram along the AA' direction in the specific structural diagram shown in Fig. 7;

Fig. 9b is a schematic partial cross-sectional view of the specific structure shown in Fig. 7 along the AA' direction;

FIG. 10 is a schematic diagram of specific structures of still other display panels provided by the embodiments of the present disclosure;

11 is a schematic diagram of specific structures of still other display panels provided by the embodiments of the present disclosure;

FIG. 12 is a schematic diagram of a specific structure of a second area of still other display panels provided by the embodiments of the present disclosure; FIG.

Fig. 13 is a partial cross-sectional structural diagram along the AA' direction in the specific structural diagram shown in Fig. 11;

FIG. 14 is a schematic diagram of specific structures of still other display panels provided by the embodiments of the present disclosure;

FIG. 15 is a schematic diagram of specific structures of still other display panels provided by the embodiments of the present disclosure.

Detailed ways

In order to make the objectives, technical solutions, and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be described clearly and completely in conjunction with the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, rather than all of the embodiments. And if there is no conflict, the embodiments in the present disclosure and the features in the embodiments can be combined with each other. Based on the described embodiments of the present disclosure, all other embodiments obtained by a person of ordinary skill in the art without creative labor are within the protection scope of the present disclosure.

Unless otherwise defined, the technical or scientific terms used in the present disclosure shall have the usual meanings understood by those with ordinary skills in the field to which this disclosure belongs. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "include" and other similar words mean that the element or item appearing before the word encompasses the element or item listed after the word and its equivalents, but does not exclude other elements or items. Similar words such as "connected" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

It should be noted that the size and shape of each figure in the drawings do not reflect the true ratio, and the purpose is only to illustrate the present disclosure. And the same or similar reference numerals indicate the same or similar elements or elements with the same or similar functions.

With the development of display technology, the full screen has a larger screen-to-body ratio and an ultra-narrow bezel. Compared with ordinary display screens, it can greatly improve the viewer's visual effect, and thus has received extensive attention. Generally, in a display device such as a mobile phone that uses a full-screen display, in order to realize the self-portrait and call functions, a front camera, earpiece, etc. are usually set on the front of the display device. Generally, the display panel is generally provided with a notch area A2 for setting the front camera, earpiece and other devices. However, due to the existence of the gap area A2, the scan line and the data line need to be routed according to the gap area A2, which causes a coupling effect between the scan line and the data line, which causes signal interference and affects the display effect.

In view of this, the embodiments of the present disclosure provide a display panel, which can reduce the coupling effect between the scan line and the data line, reduce signal interference, and improve the display effect.

As shown in FIG. 1, the display panel provided by the embodiment of the present disclosure may include: a notch area A2, a conventional display area A1, and a winding area A3. Among them, the conventional display area A1 surrounds the wire area A3, and the winding area A3 surrounds the gap area A2. Exemplarily, the display panel may further include a base substrate, and the base substrate 1000 may be a glass substrate, a flexible substrate, a silicon substrate, etc., which is not limited herein. When the display panel is applied to a display device, devices such as cameras and earpieces are generally provided. Therefore, in order to set up devices such as cameras and earpieces, the notch area A2 may be a hollow area of the base substrate 1000. For example, in the actual preparation process, the position of the base substrate 1000 corresponding to the notch area A2 is cut into a hollow area to be used for setting a camera, earpiece and other devices in the display device. Alternatively, the base substrate 1000 may not be cut, but the lines on the base substrate 1000 may be avoided to make the position corresponding to the notch area A2 a transparent area to form the notch area A2.

In practical applications, the display panel may generally also include a frame area surrounding the conventional display area A1. Elements such as electrostatic discharge circuit and gate drive circuit can be arranged in the frame area. Of course, the display panel may not be provided with a frame area, which can be designed and determined according to the requirements of the actual application environment, and is not limited here.

In specific implementation, in the embodiment of the present disclosure, as shown in FIG. 1, the conventional display area A1 may further include a plurality of pixel units PX. Wherein, the pixel unit PX may include a plurality of sub-pixels spx. Exemplarily, as shown in FIG. 1 and FIG. 2a, the sub-pixel spx may include: a pixel driving circuit 0121 and a light emitting device 0120. Among them, the pixel driving circuit 0121 has a transistor and a capacitor, and generates an electrical signal through the interaction of the transistor and the capacitor, and the generated electrical signal is input to the first light-emitting electrode of the light-emitting device 0120. In addition, a corresponding voltage is applied to the second light-emitting electrode of the light-emitting device 0120 to drive the light-emitting device 0120 to emit light.

As shown in FIG. 2a, the pixel driving circuit 0121 may include: a driving control circuit 0122, a first light emission control circuit 0123, a second light emission control circuit 0124, a data writing circuit 0126, a storage circuit 0127, a threshold compensation circuit 0128, and a reset circuit 0129 .

The drive control circuit 0122 may include a control terminal, a first terminal, and a second terminal. And the driving control circuit 0122 is configured to provide the light-emitting device 0120 with a driving current for driving the light-emitting device 0120 to emit light. For example, the first light emission control circuit 0123 is connected to the first terminal of the drive control circuit 0122 and the first voltage terminal VDD. And the first light emission control circuit 0123 is configured to realize the on or off the connection between the drive control circuit 0122 and the first voltage terminal VDD.

The second light emitting control circuit 0124 is electrically connected to the second end of the driving control circuit 0122 and the first electrode of the light emitting device 0120. And the second light-emitting control circuit 0124 is configured to realize that the connection between the driving control circuit 0122 and the light-emitting device 0120 is turned on or off.

The data writing circuit 0126 is electrically connected to the first end of the drive control circuit 0122. And the second light emission control circuit 0124 is configured to write the signal on the data line VD into the storage circuit 0127 under the control of the signal on the scan line GA2.

The storage circuit 0127 is electrically connected to the control terminal of the drive control circuit 0122 and the first voltage terminal VDD. And the storage circuit 0127 is configured to store data signals.

The threshold compensation circuit 0128 is electrically connected to the control terminal and the second terminal of the drive control circuit 0122. And the threshold compensation circuit 0128 is configured to perform threshold compensation on the drive control circuit 0122.

The reset circuit 0129 is electrically connected to the control terminal of the drive control circuit 0122 and the first electrode of the light emitting device 0120. And the reset circuit 0129 is configured to reset the control terminal of the drive control circuit 0122 and the first electrode of the light emitting device 0120 under the control of the signal on the gate line GA1.

Wherein, the light-emitting device 0120 may be configured as an electroluminescent diode, such as at least one of OLED and QLED. Wherein, the light-emitting device 0120 may include a first electrode, a light-emitting function layer, and a second electrode that are stacked. Illustratively, the first electrode may be an anode, and the second electrode may be a cathode. The light-emitting functional layer may include a light-emitting layer. Further, the light-emitting functional layer may also include film layers such as a hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer, and an electron injection layer. Of course, in actual applications, the light emitting device 0120 can be designed and determined according to the requirements of the actual application environment, which is not limited here.

Exemplarily, as shown in FIG. 2a, the drive control circuit 0122 includes a drive transistor T1, the control end of the drive control circuit 0122 includes the gate of the drive transistor T1, and the first end of the drive control circuit 0122 includes the first end of the drive transistor T1. The second terminal of the driving control circuit 0122 includes the second terminal of the driving transistor T1.

Exemplarily, as shown in FIG. 2a, the data writing circuit 0126 includes a data writing transistor T2. The storage circuit 0127 includes a storage capacitor CST. The threshold compensation circuit 0128 includes a threshold compensation transistor T3. The first light emission control circuit 0123 includes a first light emission control transistor T4. The second light emission control circuit 0124 includes a second light emission control transistor T5. The reset circuit 0129 includes a first reset transistor T6 and a second reset transistor T7.

Specifically, the first electrode of the data writing transistor T2 is electrically connected to the first electrode of the driving transistor T1, the second electrode of the data writing transistor T2 is configured to be electrically connected to the data line VD to receive the data signal, and the data writing transistor The gate of T2 is configured to be electrically connected to the second scan line GA2 to receive a scan signal.

The first pole of the storage capacitor CST is electrically connected to the first power supply terminal VDD, and the second pole of the storage capacitor CST is electrically connected to the gate of the driving transistor T1.

The first electrode of the threshold compensation transistor T3 is electrically connected to the second electrode of the driving transistor T1, the second electrode of the threshold compensation transistor T3 is electrically connected to the gate of the driving transistor T1, and the gate of the threshold compensation transistor T3 is configured to be connected to the second electrode. The scan line GA2 is electrically connected to receive the scan signal.

The first electrode of the first reset transistor T6 is configured to be electrically connected to the reset signal line VINIT to receive the first reset signal, the second electrode of the first reset transistor T6 is electrically connected to the gate of the driving transistor T1, and the first reset transistor T6 The gate of is configured to be electrically connected to the first scan line GA1 to receive a control signal.

The first electrode of the second reset transistor T7 is configured to be electrically connected to the reset signal line VINIT to receive the second reset signal, the second electrode of the second reset transistor T7 is electrically connected to the first electrode of the light emitting device 0120, and the second reset transistor The gate of T7 is configured to be electrically connected to the first scan line GA1 to receive a control signal.

The first electrode of the first light emission control transistor T4 is electrically connected to the first power supply terminal VDD, the second electrode of the first light emission control transistor T4 is electrically connected to the first electrode of the drive transistor T1, and the gate of the first light emission control transistor T4 is electrically connected to the first electrode of the driving transistor T1. It is configured to be electrically connected to the light emission control line EM to receive the light emission control signal.

The first electrode of the second light emission control transistor T5 is electrically connected to the second electrode of the driving transistor T1, the second electrode of the second light emission control transistor T5 is electrically connected to the first electrode of the light emitting device 0120, and the gate of the second light emission control transistor T5 The pole is configured to be electrically connected with the emission control line EM to receive the emission control signal.

The second electrode of the light emitting device 0120 is electrically connected to the second power supply terminal VSS. Wherein, the first electrode and the second electrode of the above-mentioned transistor can be determined as the source electrode or the drain electrode according to the actual application, which is not limited herein.

Exemplarily, the threshold compensation transistor T3 may have a double gate structure. One of the first power supply terminal VDD and the second power supply terminal VSS is a high-voltage terminal, and the other is a low-voltage terminal. For example, in the embodiment shown in FIG. 2a, the first power terminal VDD is a voltage source to output a constant first voltage, and the first voltage is a positive voltage; and the second power terminal VSS may be a voltage source to output a constant first voltage. Two voltages, the second voltage is a negative voltage, etc. For example, in some examples, the second power terminal VSS may be grounded.

The signal timing diagram corresponding to the pixel driving circuit shown in FIG. 2a is shown in FIG. 2b. In one frame of display time, the working process of the pixel drive circuit has three stages: T10 stage, T20 stage, and T30 stage. Among them, ga1 represents the signal transmitted on the first scan line GA1, ga2 represents the signal transmitted on the second scan line GA2, and em represents the signal transmitted on the light-emitting control line EM.

In the T10 phase, the signal ga1 controls the first reset transistor T6 and the second reset transistor T7 to conduct. The turned-on first reset transistor T6 provides the signal transmitted on the reset signal line VINIT to the gate of the driving transistor T1 to reset the gate of the driving transistor T1. The turned-on second reset transistor T7 provides the signal transmitted on the reset signal line VINIT to the first electrode of the light-emitting device 0120 to reset the first electrode of the light-emitting device 0120. In addition, in this stage, the signal ga2 controls the data writing transistor T2 and the threshold compensation transistor T to be turned off. The signal em controls both the first light-emission control transistor T4 and the second light-emission control transistor T5 to be turned off.

In the T20 stage, the signal ga2 controls the data writing transistor T2 and the threshold compensation transistor T3 to be turned on, so that the data signal transmitted on the data line VD can charge the gate of the driving transistor T1 to make the gate of the driving transistor T1 The voltage becomes: Vdata+|Vth|. Among them, Vth represents the threshold voltage of the driving transistor T1, and Vdata represents the voltage of the data signal. Moreover, in this stage, the signal ga1 controls both the first reset transistor T6 and the second reset transistor T7 to be turned off. The signal em controls both the first light-emission control transistor T4 and the second light-emission control transistor T5 to be turned off.

In the T30 stage, the signal em controls both the first light-emitting control transistor T4 and the second light-emitting control transistor T5 to be turned on. The turned-on first light emitting control transistor T4 provides the voltage Vdd of the first power supply terminal VDD to the first pole of the driving transistor T1, so that the voltage of the first pole of the driving transistor T1 is Vdd. The driving transistor T1 generates a driving current according to its gate voltage Vdata+|Vth| and the voltage Vdd of the first pole. The driving current is provided to the light-emitting device 0120 through the turned-on second light-emitting control transistor T5 to drive the light-emitting device 0120 to emit light. Moreover, in this stage, the signal ga1 controls both the first reset transistor T6 and the second reset transistor T7 to be turned off. The signal ga2 controls the data writing transistor T2 and the threshold compensation transistor T3 to be turned off.

It should be noted that, in the embodiment of the present disclosure, the pixel driving circuit in the sub-pixel may not only have the structure shown in FIG. 2a, but also may have a structure including other numbers of transistors, which is not limited in the embodiment of the present disclosure. .

FIG. 3 is a schematic diagram of a layout structure of a pixel driving circuit provided by some embodiments of the present disclosure. 4a to 4d are schematic diagrams of various layers of a pixel driving circuit provided by some embodiments of the disclosure. Among them, the examples shown in FIGS. 3 to 4d take a pixel driving circuit of a sub-pixel spx as an example. 3 to 4d also show the first scan line GA1, the second scan line GA2, the reset signal line VINIT, the light emission control line EM, the data line VD, and the power supply line VDD1 electrically connected to the pixel driving circuit 0121. Wherein, the driving voltage (ie, the first voltage) is input to the first power supply terminal VDD through the power supply line VDD1. Exemplarily, a plurality of data lines VD may be arranged along the first direction F1.

Illustratively, as shown in FIGS. 3, 4a, and 5, the semiconductor layer 500 of the pixel driving circuit 0121 is shown. The semiconductor layer 500 may be formed by patterning a semiconductor material. The semiconductor layer 500 can be used to make the aforementioned driving transistor T1, data writing transistor T2, threshold compensation transistor T3, first light emission control transistor T4, second light emission control transistor T5, first reset transistor T6, and second reset transistor T7. The source layer, each active layer may include a source region, a drain region, and a channel region between the source region and the drain region. For example, Figure 4a illustrates the channel region T1-A of the driving transistor T1, the channel region T2-A of the data writing transistor T2, and the two channel regions T31-A and T32-A of the threshold compensation transistor T3. A channel region T4-A of the light emission control transistor T4, a channel region T5-A of the second light emission control transistor T5, a channel region T6-A of the first reset transistor T6, and a channel region of the second reset transistor T7 T7-A.

And, as an example, the active layer of each transistor may be integrally provided. Further, the semiconductor layer 500 can be made of amorphous silicon, polysilicon, oxide semiconductor materials, or the like. It should be noted that the aforementioned source region and drain region may be regions doped with n-type impurities or p-type impurities.

Exemplarily, as shown in FIG. 5, a first gate insulating layer 610 is formed on the aforementioned semiconductor layer 500 to protect the aforementioned semiconductor layer 500. As shown in Figs. 3, 4b, and 5, the gate conductive layer 300 of the pixel driving circuit 0121 is shown. The gate conductive layer 300 is disposed on the side of the first gate insulating layer 610 away from the base substrate 1000 so as to be insulated from the semiconductor layer 500. The gate conductive layer 300 may include: a plurality of scan lines, the second electrode CC2a of the storage capacitor CST, a plurality of light emission control lines EM, and the gate of the driving transistor T1, the gate of the data writing transistor T2, and the gate of the threshold compensation transistor T3. The gate electrode, the gate of the first light emission control transistor T4, the gate of the second light emission control transistor T5, the gate of the first reset transistor T6, and the gate of the second reset transistor T7. Illustratively, the plurality of scan lines includes, for example, a plurality of first gate lines GA1 and a plurality of second gate lines GA2.

For example, as shown in FIGS. 3 to 4b, the gate of the data writing transistor T2 may be the first part where the second scan line GA2 overlaps the semiconductor layer 500 (for example, the groove between the second scan line GA2 and the data writing transistor T2). The first part where the track area T2-A overlaps), the gate of the first light-emission control transistor T4 may be the first part where the light-emission control line EM overlaps the semiconductor layer 500, and the gate of the second light-emission control transistor T5 may be the light-emission control The second part where the line EM overlaps the semiconductor layer 500, the gate of the first reset transistor T6 is the first part where the first scan line GA1 overlaps the semiconductor layer 500, and the gate of the second reset transistor T7 is the first scan line GA1 and The second part of the overlap of the semiconductor layer 500, the threshold compensation transistor T3 may be a thin film transistor with a double gate structure, and a gate of the threshold compensation transistor T3 may be the second part of the overlap of the second scan line GA2 and the semiconductor layer 500 (for example The second scan line GA2 overlaps the channel region T32-A), and the other gate of the threshold compensation transistor T3 may be a portion where the portion protruding from the second scan line GA2 overlaps the semiconductor layer 500. Exemplarily, the gate of the driving transistor T1 may be set as the second electrode CC2a of the storage capacitor CST. It can also be said that the gate of the driving transistor T1 and the second electrode CC2a of the storage capacitor CST have an integral structure.

It should be noted that each dashed rectangular frame in FIG. 4a shows each part where the gate conductive layer 300 and the semiconductor layer 500 overlap in the sub-pixel spx.

Exemplarily, as shown in FIGS. 3 and 4b, the first scan line GA1, the second scan line GA2, and the emission control line EM are arranged along the second direction F2, and the orthographic projection of the second scan line GA2 on the base substrate 1000 It is located between the orthographic projection of the first scan line GA1 on the base substrate 1000 and the orthographic projection of the emission control line EM on the base substrate 1000.

Exemplarily, as shown in FIGS. 3 and 4b, in the second direction F2, the orthographic projection of the second pole CC2a of the storage capacitor CST on the base substrate 1000 is located on the orthographic projection of the second scan line GA2 on the base substrate 1000 And the emission control line EM is between the orthographic projections of the base substrate 1000. The orthographic projection of the part protruding from the second scan line GA2 on the base substrate 1000 is located on the side of the orthographic projection of the second scan line GA2 on the base substrate 1000 away from the orthographic projection of the light emission control line EM on the base substrate 1000.

Exemplarily, as shown in FIGS. 3 and 4b, in the second direction F2, the gate of the data writing transistor T2, the gate of the threshold compensation transistor T3, the gate of the first reset transistor T6, and the second reset transistor The gates of T7 are all located on the first side of the gate of the driving transistor T1, and the gates of the first light-emitting control transistor T4 and the gate of the second light-emitting control transistor T5 are both located on the second side of the gate of the driving transistor T1.

For example, in some embodiments, as shown in FIGS. 3 and 4b, in the first direction F1, the gate of the data writing transistor T2 and the gate of the first light emission control transistor T4 are both located at the gate of the driving transistor T1. On the third side of the threshold value compensation transistor T3, the gate of the second light emission control transistor T5 and the gate of the second reset transistor T7 are all located on the fourth side of the gate of the driving transistor T1. Wherein, the third side and the fourth side of the gate of the driving transistor T1 are opposite sides of the gate of the driving transistor T1 in the first direction F1.

Exemplarily, as shown in FIG. 5, a second gate insulating layer 620 is formed on the aforementioned gate conductive layer 300 to protect the aforementioned gate conductive layer 300. As shown in FIG. 3, FIG. 4c, and FIG. 5, the capacitor electrode layer 400 of the pixel driving circuit 0121 is shown. The capacitor electrode layer 400 is disposed on the side of the second gate insulating layer 620 away from the base substrate 1000. The capacitor electrode layer 400 may include a first electrode CC1a of the storage capacitor CST, a reset signal line VINIT, and a voltage stabilizing part 410. Exemplarily, the orthographic projection of the first pole CC1a of the storage capacitor CST on the base substrate 1000 and the orthographic projection of the second pole CC2a of the storage capacitor CST on the base substrate 1000 at least partially overlap to form the storage capacitor CST. The orthographic projection of the voltage stabilizing portion 410 on the base substrate 1000 and the orthographic projection of the source region of the active layer of the data writing transistor T2 on the base substrate 1000 have an overlapping area. And, the orthographic projection of the voltage stabilizing portion 410 on the base substrate 1000 and the orthographic projection of the drain region of the active layer of the first reset transistor T6 on the base substrate 1000 have an overlapping area. In addition, the conductor area between the orthographic projection of the voltage stabilizing portion 410 on the base substrate 1000 and the channel regions T31-A and T32-A of the adjacent threshold compensation transistor T3 has an overlapping area on the orthographic projection of the base substrate 1000 , In order to reduce the leakage current caused by the photoelectric effect.

Exemplarily, as shown in FIG. 5, an interlayer dielectric layer 630 is formed on the aforementioned capacitor electrode layer 400 to protect the aforementioned capacitor electrode layer 400. As shown in FIGS. 3, 4d, and 5, the first conductive layer 100 of the pixel driving circuit 0121 is shown. The first conductive layer 100 is disposed on the side of the interlayer dielectric layer 630 away from the base substrate 1000. The first conductive layer 100 may include: a data line VD, a power supply line VDD1, and

bridge portions

341a, 342a, and 343a. Wherein, the data line VD and the power line VDD1 are arranged at intervals.

Fig. 5 is a schematic cross-sectional view of the layout structure shown in Fig. 3 along the AA' direction. A first gate insulating layer 610 is provided between the semiconductor layer 500 and the gate conductive layer 300, a second gate insulating layer 620 is provided between the gate conductive layer 300 and the capacitor electrode layer 400, and the capacitor electrode layer 400 is between the first conductive layer 100 An interlayer dielectric layer 630 is provided therebetween, and an interlayer insulating layer 640 is provided on the side of the first conductive layer 100 away from the base substrate 1000. Further, a planarization layer 650 is provided on the side of the interlayer insulating layer 640 away from the base substrate 1000, and a first electrode layer 600 is provided on the side of the planarization layer 650 away from the base substrate 1000. On the side of the first electrode layer 600 away from the base substrate 1000, a pixel defining layer 660, a light-emitting function layer 0122, and a second electrode layer 0123 are sequentially provided. Wherein, the first electrode layer 600 may include a plurality of first light-emitting electrodes spaced apart from each other, and the first light-emitting electrodes are electrically connected to the bridging portion 343a through via holes penetrating the planarization layer 650 and the interlayer insulating layer 640. It should be noted that the first light-emitting electrode, the light-emitting functional layer 0122, and the second electrode layer 0123 may form the above-mentioned light-emitting device.

3 and 5, the sub-pixel spx may include a first connection via, a second connection via, a third connection via, and a fourth connection via; wherein the first connection via penetrates the first gate The insulating layer 610, the second gate insulating layer 620 and the interlayer dielectric layer 630; the second connecting via hole penetrates the second gate insulating layer 620 and the interlayer dielectric layer 630; the third connecting via hole penetrates the interlayer dielectric layer 630.

Exemplarily, the sub-pixel spx may include first connection through

holes

381a, 382a, 384a, 387a, and 388a. The sub-pixel spx may include a second connection via 385a. The sub-pixel spx may include

third connection vias

386a and 3832a.

The data line VD is electrically connected to the source region T2-S of the data writing transistor T2 in the semiconductor layer 500 through at least one first connection via 381a. The power supply line VDD1 is electrically connected to the source region of the corresponding first light emission control transistor T4 in the semiconductor layer 500 through at least one first connection via 382a. One end of the bridge portion 341a is electrically connected to the drain region of the corresponding threshold compensation transistor T3 in the semiconductor layer 500 through at least one first connection via 384a. The other end of the bridge portion 341a is electrically connected to the gate of the driving transistor T1 in the gate conductive layer 300 (ie, the second electrode CC2a of the storage capacitor CST) through at least one second connection via 385a. One end of the bridge portion 342a is electrically connected to the reset signal line VINIT through at least one third connection via 386a, and the other end of the bridge portion 342a is connected to the source of the first reset transistor T6 in the semiconductor layer 500 via at least one first connection via 387a. The pole area T6-S is electrically connected. The bridge portion 343a is electrically connected to the drain region of the second light emission control transistor T5 in the semiconductor layer 500 through at least one first connection via 388a. The power line VDD1 is electrically connected to the first electrode CC1a of the storage capacitor CST in the capacitor electrode layer 400 through at least one third connection via 3832a.

Exemplarily, the first connection through

holes

381a, 382a, 384a, 387a, and 388a in the sub-pixels may be provided with one or two or more respectively. In actual applications, the design can be determined according to the requirements of the actual application environment, which is not limited here.

Exemplarily, one second connection through hole 385a in the sub-pixel may be provided, or two or more may be provided. In actual applications, the design can be determined according to the requirements of the actual application environment, which is not limited here.

Exemplarily, the third connection through

holes

386a and 3832a in the sub-pixels may be provided with one respectively, or two or more thereof may be provided respectively. In actual applications, the design can be determined according to the requirements of the actual application environment, which is not limited here.

For example, as shown in FIGS. 3 to 4d, in the second direction F2, the first scan line GA1, the second scan line GA2, and the reset signal line VINIT are all located on the first side of the gate of the driving transistor T1, and the light emission control The line EM is located on the second side of the driving transistor T1.

It should be noted that the position arrangement relationship of the transistors in each sub-pixel spx is not limited to the examples shown in FIGS. 3 to 4d, and the positions of the above-mentioned transistors can be specifically set according to actual application requirements.

It should be noted that the first direction F1 may be the row direction of the sub-pixels, and the second direction F2 may be the column direction of the sub-pixels. Alternatively, the first direction F1 may also be the column direction of the sub-pixels, and the second direction F2 may be the row direction of the sub-pixels. In actual applications, it can be set according to actual application requirements, which is not limited here. In the following description, the first direction F1 may be the row direction of the sub-pixels, and the second direction F2 may be the column direction of the sub-pixels.

In specific implementation, in the embodiment of the present disclosure, as shown in FIG. 6, the plurality of data lines in the first conductive layer 100 may include a data line VD1 and a data line VD2. Wherein, the data lines VD1 and VD2 are both located in the conventional display area A1, and the data lines VD1 and VD2 are respectively arranged along the first direction F1. The data line VD1 extends from the lower side of the regular display area A1 to the upper side of the regular display area A1 along the second direction F2. The data line VD2 extends along the second direction F2 and is divided by the notch area A2, that is, a part of the data line VD2 can extend from the lower side of the conventional display area A1 to the winding area A3, and another part of the data line VD2 It extends from the upper side of the regular display area A1 to the winding area A3.

In specific implementation, in the embodiment of the present disclosure, as shown in FIG. 6, the first conductive layer 100 may further include: a plurality of data transmission lines 711 arranged at intervals. Among them, a plurality of data transmission lines 711 are located in the winding area A3. In addition, one data line VD2 corresponds to one data transmission line 711. The connecting part of the same data line VD2 divided by the notch area A2 is electrically connected through the corresponding data transmission line 711. In addition, the first scan line GA1, the second scan line GA2, and the light-emitting control line EM corresponding to the notch area A2 also extend around the notch area A2, that is, in the winding area A3. As a result, the number of signal lines provided in the winding area A3 is relatively large, and therefore the pixel driving circuit cannot be provided in the winding area A3. This causes the screen-to-body ratio of the display panel to decrease.

In specific implementation, in the embodiment of the present disclosure, as shown in FIGS. 2a and 7 to 9b, a plurality of pixel driving circuits 0121 are provided on the base substrate 1000, which are located on the side of the pixel driving circuit 0121 away from the base substrate 1000 Of multiple light emitting devices 0120. Among them, a pixel driving circuit 0121 is electrically connected to a light emitting device 0120 correspondingly. Among them, a plurality of pixel driving circuits 0121 are located in the conventional display area A1. Wherein, the orthographic projection of at least one of the plurality of light-emitting devices on the base substrate 1000 overlaps the winding area A3, and the remaining light-emitting devices are located in the conventional display area A1. And, the light emitting device overlapping the orthographic projection of the base substrate 1000 and the winding area A3 is electrically connected to the corresponding pixel driving circuit 0121 through the first conductive line 311, and the first conductive line 311 extends from the conventional display area A1 to the winding area A1. Line area A3.

In the embodiment of the present disclosure, by overlapping the orthographic projection of at least one light-emitting device on the base substrate 1000 with the winding area A3, the remaining light-emitting devices are located in the conventional display area A1. In this way, the light-emitting device 0120 can be arranged on the winding area A3 perpendicular to the base substrate 1000, so that the winding area A3 can achieve a display effect.

In specific implementation, in the embodiments of the present disclosure, as shown in FIGS. 7 to 9b, the light-emitting area Q of the light-emitting device 0120 that is electrically connected to the pixel driving circuit 0121 close to the winding area A3 can be located on the front side of the base substrate 1000. The projection and the winding area A3 have an overlapping area. Exemplarily, for light-emitting devices whose orthographic projection on the base substrate 1000 overlaps the winding area A3, some of these light-emitting devices may be located in the winding area A3 by the orthographic projection of some of these light-emitting devices on the base substrate 1000. And the orthographic projection of some of these light-emitting devices on the base substrate 1000 and the winding area A3 are partially overlapped. Of course, the number of light-emitting devices whose orthographic projection of the base substrate 1000 is located in the winding area A3, and the number of light-emitting devices that partially overlap the orthographic projection of the base substrate 1000 and the winding area A3 can be based on actual applications. The requirements are determined by design and are not limited here.

In specific implementation, in the embodiment of the present disclosure, as shown in FIGS. 7 to 9b, the conventional display area may include: a first area AH1, a second area AH2, and a third area AH3 arranged along the second direction F2. The second area AH2 includes a first sub-area AH2-1 and a second sub-area AH2-2 arranged along the first direction F1; wherein the first sub-area AH2-1 and the second sub-area AH2-2 are separated by a gap area A2 Open; can be perpendicular to the base substrate 1000, the orthogonal projection of the base substrate 1000 overlapped with the winding area A3 of the light emitting device in the second direction F2 is located in the first sub-area AH2-1 and the second At least one of the sub-areas AH2-2.

Exemplarily, as shown in FIGS. 7 to 9b, in the first sub-area AH2-1, the light-emitting area Q of the light-emitting device electrically connected to the pixel driving circuit close to the winding area can be projected on the base substrate 1000 and The winding area has an overlapping area. For example, the light-emitting area Q of the light-emitting device electrically connected to the pixel driving circuit closest to the winding area A3 may have an overlap area between the orthographic projection of the base substrate 1000 and the winding area.

Exemplarily, as shown in FIG. 7 to FIG. 9b, in the second sub-area AH2-2, the light-emitting area Q of the light-emitting device electrically connected to the pixel driving circuit close to the winding area can be projected on the base substrate 1000 and The winding area has an overlapping area. For example, the light emitting area Q of the light emitting device electrically connected to the pixel driving circuit adjacent to the winding area A3 may have an overlap area between the orthographic projection of the base substrate 1000 and the winding area.

It should be noted that, as shown in FIG. 5, the pixel defining layer 660 has a plurality of openings, and one opening corresponds to one light-emitting device. In addition, the opening may expose the first light-emitting electrode 610 of the corresponding light-emitting device, and the light-emitting function layer 0122 is in contact with the area of the first light-emitting electrode 610 exposed by the opening, so that the opening of the pixel defining layer 660 can be in contact with the main body of the first light-emitting electrode. The overlapping area of the portion 410 is the light-emitting area Q of each light-emitting device.

In specific implementation, in the embodiment of the present disclosure, as shown in FIG. 5 and FIG. 7 to FIG. 9b, the light-emitting devices in the first area AH1 and the third area AH3 are first light-emitting devices 0120-1, and each first The area of the area enclosed by the orthographic projection of the base substrate 1000 of the light-emitting area Q of the light-emitting device 0120-1 is approximately the same. In addition, the pixel drive circuit electrically connected to the first light-emitting device 0120-1 is the first pixel drive circuit 0121-1, that is, the pixel drive circuits in the first area AH1 and the third area AH3 are the first pixel drive circuit 0121-1 And the area of the area enclosed by the orthographic projection of each first pixel driving circuit 0121-1 on the base substrate 1000 is approximately the same. Exemplarily, the structure of the first pixel driving circuit 0121-1 may be as shown in FIG. 2a, and the schematic diagram of the layout structure of the first pixel driving circuit 0121-1 may be as shown in FIG. The first light-emitting electrode in the first light-emitting device 0120-1 can be electrically connected to the bridge portion 343a through the via 651a penetrating the interlayer insulating layer 640 and the planarization layer 650, so that the first pixel driving circuit 0121-1 can drive the electric power. The connected first light emitting device 0120-1 emits light. It should be noted that the area enclosed by the orthographic projection of the first pixel driving circuit 0121-1 on the base substrate 1000 refers to the layout structure of the first pixel driving circuit 0121-1 in one sub-pixel on the front of the base substrate 1000. The area enclosed by the projection.

In specific implementation, in the embodiment of the present disclosure, as shown in FIG. 5 and FIG. 7 to FIG. 9b, the light-emitting device overlapping the orthographic projection of the base substrate 1000 and the winding area A3 is the second light-emitting device 0120-2 The pixel driving circuit electrically connected to the second light-emitting device 0120-2 is the second pixel driving circuit 0121-2. Exemplarily, the area of the area enclosed by the orthographic projection of each second pixel driving circuit 0121-2 on the base substrate 1000 and the area enclosed by the orthographic projection of the first pixel driving circuit 0121-1 on the base substrate 1000 can be made Roughly equal. For example, the structure of the second pixel driving circuit 0121-2 can be shown in FIG. 2a, and the schematic layout structure of the second pixel driving circuit 0121-2 can also be shown in FIG. 3, so that the second pixel can be driven The layout structure of the circuit 0121-2 is approximately the same as the layout structure of the first pixel driving circuit 0121-1, and the size of the layout structure of the second pixel driving circuit 0121-2 is the same as the layout structure of the first pixel driving circuit 0121-1. The dimensions are roughly the same. In this way, the layout structure of each film layer of the second pixel driving circuit 0121-2 and the first pixel driving circuit 0121-1 does not need to be changed, and the uniformity of the manufacturing process is improved.

In specific implementation, in the embodiment of the present disclosure, as shown in FIG. 5 and FIG. 7 to FIG. 10, the second pixel driving circuit 0121-2 in the second area AH2 can be connected to the first area AH1 and the second area. The first pixel driving circuit 0121-1 in AH2 is located in the same column. Exemplarily, the second pixel driving circuit 0121-2 and the first pixel driving circuit 0121-1 are arranged in an array on the base substrate 1000. Wherein, one column of pixel driving circuit is electrically connected to at least one data line. For example, one data line VD1 is electrically connected to the first pixel driving circuit 0121-1 and the second pixel driving circuit 0121-2 in the same column.

In specific implementation, in the embodiment of the present disclosure, as shown in FIG. 5 and FIG. 7 to FIG. 9b, the area of the area enclosed by the orthographic projection of the base substrate 1000 of the light-emitting area Q of the second light-emitting device 0120-2 can be The light emitting area Q of the first light emitting device 0120-1 is larger than the area enclosed by the orthographic projection of the base substrate 1000. In this way, the second light-emitting device 0120-2 electrically connected to the second pixel driving circuit 0121-2 adjacent to the winding area can be enlarged, so that part of the light-emitting area Q of the second light-emitting device 0120-2 is arranged on the winding area. , So that the winding area can be displayed.

In the specific implementation, in the embodiment of the present disclosure, as shown in FIG. 5 and FIG. 7 to FIG. 9b, the second pixel driving circuit 0121-2 can be located in the first sub-region AH2-1, which is aimed at the second pixel driving circuit. The second light-emitting device 0120-2 electrically connected to 0121-2 can make the area of the light-emitting area Q of the second light-emitting device 0120-2 in the orthographic projection of the base substrate 1000 larger than that of the first light-emitting device 0120-1 The area of the area enclosed by the orthographic projection of the area Q on the base substrate 1000. In this way, the second light-emitting device 0120-2 electrically connected to the second pixel driving circuit 0121-2 adjacent to the winding area can be enlarged, so that part of the light-emitting area Q of the second light-emitting device 0120-2 is arranged on the winding area. , So that the winding area can be displayed.

In specific implementation, in the embodiment of the present disclosure, as shown in FIG. 7 to FIG. 9b, the second pixel driving circuit 0121-2 can also be located in the second sub-region AH2-2, so that the second pixel driving circuit 0121 -2 The electrically connected second light-emitting device 0120-2 can make the light-emitting area Q of the second light-emitting device 0120-2 in the orthographic projection area of the base substrate 1000 larger than the light-emitting area of the first light-emitting device 0120-1 The area of the area enclosed by the orthographic projection of Q on the base substrate 1000. In this way, the second light-emitting device 0120-2 electrically connected to the second pixel driving circuit 0121-2 close to the winding area can be enlarged, so that part of the light-emitting area Q of the second light-emitting device 0120-2 is arranged on the winding area. , So that the winding area can be displayed.

Exemplarily, as shown in FIGS. 7 to 9b, along the first direction and pointing from the notch area to the first sub-area AH2-1 (that is, the direction of the arrow S1), the light-emitting area Q of the second light-emitting device 0120-2 can be The area of the area enclosed by the orthographic projection of the base substrate 1000 decreases successively.

Exemplarily, as shown in FIGS. 7 and 8, along the first direction and pointing from the notch area to the second sub-area AH2-2 (that is, the direction of the arrow S2), the light-emitting area Q of the second light-emitting device 0120-2 can also be made The area of the area enclosed by the orthographic projection of the base substrate 1000 decreases successively.

In specific implementation, in the embodiment of the present disclosure, as shown in FIG. 10, the area of the area enclosed by the orthographic projection of the base substrate 1000 of the light-emitting area Q of each second light-emitting device 0120-2 can also be approximately equal. In this way, the size of the opening of the pixel defining layer in the second area AH2 can be uniformly set.

In specific implementation, in the embodiment of the present disclosure, as shown in FIG. 7, the light-emitting device located in the second area AH2 is the third light-emitting device 0120-3, and the pixel driving circuit electrically connected to the third light-emitting device 0120-3 is The third pixel driving circuit 0121-3; wherein, the area of the area enclosed by the orthographic projection of each third pixel driving circuit 0121-3 on the base substrate 1000 is the same as the orthographic projection of the first pixel driving circuit 0121-1 on the base substrate 1000 The area of the enclosed area is approximately equal. Exemplarily, the structure of the third pixel driving circuit 0121-3 may be shown in FIG. 2a, and the schematic layout structure of the third pixel driving circuit 0121-3 may also be shown in FIG. The layout structure of the pixel drive circuit 0121-3 and the layout structure of the first pixel drive circuit 0121-1 are approximately the same, and the size of the layout structure of the third pixel drive circuit 0121-3 and the layout of the first pixel drive circuit 0121-1 The size of the structure is roughly the same. In this way, the layout structure of each film layer of the third pixel driving circuit 0121-3 and the first pixel driving circuit 0121-1 does not need to be changed, and the uniformity of the manufacturing process is improved.

In specific implementation, in the embodiments of the present disclosure, as shown in FIGS. 7 and 8, the area of the light-emitting area Q of the third light-emitting device 0120-3 in the orthographic projection of the base substrate 1000 can be made smaller than that of the second The area of the area enclosed by the orthographic projection of the base substrate 1000 of the light-emitting area Q of the light-emitting device 0120-2. Exemplarily, along the first direction F1 and pointing from the notch area A2 to the first sub-area AH2-1, the area of the light-emitting area Q of the third light-emitting device 0120-3 in the orthographic projection of the base substrate 1000 can be sequentially Decrease. Exemplarily, along the first direction F1 and pointing from the notch area A2 to the first sub-area AH2-2, the area of the light-emitting area Q of the third light-emitting device 0120-3 in the orthographic projection of the base substrate 1000 can be sequentially Decrease.

In specific implementation, in the embodiment of the present disclosure, as shown in FIG. 10, the area of the light-emitting area Q of the third light-emitting device 0120-3 in the orthographic projection of the base substrate 1000 can be the same as that of the second light-emitting device 0120. The area of the area enclosed by the orthographic projection of the -2 light-emitting area Q on the base substrate 1000 is approximately the same.

In specific implementation, in the embodiments of the present disclosure, as shown in FIGS. 7 to 10, for at least one third light-emitting device 0120-3 adjacent to the second light-emitting device 0120-2, the third light-emitting device 0120-3 The second conductive line 312 is electrically connected to the third pixel driving circuit 0121-3. Since the third light-emitting device 0120-3 overlaps the winding area A3 in the direction perpendicular to the base substrate 1000, the third light-emitting device 0120-3 adjacent to the second light-emitting device 0120-2 and the corresponding first light-emitting device 0120-3 The three-pixel driving circuit 0121-3 may deviate, so by providing the second conductive line 312, the third pixel driving circuit 0121-3 can be electrically connected to the corresponding third light-emitting device 0120-3.

It should be noted that only one transistor in the first pixel driving circuit 0121-1, the second pixel driving circuit 0121-2, and the third pixel driving circuit 0121-3 is shown in FIG. 7, FIG. 8, and FIG. 10. The specific structures of the first pixel driving circuit 0121-1, the second pixel driving circuit 0121-2, and the third pixel driving circuit 0121-3 may be as shown in FIG. 3, and will not be described here.

In specific implementation, in the embodiment of the present disclosure, as shown in FIG. 7, the orthographic projection of the light-emitting area Q of the first light-emitting device 0120-1 on the base substrate 1000 has a first width W1 along the first direction, and The orthographic projection of the light emitting area Q of the first light emitting device 0120-1 on the base substrate 1000 has a second width W2 in the second direction. The first width W1 of the light-emitting area Q of each first light-emitting device 0120-1 is approximately the same, and the second width W2 of the light-emitting area Q of each first light-emitting device 0120-1 is approximately the same.

In specific implementation, in the embodiment of the present disclosure, as shown in FIG. 7, the orthographic projection of the light-emitting area Q of the second light-emitting device 0120-2 on the base substrate 1000 has a third width W3 along the first direction, and The orthographic projection of the light emitting area Q of the second light emitting device 0120-2 on the base substrate 1000 has a fourth width W4 in the second direction. Wherein, the third width W3 can be made larger than the first width W1, and the second width W2 and the fourth width W4 are approximately equal. Of course, in actual applications, specific values of the first width W1, the second width W2, the third width W3, and the fourth width W4 can be set according to the requirements of the actual application, which are not limited herein.

In the specific implementation, in the embodiment of the present disclosure, as shown in FIG. 5 and FIG. 7 to FIG. 10, the first conductive line 311 and the scan line may be provided with the same layer and the same material. That is, the first conductive line 311 is disposed in the gate conductive layer 300. In addition, the first conductive line 311 and the scan line are spaced apart from each other; one second pixel driving circuit 0121-2 is electrically connected to the second light emitting device 0120-2 through at least one first conductive line 311. Exemplarily, a second pixel driving circuit 0121-2 is electrically connected to the second light emitting device 0120-2 through a first conductive line 311, so that the current generated by the second pixel driving circuit 0121-2 can be supplied to the second light emitting device. The device 0120-2, in turn, drives the second light-emitting device 0120-2 to emit light.

Wherein, the first end of the first conductive line 311 also needs to be electrically connected to the bridge portion 343a in the corresponding second pixel driving circuit 0121-2 through the via hole penetrating the second gate insulating layer 620 and the interlayer dielectric layer 630, and the first The second end of the conductive line 311 is electrically connected to the first light-emitting electrode of the second light-emitting device 0120-2 through the via hole that penetrates the second gate insulating layer 620, the interlayer dielectric layer 630, the planarization layer 650, and the interlayer insulating layer 640. connect.

In the specific implementation, in the embodiment of the present disclosure, as shown in FIG. 5 and FIG. 7 to FIG. 10, the second conductive line 312 and the scan line may be provided with the same layer and the same material. In other words, the second conductive line 312 is disposed in the gate conductive layer 300. In addition, the second conductive line 312 and the scan line are spaced apart from each other; one second pixel driving circuit 0121-3 is electrically connected to the third light-emitting device 0120-3 through at least one second conductive line 312. Exemplarily, a third pixel driving circuit 0121-3 is electrically connected to the third light emitting device 0120-3 through a second conductive line 312, so that the current generated by the third pixel driving circuit 0121-3 can be supplied to the third light emitting device. The device 0120-3, in turn, drives the third light-emitting device 0120-3 to emit light.

Wherein, the first end of the second conductive line 312 also needs to be electrically connected to the bridge portion 343a in the third pixel driving circuit 0121-3 through the via hole penetrating the second gate insulating layer 620 and the interlayer dielectric layer 630, and the second The second end of the conductive line 312 is electrically connected to the first light-emitting electrode of the third light-emitting device 0120-3 through the via hole that penetrates the second gate insulating layer 620, the interlayer dielectric layer 630, the planarization layer 650, and the interlayer insulating layer 640. connect.

It should be noted that in the actual process, due to the limitations of the process conditions or other factors, the equality of the above-mentioned features may not be completely equal, and there may be some deviations. Therefore, the equality relationship between the above-mentioned features as long as the above-mentioned conditions are roughly met. That is, all belong to the protection scope of the present disclosure. For example, the above-mentioned equality may be the allowable equality within the allowable error range.

It should be noted that FIG. 9 only illustrates the data line, the data transmission line 711, and the bridge portion 343a in the first conductive layer, and the first conductive line 311 and the second conductive line 312 in the gate conductive layer. For the rest of the structure, reference may be made to the content shown in FIG. 3 to FIG. 5, and details are not described here.

The embodiments of the present disclosure provide some display panels. The schematic structural diagrams of the display panels are shown in FIG. 11 to FIG. Only the differences between this embodiment and the above-mentioned embodiments are described below, and the similarities are not repeated here.

In specific implementation, in the embodiment of the present disclosure, as shown in FIGS. 11 to 13, the light emitting device overlapping the orthographic projection of the base substrate 1000 and the winding area A3 is the second light emitting device 0120-2, which is the same as the second light emitting device 0120-2. The pixel driving circuit electrically connected to the two light-emitting devices 0120-2 is the second pixel driving circuit 0121-2. Exemplarily, the distribution density of the second pixel driving circuit 0121-2 is greater than the distribution density of the first pixel driving circuit 0121-1. In this way, more second pixel driving circuits 0121-2 can be arranged in the second area AH2. Exemplarily, the area of the light-emitting area Q of each second light-emitting device 0120-2 in the orthographic projection of the base substrate 1000 can be made to be the same as the light-emitting area Q of the first light-emitting device 0120-1 on the front of the base substrate 1000. The area enclosed by the projection is approximately the same. In this way, the manufacturing processes of the first light-emitting device 0120-1 and the second light-emitting device 0120-2 can be unified.

In specific implementation, in the embodiments of the present disclosure, as shown in FIGS. 11 to 13, the second light-emitting device 0120-2 in the second area AH2 can be made to correspond to the second light emitting device 0120-2 in the first area AH1 and the second area AH2, respectively. A light emitting device 0120-1 is located in the same column. In this way, the first light-emitting device 0120-1 and the second light-emitting device 0120-2 can be arranged in an array.

In specific implementation, in the embodiments of the present disclosure, as shown in FIGS. 11 to 15, the pixel driving circuit electrically connected to a column of light-emitting devices can be electrically connected to at least one data line. For example, the first pixel driving circuit 0121-1 corresponding to the first light emitting device 0120-1 and the second pixel driving circuit 0121-2 corresponding to the second light emitting device 0120-2 in the same column are electrically connected to one data line.

Exemplarily, as shown in FIGS. 11 to 13, the distribution density of the second pixel driving circuit 0121-2 in the first sub-region AH2-1 can be made greater than the distribution density of the first pixel driving circuit 0121-1. It is also possible to make the distribution density of the second pixel driving circuit 0121-2 adjacent to the winding area in the first sub-region AH2-1 greater than the distribution density of the first pixel driving circuit 0121-1.

Exemplarily, as shown in FIGS. 11 to 13, the distribution density of the second pixel driving circuit 0121-2 in the second sub-region AH2-2 may be greater than the distribution density of the first pixel driving circuit 0121-1. It is also possible to make the distribution density of the second pixel driving circuit 0121-2 adjacent to the winding area in the second sub-region AH2-2 greater than the distribution density of the first pixel driving circuit 0121-1.

Exemplarily, in at least one of the first sub-region AH2-1 and the second sub-region AH2-2, the area enclosed by the orthographic projection of the second pixel driving circuit 0121-2 on the base substrate 1000 is smaller than that of the first sub-region AH2-1 and the second sub-region AH2-2. The area of the area enclosed by the orthographic projection of a pixel driving circuit 0121-1 on the base substrate 1000. Exemplarily, as shown in FIG. 14, the area enclosed by the orthographic projection of the second pixel driving circuit 0121-2 on the base substrate 1000 is smaller than the area enclosed by the orthographic projection of the first pixel driving circuit 0121-1 on the base substrate 1000. The area of the area. In other words, the occupied area of the second pixel driving circuit 0121-2 on the base substrate 1000 can be reduced, so that more second pixel driving circuits 0121-2 can be arranged in a row.

In specific implementation, in the embodiments of the present disclosure, as shown in FIGS. 11 to 14, the area enclosed by the orthographic projection of each second pixel driving circuit 0121-2 on the base substrate 1000 can be approximately equal. In this way, the preparation process can be unified.

In specific implementation, in the embodiment of the present disclosure, as shown in FIG. 15, along the first direction and pointing from the notch area to the first sub-area AH2-1 (that is, the direction of the arrow S1), the second pixel driving circuit may also be The area of the area enclosed by the orthographic projection of 0121-2 on the base substrate 1000 sequentially increases. In the same way, the area of the area enclosed by the orthographic projection of the second pixel driving circuit 0121-2 on the base substrate 1000 along the first direction and pointing from the notch area to the second sub-area AH2-2 can also be increased sequentially. This implementation manner may be substantially the same as that in FIG. 15 and will not be repeated here.

In specific implementation, in the embodiments of the present disclosure, the transistors and storage capacitors included in the first pixel driving circuit 0121-1 can be made the same as the transistors and storage capacitors included in the second pixel driving circuit 0121-2. When preparing the second pixel driving circuit 0121-2, the occupied area of the second pixel driving circuit 0121-2 is reduced.

In specific implementation, in the embodiment of the present disclosure, the number of transistors in the second pixel driving circuit 0121-2 can also be made smaller than the number of transistors in the first pixel driving circuit 0121-1. In this way, the occupied area of the second pixel driving circuit 0121-2 can also be reduced. For example, the first reset transistor and the second reset transistor in FIG. 2a can be deleted and used as the second pixel driving circuit 0121-2 to reduce the occupied area of the second pixel driving circuit 0121-2. Alternatively, a 2T1C pixel circuit can also be used as the second pixel driving circuit 0121-2 to reduce the area occupied by the second pixel driving circuit 0121-2. In actual applications, it can be designed and determined according to actual application requirements, which is not limited here.

In specific implementation, in the embodiments of the present disclosure, as shown in FIGS. 11 to 15, the light-emitting device located in the second area AH2 is the third light-emitting device 0120-3, and the pixel electrically connected to the third light-emitting device 0120-3 The driving circuit is a third pixel driving circuit 0121-3; wherein, the orthographic projection of the light-emitting area Q of the third light-emitting device 0120-3 on the base substrate 1000 and the light-emitting area Q of the first light-emitting device 0120-1 on the base substrate 1000 The orthographic projections are roughly equal. In this way, the orthographic projection of the light-emitting area Q of the third light-emitting device 0120-3 on the base substrate 1000 can be approximately equal, and the orthographic projection of the light-emitting area Q of the second light-emitting device 0120-2 on the base substrate 1000 is approximately equal, and the first light-emitting device The orthographic projection of the light-emitting area Q of 0120-1 on the base substrate 1000 is approximately equal.

In specific implementation, in the embodiment of the present disclosure, as shown in FIG. 11 to FIG. 15, along the first direction and pointing from the notch area to the first sub-area AH2-1 (that is, the direction of the arrow S1), the third pixel can be driven The area of the area enclosed by the orthographic projection of the circuit 0121-3 on the base substrate 1000 decreases successively.

In specific implementation, in the embodiment of the present disclosure, as shown in FIG. 11 to FIG. 15, along the first direction and pointing from the notch area to the second sub-area AH2-2 (that is, the direction of the arrow S2), the third pixel can be driven The area of the area enclosed by the orthographic projection of the circuit 0121-3 on the base substrate 1000 decreases successively.

It should be noted that FIG. 13 only illustrates the data line, the data transmission line 711, and the bridge portion 343a in the first conductive layer, and the first conductive line 311 and the second conductive line 312 in the gate conductive layer. For the rest of the structure, reference may be made to the content shown in FIG. 3 to FIG. 5, and details are not described here.

It should be noted that the above-mentioned drawings merely illustrate the display panel provided by the embodiments of the present disclosure, and do not represent the specific structure of the display panel in practical applications. The specific structure in the display panel can be implemented on the basis of satisfying the content described in the embodiments of the present disclosure, and will not be repeated here.

Based on the same inventive concept, the embodiment of the present disclosure also provides a display device, including the above-mentioned display panel provided by the embodiment of the present disclosure. The display device can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, and the like. Other indispensable components of the display device are understood by those of ordinary skill in the art, and will not be repeated here, and should not be used as a limitation to the present disclosure. For the implementation of the display device, reference may be made to the above-mentioned embodiment of the display panel, and the repetition is not repeated here.

Although the preferred embodiments of the present disclosure have been described, those skilled in the art can make additional changes and modifications to these embodiments once they learn the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present disclosure.

Obviously, those skilled in the art can make various changes and modifications to the embodiments of the present disclosure without departing from the spirit and scope of the embodiments of the present disclosure. In this way, if these modifications and variations of the embodiments of the present disclosure fall within the scope of the claims of the present disclosure and equivalent technologies, the present disclosure also intends to include these modifications and variations.

Claims

A display panel, which includes:

Conventional display area;

A winding area, wherein the conventional display area surrounds the winding area,

A gap area, wherein the winding area surrounds the gap area;

Multiple pixel drive circuits located in the conventional display area;

A plurality of light-emitting devices are located on a side of the pixel drive circuit away from the base substrate, and one of the pixel drive circuits is electrically connected to one of the light-emitting devices;

Wherein, the orthographic projection of at least one of the plurality of light-emitting devices on the base substrate overlaps the winding area, and the remaining light-emitting devices are located in the conventional display area;

The light emitting device overlapping the orthographic projection of the base substrate and the winding area is electrically connected to the corresponding pixel driving circuit through a first conductive line, and the first conductive line extends from the conventional display area To the winding area.
3. The display panel of claim 1, wherein the normal display area comprises: a first area, a second area, and a third area arranged in a second direction;

The second area includes a first sub-area and a second sub-area arranged along a first direction; wherein the first sub-area and the second sub-area are separated by the notch area;

The orthographic projection of the light emitting device in the second direction that overlaps the orthographic projection of the base substrate and the winding area is located in at least one of the first sub-area and the second sub-area .
The display panel of claim 2, wherein the light-emitting devices in the first area and the third area are first light-emitting devices, and the light-emitting area of each of the first light-emitting devices is located on the base substrate. The area enclosed by the orthographic projection is roughly equal;

The pixel driving circuit electrically connected to the first light-emitting device is a first pixel driving circuit, and the area enclosed by the orthographic projection of each of the first pixel driving circuits on the base substrate is approximately the same.
The display panel of claim 3, wherein the light-emitting device overlapping the orthographic projection of the base substrate and the winding area is a second light-emitting device, and a pixel electrically connected to the second light-emitting device is driven The circuit is a second pixel driving circuit;

The area of the light-emitting area of the second light-emitting device enclosed by the orthographic projection of the base substrate is larger than the area of the light-emitting area enclosed by the orthographic projection of the first light-emitting device.
The display panel of claim 4, wherein, along the first direction and directed from the notch area to at least one of the first sub-area and the second sub-area, the second light-emitting area The area of the light-emitting area of the device in the area enclosed by the orthographic projection of the base substrate decreases successively.
7. The display panel of claim 4, wherein the area of the area enclosed by the orthographic projection of the light-emitting area of each of the second light-emitting devices on the base substrate is approximately the same.
The display panel according to any one of claims 4-6, wherein the area of the area enclosed by the orthographic projection of each of the second pixel driving circuits on the base substrate is the same as that of the first pixel driving circuit in the The area enclosed by the orthographic projection of the base substrate is approximately the same.
7. The display panel of claim 7, wherein the second pixel driving circuit is located in the same column as the first pixel driving circuit in the first area and the second area, respectively.
8. The display panel according to any one of claims 4-8, wherein the orthographic projection of the light-emitting area of the first light-emitting device on the base substrate has a first width along the first direction, and The orthographic projection of the light emitting area of the first light emitting device on the base substrate has a second width along the second direction;

The orthographic projection of the light-emitting area of the second light-emitting device on the base substrate has a third width along the first direction, and the orthographic projection of the light-emitting area of the second light-emitting device on the base substrate Having a fourth width along the second direction;

The third width is greater than the first width, and the second width is substantially equal to the fourth width.
9. The display panel according to any one of claims 4-9, wherein the light-emitting device located in the second area is a third light-emitting device, and the pixel driving circuit electrically connected to the third light-emitting device is a third pixel driving device. Circuit

The area of the area enclosed by the orthographic projection of each of the third pixel driving circuits on the base substrate is substantially equal to the area of the enclosed area by the orthographic projection of the first pixel driving circuit on the base substrate.
The display panel of claim 10, wherein the area enclosed by the orthographic projection of the light-emitting area of the third light-emitting device on the substrate is smaller than that of the light-emitting area of the second light-emitting device on the substrate. The area of the area enclosed by the orthographic projection of the substrate;

Along the first direction and pointing from the notch area to at least one of the first sub-area and the second sub-area, the light-emitting area of the third light-emitting device is located directly on the base substrate The area of the area enclosed by the projection decreases successively.
The display panel of claim 10, wherein the area of the area enclosed by the orthographic projection of the third light-emitting device on the base substrate is the same as the light-emitting area of the second light-emitting device on the substrate. The area enclosed by the orthographic projection of the substrate is approximately the same.
The display panel of claim 3, wherein the light-emitting device overlapping the orthographic projection of the base substrate and the winding area is a second light-emitting device, and a pixel electrically connected to the second light-emitting device is driven The circuit is a second pixel driving circuit;

The distribution density of the second pixel driving circuit is greater than the distribution density of the first pixel driving circuit.
The display panel according to claim 13, wherein the area enclosed by the orthographic projection of the second pixel driving circuit on the base substrate is smaller than the orthographic projection of the first pixel driving circuit on the base substrate The area of the enclosed area.
The display panel of claim 14, wherein, along the first direction and directed from the notch area to at least one of the first sub-area and the second sub-area, the second pixel The area of the area enclosed by the orthographic projection of the driving circuit on the base substrate increases sequentially.
15. The display panel of claim 14, wherein the area enclosed by the orthographic projection of each of the second pixel driving circuits on the base substrate is approximately the same.
16. The display panel of any one of claims 14-16, wherein the number of transistors in the second pixel driving circuit is smaller than the number of transistors in the first pixel driving circuit.
The display panel according to any one of claims 13-17, wherein the area of the light-emitting area of each second light-emitting device enclosed by the orthographic projection of the base substrate is equal to the light-emitting area of the first light-emitting device. The area of the area enclosed by the orthographic projection of the base substrate is approximately the same.
19. The display panel of claim 18, wherein the second light emitting devices in the second area are respectively located in the same column as the first light emitting devices in the first area and the second area.
19. The display panel of any one of claims 13-19, wherein the light emitting device located in the second area is a third light emitting device, and the pixel driving circuit electrically connected to the third light emitting device is a third pixel driving Circuit

The orthographic projection of the light-emitting area of the third light-emitting device on the base substrate is less than or approximately equal to the orthographic projection of the light-emitting area of the first light-emitting device on the base substrate.
22. The display panel of claim 20, wherein, along the first direction and directed from the notch area to at least one of the first sub-area and the second sub-area, the third pixel The area of the area enclosed by the orthographic projection of the driving circuit on the base substrate decreases successively.
The display panel of claim 10 or 20, wherein, for at least one third light emitting device adjacent to the second light emitting device, the third light emitting device is driven with the third pixel through a second conductive line The circuit is electrically connected.
22. The display panel of claim 22, wherein the display panel further comprises: a plurality of scan lines; wherein one row of the pixel driving circuit is electrically connected to at least one of the scan lines;

At least one of the first conductive line and the second conductive line and the scan line have the same layer and the same material and are arranged at intervals.
A display device comprising the display panel according to any one of claims 1-23.