CN115116332B - Display panel and display device - Google Patents
Display panel and display device Download PDFInfo
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- CN115116332B CN115116332B CN202210767702.7A CN202210767702A CN115116332B CN 115116332 B CN115116332 B CN 115116332B CN 202210767702 A CN202210767702 A CN 202210767702A CN 115116332 B CN115116332 B CN 115116332B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
- G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
- G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/2007—Display of intermediate tones
- G09G3/2074—Display of intermediate tones using sub-pixels
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/2085—Special arrangements for addressing the individual elements of the matrix, other than by driving respective rows and columns in combination
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- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
The application discloses a display panel and a display device, wherein the display panel is provided with a hole digging area and a display area; the display area comprises a first display area and a second display area which are adjacently arranged, and the first display area is positioned between the hole digging area and the second display area; the display panel comprises a substrate positioned in a display area, a plurality of signal lines positioned in a first display area and arranged on the substrate, a plurality of first light-emitting units positioned in the first display area and positioned on the plurality of signal lines, a plurality of pixel circuit units positioned in a second display area and mutually adjacent on the substrate, and a plurality of second light-emitting units positioned in the second display area and positioned on the plurality of pixel circuit units; the plurality of pixel circuit units are respectively and electrically connected with the plurality of first light emitting units and the plurality of second light emitting units in a one-to-one correspondence manner, and the size of one part of pixel circuit units in the plurality of pixel circuit units is smaller than that of the other part of pixel circuit units. The application can reduce the frame width of the hole digging area and improve the screen occupation ratio of the display panel.
Description
Technical Field
The application relates to the technical field of display, in particular to a display panel and a display device.
Background
Current mobile electronic terminals, particularly mobile phones, pursue the dual advantages of portability and large screen displays, which require electronic products with as high a screen ratio as possible. The design of the hole digging camera is one of methods for improving the screen occupation ratio, wherein a hole digging area designed on the screen for placing the front camera is an Ocut area. The edge of the Ocut region usually accommodates tens of signal lines, a packaging structure and the like, so that the width of the frame of the Ocut region is not easy to narrow. If the width of the frame of the Ocut area is too large, a circle of black edges appear on the periphery of the camera, so that the user visual experience is poor.
Disclosure of Invention
The application provides a display panel and a display device, which can reduce the frame width of a hole digging area and improve the screen occupation ratio of the display panel, thereby improving the visual experience of a user.
The application provides a display panel which is provided with a hole digging area and a display area positioned at the periphery of the hole digging area; the display area comprises a first display area and a second display area which are adjacently arranged, and the first display area is positioned between the hole digging area and the second display area;
the display panel comprises a substrate positioned in the display area, a plurality of signal lines positioned in the first display area and sequentially arranged on the substrate side by side, a plurality of first light-emitting units positioned in the first display area and positioned at one side of the plurality of signal lines far away from the substrate, a plurality of pixel circuit units positioned in the second display area and mutually adjacent on the substrate, and a plurality of second light-emitting units positioned in the second display area and positioned at one side of the plurality of pixel circuit units far away from the substrate;
the pixel circuit units are respectively and electrically connected with the first light-emitting units and the second light-emitting units in a one-to-one correspondence manner, and the orthographic projection area of one part of the pixel circuit units on the substrate is smaller than that of the other part of the pixel circuit units on the substrate.
Optionally, the second display area includes a first sub display area and a second sub display area that are adjacently disposed; the first sub-display area is positioned between the second sub-display area and the first display area;
the orthographic projection area of each pixel circuit unit positioned in the first sub-display area on the substrate is smaller than the orthographic projection area of each pixel circuit unit positioned in the second sub-display area on the substrate, and the orthographic projection areas of a plurality of pixel circuit units positioned in the second sub-display area on the substrate are the same.
Optionally, the orthographic projection areas of the plurality of pixel circuit units located in the first sub-display area on the substrate are the same.
Optionally, the plurality of pixel circuit units are distributed in a plurality of rows and a plurality of columns in the first sub-display area and the second sub-display area; the first sub-display area and the first display area are arranged side by side in the row direction;
the width of each pixel circuit unit in the column direction is the same, and the width of the pixel circuit unit in the row direction of the first sub-display area is smaller than the width of the pixel circuit unit in the row direction of the second sub-display area.
Optionally, the plurality of pixel circuit units are distributed in a plurality of rows and a plurality of columns in the first sub-display area and the second sub-display area; the first sub-display area and the first display area are arranged side by side in the column direction;
the width of each pixel circuit unit in the row direction is the same, and the width of the pixel circuit unit in the column direction of the first sub-display area is smaller than the width of the pixel circuit unit in the column direction of the second sub-display area.
Optionally, the plurality of pixel circuit units are distributed in a plurality of rows and a plurality of columns in the first sub-display area and the second sub-display area; the first display area is arranged around the hole digging area; the first sub-display area includes a first area located at both sides of the first display area in the row direction and a second area located at both sides of the first display area in the column direction;
the width of the pixel circuit units located in the first region in the row direction is smaller than the width of the pixel circuit units located in the second sub-display area in the row direction, and the widths of the pixel circuit units in the first region and the second sub-display area in the column direction are the same; the width of the pixel circuit units located in the second region in the column direction is smaller than the width of the pixel circuit units located in the second sub-display area in the column direction, and the widths of the pixel circuit units in the second region and the second sub-display area in the row direction are the same.
Optionally, the size and shape of the orthographic projection of the first light emitting unit on the substrate are the same as the size and shape of the orthographic projection of the second light emitting unit on the substrate, and the arrangement period and density of the first light emitting unit and the second light emitting unit are the same.
Optionally, the plurality of first light emitting units and the plurality of second light emitting units are distributed in a plurality of rows and a plurality of columns;
the second light-emitting units in the second sub-display area are arranged in one-to-one correspondence with the pixel circuit units in the corresponding electrical connection, and the second light-emitting units in the first sub-display area are arranged in dislocation with the pixel circuit units in the corresponding electrical connection.
Optionally, the first display area is disposed around the hole digging area; the display panel further comprises a first wiring part and a second wiring part which are separated by the hole digging part; the signal wire extends at least partially along the edge direction of the hole digging area and is electrically connected with the first wire routing part and the second wire routing part respectively.
The application also provides a display device which comprises the display panel and the optical sensor arranged in the hole digging area.
According to the display panel and the display device, the plurality of signal lines and the plurality of first light-emitting units positioned above the plurality of signal lines are arranged in the first display area close to the hole digging area, and the size of part of pixel driving circuits is compressed in the second display area far away from the hole digging area so as to add the plurality of pixel driving circuits which are correspondingly and electrically connected with the plurality of first light-emitting units; the display area is increased, the frame width of the hole digging area is reduced, the screen occupation ratio of the display panel is improved, and the visual experience of a user is improved.
Drawings
The technical solution and other advantageous effects of the present application will be made apparent by the following detailed description of the specific embodiments of the present application with reference to the accompanying drawings.
Fig. 1 is a schematic top view of a display panel in the prior art.
Fig. 2 is a schematic diagram of a partial structure of the display panel provided in fig. 1.
Fig. 3 is a schematic top view of a display panel according to an embodiment of the application.
Fig. 4 is an enlarged partial view of the portion a in fig. 3.
Fig. 5 is a schematic distribution diagram of a first sub-display area of a display panel according to an embodiment of the present application.
Fig. 6 is a schematic distribution diagram of a first sub-display area of another display panel according to an embodiment of the application.
Fig. 7 is a schematic distribution diagram of a first sub-display area of another display panel according to an embodiment of the application.
Fig. 8 is a schematic distribution diagram of a first sub-display area of another display panel according to an embodiment of the application.
Fig. 9 is a schematic partial top view of a display area of a display panel according to an embodiment of the application.
Fig. 10 is a schematic cross-sectional structure of a display device according to an embodiment of the application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. It will be apparent that the described embodiments are only some, but not all, embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to fall within the scope of the application.
In the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings are merely for convenience in describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present application. Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more of the described features. In the description of the present application, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.
In the description of the present application, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; can be mechanically connected, electrically connected or can be communicated with each other; can be directly connected or indirectly connected through an intermediate medium, and can be communicated with the inside of two elements or the interaction relationship of the two elements. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art according to the specific circumstances.
In the present application, unless expressly stated or limited otherwise, a first feature "above" or "below" a second feature may include both the first and second features being in direct contact, as well as the first and second features not being in direct contact but being in contact with each other through additional features therebetween. Moreover, a first feature being "above," "over" and "on" a second feature includes the first feature being directly above and obliquely above the second feature, or simply indicating that the first feature is higher in level than the second feature. The first feature being "under", "below" and "beneath" the second feature includes the first feature being directly under and obliquely below the second feature, or simply means that the first feature is less level than the second feature.
The following disclosure provides many different embodiments, or examples, for implementing different features of the application. In order to simplify the present disclosure, components and arrangements of specific examples are described below. They are, of course, merely examples and are not intended to limit the application. Furthermore, the present application may repeat reference numerals and/or letters in the various examples, which are for the purpose of brevity and clarity, and which do not themselves indicate the relationship between the various embodiments and/or arrangements discussed. In addition, the present application provides examples of various specific processes and materials, but one of ordinary skill in the art will recognize the application of other processes and/or the use of other materials.
Fig. 1 and 2 provide an exemplary display panel 1', the display panel 1' having a cutout region (i.e., ocut region) 2' for placing a front camera, and a display region 3' disposed around the cutout region 2 '; the display area 3 'of the display panel 1' is provided with a plurality of pixel circuit units 4 'which are distributed in a plurality of rows and a plurality of columns and are sequentially arranged adjacently in the row direction and the column direction, and a light emitting unit 5' which is arranged on the plurality of pixel circuit units 4 'and is electrically connected with the plurality of pixel circuit units 4' in a one-to-one correspondence manner; the area of the orthographic projection of each pixel circuit unit 4 'in the direction perpendicular to the display panel 1' is the same. Since the frame area 7 'for accommodating the package structure and the plurality of signal lines (e.g., data line windings) 6' is further included between the hole area 2 'and the display area 3', the frame of the hole area 2 'is too wide, which results in a circle of black edges around the camera, and the user's visual experience is poor.
In order to solve the above technical problems, the present application provides a new display panel and display device, with specific reference to the following description of embodiments.
As shown in fig. 3 and 4, the embodiment of the present application provides a display panel 1, the display panel 1 having a hole digging area (i.e., an Ocut area) 2 and a display area 3 located at the periphery of the hole digging area 2; the display area 3 comprises a first display area 4 and a second display area 5 which are adjacently arranged, and the first display area 4 is positioned between the hole digging area 2 and the second display area 5.
As shown in fig. 4, the display panel 1 includes a substrate (not shown in the drawing) located in the display area 3, a plurality of signal lines (e.g., data line wiring) 7 located in the first display area 4 and sequentially arranged side by side on the substrate, a plurality of first light emitting units 8 located in the first display area 4 and located on a side of the plurality of signal lines 7 away from the substrate, a plurality of pixel circuit units 9 located in the second display area 5 and mutually adjoining on the substrate, and a plurality of second light emitting units 10 located in the second display area 5 and located on a side of the plurality of pixel circuit units 9 away from the substrate.
The plurality of pixel circuit units 9 are respectively and electrically connected with the plurality of first light emitting units 8 and the plurality of second light emitting units 10 in a one-to-one correspondence manner, and the orthographic projection area of one part of the pixel circuit units 9 on the substrate is smaller than the orthographic projection area of the other part of the pixel circuit units 9 on the substrate.
Specifically, the first display area 4 is disposed around the hole digging area 2; the display panel 1 further includes a first wiring portion and a second wiring portion (not shown in the drawings) separated by the hole-bored area 2; the signal line 7 extends at least partially along the edge direction of the hole digging region and is electrically connected with the first wiring portion and the second wiring portion respectively. It will be appreciated that the signal lines 7 in the embodiment of the present application are connection lines for connecting two wiring portions separated by the hole-digging region 2. In a specific embodiment, the first wire portion and the second wire portion are data wires extending along a same direction and used for transmitting a same data signal, and the corresponding signal wire 7 is a data wire winding and used for communicating the first wire portion and the second wire portion. In other embodiments, the signal line 7 may be a scan line winding; of course, the specific winding type is not limited thereto.
It should be noted that, the front projection area of a part of the pixel circuit units 9 on the substrate is smaller than the front projection area of another part of the pixel circuit units 9 on the substrate in the plurality of pixel circuit units 9, which means the size comparison between the front projection areas of the single pixel circuit units 9 on the substrate. For convenience of description, a part of the following will represent the projected area in terms of dimensions.
It can be understood that the embodiment of the present application is improved on the basis of the display panel 1 shown in fig. 1 and 2, and on the basis of not changing the positional relationship between the hole digging area 2 and the signal lines 7, a plurality of first light emitting units 8 are added on the plurality of signal lines 7, and the size of a part of the pixel circuit units 9 in the second display area 5 is compressed, so as to add the pixel circuit units 9 correspondingly and electrically connected to the first light emitting units 8.
Specifically, the size of the partial pixel circuit units 9 in the second display area 5 is compressed such that the orthographic projection area of the partial pixel circuit units 9 on the substrate is smaller than the orthographic projection area of the other partial pixel circuit units 9 on the substrate. It will be appreciated that the size of the pixel circuit unit 9 which is not compressed may be the size of the pixel circuit unit in a display panel of the prior art (e.g., the display panel 1' shown in fig. 1 and 2).
It should be noted that, the size of the pixel circuit unit 9 is compressed to be narrowed within the allowable range of the process capability, so as to avoid affecting the normal functions of the pixel circuit unit 9.
Specifically, when the accommodation space required for the pixel circuit units 9 electrically connected to the first light emitting unit 8 is added to the second display area 5, a certain number of pixel circuit units 9 may be selected for compression, and the larger the number of compressed pixel circuit units 9, the smaller the influence on the pixel circuit units 9.
As shown in fig. 2, the width of the visual frame of the hole-digging area 2 'of the display panel 1' in the prior art is equal to the distance D1 between the display area 3 'and the hole-digging area 2', which is equal to the distance between the second display area 5 and the hole-digging area 2 in the present application; as shown in fig. 4, in the embodiment of the present application, the width of the visual frame of the hole digging area 2 of the display panel 1 is equal to the distance D2 between the first display area 4 and the hole digging area 2; clearly, D2 is smaller than D1. Therefore, the embodiment of the application can visually reduce the frame width of the hole digging area.
Specifically, as shown in fig. 4, the second display area 5 includes a first sub display area 11 and a second sub display area 12 that are adjacently disposed; the first sub-display area 11 is located between the second sub-display area 12 and the first display area 4; the front projection area of each pixel circuit unit 9 located in the first sub-display area 11 on the substrate is smaller than the front projection area of each pixel circuit unit 9 located in the second sub-display area 12 on the substrate, and the front projection areas of the plurality of pixel circuit units 9 located in the second sub-display area 12 on the substrate are the same.
It will be appreciated that the present application compresses only the size of the pixel circuit units 9 in the first sub-display area 11 disposed close to the first display area 4, while does not compress the size of the pixel circuit units 9 located in the second sub-display area 12 (i.e., away from the first display area 4).
Specifically, the orthographic projection areas of the plurality of pixel circuit units 9 located in the first sub-display area 11 on the substrate are the same, that is, the compressed size of each pixel circuit unit 9 in the first sub-display area 11 is the same, which is beneficial to simplifying the process. Of course, the front projection of the plurality of pixel circuit units 9 located in the first sub-display area 11 on the substrate may also gradually decrease in one direction, but may cause a complex process.
Specifically, the plurality of pixel circuit units 9 are distributed in a plurality of rows and columns in the first sub-display area 11 and the second sub-display area 12.
In a specific embodiment, as shown in fig. 5 and 6, the first sub-display area 11 is disposed side by side with the first display area 4 in the row direction; as shown in fig. 4, the width of each pixel circuit unit 9 in the column direction is the same, and the width W1 of the pixel circuit unit 9 in the row direction in the first sub-display area 11 is smaller than the width W2 of the pixel circuit unit 9 in the row direction in the second sub-display area 12. It will be appreciated that in this embodiment, the pixel circuit units 9 in the first sub-display area 11 are compressed in size in the row direction.
Of course, in another specific embodiment, the first sub-display area and the first display area may also be arranged side by side in the column direction; the width of each pixel circuit unit in the row direction is the same, and the width of the pixel circuit unit in the first sub-display area in the column direction is smaller than the width of the pixel circuit unit in the second sub-display area in the column direction. It will be appreciated that in this embodiment, the pixel circuit units in the first sub-display section are compressed in size in the column direction.
In another embodiment, as shown in fig. 7 and 8, the first display area 4 is disposed around the hole digging area 2; the first sub-display area 11 includes first areas 13 located on both sides of the first display area 4 in the row direction and second areas 14 located on both sides of the first display area 4 in the column direction. Specifically, the width of the pixel circuit unit 9 located in the first region 13 in the row direction is smaller than the width of the pixel circuit unit 9 located in the second sub-display area 12 in the row direction, and the widths of the pixel circuit units 9 in the first region 13 and the second sub-display area 12 in the column direction are the same; the width of the pixel circuit unit 9 located in the second region 14 in the column direction is smaller than the width of the pixel circuit unit 9 located in the second sub-display area 12 in the column direction, and the widths of the pixel circuit units 9 in the second region 14 and the second sub-display area 12 in the row direction are the same. It will be appreciated that in this embodiment, the pixel circuit cells 9 in the first region 13 are compressed in the row direction and the pixel circuit cells 9 in the second region 14 are compressed in the column direction.
Specifically, as shown in fig. 5 and 6, when the first sub-display area 11 is arranged side by side in the row direction with the first display area 4, the second sub-display area 12 is adjacent to the first sub-display area 11 at least in the column direction; as shown in fig. 7 and 8, when the first sub-display area 11 and the first display area 4 are arranged side by side in the column direction, the second sub-display area 12 is adjacent to the first sub-display area 11 at least in the row direction. It will be appreciated that when the first sub-display area 11 is arranged side by side with the first display area 4 in the row direction, the second sub-display area 12 may also be arranged partially side by side with the first sub-display area 11 in the row direction, and when the first sub-display area 11 is arranged side by side with the first display area 4 in the column direction, the second sub-display area 12 may also be arranged partially side by side with the first sub-display area 11 in the column direction.
Specifically, as shown in fig. 4, the size and shape of the orthographic projection of the first light emitting unit 8 on the substrate are the same as the size and shape of the orthographic projection of the second light emitting unit 10 on the substrate, respectively, and the arrangement period and density of the first light emitting unit 8 and the second light emitting unit 10 are the same.
It will be appreciated that the structure and arrangement of the first light emitting unit 8 added to the first display area 4 is the same as the structure and arrangement of the second light emitting unit 10 located in the second display area 5. That is, the present application does not require changing the structural size, arrangement period and arrangement density of the light emitting units, and only requires increasing the number of light emitting units.
Specifically, each first light emitting unit 8 and each second light emitting unit 10 includes at least two sub light emitting units emitting different colors of light; the pixel driving unit includes at least two sub-pixel driving units respectively and correspondingly electrically connected with the at least two sub-light emitting units. It will be appreciated that different pixel arrangements may include different numbers of sub-light emitting units per light emitting unit.
In a specific embodiment, as shown in fig. 4 and 9, each first light emitting unit 8 includes two sub light emitting units for emitting different colors of light, for example, a first sub light emitting unit 15 and a second sub light emitting unit 15'; and each of the second light emitting units 10 includes two sub light emitting units for emitting light of different colors. In this embodiment, each adjacent two first light emitting units 8 (or second light emitting units 10) in the row direction and in the column direction are one arrangement unit 17, one of the light emitting units in each arrangement unit 17 includes one blue sub light emitting unit (B) and one green sub light emitting unit (G), the other light emitting unit includes one red sub light emitting unit (R) and one green sub light emitting unit (G), and the adjacent blue sub light emitting units (B), green sub light emitting units (G), and red sub light emitting units (R) are distributed in a triangle shape. Since the second light emitting unit 10 is identical to the first light emitting unit 8, the arrangement of the second light emitting unit 10 will not be described here.
In another embodiment, each of the first light emitting units (second light emitting units) may further include three sub light emitting units for emitting different colors of light, for example, a red sub light emitting unit (R), a green sub light emitting unit (G), and a blue sub light emitting unit (B).
Specifically, the first light emitting unit (second light emitting unit) includes an anode layer, a pixel defining layer, a supporting layer, a light emitting material layer, and a cathode layer, which are sequentially disposed.
Specifically, as shown in fig. 4, the plurality of first light emitting units 8 and the plurality of second light emitting units 10 are distributed in a plurality of rows and a plurality of columns; the plurality of second light emitting units 10 in the second sub-display area 12 are arranged in one-to-one correspondence with the plurality of pixel circuit units 9 correspondingly electrically connected, and the plurality of second light emitting units 10 in the first sub-display area 11 are arranged in a staggered manner with the plurality of pixel circuit units 9 correspondingly electrically connected.
Specifically, as shown in fig. 9, the display panel 1 further includes connection wirings 18 between each of the first light emitting units 8 and the corresponding pixel circuit unit 9. Since each of the first light emitting units 8 includes at least the first and second sub-light emitting units 15 and 15', the corresponding pixel circuit unit 9 corresponding to the first light emitting unit 8 includes at least the first and second sub-pixel circuit units 16 and 16' corresponding to the first and second sub-light emitting units 15 and 15'; and each of the first sub-light emitting units 15 and the corresponding first sub-pixel circuit units 16 and each of the second sub-light emitting units 15 'and the corresponding second sub-pixel circuit units 16' are electrically connected through connection wires 18.
In fig. 9, the connection object of the connection trace 18 is schematically indicated by a line with an arrow, and the specific arrangement is not limited.
In the embodiment of the application, on the basis of not changing the positions of the windings (such as the plurality of signal lines 7) on the frame of the hole digging area 2 and not changing the whole area of the pixel circuit units 9 of the display area 3, a plurality of first light emitting units 8 are arranged above the plurality of signal lines 7 to form a first display area 4, and the sizes of part of the pixel circuit units 9 in the second display area 5 adjacent to the first display area 4 are compressed to add a plurality of pixel circuit units 9 correspondingly and electrically connected with the plurality of first light emitting units 8, so that the arrangement of the pixel circuit units 9 in the first display area 4 is avoided; according to the application, on one hand, the problem of insufficient space of the first display area 4 can be solved, and on the other hand, the frame width of the hole digging area 2 is reduced while the display area is increased, the screen occupation ratio of the display panel 1 is improved, and the visual experience of a user is improved.
As shown in fig. 10, the present application further provides a display device 19, where the display device 19 includes the display panel 1 described in the above embodiment and the optical sensor 20 disposed in the hole digging area 2.
Specifically, the optical sensor 20 includes a camera, a fingerprint recognition sensor, a face recognition sensor, or other sensors.
Specifically, the display device 19 further includes a protection layer 21 disposed on the light-emitting surface of the display panel 1 to protect the display panel 1.
In the embodiment of the application, a plurality of signal lines 7 and a plurality of first light emitting units 8 positioned above the plurality of signal lines 7 are arranged in a first display area 4 which is close to a hole digging area 2, and the size of part of pixel driving circuits is compressed in a second display area 5 which is far away from the hole digging area 2 so as to add a plurality of pixel driving circuits which are correspondingly and electrically connected with the plurality of first light emitting units 8; the display area is increased, the frame width of the hole digging area 2 is reduced, the screen occupation ratio of the display panel 1 is improved, a circle of black edges are avoided around the periphery of the optical sensor (such as a camera) 20, and the visual experience of a user is improved.
In the foregoing embodiments, the descriptions of the embodiments are emphasized, and for parts of one embodiment that are not described in detail, reference may be made to related descriptions of other embodiments.
The display panel and the display device provided by the embodiments of the present application are described in detail, and specific examples are applied to illustrate the principles and the embodiments of the present application, and the description of the above embodiments is only used to help understand the technical solution and the core idea of the present application; those of ordinary skill in the art will appreciate that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the application.
Claims (5)
1. A display panel, characterized by having a hole digging area and a display area located at the periphery of the hole digging area; the display area comprises a first display area and a second display area which are adjacently arranged, and the first display area is positioned between the hole digging area and the second display area;
the display panel comprises a substrate positioned in the display area, a plurality of signal lines positioned in the first display area and sequentially arranged on the substrate side by side, a plurality of first light-emitting units positioned in the first display area and positioned at one side of the plurality of signal lines far away from the substrate, a plurality of pixel circuit units positioned in the second display area and mutually adjacent on the substrate, and a plurality of second light-emitting units positioned in the second display area and positioned at one side of the plurality of pixel circuit units far away from the substrate;
the pixel circuit units are respectively and electrically connected with the first light-emitting units and the second light-emitting units in a one-to-one correspondence manner; the second display area comprises a first sub display area and a second sub display area which are adjacently arranged; the first sub-display area is positioned between the second sub-display area and the first display area; the orthographic projection area of each pixel circuit unit positioned in the first sub-display area on the substrate is smaller than that of each pixel circuit unit positioned in the second sub-display area; the orthographic projection areas of the pixel circuit units positioned in the first sub-display area on the substrate are the same, and the orthographic projection areas of the pixel circuit units positioned in the second sub-display area on the substrate are the same;
the pixel circuit units are distributed in a plurality of rows and columns in the first sub-display area and the second sub-display area; the first sub-display area and the first display area are arranged side by side in the row direction or the column direction;
when the first sub-display area and the first display area are arranged side by side in the row direction, the width of each pixel circuit unit in the column direction is the same, and the width of the pixel circuit unit in the first sub-display area in the row direction is smaller than the width of the pixel circuit unit in the second sub-display area in the row direction;
when the first sub-display area and the first display area are arranged side by side in the column direction, the width of each pixel circuit unit in the row direction is the same, and the width of the pixel circuit unit in the first sub-display area in the column direction is smaller than the width of the pixel circuit unit in the second sub-display area in the column direction.
2. The display panel according to claim 1, wherein the size and shape of the orthographic projection of the first light emitting unit on the substrate are the same as the size and shape of the orthographic projection of the second light emitting unit on the substrate, respectively, and the arrangement period and density of the first light emitting unit and the second light emitting unit are the same.
3. The display panel of claim 2, wherein the plurality of first light emitting units and the plurality of second light emitting units are distributed in a plurality of rows and a plurality of columns;
the second light-emitting units in the second sub-display area are arranged in one-to-one correspondence with the pixel circuit units in the corresponding electrical connection, and the second light-emitting units in the first sub-display area are arranged in dislocation with the pixel circuit units in the corresponding electrical connection.
4. The display panel of claim 1, wherein the first display region is disposed around the cutout region; the display panel further comprises a first wiring part and a second wiring part which are separated by the hole digging part; the signal wire extends at least partially along the edge direction of the hole digging area and is electrically connected with the first wire routing part and the second wire routing part respectively.
5. A display device comprising the display panel of any one of claims 1 to 4 and an optical sensor provided in the hole-bored area.
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| CN202210767702.7A CN115116332B (en) | 2022-06-30 | 2022-06-30 | Display panel and display device |
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| CN202210767702.7A CN115116332B (en) | 2022-06-30 | 2022-06-30 | Display panel and display device |
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| CN115116332B (en) * | 2022-06-30 | 2023-09-01 | 武汉华星光电半导体显示技术有限公司 | Display panel and display device |
Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109119447A (en) * | 2018-08-29 | 2019-01-01 | 武汉天马微电子有限公司 | Display panel and display device |
| CN109377882A (en) * | 2018-11-29 | 2019-02-22 | 武汉华星光电技术有限公司 | A kind of flexible display panels |
| CN112542092A (en) * | 2020-12-08 | 2021-03-23 | 合肥维信诺科技有限公司 | Display panel and display device |
| CN112599580A (en) * | 2020-12-14 | 2021-04-02 | 合肥维信诺科技有限公司 | Display panel and display device |
| WO2021244228A1 (en) * | 2020-06-02 | 2021-12-09 | 京东方科技集团股份有限公司 | Display panel, display device, and manufacturing method for display panel |
| CN113994419A (en) * | 2020-05-27 | 2022-01-28 | 京东方科技集团股份有限公司 | Display panel and display device |
| CN114335069A (en) * | 2020-09-29 | 2022-04-12 | 京东方科技集团股份有限公司 | Display panel and display device |
| WO2022088030A1 (en) * | 2020-10-30 | 2022-05-05 | 京东方科技集团股份有限公司 | Display substrate, display panel, and display device |
| CN114464658A (en) * | 2022-01-29 | 2022-05-10 | 昆山国显光电有限公司 | Display panel and display device |
| CN115116332A (en) * | 2022-06-30 | 2022-09-27 | 武汉华星光电半导体显示技术有限公司 | Display panel and display device |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101097338B1 (en) * | 2010-03-05 | 2011-12-21 | 삼성모바일디스플레이주식회사 | Organic light emitting display device |
| US20210201721A1 (en) * | 2019-12-31 | 2021-07-01 | Wuhan China Star Optoelectronics Semiconductor Display Technology Co.,Ltd | Foldable display panel and foldable display device |
-
2022
- 2022-06-30 CN CN202210767702.7A patent/CN115116332B/en active Active
Patent Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109119447A (en) * | 2018-08-29 | 2019-01-01 | 武汉天马微电子有限公司 | Display panel and display device |
| CN109377882A (en) * | 2018-11-29 | 2019-02-22 | 武汉华星光电技术有限公司 | A kind of flexible display panels |
| CN113994419A (en) * | 2020-05-27 | 2022-01-28 | 京东方科技集团股份有限公司 | Display panel and display device |
| WO2021244228A1 (en) * | 2020-06-02 | 2021-12-09 | 京东方科技集团股份有限公司 | Display panel, display device, and manufacturing method for display panel |
| CN114335069A (en) * | 2020-09-29 | 2022-04-12 | 京东方科技集团股份有限公司 | Display panel and display device |
| WO2022088030A1 (en) * | 2020-10-30 | 2022-05-05 | 京东方科技集团股份有限公司 | Display substrate, display panel, and display device |
| CN112542092A (en) * | 2020-12-08 | 2021-03-23 | 合肥维信诺科技有限公司 | Display panel and display device |
| CN112599580A (en) * | 2020-12-14 | 2021-04-02 | 合肥维信诺科技有限公司 | Display panel and display device |
| CN114464658A (en) * | 2022-01-29 | 2022-05-10 | 昆山国显光电有限公司 | Display panel and display device |
| CN115116332A (en) * | 2022-06-30 | 2022-09-27 | 武汉华星光电半导体显示技术有限公司 | Display panel and display device |
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|---|---|
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