CN112967682B

CN112967682B - Display panel and display device

Info

Publication number: CN112967682B
Application number: CN202110369422.6A
Authority: CN
Inventors: 李敏; 芦兴; 王永志; 彭涛
Original assignee: Wuhan Tianma Microelectronics Co Ltd
Current assignee: Wuhan Tianma Microelectronics Co Ltd
Priority date: 2019-12-19
Filing date: 2019-12-19
Publication date: 2022-05-27
Anticipated expiration: 2039-12-19
Also published as: CN110992880B; CN112967682A; CN110992880A

Abstract

The invention discloses a display panel and a display device, wherein a threshold compensation circuit comprises: a first threshold compensation transistor, a second threshold compensation transistor and a shield capacitor; here, by providing the first threshold compensation transistor and the second threshold compensation transistor, the length L of the channel region of the transistor can be increased, and since the current I of the transistor is inversely proportional to the length L of the channel region, the current I of the transistor can be decreased when the length L of the channel region is increased, so that the amount of charge flowing from the node N4 into the node N1 can be reduced. Further, by providing the shield capacitor, the effect of the shield capacitor storing the electric charge can be utilized so that the electric charge of the node N4 is stored in the shield capacitor. Thus, when the signal on the scanning signal line is switched, the charge injection of the node N4 into the node N1 can be avoided, so that the voltage of the gate of the driving transistor can be kept stable, and the display uniformity of the display panel can be improved.

Description

Display panel and display device

The application is a divisional application with the application date of 2019, 12 and 19, and the application number of 201911318851.X, and the name of 'a display panel and a display device' is invented and created.

Technical Field

The present invention relates to the field of display technologies, and in particular, to a display panel and a display device.

Background

An Organic Light Emitting Diode (OLED) Display is one of the hot spots in the research field of flat panel displays, and compared with a Liquid Crystal Display (LCD), an OLED Display has the advantages of low energy consumption, low production cost, self-luminescence, wide viewing angle, fast response speed, and the like. Among them, the pixel circuit for controlling the light emission of the light emitting device is the core technical content of the OLED display, and has important research significance. However, the voltage of the gate of the driving transistor is unstable, which causes unstable light emission and thus causes a problem of luminance unevenness.

Disclosure of Invention

Embodiments of the present invention provide a display panel and a display device, so as to solve the problem of unstable gate voltage of a driving transistor due to leakage current.

An embodiment of the present invention provides a display panel, including: the liquid crystal display device comprises a substrate base plate, a plurality of sub-pixels and a plurality of scanning signal lines, wherein the sub-pixels and the scanning signal lines are positioned on the substrate base plate; a row of sub-pixels corresponds to at least one scanning signal line; each of the sub-pixels includes a pixel circuit; the pixel circuit comprises a threshold compensation circuit and a drive transistor; the threshold compensation circuit includes: a first threshold compensation transistor, a second threshold compensation transistor and a shield capacitor;

a gate of the first threshold compensation transistor and a gate of the second threshold compensation transistor are electrically connected to the corresponding scan signal line, a first pole of the first threshold compensation transistor is electrically connected to the gate of the driving transistor, a second pole of the first threshold compensation transistor is electrically connected to a first pole of the second threshold compensation transistor, and a second pole of the second threshold compensation transistor is electrically connected to a second pole of the driving transistor;

a first electrode of the shielding capacitor is electrically connected with a second electrode of the first threshold compensation transistor, and a second electrode of the shielding capacitor is electrically connected with a fixed voltage signal end;

the orthographic projection of the second electrode of the shielding capacitor on the substrate base plate is not overlapped with the orthographic projection of a scanning signal line electrically connected with the first threshold compensation transistor on the substrate base plate.

The embodiment of the invention also provides a display device which comprises the display panel.

The invention has the following beneficial effects:

in the display panel and the display device according to the embodiments of the present invention, the threshold compensation circuit includes: a first threshold compensation transistor, a second threshold compensation transistor and a shield capacitor; here, by providing the first threshold compensation transistor and the second threshold compensation transistor, the length L of the channel region of the transistor can be increased, and since the current I of the transistor is inversely proportional to the length L of the channel region, the current I of the transistor can be decreased when the length L of the channel region is increased, so that the amount of charge flowing from the node N4 into the node N1 can be reduced. Further, by providing the shield capacitor, the effect of the shield capacitor storing the electric charge can be utilized so that the electric charge of the node N4 is stored in the shield capacitor. Thus, when the signal on the scanning signal line is switched, the charge injection of the node N4 into the node N1 can be avoided, so that the voltage of the gate of the driving transistor can be kept stable, and the display uniformity of the display panel can be improved.

Drawings

Fig. 1 is a schematic structural diagram of a pixel circuit in the related art;

FIG. 2 is a signal timing diagram corresponding to the pixel circuit shown in FIG. 1;

FIG. 3 is a schematic diagram of a display panel according to an embodiment of the present invention;

FIG. 4 is a schematic structural diagram of a pixel circuit according to an embodiment of the present invention;

FIG. 5 is a signal timing diagram corresponding to the pixel circuit shown in FIG. 4;

FIG. 6 is a diagram illustrating a layout structure of a pixel circuit according to an embodiment of the present invention;

fig. 7 is a schematic cross-sectional view along direction AA' of the layout structure of the pixel circuit shown in fig. 6;

FIG. 8 is a schematic diagram of another layout structure of a pixel circuit according to an embodiment of the present invention;

fig. 9 is a schematic cross-sectional view along direction AA' of the layout structure of the pixel circuit shown in fig. 8;

FIG. 10 is a schematic diagram illustrating a layout structure of a pixel circuit according to yet another embodiment of the present invention;

fig. 11 is a schematic cross-sectional view along the direction AA' of the layout structure of the pixel circuit shown in fig. 10;

FIG. 12 is a schematic diagram illustrating a layout structure of a pixel circuit according to yet another embodiment of the present invention;

fig. 13 is a schematic cross-sectional view along the direction AA' in the schematic layout structure of the pixel circuit shown in fig. 12;

fig. 14 is a schematic structural diagram of a display device in an embodiment of the invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the drawings of the embodiments of the present invention. It is to be understood that the embodiments described are only a few embodiments of the present invention, and not all embodiments. And the embodiments and features of the embodiments may be combined with each other without conflict. All other embodiments, which can be derived by a person skilled in the art from the described embodiments of the invention without any inventive step, are within the scope of protection of the invention.

Unless defined otherwise, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this invention belongs. The use of "first," "second," and similar terms in the present application do not denote any order, quantity, or importance, but rather the terms are used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

It should be noted that the sizes and shapes of the figures in the drawings are not to be considered true scale, but are merely intended to schematically illustrate the present invention. And the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout.

As shown in fig. 1, the pixel circuit may include: switching transistors M01-M06, a driving transistor M0 and a capacitor C0. A circuit timing diagram corresponding to the pixel circuit shown in fig. 1 is shown in fig. 2. The specific working process is basically the same as that in the related art, and is not described herein.

In practical applications, the switching transistor M04 may be configured as a double gate structure type transistor. That is, the switching transistor M04 may include: a sub transistor M041 and a sub transistor M042. In the stage T02, the signal S02 is a low level signal, so that the sub-transistor M041 and the sub-transistor M042 are both turned on, and a current flows from the node N3 to the node N1 through the sub-transistor M042 and the sub-transistor M041, so that the node N4 has charges. However, at the moment when the signal S02 is switched from the low level signal to the high level signal, since the sub-transistor M041 is not immediately turned off, the charge stored at the node N4 is injected into the node N1, so that the voltage at the node N1 changes, i.e., the gate voltage of the driving transistor M0 changes, and thus the luminance changes. The voltage variation of the node N1 is different in different areas of the display panel, so that the display panel has the problem of display non-uniformity.

Specifically, in the stage T03, the current I generated by the driving transistor M0 to drive the light emitting device L to emit light satisfies the formula: k (Vdd-VN1- | Vth |)²Where k is a structural parameter, Vdd represents a voltage on the first power line PVDD, VN1 represents a voltage on the node N1, and Vth represents a threshold voltage of the driving transistor M0. At the instant when the signal S02 switches from a low signal to a high signal, the charge stored at the node N4 is injected into the node N1, which causes the voltage VN1 at the node N1 to increase. As can be seen from the formula satisfied by the current I, VN1 rises and the current I falls, thereby causing a problem that the luminance of the light emitting device declines.

It should be noted that, in an ideal state, when the signal S02 is switched from a low-level signal to a high-level signal, the sub-transistors M042 and M041 may be in an off state. However, in practical applications, the sub-transistors M042 and M041 are not immediately turned off, so that the nodes N4 and N1 are turned on through the sub-transistor M041, and the charge stored at the node N4 is injected into the node N1.

An embodiment of the present invention provides a display panel, as shown in fig. 3 and 4, which may include: a substrate 10, a plurality of sub-pixels spx and a plurality of scanning signal lines on the substrate 10; a row of sub-pixels spx corresponds to at least one scanning signal line; each sub-pixel spx includes a pixel circuit 001; the pixel circuit 001 includes a threshold compensation circuit 002 and a drive transistor M0; the threshold compensation circuit 002 may include: a first threshold compensation transistor M41, a second threshold compensation transistor M42, and a shield capacitor CF.

The gate of the first threshold compensation transistor M41 and the gate of the second threshold compensation transistor M42 are electrically connected to the corresponding scan signal line, the first pole of the first threshold compensation transistor M41 is electrically connected to the gate of the driving transistor M0, the second pole of the first threshold compensation transistor M41 is electrically connected to the first pole of the second threshold compensation transistor M42, and the second pole of the second threshold compensation transistor M42 is electrically connected to the second pole of the driving transistor M0; the node N4 is connected between the second pole of the first threshold compensation transistor M41 and the first pole of the second threshold compensation transistor M42.

A first electrode of the shielding capacitor CF is electrically connected with a second electrode of the first threshold compensation transistor M41, and a second electrode of the shielding capacitor CF is electrically connected with a fixed voltage signal end;

the orthographic projection of the second electrode of the shielding capacitor CF on the substrate base plate 10 and the orthographic projection of the scanning signal line electrically connected with the first threshold compensation transistor M41 on the substrate base plate 10 do not overlap.

In the display panel provided in the embodiment of the present invention, the threshold compensation circuit includes: a first threshold compensation transistor, a second threshold compensation transistor and a shield capacitor; here, by providing the first threshold compensation transistor and the second threshold compensation transistor, the length L of the channel region of the transistor can be increased, and since the current I of the transistor is inversely proportional to the length L of the channel region, the current I of the transistor can be decreased when the length L of the channel region is increased, so that the amount of charge flowing from the node N4 into the gate of the driving transistor (i.e., the node N1) can be reduced. Further, by providing the shield capacitor, the effect of the shield capacitor storing the electric charge can be utilized so that the electric charge of the node N4 is stored in the shield capacitor. Thus, when the signal on the scanning signal line is switched, the charge of the node N4 can be prevented from being injected into the node N1, so that the voltage of the grid electrode of the driving transistor can be kept stable, and the display uniformity of the display panel can be improved.

It should be noted that the fixed voltage signal terminal may be loaded with a voltage signal with a fixed voltage value, so that the voltage of the second electrode of the shielding capacitor may be constant, and the charge injection into the node N1 of the node N4 may be further avoided. Moreover, because the voltage of the second electrode of the shielding capacitor is constant, the interference of the voltage of the second electrode of the shielding capacitor to the charge of the node N4 can be avoided, the charge of the node N4 can be further kept stable, and the display effect is improved.

In specific implementation, in the embodiment of the present invention, as shown in fig. 3 and 4, the sub-pixel spx may further include a light emitting device L. The light emitting device L may include an anode, a light emitting functional layer, and a cathode, which are stacked. In practical applications, the pixel unit PX may include a red sub-pixel, a green sub-pixel, and a blue sub-pixel to realize an image display function by red, green, and blue color mixing. It is also possible to make the pixel unit PX include a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel to realize an image display function by red, green, blue, and white color mixing.

Illustratively, the light emitting functional layer may include an electroluminescent material. Further, the light-emitting functional layer may further include a hole injection layer, a hole transport layer, an electron injection layer, an electron transport layer, and the like. Of course, in practical applications, the specific structure of the light emitting function layer may be designed and determined according to practical application environments, and is not limited herein.

In a specific implementation, the light emitting device L may include: at least one of Organic Light Emitting Diodes (OLEDs) and Quantum Dot Light Emitting Diodes (QLEDs). When the light emitting device L is an OLED, an anode of the OLED is a first pole of the light emitting device L, and a cathode of the OLED is a second pole of the light emitting device L. In addition, the light emitting device L generally has a light emission threshold voltage, and light emission is performed when a voltage across the light emitting device L is greater than or equal to the light emission threshold voltage. In practical applications, the specific structure of the light emitting device L may be designed and determined according to practical application environments, and is not limited herein.

In practical implementation, as shown in fig. 3 and 4, a row of sub-pixels corresponds to two scan signal lines, the scan signal lines may have a first scan signal line S1 and a second scan signal line S2, and a row of sub-pixels corresponds to one first scan signal line S1 and one second scan signal line S2. Also, the display panel may further include: a plurality of light emission control signal lines EM, a plurality of DATA lines DATA, a first power line PVDD, a plurality of reference voltage signal lines VREF; one row of sub-pixels spx corresponds to one emission control signal line EM; one row of sub-pixels spx corresponds to one reference voltage signal line VREF, and one column of sub-pixels corresponds to one DATA line DATA.

In specific implementation, in the embodiment of the present invention, as shown in fig. 4, the pixel circuit 001 may further include: a first light emission control transistor M1, a data write transistor M2, an initialization transistor M3, a reset transistor M5, a second light emission control transistor M6, and a storage capacitor CST; wherein the content of the first and second substances,

the gate of the first light emission controlling transistor M1 is electrically connected to the corresponding light emission control signal line EM, the first pole of the first light emission controlling transistor M1 is electrically connected to the first power supply line PVDD, and the second pole of the first light emission controlling transistor M1 is electrically connected to the first pole of the driving transistor M0.

The gate of the data write transistor M2 is electrically connected to the corresponding second scan signal line S2, the first pole of the data write transistor M2 is electrically connected to the corresponding data line, and the second pole of the data write transistor M2 is electrically connected to the first pole of the drive transistor M0.

The gate of the initialization transistor M3 is electrically connected to the corresponding first scan signal line S1, the first pole of the initialization transistor M3 is electrically connected to the reference voltage signal line VREF, and the second pole of the initialization transistor M3 is electrically connected to the first pole of the light emitting device L.

The gate of the first threshold compensation transistor M41 and the gate of the second threshold compensation transistor M42 are electrically connected to the corresponding second scan signal line S2.

The gate of the reset transistor M5 is electrically connected to the corresponding first scan signal line S1, the first pole of the reset transistor M5 is electrically connected to the reference voltage signal line VREF, and the second pole of the reset transistor M5 is electrically connected to the gate of the driving transistor M0.

The gate of the second light emission controlling transistor M6 is electrically connected to the corresponding light emission control signal line EM, the first pole of the second light emission controlling transistor M6 is electrically connected to the second pole of the driving transistor M0, and the second pole of the second light emission controlling transistor M6 is electrically connected to the first pole of the light emitting device L.

A first electrode of the storage capacitor CST is electrically connected to the gate of the driving transistor M0, and a second electrode of the storage capacitor CST is electrically connected to the first power supply line PVDD.

The second electrode of the light emitting device L is electrically connected to a second power source terminal.

Illustratively, the transistors described above may each be provided as a P-type transistor. Alternatively, the transistors may be all N-type transistors, which is not limited herein. And, the first pole can be set as the source and the second pole as the drain according to the type of the transistor and the type of the voltage loaded on the gate; alternatively, the first pole is set as the drain, and the second pole is set as the source, which may be determined according to the practical application environment, and is not limited herein.

In one embodiment, the voltage of the first power line may be a high voltage, and the voltage of the second power line may be a low voltage or a ground voltage. Of course, in practical applications, the specific value of the voltage may be determined according to practical application environments, and is not limited herein.

In a specific implementation, each of the transistors may be a Thin Film Transistor (TFT) or a Metal Oxide semiconductor field effect Transistor (MOS), and is not limited herein.

In particular, fig. 5 illustrates a timing diagram of signals of the pixel circuit shown in fig. 4. Where S1 represents a signal on the first scan signal line S1, S2 represents a signal on the second scan signal line S2, and EM represents a signal on the light emission control signal line EM. Specifically, one frame time may include: stage T1-T3.

In the stage T1, since the signal s2 is a high-level signal, the data writing transistor M2, the first threshold compensation transistor M41, and the second threshold compensation transistor M42 are all turned off. Since the signal em is a high level signal, both the first and second light emitting control transistors M1 and M6 are turned off. Since the signal s1 is a low-level signal, both the initialization transistor M3 and the reset transistor M5 are turned on.

The turned-on initialization transistor M3 supplies the signal on the reference voltage signal line VREF to the first terminal of the light emitting device L to reset the light emitting device L. The turned-on reset transistor M5 supplies the signal on the reference voltage signal line VREF to the gate of the driving transistor M0 to reset the gate of the driving transistor M0.

In the stage T2, since the signal em is a high level signal, both the first light emission control transistor M1 and the second light emission control transistor M6 are turned off. Since the signal s1 is a high-level signal, both the initialization transistor M3 and the reset transistor M5 are turned off. Since the signal s2 is a low level signal, the data writing transistor M2, the first threshold compensation transistor M41 and the second threshold compensation transistor M42 are all turned on.

The turned-on DATA write transistor M2 supplies the voltage Vdata on the DATA line DATA to the first pole of the driving transistor M0. And the turned-on first and second threshold compensation transistors M41 and M42 may electrically connect the gate and the second pole of the driving transistor M0 to form the driving transistor M0 in a diode connection structure, so that the voltage Vdata of the first pole of the driving transistor M0 charges the gate of the driving transistor M0 through the driving transistor M0 in a diode structure, and when the voltage of the gate of the driving transistor M0 becomes Vdata- | Vth |, the driving transistor M0 is turned off and stores the voltage of the gate of the driving transistor M0 through the storage capacitor CST. Where Vth represents the threshold voltage of the driving transistor M0.

In the stage T3, since the signal s1 is a high-level signal, both the initialization transistor M3 and the reset transistor M5 are turned off. Since the signal s2 is a high level signal, the data writing transistor M2, the first threshold compensation transistor M41 and the second threshold compensation transistor M42 are all turned off. Since the signal em is a low level signal, both the first light emission controlling transistor M1 and the second light emission controlling transistor M6 are turned on.

The turned-on first lighting control transistor M1 supplies the voltage Vdd on the first power supply line PVDD to the first pole of the driving transistor M0, and the gate voltage of the driving transistor M0 is Vdata- | Vth |. The driving transistor M0 generates the current IL for driving the light emitting device L to emit light according to the formula: IL ═ k (Vdd-Vdata)². Also, the current IL may be supplied to the anode of the light emitting device L through the turned-on second light emission controlling transistor M6, and the cathode of the light emitting device L is applied with a low voltage signal to make the light emitting device L emit light.

In the display panel of the embodiment of the invention, the electric charge of the node N4 can be stored in the shielding capacitor CF by the effect of the shielding capacitor CF storing the electric charge when the signal s2 is switched from a low-level signal to a high-level signal. Therefore, the injection of the charge of the node N4 into the node N1 can be avoided, so that the voltage of the gate of the driving transistor M0 can be kept stable, the current IL can be kept stable, and the display uniformity of the display panel can be improved.

Illustratively, in order to reduce the influence of the leakage current on the gate voltage of the driving transistor M0, in a specific implementation, as shown in fig. 4, the reset transistor M5 may be provided as a transistor of a double gate type structure. Specifically, the reset transistor M5 may include: a first initialization transistor M51 and a second initialization transistor M52; the gates of the first initialization transistor M51 and the second initialization transistor M52 are electrically connected to the first scan signal line S1, the first pole of the first initialization transistor M51 is electrically connected to the reference voltage signal line VREF, the second pole of the first initialization transistor M51 is electrically connected to the first pole of the second initialization transistor M52, and the second pole of the second initialization transistor M52 is electrically connected to the gate of the driving transistor M0.

Exemplarily, the following description is made with reference to fig. 6 and 7. Fig. 6 is a schematic diagram of a Layout (Layout) of the pixel circuit on the substrate 10. Fig. 7 is a schematic cross-sectional structure along the AA' direction in the layout diagram shown in fig. 6.

Fig. 6 and 7 are schematic diagrams illustrating a positional relationship of the stack of the active semiconductor layer 400, the first conductive layer 100, the second conductive layer 200, and the third conductive layer 300 in the pixel circuit. It should be noted that the display panel may further include: a gate insulating layer 610 between the active semiconductor layer 400 and the first conductive layer 100, an interlayer dielectric layer 620 between the first conductive layer 100 and the second conductive layer 200, and an interlayer insulating layer 630 between the second conductive layer 200 and the third conductive layer 300. Further, the display panel may further include: the buffer layer 640 between the active layer of the first threshold compensation transistor M41 and the base substrate 10, that is, the buffer layer 640 is between the active semiconductor layer 400 and the base substrate 10 to improve the adhesion of the active semiconductor layer 400.

In specific implementation, in the embodiment of the present invention, as shown in fig. 6 and 7, the active semiconductor layer 400 may be formed by patterning using a semiconductor material. The active semiconductor layer 400 may be used to fabricate active layers of the transistors described above, and each active layer may include a source region, a drain region, and a channel region between the source and drain regions. For example, the active layer of the first threshold compensation transistor M41 includes a first source region M41-S, a first drain region M41-D, and a first channel region M41-A between the first source region M41-S and the first drain region M41-D; the first source region M41-S serves as the first pole of the first threshold compensation transistor M41, and the first drain region M41-D serves as the second pole of the first threshold compensation transistor M41. The active layer of the second threshold compensation transistor M42 includes a second source region M42-S, a second drain region M42-D, and a second channel region M42-A between the second source region M42-S and the second drain region M42-D; the second source region M42-S serves as a first pole of the second threshold compensation transistor M42, and the second drain region M42-D serves as a second pole of the second threshold compensation transistor M42.

Exemplarily, FIG. 7 shows the first source region M41-S, the first drain region M41-D and the first channel region M41-A of the active layer of the first threshold compensation transistor M41. The second source region M42-S, the second drain region M42-D and the second channel region M42-A of the active layer of the second threshold compensation transistor M42. The source region M6-S (as the first pole of the second light emission control transistor M6), the drain region M6-D (as the second pole of the second light emission control transistor M6), and the channel region M6-a of the active layer of the second light emission control transistor M6. The source region M2-S of the active layer of the data write transistor M2 (as the first pole of the data write transistor M2).

Illustratively, in particular implementations, the first drain region M41-D and the second source region M42-S may be provided as a unitary structure. Of course, in practical applications, the design may be determined according to practical application environments, and is not limited herein.

Illustratively, the active layer of the transistor may be integrally provided. Illustratively, the active semiconductor layer 400 may be made of amorphous silicon, polycrystalline silicon, an oxide semiconductor material, or the like. Note that the source region and the drain region may be regions doped with n-type impurities or p-type impurities.

In specific implementation, in the embodiment of the present invention, as shown in fig. 6 and fig. 7, the first conductive layer 100 may include: the first scanning signal line S1, the second scanning signal line S2, the emission control signal line EM, the gates of the transistors in the pixel circuit, and the first electrode of the storage capacitor CST. For example, fig. 6 and 7 show the first scanning signal line S1, the second scanning signal line S2, the emission control signal line EM, the gates M41-G of the first threshold compensation transistor M41, the gates M42-G of the second threshold compensation transistor M42, and the gates M6-G of the second emission control transistor M6. Also, a gate electrode (not shown in fig. 7) of the driving transistor M0 may serve as a first electrode of the storage capacitor CST. In a direction perpendicular to the plane of the base substrate 10, the first scanning signal line S1, the second scanning signal line S2, the emission control signal line EM, and the active semiconductor layer 400 have an overlapping region. For an overlapping region of the first scan signal line S2 and the active semiconductor layer 400, the first scan signal line S2 in the overlapping region may be a gate M41-G of the first threshold compensation transistor M41 and a gate M42-G of the second threshold compensation transistor M42, and the active semiconductor layer 400 in the overlapping region may be a channel region M41-a of the first threshold compensation transistor M41 and a channel region M42-a of the second threshold compensation transistor M42. For the same reason, the description is omitted here.

In specific implementation, in the embodiment of the present invention, as shown in fig. 6 and fig. 7, the second conductive layer 200 may include: a reference voltage signal line VREF, an electrode conductive part CST-2, and a first anode connection layer 220. The electrode conductive portion CST-2 serves as a second electrode of the storage capacitor CST. That is, the second electrode of the storage capacitor CST is located on the side of the gate of the drive transistor M0 facing away from the substrate 10.

In specific implementation, in the embodiment of the present invention, as shown in fig. 6 and fig. 7, the third conductive layer 300 may include: a DATA line DATA, a first power line PVDD, a connection portion for electrically connecting the transistor and the storage capacitor CST, and a second anode connection layer. For example, fig. 6 and 7 show the DATA line DATA, the first power line PVDD, the connection part 320 electrically connecting the first source region M41-S of the first threshold compensation transistor M41 and the gate of the driving transistor M0, and the second anode connection layer 310. One end of the connection portion 320 is electrically connected to the first source region M41-S of the first threshold compensation transistor M41 through a via 632 penetrating through the gate insulating layer 610, the interlayer dielectric layer 620 and the interlayer insulating layer 630, and the other end of the connection portion 320 is electrically connected to the gate of the driving transistor M0 through a via penetrating through the interlayer dielectric layer 620 and the interlayer insulating layer 630. One end of the second anode connection layer 310 is electrically connected to the first anode connection layer 220 through a via hole penetrating the interlayer insulating layer 630, and the first anode connection layer 220 is electrically connected to the drain region M6-D of the second emission control transistor M6 through a via hole penetrating the interlayer dielectric layer 620 and the gate insulating layer 610. Furthermore, a planarization layer is further disposed on a side of the third conductive layer 300 away from the substrate 10, and an anode of the light emitting device L and an anode cathode of the light emitting functional layer are sequentially disposed on a side of the planarization layer away from the substrate 10. Wherein the anode is electrically connected to the second anode connection layer 310 through a via hole penetrating the planarization layer.

In specific implementation, in the embodiment of the present invention, as shown in fig. 6 and 7, for the first scanning signal line S1, the second scanning signal line S2, the reference voltage signal line VREF, and the emission control signal line EM corresponding to the same row of sub-pixels, the forward projection of the second scanning signal line S2 on the substrate 10 is located between the forward projection of the first scanning signal line S1 on the substrate 10 and the forward projection of the emission control signal line EM on the substrate 10. The orthographic projection of the area where the driving transistor is located on the substrate 10 is located between the orthographic projection of the second scanning signal line S2 on the substrate 10 and the orthographic projection of the light emission control signal line EM on the substrate 10. The orthographic projection of the first scanning signal line S1 on the base board 10 is located between the orthographic projection of the reference voltage signal line VREF on the base board 10 and the orthographic projection of the second scanning signal line S2 on the base board 10. Of course, in practical applications, the embodiment of the signal line may be designed and determined according to practical application environments, and is not limited herein.

In practical implementation, in the embodiment of the present invention, the material of the first conductive layer 100, the second conductive layer 200, and the third conductive layer 300 may be a metal material, such as gold, silver, copper, aluminum, molybdenum, and the like, which is not limited herein.

It should be noted that the embodiments of the active semiconductor layer 400, the first conductive layer 100, the second conductive layer 200, and the third conductive layer 300 may be substantially the same as those in the related art, and are not described in detail herein.

For example, in practical implementation, in an embodiment of the present invention, as shown in fig. 6 and fig. 7, the display panel may further include: shielding layers corresponding to the sub-pixels one by one; wherein, for the same sub-pixel, at least one of the first drain region and the second source region has an overlapping region in the orthographic projection of the substrate base plate 10 and the orthographic projection of the shielding layer in the substrate base plate 10. And, the shielding layer is the second electrode of the shielding capacitance CF, and at least one of the first drain region and the second source region having an overlap region with the shielding layer is the first electrode of the shielding capacitance CF. Illustratively, the orthographic projection of one data line on the substrate base plate 10 and the orthographic projection of the shielding layer in the sub-pixel of the adjacent column on the substrate base plate 10 have an overlapping area. Illustratively, the orthographic projection of the first power line PVDD on the substrate base plate 10 and the orthographic projection of the shielding layer on the substrate base plate 10 also have an overlapping region.

Illustratively, in particular implementation, in an embodiment of the present invention, as shown in fig. 6 and 7, the shielding layer may include a first shielding layer 210; the first shielding layer 210 is disposed in the same layer and insulated from the second electrode (i.e., the electrode conductive portion CST-2) of the storage capacitor CST. I.e. the first shield layer 210 is located at the second conductive layer 200. Thus, the same patterning process can be used to form other structures in the first shielding layer 210 and the second conductive layer 200, thereby reducing the difficulty of process preparation and reducing the cost.

For example, in practical implementation, in an embodiment of the present invention, as shown in fig. 6 and fig. 7, the display panel may include: first shielding layers 210 corresponding to the respective sub-pixels one by one; each data line is located on a side of the first shielding layer 210 facing away from the substrate 10. At least one of the first drain region M41-D and the second source region M42-S has an overlap region with an orthogonal projection of the first shielding layer 210 on the substrate 10 for the same sub-pixel. Also, the first shielding layer 210 is provided as a second electrode of the shielding capacitance CF, and at least one of the first drain region and the second source region having an overlapping region with the first shielding layer 210 is provided as a first electrode of the shielding capacitance CF. Also, an orthogonal projection of the first power line PVDD on the substrate board 10 and an orthogonal projection of the first shielding layer 210 on the substrate board 10 may have an overlapping region.

Illustratively, in practical implementation, in the embodiment of the present invention, as shown in fig. 6 and 7, the first drain region M41-D and the second source region M42-S are provided as an integral structure, so that the orthographic projection of the first shielding layer 210 on the substrate 10 may have an overlapping region with the integral structure formed by the first drain region M41-D and the second source region M42-S on the orthographic projection of the substrate 10. Also, the orthographic projection of the first shielding layer 210 on the base substrate 10 does not overlap the orthographic projection of the first scanning signal line S1 and the second scanning signal line S2 on the base substrate 10. This can prevent the first shielding layer 210 from interfering with signals transmitted on the first scanning signal line S1 and the second scanning signal line S2.

In particular, in the embodiment of the present invention, a fixed voltage signal terminal may be electrically connected to the first shielding layer 210, so as to apply a voltage signal with a fixed voltage value to the first shielding layer 210.

Illustratively, in a specific implementation, in an embodiment of the present invention, the fixed voltage signal terminal may be electrically connected to the first power line PVDD. For example, as shown in fig. 6 and 7, the first power line PVDD is electrically connected to the first shielding layer 210 through a via 631 penetrating the interlayer insulating layer 630, so that the voltage transmitted on the first power line PVDD is applied to the first shielding layer 210. Therefore, the first power line PVDD for transmitting the fixed voltage value signal in the display panel can be used for transmitting the signal for the first shielding layer 210, so that the signal line for transmitting the fixed voltage value signal is not required to be additionally arranged, the wiring design difficulty is reduced, and the process preparation difficulty is reduced.

Illustratively, in practical implementation, in the embodiment of the present invention, as shown in fig. 6 and 7, the orthographic projection of one DATA line DATA on the substrate 10 and the orthographic projection of the first shielding layer 210 corresponding to the adjacent column of sub-pixels on the substrate 10 have an overlapping region. And, for the DATA line DATA and the first power line PVDD having an overlapping area with the orthographic projection of the first shielding layer 210 on the substrate 10, the first power line PVDD is located between the DATA line DATA and the sub-pixel corresponding to the DATA line DATA. For example, if a column of sub-pixels corresponds to one first power line PVDD, the same column of sub-pixels may correspond to one first power line PVDD and one DATA line DATA, and each sub-pixel in a column of sub-pixels corresponds to one first shielding layer 210, so that there may be two adjacent columns of sub-pixels, and in the row direction from the left side to the right side, the orthogonal projection of the first power line PVDD and the DATA line DATA corresponding to the first column of sub-pixels on the substrate 10 has an overlapping region with the orthogonal projection of the first shielding layer 210 corresponding to the second column of sub-pixels on the substrate 10. And, the first power line PVDD corresponding to the first column of sub-pixels is electrically connected to the first shielding layer 210 corresponding to the second column of sub-pixels through a via hole penetrating the interlayer insulating layer 630. Since the connection portion 320 needs to be electrically connected to the first source region M41-S of the first threshold compensation transistor M41 through the via 632, the first power line PVDD corresponding to the first column of sub-pixels is electrically connected to the first shielding layer 210 corresponding to the second column of sub-pixels, so that the influence on the via 632 can be avoided, and the via 632 can be directly prepared by a preparation method in the related art without adjusting the position of the via 632, thereby reducing the process preparation difficulty and the design difficulty.

The embodiment of the invention provides another display panel, and the structural schematic diagrams thereof are shown in fig. 8 and fig. 9. Which is modified from the embodiments described in the above embodiments. Only the differences between the present embodiment and the above embodiments will be described below, and the descriptions of the same parts will be omitted.

In particular implementation, in the embodiment of the present invention, as shown in fig. 8 and 9, the shielding layer may also include a second shielding layer 220; wherein the second shielding layer 220 may be located between the base substrate 10 and the buffer layer 640. That is, a fourth conductive layer may be disposed between the substrate base plate 10 and the buffer layer 640, and the fourth conductive layer may include a plurality of second shield layers 220 disposed at intervals.

Specifically, in practical implementation, in the embodiment of the present invention, as shown in fig. 8 and 9, the display panel may further include: a second shielding layer 220 corresponding to each sub-pixel spx one to one; wherein, for the same sub-pixel, at least one of the first drain region M41-D and the second source region M42-S has an overlapping region in the orthographic projection of the substrate base plate 10 and the orthographic projection of the second shielding layer 220 in the substrate base plate 10. Also, the second shielding layer 220 is a second electrode of the shielding capacitance CF, and at least one of the first drain region and the second source region having an overlapping region with the second shielding layer 220 is a first electrode of the shielding capacitance CF. Also, an orthogonal projection of the first power line PVDD on the substrate board 10 and an orthogonal projection of the second shielding layer 220 on the substrate board 10 have an overlapping region.

For example, in practical implementation, in the embodiment of the present invention, as shown in fig. 8 and 9, the first drain region M41-D and the second source region M42-S may be provided as an integral structure, and the orthographic projection of the second shielding layer 220 on the substrate 10 may have an overlapping region with the integral structure formed by the first drain region M41-D and the second source region M42-S on the orthographic projection of the substrate 10. Also, the orthographic projection of the second shielding layer 220 on the base substrate 10 does not overlap the orthographic projection of the first scanning signal line S1 and the second scanning signal line S2 on the base substrate 10.

In practical implementation, in the embodiment of the present invention, the fixed voltage signal terminal is electrically connected to the second shielding layer 220, so as to apply a voltage signal with a fixed voltage value to the second shielding layer 220. Illustratively, the fixed voltage signal terminal may be electrically connected to the first power line PVDD. For example, as shown in fig. 8 and 9, the first power line PVDD may be electrically connected to the second shielding layer 220 through a via hole 633 penetrating the buffer layer 640, the gate insulating layer 610, the interlayer dielectric layer 620, and the interlayer insulating layer 630, so that the voltage transmitted on the first power line PVDD is applied to the second shielding layer 220.

Illustratively, in practical implementation, in the embodiment of the present invention, as shown in fig. 8 and 9, an orthogonal projection of one DATA line DATA on the substrate 10 and an orthogonal projection of the second shielding layer 220 corresponding to the adjacent column of sub-pixels on the substrate 10 have an overlapping region. Also, for the DATA line DATA and the first power line PVDD having an overlapping area with the orthographic projection of the second shielding layer 220 on the substrate 10, the first power line PVDD is located between the DATA line DATA and the sub-pixel corresponding to the DATA line DATA. For example, a column of sub-pixels may correspond to one first power line PVDD, the same column of sub-pixels may correspond to one first power line PVDD and one DATA line DATA, and each sub-pixel in a column of sub-pixels may correspond to one second shielding layer 220, so that every two adjacent columns of sub-pixels may be provided, and in a row direction from the left side to the right side, a forward projection of the first power line PVDD and the DATA line DATA corresponding to the first column of sub-pixels on the substrate 10 may have an overlapping region with a forward projection of the second shielding layer 220 corresponding to the second column of sub-pixels on the substrate 10. Furthermore, the first power line PVDD corresponding to the first column of sub-pixels may be electrically connected to the second shielding layer 220 corresponding to the second column of sub-pixels through a via hole 633 penetrating the buffer layer 640, the gate insulating layer 610, the interlayer dielectric layer 620, and the interlayer insulating layer 630. Since the connection portion 320 needs to be electrically connected to the first source region M41-S of the first threshold compensation transistor M41 through the via 632, the first power line PVDD corresponding to the first column of sub-pixels is electrically connected to the second shielding layer 220 corresponding to the second column of sub-pixels, so as to avoid the influence on the via 632, and thus the via 632 can be directly prepared by using a preparation method in the related art without adjusting the position of the via 632, thereby reducing the process preparation difficulty and the design difficulty.

It should be noted that the embodiments of the active semiconductor layer 400, the first conductive layer 100, the second conductive layer 200, and the third conductive layer 300 shown in fig. 8 and fig. 9 may be substantially the same as the structures in the above embodiments, and detailed descriptions thereof are omitted.

The embodiment of the invention provides another display panel, and the structural schematic diagram of the display panel is shown in fig. 10 and fig. 11. Which is modified from the embodiments described in the above embodiments. Only the differences between the present embodiment and the above embodiments will be described below, and the descriptions of the same parts will be omitted.

In practical implementation, in the embodiment of the present invention, as shown in fig. 10 and 11, the display panel may have both the first shielding layer 210 and the second shielding layer 220. Therefore, the storage capacity of the shielding capacitor CF can be improved, and the charge injection of the node N4 into the node N1 can be further avoided, so that the voltage of the grid electrode of the driving transistor can be kept stable, and the display uniformity of the display panel can be improved.

For example, in practical implementation, in the embodiment of the present invention, as shown in fig. 10 and 11, an orthogonal projection of the first shielding layer 210 on the base substrate 10 may be overlapped with an orthogonal projection of the second shielding layer 220 on the base substrate 10. The orthographic projection of the second shielding layer 220 on the substrate 10 can also be made to cover the orthographic projection of the first shielding layer 210 on the substrate 10. Alternatively, as shown in fig. 10 and 11, an orthogonal projection of the first shielding layer 210 on the base substrate 10 may be overlapped with an orthogonal projection of the second shielding layer 220 on the base substrate 10. This can reduce the design difficulty and the process preparation difficulty of the first shielding layer 210 and the second shielding layer 220. Of course, in practical applications, the embodiments of the first shielding layer 210 and the second shielding layer 220 may be designed and determined according to practical application environments, and are not limited herein.

For example, in specific implementation, in the embodiment of the present invention, the implementation of the first shielding layer 210 may be substantially the same as that in the above embodiment, and details are not described herein.

For example, in practical implementation, in the embodiment of the present invention, as shown in fig. 10 and 11, the first power line PVDD may be electrically connected to the first shielding layer 210 through a via 634 penetrating through the interlayer insulating layer 630, and the first shielding layer 210 may be electrically connected to the second shielding layer 220 through a via 635 penetrating through the interlayer dielectric layer 620, the gate insulating layer 610, and the buffer layer 640.

It should be noted that the embodiments of the active semiconductor layer 400, the first conductive layer 100, the second conductive layer 200, and the third conductive layer 300 shown in fig. 10 and fig. 11 may be substantially the same as the structures in the above embodiments, and detailed descriptions thereof are omitted.

The embodiment of the invention provides another display panel, and the structural schematic diagram of the display panel is shown in fig. 12 and 13. Which is modified from the embodiments described in the above embodiments. Only the differences between the present embodiment and the above embodiments will be described below, and the descriptions of the same parts will be omitted.

In particular implementation, in the embodiment of the present invention, as shown in fig. 12 and 13, the shielding layer may also include a third shielding layer 230. The third shielding layer 230 is disposed in the same layer and insulated from the second electrode (i.e., the electrode conductive portion CST-2) of the storage capacitor CST. I.e. the third shield layer 230 may be located at the second conductive layer 200. Specifically, the display panel may further include: a third shielding layer 230 corresponding to each sub-pixel one to one; wherein, each data line may be located at a side of the third shielding layer 230 facing away from the substrate base plate 10. At least one of the first drain region M41-D and the second source region M42-S has an overlap region with an orthogonal projection of the third shielding layer 230 on the substrate 10 for the same sub-pixel. Also, the third shielding layer 230 is a second electrode of the shielding capacitance CF, and at least one of the first drain region and the second source region having an overlapping region with the third shielding layer 230 is a first electrode of the shielding capacitance CF. Also, an orthogonal projection of the first power line PVDD on the substrate board 10 and an orthogonal projection of the third shielding layer 230 on the substrate board 10 have an overlapping region.

Illustratively, in practical implementation, in the embodiment of the present invention, as shown in fig. 12 and 13, the first drain region M41-D and the second source region M42-S are a unitary structure, and the orthographic projection of the third shielding layer 230 on the substrate 10 may have an overlapping region with the unitary structure formed by the first drain region M41-D and the second source region M42-S on the orthographic projection of the substrate 10. Also, the orthographic projection of the third shielding layer 230 on the base substrate 10 does not overlap the orthographic projection of the first scanning signal line S1 and the second scanning signal line S2 on the base substrate 10.

Illustratively, in particular implementation, in the embodiment of the present invention, the third shielding layer 230 is applied with a voltage signal with a fixed voltage value. Illustratively, the fixed-voltage signal terminal may be electrically connected to the reference-voltage signal line VREF. For example, as shown in fig. 12 and 13, the third shielding layer 230 may be directly electrically connected to the reference voltage signal line VREF, so that the voltage signal with a fixed voltage value transmitted on the reference voltage signal line VREF is applied to the third shielding layer 230.

Further, in the embodiment of the present invention, as shown in fig. 12 and 13, each of the reference voltage signal lines VREF may be extended downward to form a protruding portion, so that the protruding portion forms the third shielding layer 230. This may allow the third shielding layer 230 and the reference voltage signal line VREF corresponding to the same row of sub-pixels to be provided as an integral structure. In addition, the reference voltage signal line VREF and the third shielding layer 230 may be located on the second conductive layer 200, so that when the display panel is manufactured, a pattern originally forming the reference voltage signal line VREF may be set to form the reference voltage signal line VREF and the third shielding layer 230 at the same time. Therefore, the process preparation difficulty can be reduced, the process preparation efficiency can be improved, and the cost can be reduced.

For example, in practical implementation, in an embodiment of the present invention, as shown in fig. 12 and 13, a forward projection of one DATA line DATA on the substrate 10 may have an overlapping region with a forward projection of the third shielding layer 230 corresponding to the adjacent column of sub-pixels on the substrate 10. Also, for the DATA line DATA and the first power line PVDD having an overlapping area with the orthographic projection of the third shielding layer 230 on the substrate 10, the first power line PVDD is located between the DATA line DATA and the sub-pixel corresponding to the DATA line DATA. For example, if a column of sub-pixels corresponds to one first power line PVDD, the same column of sub-pixels may correspond to one first power line PVDD and one DATA line DATA, and each sub-pixel in a column of sub-pixels corresponds to one third shielding layer 230, so that there may be two adjacent columns of sub-pixels, and in the row direction from the left side to the right side, the orthographic projection of the first power line PVDD and the DATA line DATA corresponding to the first column of sub-pixels on the substrate 10 has an overlapping region with the orthographic projection of the third shielding layer 230 corresponding to the second column of sub-pixels on the substrate 10.

Further, in practical implementation, in the embodiment of the present invention, as shown in fig. 12 and fig. 13, the shape of the third shielding layer 230 is set to be a polygonal line shape (for example, the shape of the third shielding layer 230 is "L" shape). Since the connection portion 320 needs to be electrically connected to the first source region M41-S of the first threshold compensation transistor M41 through the via 632, the third shielding layer 230 is shaped as a zigzag, so that the influence on the via 632 can be avoided, the via 632 can be directly prepared by a preparation method in the related art without adjusting the position of the via 632, and the process preparation difficulty and the design difficulty are reduced.

It should be noted that the embodiments of the active semiconductor layer 400, the first conductive layer 100, the second conductive layer 200, and the third conductive layer 300 shown in fig. 12 and 13 may be substantially the same as the structures in the above embodiments, and detailed descriptions thereof are omitted.

Based on the same inventive concept, the embodiment of the invention further provides a display device, which comprises the display panel provided by the embodiment of the invention. The principle of the display device to solve the problem is similar to the display panel, so the implementation of the display device can be referred to the implementation of the display panel, and repeated details are not repeated herein.

In practical implementation, in the embodiment of the present invention, the display device may be a full-screen mobile phone as shown in fig. 14. Of course, in practical implementation, the display device may also be any product or component with a display function, such as a vehicle-mounted display device, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, and a navigator. Other essential components of the display device are understood by those skilled in the art, and are not described herein or should not be construed as limiting the invention.

In the display panel and the display device according to the embodiments of the present invention, the threshold compensation circuit includes: a first threshold compensation transistor, a second threshold compensation transistor and a shield capacitor; here, by providing the first threshold compensation transistor and the second threshold compensation transistor, the length L of the channel region of the transistor can be increased, and since the current I of the transistor is inversely proportional to the length L of the channel region, the current I of the transistor can be decreased when the length L of the channel region is increased, so that the amount of charge flowing from the node N4 into the node N1 can be reduced. By providing the shield capacitor, the charge at the node N4 can be stored in the shield capacitor by the effect of the shield capacitor in storing the charge. Thus, when the signal on the scanning signal line is switched, the charge injection of the node N4 into the node N1 can be avoided, so that the voltage of the gate of the driving transistor can be kept stable, and the display uniformity of the display panel can be improved.

It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.

Claims

1. A display panel, comprising: the liquid crystal display device comprises a substrate base plate, a plurality of sub-pixels and a plurality of scanning signal lines, wherein the sub-pixels and the scanning signal lines are positioned on the substrate base plate; a row of sub-pixels corresponds to at least one scanning signal line;

the sub-pixel comprises a pixel circuit; the pixel circuit comprises a threshold compensation circuit and a drive transistor; wherein the threshold compensation circuit comprises: a first threshold compensation transistor, a second threshold compensation transistor and a shield capacitor;

a gate of the first threshold compensation transistor and a gate of the second threshold compensation transistor are electrically connected to corresponding scan signal lines, a first pole of the first threshold compensation transistor is electrically connected to a gate of the driving transistor, a second pole of the first threshold compensation transistor is electrically connected to a first pole of the second threshold compensation transistor, and a second pole of the second threshold compensation transistor is electrically connected to a second pole of the driving transistor;

a first electrode of the shield capacitor is electrically connected to a second electrode of the first threshold compensation transistor; the second electrode of the shielding capacitor is electrically connected with the fixed voltage signal end;

the orthographic projection of the second electrode of the shielding capacitor on the substrate base plate is not overlapped with the orthographic projection of a scanning signal line electrically connected with the first threshold compensation transistor on the substrate base plate;

the pixel circuit further includes: a reset transistor; the grid electrode of the reset transistor is electrically connected with the corresponding scanning signal line, the reset transistor comprises a first initialization reset transistor and a second initialization reset transistor, the first pole of the first initialization transistor of the reset transistor is electrically connected with the reference voltage signal line, the second pole of the second initialization transistor of the reset transistor is electrically connected with the grid electrode of the driving transistor, and the second pole of the first initialization transistor is electrically connected with the first pole of the second initialization transistor; a scanning signal line electrically connected to the gate of the reset transistor and a scanning signal line electrically connected to the first threshold compensation transistor are different for the same pixel circuit;

a space exists between the orthographic projection of the first electrode of the shielding capacitor on the substrate and the orthographic projection of the channel of the second initialization transistor of the reset transistor on the substrate.

2. The display panel of claim 1, wherein the display panel further comprises a plurality of data lines and a plurality of first power lines, a column of sub-pixels corresponding to at least one of the data lines;

the pixel circuit further includes: a first emission control transistor, a gate of which is electrically connected to an emission control signal terminal EIMT, a first pole of which is electrically connected to the first power line, and a second pole of which is electrically connected to the first pole of the driving transistor;

an interval exists between the orthographic projection of the data line electrically connected with the pixel circuit on the substrate and the orthographic projection of the channel of the first light-emitting control transistor on the substrate.

3. The display panel according to claim 2, wherein for the first power supply line and the data line electrically connected to the same pixel circuit, the first power supply line is located between the data line and a channel of the second threshold compensation transistor in a direction perpendicular to a plane in which the substrate base plate is located.

4. The display panel of claim 3, wherein the pixel circuit further comprises: a data write transistor; wherein a gate electrode of the data writing transistor is electrically connected to a corresponding scanning signal line, a first electrode of the data writing transistor is electrically connected to the data line corresponding to the pixel circuit, and a second electrode of the data writing transistor is electrically connected to the first electrode of the driving transistor;

each data line is positioned on one side of the second electrode of the shielding capacitor, which faces away from the substrate base plate.

5. The display panel according to claim 4, wherein a forward projection of one of the data lines on the substrate base plate has an overlapping area with a forward projection of the second electrode of the shielding capacitor in the adjacent column of sub-pixels on the substrate base plate.

6. The display panel of claim 2, wherein the fixed voltage signal terminal is electrically connected to the first power line.

7. The display panel according to claim 1, further comprising an active semiconductor layer; the active semiconductor layer includes a first active structure;

the first active structure is connected with a channel of the first threshold compensation transistor, the first active structure is connected with a channel of the second threshold compensation transistor, and the first active structure is multiplexed as a first electrode of the shielding capacitor.

8. The display panel according to claim 1, wherein the display panel further comprises: an active semiconductor layer;

the first electrode of the shielding capacitor is located on the active semiconductor layer.

9. The display panel of claim 8, wherein the active layer of the first threshold compensation transistor comprises a first source region, a first drain region, and a first channel region between the first source region and the first drain region; wherein the first source region serves as a first pole of the first threshold compensation transistor and the first drain region serves as a second pole of the first threshold compensation transistor;

the active layer of the second threshold compensation transistor comprises a second source region, a second drain region and a second channel region between the second source region and the second drain region; wherein the second source region serves as a first pole of the second threshold compensation transistor and the second drain region serves as a second pole of the second threshold compensation transistor;

the display panel further includes: a shielding layer corresponding to the sub-pixel; wherein, for the same sub-pixel, the orthographic projection of at least one of the first drain region and the second source region on the substrate has an overlapping region with the orthographic projection of the shielding layer on the substrate;

the shielding layer is a second electrode of the shielding capacitor, and at least one of the first drain region and the second source region which have an overlapping region with the shielding layer is multiplexed as a first electrode of the shielding capacitor.

10. The display panel of claim 9, wherein the pixel circuit further comprises: a storage capacitor electrically connected to the gate of the driving transistor; the grid electrode of the driving transistor is used as a first electrode of the storage capacitor, and a second electrode of the storage capacitor is positioned on one side, away from the substrate, of the grid electrode of the driving transistor;

the shielding layer comprises a first shielding layer; the first shielding layer and the second electrode of the storage capacitor are arranged at the same layer and in an insulating mode.

11. The display panel according to claim 9, wherein the display panel further comprises: a buffer layer between the active layer of the first threshold compensation transistor and the substrate base plate;

the shielding layer comprises a second shielding layer; the second shielding layer is located between the substrate base plate and the buffer layer.

12. The display panel of claim 1, wherein the fixed voltage signal terminal is electrically connected to the reference voltage signal line.

13. A display device characterized by comprising the display panel according to any one of claims 1 to 12.